JP2022172706A - Dc/dc converter, control circuit thereof, and electronic device - Google Patents

Abstract

To realize 100% duty cycle output in a DC/DC converter having an n-type high-side transistor.SOLUTION: A pulse width modulator 210 performs a pulse width modulation on an on-time signal ONTIME so that output voltage VOUT approaches a target level VOUT(REF). A charge pump circuit 202 includes an output node configured to be connectable to a bootstrap terminal BST and generates a voltage VCP higher than an input voltage VIN of a DC/DC converter 100 while an enable signal CHGPMPEN is asserted. A logic circuit 220 generates a control pulse signal HG on the basis of the on-time signal ONTIME, and asserts the enable signal CHGPMP while a pulse width of the on-time signal ONTIME exceeds a first threshold value τ1, and fixes the control pulse signal HG for high sides to high when the pulse width exceeds a second threshold value τ2.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to a DC/DC converter (switching regulator).

Various electronic devices such as consumer devices such as smartphones and tablet computers, automotive devices, OA devices, and industrial devices have circuit components that require a power supply voltage that is lower or higher than the battery voltage or external power supply voltage. is installed. A step-down DC/DC converter (Buck converter) or a step-up DC/DC converter is used to supply an appropriate power supply voltage to such circuit components.

JP 2014-117042 A JP 2019-037116 A

When the input voltage of the DC/DC converter drops to the target level of the output voltage, the output voltage is maintained close to the target level by permanently turning on the high-side transistor, that is, setting the duty cycle to 100%. be able to.

Here, when the high-side transistor of the step-down DC/DC converter is configured as an N-type, it is necessary to generate a bootstrap voltage higher than the input voltage using a bootstrap circuit and generate a gate drive signal for the high-side transistor.

However, the operation of the bootstrap circuit requires switching of the DC/DC converter. In other words, if the high-side transistor is fixedly turned on, the bootstrap circuit becomes inoperable, the bootstrap voltage gradually decreases, and eventually the high-side transistor cannot be kept on.

The present disclosure has been made in such circumstances, and one exemplary object of certain aspects thereof is to provide a control circuit capable of outputting a duty cycle of 100% in a DC/DC converter having an N-type high-side transistor. in the offer of

A control circuit according to one aspect of the present disclosure is a step-down DC/DC converter control circuit having an N-type high-side transistor, and includes a bootstrap terminal and a DC/DC converter output voltage that approaches a target level. A pulse width modulator that generates an on-time signal that is pulse-width modulated to , its power supply node is connected to the bootstrap terminal, and a gate drive signal corresponding to the high-side control pulse signal is applied to the control terminal of the high-side transistor. a charge pump circuit having an output node connected to the bootstrap terminal and generating a voltage higher than the input voltage of the DC/DC converter while the enable signal is asserted; (i) generating a control pulse signal based on the on-time signal; (ii) asserting an enable signal while the pulse width of the on-time signal exceeds a first threshold; (iii) pulsing the on-time signal; a logic circuit for fixing the high-side control pulse signal high when it exceeds a second threshold whose width is longer than the first threshold.

Arbitrary combinations of the above constituent elements, and mutually replacing constituent elements and expressions in methods, devices, systems, etc. are also effective as embodiments of the present invention.

According to one aspect of the present disclosure, a DC/DC converter having an N-type high-side transistor can output a 100% duty cycle.

FIG. 1 is a block diagram of a DC/DC converter according to an embodiment. FIG. 2 is a waveform diagram explaining the operation of the DC/DC converter of FIG. FIG. 3 is a block diagram of a control circuit according to the first embodiment; FIG. 4 is an operation waveform diagram of the control circuit of FIG. FIG. 5 is a circuit diagram showing part of the logic circuit. FIG. 6 is a block diagram of a control circuit according to the second embodiment. FIG. 7 is a diagram illustrating an example of an electronic device including the step-down DC/DC converter according to the embodiment;

(Overview of embodiment)
SUMMARY OF THE INVENTION Several exemplary embodiments of the disclosure are summarized. This summary presents, in simplified form, some concepts of one or more embodiments, as a prelude to the more detailed description that is presented later, and for the purpose of a basic understanding of the embodiments. The size is not limited. Moreover, this summary is not an exhaustive overview of all possible embodiments and is not intended to limit essential elements of an embodiment. For convenience, "one embodiment" may be used to refer to one embodiment (example or variation) or multiple embodiments (examples or variations) disclosed herein.

This summary is intended to neither identify key or critical elements of all embodiments nor delineate the scope of some or all aspects. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later.

A control circuit according to one embodiment controls a step-down DC/DC converter having an N-type high-side transistor. The control circuit includes a bootstrap terminal, a pulse width modulator that generates an on-time signal that is pulse width modulated so that the output voltage of the DC/DC converter approaches a target level, and a power supply node connected to the bootstrap terminal. A high-side driver that supplies a gate drive signal corresponding to the control pulse signal to the control terminal of the high-side transistor, and its output node are connected to the bootstrap terminal. a charge pump circuit that generates a voltage higher than the input voltage of the DC converter; (i) generating a control pulse signal based on the on-time signal; and (ii) the pulse width of the on-time signal exceeds a first threshold. and (iii) fixing the high-side control pulse signal to high when the pulse width of the on-time signal exceeds a second threshold value longer than the first threshold value. , and a logic circuit.

During normal duty cycle operation, when the pulse width of the on-time signal exceeds a first threshold, the charge pump circuit is enabled and ready for a 100% duty cycle output. When the pulse width becomes longer and exceeds the second threshold, the gate of the high-side transistor is fixed at a high level, resulting in a 100% duty cycle output. Switching stops, but the charge pump circuit maintains the voltage on the bootstrap terminal, so the 100% duty cycle output continues. Thus, this control circuit is capable of outputting a 100% duty cycle.

In one embodiment, after fixing the high-side control pulse signal to high, the logic circuit compares the on-time determined according to the input voltage and the output voltage with a third threshold, and the on-time is compared with the third threshold. If it is shorter than the value, the fixation of the high-side control pulse signal to high may be released. This sequence allows the 100% duty cycle output to be terminated and normal switching operation to resume when the input voltage rises above the target level of the output voltage.

In one embodiment, the determination of the pulse width (or on-time) of the on-time signal may be based on the period during which the on-time signal itself is high, from the trigger of the on-time beginning to the end of the on-time. It may be based on time to trigger.

In one embodiment, the logic circuit includes a first detection circuit that compares the pulse width of the on-time signal to a first threshold and a second detection circuit that compares the pulse width of the on-time signal to a second threshold. , and a third detection circuit that compares the on-time to a third threshold.

In one embodiment, the logic circuit includes a first input node that receives the output of the second detection circuit, a second input node that receives the output of the third detection circuit, an output node at which the fixed on signal is generated, and a selection based on the fixed on signal. A multiplexer having a control node to which the signal is input may also be included. This enables hysteresis control.

In one embodiment, the first threshold may be longer than 1.5 times the switching period. In one embodiment, the second threshold may be longer than the first threshold. In one embodiment, the third threshold may be equal to the switching period during switching operation of the DC/DC converter.

In one embodiment, the pulse width modulator compares a feedback signal corresponding to the output voltage of the DC/DC converter with a threshold voltage defining a target level, and when the feedback signal falls below the threshold voltage, the predetermined level is reached. a comparator for generating a comparator output signal, and a timer circuit for starting counting an on-time when the comparator output signal reaches a predetermined level, the on-time being proportional to the output voltage and the input voltage of the DC/DC converter. and a timer circuit that is inversely proportional to , and the on-time signal may be reset by the output of the timer circuit.

In one embodiment, the third detection circuit may cause the timer circuit to start timing the ON time when the comparator output signal reaches a complementary level of the predetermined level.

In one embodiment, the pulse width modulator may further include an error amplifier that amplifies the error between the feedback signal and the reference voltage to generate the threshold voltage.

In one embodiment, the pulse width modulator includes an error amplifier that amplifies an error between a feedback signal and a reference voltage responsive to the output voltage of the DC/DC converter to generate an error signal, and a DC A current comparator that compares an error signal with a current detection signal that indicates the current flowing through the /DC converter, and an on-time signal generation circuit that outputs an on-time signal whose level transitions based on the output of the current comparator.

In one embodiment, the on-time signal generation circuit may include an oscillator and a flip-flop that is set based on the output of the oscillator and reset based on the output of the current comparator.

In one embodiment, the control circuit may be monolithically integrated on a single semiconductor substrate. "Integrated integration" includes the case where all circuit components are formed on a semiconductor substrate, and the case where the main components of a circuit are integrated. A resistor, capacitor, or the like may be provided outside the semiconductor substrate. By integrating the circuits on one chip, the circuit area can be reduced and the characteristics of the circuit elements can be kept uniform.

(embodiment)
Hereinafter, the present disclosure will be described based on preferred embodiments with reference to the drawings. The same or equivalent constituent elements, members, and processes shown in each drawing are denoted by the same reference numerals, and duplication of description will be omitted as appropriate. Moreover, the embodiments are illustrative rather than limiting the invention or disclosure, and not all features and combinations thereof described in the embodiments are necessarily essential to the invention or disclosure.

In this specification, "a state in which member A is connected to member B" refers to a case in which member A and member B are physically directly connected, as well as a case in which member A and member B are electrically connected to each other. It also includes the case of being indirectly connected through other members that do not substantially affect the physical connection state or impair the functions and effects achieved by their combination.

Similarly, "the state in which member C is connected between member A and member B" includes the case where member A and member C or member B and member C are directly connected, as well as the case where they are electrically connected. It also includes the case of being indirectly connected through other members that do not substantially affect the physical connection state or impair the functions and effects achieved by their combination.

FIG. 1 is a block diagram of a DC/DC converter 100 according to an embodiment. The DC/DC converter 100 is a step-down DC/DC converter (Buck converter), receives a direct-current input voltage V _IN on an input line (input terminal) 102 , and loads a load connected to an output line (output terminal) 104 . , provides an output voltage V _OUT that is lower in voltage level than the input voltage V _IN . The DC/DC converter 100 is a constant voltage output type that stabilizes the output voltage V _OUT to the target level V _{OUT (REF)} .

The DC/DC converter 100 comprises a control circuit 200 and its peripheral circuits 110 . DC/DC converter 100 is of the synchronous rectification type, and peripheral circuit 110 includes inductor L1, output capacitor C1, and bootstrap capacitor C2. Both the high-side transistor MH and the low-side transistor ML are N-type (that is, N-channel or NPN-type), and may be a MOSFET (Metal Oxide Semiconductor Field Effect Transistor) or an IGBT (Insulated Gate Bipolar Transistor). Alternatively, it may be a bipolar transistor.

Note that the high-side transistor MH and the low-side transistor ML may be discrete elements provided outside the control circuit 200 , in which case the high-side transistor MH and the low-side transistor ML constitute the peripheral circuit 110 .

The control circuit 200 is a functional IC (Integrated Circuit) integrated on one semiconductor substrate, and includes an input pin (also called a terminal) VIN, a switching pin SW, a ground pin GND, a feedback pin FB, and a bootstrap pin BST. . An input voltage _VIN is supplied to the input pin VIN. An external inductor L1 is connected to the switching pin SW, and the ground pin PGND is grounded. The high side transistor MH is connected between the input pin VIN and the switching pin SW, and the low side transistor ML is connected between the switching pin SW and the ground pin PGND. A bootstrap capacitor C2 is connected between the bootstrap pin BST and the switching pin SW. Note that the bootstrap capacitor C2 may be integrated in the control circuit 200, in which case the bootstrap pin BST may be omitted. A feedback signal V _FB based on the output voltage V _OUT of the DC/DC converter 100 is input to the feedback pin FB. For example, the feedback signal _VFB is a voltage signal obtained by dividing the output voltage _VOUT by resistors R1 and R2.

The control circuit 200 includes a pulse width modulator 210, a logic circuit 220, a driver circuit 240, a bootstrap switch SW1, and a charge pump circuit 202 in addition to the high-side transistor MH and the low-side transistor ML.

Pulse width modulator 210 produces an on-time signal ONTIME that is pulse width modulated such that the output voltage V _OUT of DC/DC converter 100 approaches a target level V _OUT(REF) .

Specifically, the pulse width modulator 210 pulse width modulates the on-time signal ONTIME so that the feedback signal V _FB corresponding to the output voltage V _OUT approaches the reference voltage V _REF . When feedback signal V _FB is regulated to reference voltage V _REF , output voltage V _OUT of DC/DC converter 100 is regulated to V _OUT(REF) =V _REF ×(R1+R2)/R2.

The configuration and control method of the pulse width modulator 210 are not particularly limited. The pulse width modulator 210 may perform a control method using an error amplifier, for example, voltage mode control, peak current mode or average current mode control. Alternatively, the pulse width modulator 210 may perform ripple control such as hysteresis control (Bang-Bang control), bottom detection ON time fixed control, peak detection OFF time fixed control.

The logic circuit 220 is control logic that controls the control circuit 200 in an integrated manner. Logic circuitry 220 may include a portion (logic portion) of pulse width modulator 210 .

Logic circuit 220 generates control pulse signals HG and LG based on on-time signal ONTIME generated by pulse width modulator 210 .

A bootstrap switch SW1 has one end connected to a bootstrap pin BST and the other end receiving a DC voltage _VDC . The DC voltage _VDC may be the input voltage _VIN or a voltage generated by an internal regulator (not shown). The bootstrap switch SW1 performs switching in conjunction with the low-side transistor ML. That is, when the low-side transistor ML is turned on and the voltage of the switching pin SW (switching voltage V _SW ) is low, the bootstrap switch SW1 is turned on. At this time, the bootstrap capacitor C2 is charged by the DC voltage _VDC . When the low-side transistor ML is turned off and the high-side transistor MH is turned on, the switching voltage V _SW of the switching pin SW becomes high level (input voltage V _IN ). At this time, the voltage of the bootstrap pin BST (bootstrap voltage) V _BST becomes V _IN +V _DC , which is higher than the input voltage V _IN . A diode (rectifying element) may be used instead of the bootstrap switch SW1.

Driver circuit 240 drives high-side transistor MH and low-side transistor ML based on control pulse signals HG and LG generated by pulse width modulator 210 . Driver circuit 240 includes a high side driver 242 and a low side driver 244 . The high-side driver 242 generates a gate drive signal VHG for the high-side transistor MH based on the high-side control pulse signal _HG , and the low-side driver 244 drives the gate of the low-side transistor ML based on the low-side control pulse signal LG. Generates signal V _LG .

A power supply node (upper power supply terminal) N1 of the high side driver 242 is connected to the bootstrap pin BST, and a ground node (lower power supply terminal) N2 is connected to the switching pin SW. When the high-side control pulse signal HG is high, the high-side driver 242 outputs a high level, that is, the voltage _VBST of the power supply node, and when the high-side control pulse signal HG is low, the high-side driver 242 outputs a low level. , that is, it outputs the voltage VSW of the ground _node N2.

The charge pump circuit 202 can be switched between enable and disable according to the enable signal CHGPMPEN. The output node N3 of the charge pump circuit 202 is connected to the bootstrap pin BST, is enabled while the enable signal CHGPMPEN is asserted, and generates a voltage higher than the input voltage _VIN of the DC/DC converter 100 . For example, charge pump circuit 202 may be a double or triple charge pump that boosts the input voltage _VIN or any other DC voltage. The charge pump circuit 202 has an output voltage _VCP of
V _CP >V _IN +V _GS(th)
designed to meet V _GS(th) is the gate threshold voltage of the high-side transistor MH.

A function of the logic circuit 220 will be described.

The logic circuit 220 (i) generates the control pulse signals HG and LG based on the on-time signal ONTIME. The logic circuit 220 also (ii) asserts the enable signal CHGPMPEN while the pulse width Tx of the on-time signal ONTIME exceeds the _first threshold value τ1. (iii) When the pulse width Tx of the on-time signal ONTIME exceeds a _second threshold τ2 longer than the _first threshold τ1, the logic circuit 220 sets the high-side control pulse signal HG to high. fixed.

Thereafter, after fixing the high-side control pulse signal HG to high, the logic circuit 220 compares the ON time T _ON determined according to the input voltage V _IN and the output voltage V _OUT with the _third threshold value τ3, When the on-time T _ON is shorter than the _third threshold value τ3, the fixation of the high-side control pulse signal HG to high is released.

The above is the basic configuration of the DC/DC converter 100 . Next, the operation will be explained. FIG. 2 is a waveform diagram for explaining the operation of DC/DC converter 100 of FIG. FIG. 2 shows the input voltage V _IN , the ON-time signal ONTIME, the enable signal CHGPMPEN of the charge pump circuit, the internal signal (also called fixed ON signal) DUTY100, and the control pulse signals HG and LG in order from the top. It should be noted that the vertical and horizontal axes of waveform diagrams and time charts referred to in this specification are enlarged or reduced as appropriate for ease of understanding, and each waveform shown is simplified for ease of understanding. distorted, or exaggerated or emphasized.

In a step-down DC/DC converter, the duty cycle DUTY of the on-time signal ONTIME in a steady state is
DUTY = V _OUT /V _IN
determined by In the case of pulse width modulation with a constant switching period Tp, the pulse width Tx of the on-time signal ONTIME while V _IN >V _OUT holds:
TON=Tp× _DUTY =Tp× _VOUT / _VIN (1)
is equal to the on-time T _ON represented by .

Before time _t0 , the input voltage V _IN is in a normal operating state sufficiently higher than the target level of the output voltage V _OUT , and the pulse width Tx (=T _ON ) is short. Therefore, the pulse width Tx is shorter than the _first threshold value τ1, and the enable signal CHGPMPEN is negated (low).

Prior to time _t0 , the input voltage V _IN begins to drop over time. As the input voltage V _IN decreases, the duty cycle increases and the pulse width Tx (=T _ON ) increases. Then, when the pulse width Tx exceeds the _first threshold value τ1, the enable signal EN is asserted (high) for the excess time, and the charge pump circuit 202 operates.

When the input voltage V _IN drops to the target level V _OUT(REF) of the output voltage V _OUT , theoretically the pulse width will be equal to the switching period Tp and the duty cycle will be 100%. At this time, adjacent pulses are combined, and the on-time signal ONTIME continues to maintain the high level.

At time t1, when it is detected that the pulse width Tx has exceeded the _second threshold value _τ2 , the fixed ON signal DUTY100, which is an internal signal of the logic circuit 220, is asserted (high). The logic circuit 220 fixes the high-side control pulse HG to high when the fixed ON signal DUTY100 is asserted. This initiates 100% duty cycle control and V _OUT ≈V _IN .

_When the input voltage V _IN begins to rise at time t2, the on-time T _ON determined by equation (1) is shortened. When the on-time TON becomes shorter than the _third threshold value _τ3 , the fixed on-signal _DUTY100 becomes low at time t3, the 100% duty control of the high-side transistor MH is released, and the high-side transistor according to the on-time signal ONTIME is released. Switching of transistor MH resumes.

The above is the operation of the DC/DC converter 100 . In this DC/DC converter 100, the pulse width Tx of the on-time signal ONTIME or the on-time T _ON is compared with different thresholds τ ₁ to τ ₃ . When the pulse width Tx exceeds the shortest _first threshold value τ1, the charge pump circuit 202 is enabled to prepare for 100% duty cycle output. When the pulse width Tx becomes longer and exceeds the _second threshold value τ2, the gate of the high-side transistor MH is fixed at a high level, resulting in a 100% duty cycle output. At the 100% duty cycle output, switching stops, but the charge pump circuit 202 maintains the voltage V _BST on the bootstrap pin BST, so the 100% duty cycle output continues. After that, when the input voltage V _IN rises and the ON time T _ON becomes shorter than the _third threshold value τ3, the 100% duty cycle output ends and the normal switching operation is resumed. Thus, according to the control circuit 200, output with a duty cycle of 100% is possible.

This disclosure extends to various apparatus and methods that can be grasped as the block diagram or circuit diagram of FIG. 1 or derived from the above description, and is not limited to any particular configuration. Hereinafter, more specific configuration examples and embodiments will be described not to narrow the scope of the present disclosure, but to help understand and clarify the essence and operation of the present disclosure and the present invention.

(Example 1)
FIG. 3 is a block diagram of the control circuit 200A according to the first embodiment. Pulse width modulator 210 includes error amplifier 212 , comparator 214 , on-time timer 216 and ripple injection circuit 218 .

The error amplifier 212 amplifies the error between the feedback signal _VFB and the reference voltage _VREF . The output V _ERR of error amplifier 212 is a threshold voltage that defines the bottom level of feedback signal V _FB .

A ripple injection circuit 218 superimposes a ripple component V _RIP on the feedback signal V _FB . The comparator 214 compares the feedback signal V _FB ′ on which the ripple component is superimposed with the output V _ERR of the error amplifier 212 and outputs a signal COMPOUT indicating the comparison result.

Alternatively, the error amplifier 212 may be omitted and the comparator 214 may directly compare the feedback signal _VFB with the reference voltage _VREF .

Comparator output signal COMPOUT is asserted (eg, high level) when feedback signal V _FB ′ drops to output V _ERR of error amplifier 212 .

The on-time timer 216 measures the on-time T _ON represented by equation (1) in response to the assertion of the comparator output signal COMPOUT. An input voltage V _IN and an output voltage V _OUT are input to the on-time timer 216 . The on-time T _ON is adjusted to be proportional to the output voltage V _OUT and inversely proportional to the input voltage V _IN . Since the output voltage V _OUT is stabilized at the target level V _OUT(REF) , the on-time T _ON may be adjusted to be proportional to V _OUT(REF) . The on-time signal ONTIME is reset after the _on -time TON elapses after the on-time timer 216 starts counting. The pulse width Tx of the on-time signal ONTIME matches the on-time T _ON counted by the on-time timer 216 in the range of less than 100% duty cycle.

Logic circuit 220 generates control pulse signals HG and LG and enable signal CHGPMPEN based on on-time signal ONTIME and comparator output signal COMPOUT. The logic circuit 220 inserts a dead time in which both of the control pulse signals HG and LG become low so that a through current does not flow through the high-side transistor MH and the low-side transistor ML.

The above is the configuration of the control circuit 200A. Next, the operation will be explained.

FIG. 4 is an operation waveform diagram of the control circuit 200A of FIG. FIG. 4 shows the input voltage V _IN , the feedback signal V _FB , the comparator output signal COMPOUT, the internal signals ONTRSTMSK, ONTRST, the on-time signal ONTIME, the internal signal MINOFF, the enable signal CHGPMPEN, the internal signals MAXON, DUTY100 in order from the top. .

Comparator output signal COMPOUT indicates the result of threshold voltage comparison based on feedback signal _VFB and error signal _VERR , and is asserted (high) when feedback signal _VFB becomes lower than error signal _VERR .

In response to the assertion of comparator output signal COMPOUT, on-time timer 216 begins timing to measure the on-time T _ON as a function of input voltage V _IN and output voltage V _OUT to generate on-time signal ONTIME. While the on-time signal ONTIME is high, the high-side transistor MH is turned on and the low-side transistor ML is turned off.

During the period from when the on-time signal ONTIME transitions to low to when the comparator output signal COMPOUT is next asserted, the high-side transistor MH is off and the low-side transistor ML is on. The internal signal MINOFF is a signal that sets the minimum off-time, and is high for the minimum off-time after the high-side transistor MH turns off. While the internal signal MINOFF is asserted (high), the low side transistor ML is not turned off immediately even if the comparator output signal COMPOUT is asserted, but is turned off after the minimum off time is over.

The on-time reset signal ONTRST, which is an internal signal of the on-time timer 216, is asserted (high) upon completion of counting the on-time T _ON adjusted to be proportional to the output voltage V _OUT and inversely proportional to the input voltage _VIN . When the on-time reset signal ONTRST is asserted (eg, high), the on-time signal ONTIME transitions low (reset). During the period in which the high-side transistor MH is on and the on-time reset mask signal ONTRSTMSK, which is an internal signal, is high, the on-time reset signal ONTRST is masked and becomes the minimum on-time. Also, the reset of the on-time signal ONTIME is masked by the high level of the comparator output signal COMPOUT. That is, if the comparator output signal COMPOUT remains high when the on-time reset signal ONTRST goes high, the on-time signal ONTIME remains high until the comparator output signal COMPOUT transitions from high to low. do. At this time, the pulse width Tx of the on-time signal ONTIME becomes longer than the _on -time TON. This state is called a duty cycle expansion period.

A maximum on-time signal MAXON, which is an internal signal, indicates the second threshold _τ2 or the _third threshold τ3.

Prior to time _t0 , the input voltage V _IN begins to drop over time. As the input voltage V _IN decreases, the duty cycle increases and the on-time T _ON , that is, the pulse width of the on-time signal ONTIME increases. Then, when the pulse width TON of the on-time _signal ONTIME exceeds the _first threshold value τ1, the enable signal EN is asserted (high) for the excess time, and the charge pump circuit 202 operates.

At time t1, when it is detected that the pulse width Tx of the on _- time signal ONTIME has exceeded the _second threshold value τ2, the fixed on-signal DUTY100, which is an internal signal of the logic circuit 220, is asserted (high). . The logic circuit 220 fixes the high-side control pulse HG to high when the fixed ON signal DUTY100 is asserted.

After that, when the input voltage V _IN rises and becomes higher than the target level V _{OUT (REF)} of the output voltage V _OUT , the feedback signal V _FB exceeds the output V _ERR of the error amplifier 212, and the comparator output signal COMPOUT becomes transitions low (time t ₂ ). When comparator output signal COMPOUT transitions low, on-time timer 216 starts counting. Then, after the on-time TON of equation (1), which is determined according to the input voltage V _IN and the output voltage V _OUT , has elapsed, the on-time reset signal _ONTRST is asserted, and the on-time signal ONTIME transitions to low.

Logic circuit 220 compares the on-time T _ON counted by on-time timer 216 to a _third threshold τ3. When the ON time TON is shorter than the _third threshold value τ3, the fixed _ON signal DUTY100 is switched to low to release the 100% duty control. After that, the switching of the high-side transistor MH is resumed according to the on-time signal ONTIME.

The _first threshold τ1 can be defined to be longer than 1.5 times the switching period Tp during normal switching operation. The second threshold τ ₂ can be defined longer than the first threshold τ ₁ . A third threshold τ ₃ can be defined equal to the switching period Tp.

For example, when the switching period Tp is 0.5 μs, the _first threshold τ1 can be set longer than 0.75 μs, which is 1.5 times the switching period Tp, and for example Tp (=0.5 μs) may be set to 2 μs, which is four times . The second threshold τ ₂ is set longer than the first threshold τ ₁ , and may be set to 8 μs, which is twice as long as the first threshold τ ₁ , as an example. The _third threshold τ3 can be 0.5 μs, which is equal to the switching period Tp.

The above is the operation of the control circuit 200A. Next, a configuration example of the logic circuit 220 related to 100% duty cycle output will be described.

FIG. 5 is a circuit diagram showing part of the logic circuit 220. As shown in FIG. Logic circuit 220 includes a first detection circuit 222 , a second detection circuit 224 , a third detection circuit 226 and a multiplexer 228 .

A first detection circuit 222 compares the pulse width of the on-time signal ONTIME with a _first threshold τ1 to generate an enable signal CHGPMPEN. The configuration of the first detection circuit 222 is not particularly limited. It may be configured with a digital comparator that compares with _a value corresponding to the threshold value τ1.

Alternatively, the first detection circuit 222 starts counting clock signals when the on-time signal ONTIME transitions to a predetermined level, and asserts a count completion signal when the count value reaches a value corresponding to the _first threshold value τ1. and a timing determiner that determines which of the assertion of the count complete signal and the trailing edge of the on-time signal leads.

In FIG. 5, the on-time signal ONTIME is directly input to the first detection circuit 222. However, the signal defining the leading edge of the on-time signal ONTIME, that is, the comparator output signal COMPOUT and a signal that defines the trailing edge of the on-time signal ONTIME, that is, a timing signal that indicates completion of counting by the on-time timer 216 may be input.

Second detection circuit 224 and third detection circuit 226 generate fixed on signal DUTY100. A second detection circuit 224 compares the pulse width of the on-time signal ONTIME with a _second threshold τ2. The second detection circuit 224 outputs high when the pulse width exceeds the _second threshold τ2. The second detection circuit 224 can be configured similarly to the first detection circuit 222 .

The third detection circuit 226 defines the time Tb from when the input voltage V _IN exceeds the target level V _{OUT (REF)} of the output voltage V _OUT to the trailing edge of the on-time signal ONTIME as a _third threshold value τ3. If it compares and detects Tb< _τ3 , it outputs low.

Although the configuration of the third detection circuit 226 is not particularly limited, for example, it receives the comparator output signal COMPOUT as a signal indicating that the input voltage _VIN has exceeded the target level _VOUT(REF) of the output voltage _VOUT . The third detection circuit 226 can be composed of a counter and a digital comparator. The counter starts counting up triggered by the transition of the comparator output signal COMPOUT to low, and ends counting up at the trailing edge of the on-time signal ONTIME. The digital comparator compares the count value at the end of counting with a value corresponding to a _third threshold value τ3.

Alternatively, the third detection circuit 226 can be composed of a counter and a timing determiner. The counter starts counting up triggered by the transition of the comparator output signal COMPOUT to low, and asserts the count completion signal when it reaches a value corresponding to the _third threshold value τ3. The timing determiner determines which of the assertion of the count complete signal and the trailing edge of the on-time signal ONTIME comes first.

When the output of the second detection circuit 224 goes high, the logic circuit 220 asserts the fixed ON signal DUTY100 and transitions to 100% duty cycle output. Also, when the output of the third detection circuit 226 becomes low, the logic circuit 220 negates the fixed ON signal DUTY100 and shifts to normal switching operation.

A multiplexer 228 receives at its first input node (0) the output of the second detection circuit 224 and at its second input node (1) the output of the third detection circuit 226, selecting one to Output as fixed ON signal DUTY100. A selection signal based on the fixed ON signal DUTY100 is input to the control node SEL of the multiplexer 228 . This enables hysteresis control based on two thresholds τ ₂ and τ ₃ .

(Example 2)
FIG. 6 is a block diagram of a control circuit 200B according to the second embodiment. The second embodiment differs from the first embodiment in the configuration of the pulse width modulator 210 . Specifically, in the second embodiment, the pulse width modulator 210 is a current mode pulse width modulator, and includes a current detection circuit 211, an error amplifier 212, an oscillator 213, a comparator 214, and a flip-flop FF1.

The current detection circuit 211 detects a coil current (a high side current flowing through the high side transistor MH) during the ON period of the high side transistor MH, and generates a current detection signal _VCS indicating the amount of current.

The comparator 214 compares the current detection signal V _CS with the error signal V _ERR which is the output of the error amplifier 212, and asserts (high) the comparator output signal COMPOUT when V _CS >V _ERR .

The oscillator 213 oscillates with a predetermined period Tp. The flip-flop FF1 is set by the comparator output signal COMPOUT and reset every period Tp of the oscillator 213 . The output of the flip-flop FF1 becomes the on-time signal ONTIME.

The 100% duty control according to the present disclosure is also applicable to the current mode control circuit of FIG. When recovering from 100% duty control, it is necessary to detect that the input voltage _VIN has exceeded the target level _VOUT(REF) of the output voltage _VOUT . In the first embodiment, the output COMPOUT of the comparator 214 is used as a timing signal indicating that V _IN >V _{OUT (REF)} , but this cannot be done with the current mode control of FIG. Therefore, the control circuit 200B is additionally provided with a comparator 215 that compares V _IN with V _{OUT (REF)} . The logic circuit 220 measures the time Tb based on the output of the comparator 215 and compares it with the _third threshold value τ3.

Also in the control circuit 200A of FIG. 3, a comparator 215 is added in addition to the comparator 214, the time Tb is measured based on the output of the comparator 215, and comparison with the _third threshold value τ3 is performed. good too. However, in this case, one comparator 215 is added, which increases the circuit area. In other words, in the control circuit 200A of FIG. 3, if the time Tb is measured based on the comparator output signal COMPOUT and compared with the _third threshold value τ3, the number of comparators can be reduced. .

(Application)
FIG. 7 is a diagram showing an example of an electronic device 700 that includes the DC/DC converter 100 according to the embodiment. Electronic device 700 is, for example, a battery-driven device such as a mobile phone terminal, digital camera, digital video camera, tablet terminal, or portable audio player. Electronic device 700 comprises housing 702 , battery 704 , microprocessor 706 and DC/DC converter 100 . DC/DC converter 100 receives battery voltage V _BAT (=V _IN ) from battery 704 at its input terminal and provides output voltage V _OUT to microprocessor 706 or other load connected to its output terminal.

The type of the electronic device 700 is not limited to a battery-driven device, and may be an in-vehicle device, an OA device such as a facsimile, or an industrial device.

The embodiments are examples, and it should be noted that there are various modifications in the combination of each component and each processing process, and such modifications are included in the present disclosure and can constitute the scope of the present invention. It is understood by those skilled in the art.

100 DC/DC converter 102 input line 104 output line 110 peripheral circuit MH high side transistor ML low side transistor L1 inductor C1 output capacitor 200 control circuit SW1 bootstrap switch 202 charge pump circuit 210 pulse width modulator 211 current detection circuit 212 error amplifier 213 oscillator FF1 flip-flop 214 comparator 216 on-time timer 218 ripple injection circuit 220 logic circuit 222 first detection circuit 224 second detection circuit 226 third detection circuit 228 multiplexer 240 driver circuit 242 high side driver 244 low side driver 700 electronics 702 housing body 704 battery 706 microprocessor

A control circuit according to one aspect of the present disclosure is a step-down DC/DC converter control circuit having an N-type high-side transistor, and includes a bootstrap terminal and a DC/DC converter output voltage that approaches a target level. and a power supply node configured to be connectable to a bootstrap terminal, and a high-side transistor for generating a gate drive signal corresponding to the high-side control pulse signal. and a charge pump having an output node configured to be connectable to the bootstrap terminal and generating a voltage higher than the input voltage of the DC/DC converter while the enable signal is asserted. a circuit (i) generating a control pulse signal based on the on-time signal; (ii) asserting an enable signal while the pulse width of the on-time signal exceeds a first threshold; ) a logic circuit for fixing the high-side control pulse signal to high when the pulse width of the on-time signal exceeds a second threshold that is longer than the first threshold;

A control circuit according to one embodiment controls a step-down DC/DC converter having an N-type high-side transistor. The control circuit is configured to be connectable to a bootstrap terminal, a pulse width modulator that generates an on-time signal that is pulse width modulated so that the output voltage of the DC/DC converter approaches a target level, and the bootstrap terminal. It has a power supply node, a high side driver that supplies a control terminal of the high side transistor with a gate drive signal corresponding to the control pulse signal, and an output node that can be connected to a bootstrap terminal, and an enable signal is asserted. a charge pump circuit for generating a voltage higher than the input voltage of the DC/DC converter; (i) generating a control pulse signal based on the on-time signal; (iii) a high-side control pulse when the pulse width of the on-time signal exceeds a second threshold determined longer than the first threshold; a logic circuit for fixing the signal high.

Claims (15)

A step-down DC/DC converter control circuit having an N-type high-side transistor,
a bootstrap terminal;
a pulse width modulator that generates an on-time signal that is pulse width modulated so that the output voltage of the DC/DC converter approaches a target level;
a high-side driver having a power supply node connected to the bootstrap terminal and supplying a gate drive signal corresponding to the high-side control pulse signal to a control terminal of the high-side transistor;
a charge pump circuit having an output node connected to the bootstrap terminal and generating a voltage higher than the input voltage of the DC/DC converter while an enable signal is asserted;
(i) generating the high-side control pulse signal based on the on-time signal; and (ii) asserting the enable signal while the pulse width of the on-time signal exceeds a first threshold. and (iii) a logic circuit for fixing the high-side control pulse signal to high when the pulse width of the on-time signal exceeds a second threshold longer than the first threshold. ,
A control circuit. The logic circuit compares an on-time determined according to the input voltage and the output voltage with a third threshold in a state where the high-side control pulse signal is fixed to high, and the on-time is compared with a third threshold. 2. The control circuit according to claim 1, wherein the fixation of said high-side control pulse signal to high is released when it is shorter than a threshold value. The logic circuit is
a first detection circuit that compares the pulse width of the on-time signal with the first threshold;
a second detection circuit that compares the pulse width of the on-time signal with the second threshold;
a third detection circuit that compares the on-time with the third threshold;
3. The control circuit of claim 2, comprising: The logic circuit is
A first input node for receiving the output of the second detection circuit, a second input node for receiving the output of the third detection circuit, an output node for generating a fixed ON signal, and a control for inputting a selection signal based on the fixed ON signal. 4. The control circuit of claim 3, further comprising a multiplexer having a node. 5. A control circuit as claimed in any preceding claim, wherein the first threshold is longer than 1.5 times the switching period during switching operation of the DC/DC converter. 6. A control circuit as claimed in any preceding claim, wherein the second threshold is longer than the first threshold. 5. A control circuit as claimed in any one of claims 2 to 4, wherein the third threshold is equal to a switching period during switching operation of the DC/DC converter. The pulse width modulator is
Comparing a feedback signal corresponding to the output voltage of the DC/DC converter with a threshold voltage that defines the target level, and providing a comparator output signal that becomes a predetermined level when the feedback signal becomes lower than the threshold voltage. a comparator to generate;
A timer circuit that starts counting an on-time when the comparator output signal reaches the predetermined level, wherein the on-time is proportional to the output voltage and inversely proportional to the input voltage of the DC/DC converter. When,
8. A control circuit as claimed in any preceding claim, wherein the on-time signal is reset by the output of the timer circuit. 9. The control circuit of claim 8, wherein said pulse width modulator further includes an error amplifier that amplifies an error between said feedback signal and a reference voltage to generate said threshold voltage. The pulse width modulator is
Comparing a feedback signal corresponding to the output voltage of the DC/DC converter with a threshold voltage that defines the target level, and providing a comparator output signal that becomes a predetermined level when the feedback signal becomes lower than the threshold voltage. a comparator to generate;
A timer circuit that starts counting an on-time when the comparator output signal reaches the predetermined level, wherein the on-time is proportional to the output voltage and inversely proportional to the input voltage of the DC/DC converter. When,
wherein the on-time signal is reset by the output of the timer circuit;
4. The control circuit according to claim 3, wherein said third detection circuit causes said timer circuit to start counting said ON time when said comparator output signal attains a complementary level of said predetermined level. The pulse width modulator is
an error amplifier that amplifies an error between a feedback signal corresponding to the output voltage of the DC/DC converter and a reference voltage to generate an error signal;
a current comparator that compares the error signal with a current detection signal that indicates the current flowing through the DC/DC converter during the ON time of the high-side transistor;
an on-time signal generation circuit that outputs the on-time signal whose level transitions based on the output of the current comparator;
8. A control circuit as claimed in any preceding claim, comprising: The on-time signal generation circuit is
an oscillator;
a flip-flop set based on the output of the oscillator and reset based on the output of the current comparator;
12. The control circuit of claim 11, comprising: 13. The control circuit according to claim 1, monolithically integrated on one semiconductor substrate. A DC/DC converter comprising a control circuit according to any one of claims 1 to 13. An electronic device comprising the control circuit according to any one of claims 1 to 13.

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