JP2022162488A - Multilayer wiring board and method for manufacturing multilayer wiring board - Google Patents

Abstract

To provide a multilayer wiring board and a method for manufacturing the same that can suppress the generation of metal burrs.SOLUTION: A multilayer wiring board 10 having a cavity 20 in which a portion of a first surface 10F side, which is one of the front and back surfaces, is removed from a first conductive layer 13A located in the middle of the thickness direction of the multilayer wiring board, and the cavity is opened on the first side and the first conductive layer is exposed at the bottom, has a side opening 20K that opens the cavity to a first side 10M of the multilayer wiring board, and a step 34 that is machined from the edge of the side opening side of the bottom surface 20M of the cavity. Of the conductive layers disposed on a second surface 10S side, which is the other surface of the front and back surfaces of the multilayer wiring board, with respect to the first conductive layer, the conductive layer 13B located closest to the bottom surface of the cavity is away from the first side surface with respect to the step surface 38 of the step.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to a multilayer wiring board having cavities and a manufacturing method thereof.

Conventionally, as this type of multilayer wiring board, there is known a multilayer wiring board in which a part is removed to form a cavity by cutting (see, for example, Patent Document 1).

Japanese Patent Application Laid-Open No. 2012-146983 (Fig. 1, Fig. 2, etc.)

By the way, there is a demand for a multilayer wiring board having a structure in which a cavity is opened on one side surface of the multilayer wiring board. However, in such a structure, there is a concern that part of the conductive layer at the side opening of the cavity may become a metal burr and remain on the multilayer wiring board, and the metal burr may come off in a post-process and cause a problem. Therefore, the present disclosure provides a technique capable of suppressing the generation of metal burrs.

A multilayer wiring board according to an aspect of the present disclosure is a part of the first surface side, which is one of the front and back surfaces of the multilayer wiring board, from the first conductive layer located midway in the thickness direction of the multilayer wiring board. is removed to form a cavity which opens to the first surface and exposes the first conductive layer to the bottom surface, the side surface opening the cavity to the first side surface of the multilayer wiring board An opening and a stepped portion formed by cutting an edge portion of the bottom surface of the cavity on the side of the side opening, the first conductive layer being the other surface of the front and back surfaces of the multilayer wiring board rather than the first conductive layer. Of the conductive layers arranged on the second surface side, the conductive layer located closest to the bottom surface of the cavity is farther from the first side surface than the stepped surface of the stepped portion.

In a method for manufacturing a multilayer wiring board according to an aspect of the present disclosure, a position passing through a first conductive layer in the middle of the thickness direction of the multilayer wiring board from a first surface, which is one of the front and back surfaces of the multilayer wiring board, is provided. and run the router so as to draw a closed loop trajectory, then remove the portion closer to the first surface than the first conductive layer in the inner portion of the closed loop, and open to the first surface and exposing the first conductive layer to the bottom surface and forming a cavity having a cut groove at the edge of the bottom surface, wherein the The second conductive layer positioned closest to the first conductive layer among the conductive layers arranged on the second surface side, which is the other surface of the front and back surfaces, is moved from the first side surface of the multilayer wiring board to the second surface. The closed loop includes an outer edge of the multilayer wiring board on the side of the first side surface as part of the closed loop, and the outer edge of the multilayer wiring board is less than the first distance from the first side surface. The router is run so that the range within the distance of is cut, and the cavity is provided with a side opening that opens the cavity to the first side surface and a step formed by the cutting opening groove opening to the side opening side. and forming a part.

1 is a side cross-sectional view of a multilayer wiring board according to an embodiment of the present disclosure; FIG. Plan view of multilayer wiring board Enlarged side cross-sectional view showing a manufacturing process of a multilayer wiring board Side sectional view showing a manufacturing process of a multilayer wiring board Side sectional view showing a manufacturing process of a multilayer wiring board Side sectional view showing a manufacturing process of a multilayer wiring board Side sectional view showing a manufacturing process of a multilayer wiring board Side sectional view showing a manufacturing process of a multilayer wiring board Side sectional view showing a manufacturing process of a multilayer wiring board Side sectional view showing a manufacturing process of a multilayer wiring board A plan view showing a manufacturing process of a multilayer wiring board Side sectional view showing a manufacturing process of a multilayer wiring board Side sectional view showing a manufacturing process of a multilayer wiring board Enlarged side cross-sectional view showing a manufacturing process of a multilayer wiring board

As shown in FIG. 1, a multilayer wiring board 10 according to an embodiment of the present disclosure has a laminated structure in which insulating layers and conductive layers are alternately laminated. Specifically, in the laminated structure of the multilayer wiring board 10, the first buildup portion 12A is laminated on the first surface 11F, which is one surface of the front and back surfaces of the core substrate 11, and the other surface of the front and back surfaces of the core substrate 11. The second buildup portion 12B is laminated on the second surface 11S which is

The core substrate 11 is formed by laminating conductive layers 13A and 13B from both front and back sides (first surface 11F side and second surface 11S) on an insulating base material 11K as an insulating layer. The conductive layer 13A on the first surface 11F and the conductive layer 13B on the second surface 11S are each formed in a predetermined pattern and connected by through-hole conductors 14 passing through the insulating base material 11K. In the following description, the conductive layer 13A on the first surface 11F will be referred to as "first conductive layer 13A", and the conductive layer 13B on the second surface 11S will be referred to as "second conductive layer 13B".

The first buildup portion 12A and the second buildup portion 12B each have a structure in which interlayer insulating layers 15 and conductive layers 16 are alternately laminated from the core substrate 11 side. Adjacent conductive layers 16 are connected by a plurality of via conductors 15</b>D penetrating through interlayer insulating layer 15 . Via conductor 15</b>D has a tapered shape that decreases in diameter as it approaches core substrate 11 . The interlayer insulating layer 15 is, for example, a prepreg (a B-stage resin sheet obtained by impregnating a core material made of fibers such as glass cloth with a resin) or an insulating film for a build-up board (having no core material and containing, for example, an inorganic filler). It is composed of a film made of a thermosetting resin containing

A solder resist layer 17 is provided on the outermost conductive layer 16 arranged on the outermost side (the side farthest from the core substrate 11) of the conductive layers 16 of the first buildup portion 12A and the second buildup portion 12B. formed. Each solder resist layer 17 constitutes the outermost layer of the multilayer wiring board 10 . An opening 17A is formed in the solder resist layer 17, and a pad 18 is formed by a portion of the outermost conductive layer 16 exposed from the solder resist layer 17 through the opening 17A.

A cavity 20 is opened in a first surface 10</b>F, which is one of the front and back surfaces of the multilayer wiring board 10 . The cavity 20 is formed by removing a portion of the first surface 10F side of the conductive layer (in this embodiment, the first conductive layer 13A of the core substrate 11) positioned midway in the thickness direction of the multilayer wiring board 10. Become. In this embodiment, the cavity 20 penetrates through the first buildup portion 12A and exposes the first surface 11F of the core substrate 11 to the bottom surface 20M of the cavity 20 . Specifically, the first conductive layer 13A of the core substrate 11 is exposed on the bottom surface 20M of the cavity 20, and the exposed portion forms a pad 21 for component mounting. In the example of this embodiment, the exposed portion of the first conductive layer 13A is a solid pattern. Electronic component 100 accommodated in cavity 20 is mounted on pad 21 .

The cavity 20 is formed with a side opening 20K that opens to the first side surface 10M of the multilayer wiring board 10 . As shown in FIG. 2, in the present embodiment, the cavity 20 has a square shape in plan view, and a side opening 20K is provided on only one side of the cavity 20 . The cavity 20 is surrounded by the first buildup portion 12A from the remaining three sides of the cavity 20 .

As shown in FIGS. 1 and 2, a stepped portion 34 is formed at the edge of the bottom surface 20M of the cavity 20 on the side opening 20K side. In the example of the present embodiment, the stepped portion 34 is formed by cutting the edge of the open one side of the bottom surface 20M of the cavity 20 so as to be recessed in a stepped manner. extends to Specifically, the stepped surface 38 of the stepped portion 34 is cut by the side surface of the router, and the lower stepped surface 34M, which is lowered by one step by the stepped surface 38 at the stepped portion 34, is cut by the tip surface of the router. The lower surface 34M communicates with the first side surface 10M of the multilayer wiring board 10. As shown in FIG. In the example of the present embodiment, the lower surface 34M of the stepped portion 34 is positioned midway in the thickness direction of the insulating base 11K of the core substrate 11 .

In addition, in the example of this embodiment, the inner wall surface 40 of the cavity 20 is a machined surface formed by cutting. For example, this machined surface is formed by side machining of a router. The inner wall surface 40 of the cavity 20 is provided on three sides of the cavity 20 where the side opening 20K is not provided.

In addition, in the example of the present embodiment, a groove 30 is formed in the outer edge portion of the bottom surface 20M of the cavity 20. As shown in FIG. Groove 30 is a machined groove formed by the tip of the router. The groove 30 (more specifically, the inner surface of the groove 30 ) is formed continuously with the inner wall surface 40 of the cavity 20 . The inner surface of the groove 30 is composed of a groove bottom surface 30M, and a groove outer circumferential surface 30G and a groove inner circumferential surface 30N that face each other in the groove width direction of the groove 30 . The groove outer peripheral surface 30</b>G is arranged on the extension of the inner wall surface 40 of the cavity 20 and is continuous with the inner wall surface 40 . In the example of this embodiment, the grooves 30 are provided on three sides of the cavity 20 where the side openings 20K are not provided. The groove 30 communicates with the stepped portion 34 and surrounds the central portion of the bottom surface 20M of the cavity 20 together with the stepped portion 34 .

In the example of the present embodiment, the entire rectangular portion of the bottom surface 20M of the cavity 20 surrounded by the stepped portion 34 and the groove 30 serves as the component mounting pad 21 described above. Note that the pad 21 may be provided only in a portion of the portion surrounded by the stepped portion 34 and the groove 30 .

In the example of the present embodiment, the lower surface 34M of the stepped portion 34 and the groove bottom surface 30M of the groove 30 are arranged at the same depth from the first surface 11F of the core substrate 11 (see FIG. 1) and are continuous. there is The stepped portion 34 and the groove 30 are formed to a depth that penetrates the first conductive layer 13A of the core substrate 11 . In the example of the present embodiment, the lower surface 34 of the stepped portion 34 and the groove bottom surface 30M of the groove 30 are positioned midway in the thickness direction of the insulating base material 11K of the core substrate 11 . Therefore, the insulating substrate 11K is exposed on the lower surface 34M of the stepped portion 34 and the groove bottom surface 30M of the groove 30, and the conductive layer is not exposed.

As shown in FIG. 1, from the first conductive layer 13A of the core substrate 11, the second surface 10S, which is the other surface (the surface opposite to the first surface 10F) of the multilayer wiring board 10, is provided. is provided with a plurality of conductive layers. As shown in FIG. 3, among these multiple conductive layers, the conductive layer closest to the bottom surface 20M of the cavity 20, that is, the second conductive layer 13B of the core substrate 11 is the thickness of the multilayer wiring board 10. The stepped portion 34 is arranged away from the projected area in the vertical direction. Specifically, the second conductive layer 13B is further away from the first side surface 10M than the stepped surface 38 of the stepped portion 34, and the distance L1 between the second conductive layer 13B and the first side surface 10M is longer than the distance L2 between the stepped surface 38 of the stepped portion 34 and the first side surface 10M. For example, the second conductive layer 13B is preferably separated from the first side surface 10M by 300 μm or more than the stepped surface 38 of the stepped portion 34 (that is, the difference between the distance L1 and the distance L2 is 300 μm or more. preferably).

In the example of the present embodiment, all the conductive layers located closer to the second surface 10S of the multilayer wiring board 10 than the first conductive layer 13A (that is, the second conductive layer 13B and the conductive layer 16) are multilayer The stepped portion 34 is arranged apart from the projected area in the thickness direction of the wiring board 10 . Specifically, all of these conductive layers are farther from the first side surface 10M than the stepped surface 38 of the stepped portion 34 . That is, the shortest distance (distance L1 in this embodiment) among the distances between all these conductive layers and the first side surface 10M is the distance between the stepped surface 38 of the stepped portion 34 and the first side surface 10M. It is longer than L2. Therefore, the insulating layer (the insulating base material 11K in the example of the present embodiment) is exposed on the stepped surface 38 of the stepped portion 34, and the conductive layers such as the second conductive layer 13B are not exposed. Note that, for example, all the conductive layers located closer to the second surface 10S than the first conductive layer 13A are preferably separated from the first side surface 10M by 300 μm or more than the stepped surface 38 of the stepped portion 34. .

In the example of the present embodiment, the conductive layers (the second conductive layer 13B and the conductive layer 16) positioned closer to the second surface 10S than the first conductive layer 13A are It is arranged so as not to overlap with the groove 30 . These conductive layers are arranged with an interval X (for example, the interval X is preferably 300 μm or more) with respect to the region where the groove 30 is projected in the thickness direction of the multilayer wiring board 10 . Therefore, the insulating layer (insulating base material 11K in the example of the present embodiment) is exposed on the groove outer peripheral surface 30G and the groove inner peripheral surface 30N among the inner surfaces of the groove 30, and the conductive layer is not exposed. do not have.

The multilayer wiring board 10 of this embodiment is manufactured, for example, as follows.
(1) As shown in FIG. 4A, a copper-clad laminate 11Z is prepared in which copper foils 11C are laminated on both sides of an insulating substrate 11K. The insulating base material 11K contains, for example, epoxy resin or BT (bismaleimide triazine) resin and glass cloth.

(2) As shown in FIG. 4B, both surfaces of the copper clad laminate 11Z are irradiated with a laser to form through holes 14H.

(3) Electroless plating is performed to form an electroless plated film (not shown) on the copper foil 11C and the inner surface of the through hole 14H.

(4) As shown in FIG. 4C, a plating resist 50 having a predetermined pattern is formed on the electroless plating film on the front and back copper foils 11C. In addition, as will be described later, the plating resist 50 is a surface where the insulating base material 11 is cut, and the second conductive layer is formed from the planned cutting surface M on which the first side surface 10M of the multilayer wiring board 10 is formed. 13B are spaced apart by a first distance D1 or more.

(5) Electroplating is performed, and as shown in FIG. 4(D), the through-holes 14H are filled with the electroplating to form the through-hole conductors 14, and the electroless plating on the copper foil 11C is performed. An electrolytic plated film 13D is laminated on a portion of the film (not shown) exposed from the plating resist 50 .

(6) The plating resist 50 is removed, and the electroless plated film (not shown) below the plating resist 50 and the copper foil 11C are also removed. Then, as shown in FIG. 5(A), the remaining electrolytic plated film 13D, electroless plated film and copper foil 11C are applied to one surface and the other surface of the insulating substrate 11K, respectively. A first conductive layer 13A and a second conductive layer 13B are formed on the substrate. At this time, the second conductive layer 13B is formed at a position separated from the planned cutting plane M by the first distance D1. Through-hole conductors 14 connect the first conductive layer 13A and the second conductive layer 13B. Thus, the core substrate 11 is formed.

(7) As shown in FIG. 5B, a release layer 51 is laid on a portion of the first surface 11F of the core substrate 11 . The release layer 51 is made of, for example, a release film and has a rectangular shape. The peeling layer 51 is arranged such that the outer edge of one side of the peeling layer 51 is aligned with the cutting plane M described above. In addition, for example, the first conductive layer 13A of the core substrate 11 is formed so as to be arranged under the entire peeling layer 51 .

(8) As shown in FIG. 5C, the prepreg as the interlayer insulating layer 15 and the copper foil 52 are laminated on both sides of the core substrate 11, and then hot pressed. Then, interlayer insulating layers 15 are formed on both surfaces of core substrate 11 . During the hot press, the non-patterned portions of the conductive layers 13A and 13B on both the front and back surfaces of the core substrate 11 are filled with the resin of the prepreg. As the interlayer insulating layer 15, an insulating film for a buildup board may be used instead of the prepreg. In this case, an electroless plated film can be directly formed on the insulating film for the buildup board by the electroless plating treatment in (11) described below without laminating the copper foil 52 .

(9) As shown in FIG. 6A, the interlayer insulation layers 15 on both sides of the core substrate 11 are irradiated with a laser to form a plurality of via holes 15H penetrating the interlayer insulation layers 15 . For example, the plurality of via holes 15H are formed at positions shifted from the release layer 51 in the surface direction of the core substrate 11 (direction perpendicular to the thickness direction).

(10) An electroless plating process is performed to form electroless plating films (not shown) on the copper foils 52 laminated on the respective interlayer insulating layers 15 and on the inner surfaces of the via holes 15H.

(11) As shown in FIG. 6B, a plating resist 53 having a predetermined pattern is formed on the electroless plating film on the copper foil 52 laminated on each interlayer insulating layer 15 . The plating resist 53 is arranged so that the conductive layer 16 on the second surface 11S side of the core substrate 11 is formed apart from the planned cutting surface M by a first distance D1. Further, for example, the plating resist 53 is applied to the entire portion of the interlayer insulating layer 15 that is located directly above the peeling layer 51 so that the conductive layer 16 is not formed directly above the peeling layer 51 in (13) below. formed to cover the

(12) Electroplating is performed to fill the via holes 15H with the electroplating to form the via conductors 15D (see FIG. 7A). Next, the plating resist 53 is peeled off, and the electroless plated film and the copper foil 52 under the plating resist 53 are removed. Then, as shown in FIG. 7B, the electroplated film 16D, the electroless plated film and the copper foil 52 left on the interlayer insulating layer 15 form the conductive layer 16. Next, as shown in FIG. At this time, the conductive layer 16 on the second surface 11S side of the core substrate 11 is formed at a position separated from the planned cutting plane M by a first distance D1 or more (for example, 300 μm or more).

(13) Steps similar to (9) to (12) described above are repeated, and as shown in FIG. Layers are laminated one by one. Conductive layers 16 adjacent to each other in the stacking direction are connected by via conductors 15</b>D penetrating interlayer insulating layer 15 . Thereby, the first buildup portion 12A is formed on the first surface 11F of the core substrate 11, and the second buildup portion 12B is formed on the second surface 11S of the core substrate 11. FIG.

(14) As shown in FIG. 9, solder resist layers 17 are laminated on the outermost conductive layers 16 that are farthest from the core substrate 11 on both the front and back sides.

(15) As shown in FIG. 10, openings 17A are formed at predetermined locations of the solder resist layer 17 on both the front and back sides of the core substrate 11 by laser processing or photolithography, for example. Pads 18 are formed in portions of the outermost conductive layer 16 exposed from the solder resist layer 17 through the openings 17A.

(16) As shown in FIG. 11, from above the solder resist layer 17 on the first buildup portion 12A to a position passing through the peeling layer 51 and passing through the first conductive layer 13A (for example, core substrate 11 ), the router 60 rushes in. Then, the router 60 is run so as to draw a closed loop trajectory. Specifically, the router 60 is run along the outer edge of the release layer 51 in the shape of a square frame to form the annular recess 54 . One side of the annular concave portion 54 overlaps the cutting plane M described above. In other words, the router 60 is run so that the closed loop includes the outer edge portion of the multilayer wiring board 10 on the side of the first side surface 10M. Then, the one side portion of the annular recessed portion 54 is formed by cutting a range within a distance less than the first distance D1 from the plane to be cut M. As shown in FIG. In addition, the second conductive layer 13B and all the conductive layers 16 of the second buildup portion 12B are formed so as not to overlap the annular concave portion 54 when viewed from the thickness direction of the core substrate 11. It is arranged away from the annular recess 54 (for example, 300 μm or more away). In addition, the router 60 is arranged so that its rotation axis direction is the thickness direction of the core substrate 11 .

(17) Among the interlayer insulating layer 15, the conductive layer 16, the solder resist layer 17, and the peeling layer 51, the portions arranged inside the annular recess 54 are removed to form the cavity 20 (FIGS. 12 and 12). See Figure 13). Then, the portion of the conductive layer 13 on the first surface 11</b>F of the core substrate 11 that was disposed inside the annular recess 54 is exposed, and the exposed portion forms the pad 21 . A portion of the recess 54 that is deeper than the conductive layer 13 (pad 21 ) is left as an annular machined groove 30</b>A surrounding the pad 21 . Thus, the parent substrate 90 is obtained.

(18) Next, the mother board 90 is cut along the planned cutting plane M by the router 60 to form the multilayer wiring board 10 . As shown in FIGS. 12 and 13, the planned cutting surface M is set in the mother substrate 90 at an intermediate position in the groove width direction on one side of the machined groove 30A. When the mother substrate 90 is cut along the cutting plane M, the first side surface 10M of the multilayer wiring board 10 is formed from this cut surface (see FIGS. 1 and 2), and the cavity 20 is formed on the first side surface. A side opening 20K is formed that opens to 10M. In addition, the remaining portion of one side of the cut groove 30A cut by the router 60 is opened to the first side surface 10M of the multilayer wiring board 10 to form the stepped portion 34, and the rest of the cut groove 30A is formed. are left as the grooves 30 described above. At this time, the second conductive layer 13B is formed in a state further from the first side surface 10M than the stepped surface 38 of the stepped portion 34 . Note that the router for cutting the mother substrate 90 may be different from the router 60 for forming the inner wall surface 40 of the cavity 20 and the groove 30 in (16) above.

(19) The pad 21 is subjected to surface treatment such as Ni/Pd/Au plating and formation of an organic protective film (OSP). As described above, the multilayer wiring board 10 is completed.

The structure of the multilayer wiring board 10 of this embodiment and the method for manufacturing the same have been described above. Next, functions and effects of the multilayer wiring board 10 will be described. In the multilayer wiring board 10 of the present embodiment, the edge of the bottom surface 20M of the cavity 20 on the side of the side opening 20K has the stepped portion 34 formed by cutting. The router 60 for cutting is inserted to a position where it passes through the first conductive layer 13A exposed on the bottom surface 20M of 20. As shown in FIG. This makes it possible to prevent a portion of the first conductive layer 13A on the bottom surface 20M of the cavity 20 from remaining on the multilayer wiring board 10 as a metal burr. Further, in the multilayer wiring board 10, the second conductive layer 13B, which is positioned closer to the second surface 10S than the first metal layer 13A and closest to the bottom surface 20M of the cavity 20, is the side opening of the cavity 20. 20K is farther than the stepped surface 38 of the stepped portion 34 from the first side surface 10M where 20K is open. Therefore, even if the tip of the router 60 reaches the depth of the second conductive layer 13B due to variations in the penetration depth of the router 60 into the multilayer wiring board 10, the second conductive layer 13B is not cut by the router 60. Therefore, it is possible to prevent the second conductive layer 13B from remaining on the multilayer wiring board 10 as a metal burr. As a result, the occurrence of metal burrs can be suppressed in the multilayer wiring board 10 of the present embodiment. In addition, if the second conductive layer 13B is configured to be separated from the first side surface 10M by 300 μm or more from the stepped surface 38 of the stepped portion 34, the occurrence of metal burrs can be further suppressed.

In the multilayer wiring board 10 of the present embodiment, the insulating layer (insulating base material 11K) is exposed on the lower surface 34M of the stepped portion 34, and the conductive layer (second conductive layer 13B) is not exposed. Therefore, when the component mounting pads 21 on the bottom surface 20M of the cavity 20 are plated, the deposition of plating on the lower surface 34M of the stepped portion 34 can be suppressed. Also, since the conductive layer (second conductive layer 13B) is not exposed on the groove bottom surface 30M of the groove 30, plating is not deposited on the groove bottom surface 30M of the groove 30 when the pad 21 is plated. can be suppressed.

[Other embodiments]
(1) The cavity 20 may be provided at the corner of the quadrangular multilayer wiring board 10 . In this case, two sides of the cavity 20, which is rectangular in plan view, are open, and side openings 20K are formed in these two sides. Inner wall surfaces 40 are formed on the remaining two sides of the cavity 20 . Note that three sides of the cavity 20 may be open.

(2) In the above embodiment, the cavity 20 has a quadrangular shape in a plan view, but is not limited to this, and may have, for example, a polygonal shape other than a quadrilateral. Even in this case, a side opening 20K that opens the cavity 20 to the first side surface 10M of the multilayer wiring board 10 may be provided.

(3) In the above embodiment, the cutting of the parent substrate 90 for forming the multilayer wiring board 10 may be performed with a cutter instead of the router.

(4) In the above embodiment, the bottom surface 20M of the cavity 20 may not have the groove 30 .

(5) In the manufacturing method of the multilayer wiring board of the above-described embodiment, the router 60 penetrates to the core substrate 11, but the router 60 penetrates to the interlayer insulation layer 15 different from the core substrate 11, and the step portion A lower step surface 34M of 34 may be formed on the interlayer insulating layer 15 . Further, the core substrate 11 may not be arranged on the bottom surface 20M of the cavity 20, and the bottom surface 20M of the cavity 20 may be provided on the first buildup section 12A or the second buildup section 12B. may have been Also, the core substrate 11 may not be provided.

(6) In the above embodiment, all of the conductive layers (conductive layers 13B and 16) closer to the second surface 10S than the first conductive layer 13A are arranged at positions that do not overlap the lower surface 34M of the stepped portion 34. However, at least one of the conductive layers may overlap the lower surface 34M in the surface direction of the multilayer wiring board 10 (the direction perpendicular to the thickness direction).

(7) In the above embodiment, the pad 21 is provided on the entire bottom surface 20M of the cavity 20 except for the outer edge. good too.

(8) In the above embodiment, the four sides of the cavity 20 are formed by the router 60, but for example, only one side of the four sides of the cavity 20 that is open to the first side surface 10M is formed by the router. 60 and the remaining three sides of cavity 20 may be formed by laser machining. That is, at least one side of the annular recess 54 that is open to the first side surface 10M may be formed by the router 60, and the rest of the annular recess 54 may be formed by laser irradiation.

(9) In the above embodiment, the portion surrounded by the annular recess 54 is removed by peeling, but it may be removed by laser irradiation, for example.

(10) In the above embodiment, the multilayer wiring board 10 is formed by cutting the parent substrate 90. , the multilayer wiring board 10 may be formed in which the cavity 20 is open to the first side surface 10M.

Although specific examples of the technology included in the claims are disclosed in the specification and drawings, the technology described in the claims is not limited to these specific examples. Various modifications and changes of the examples are included, and a part of specific examples is also included.

REFERENCE SIGNS LIST 10 multilayer wiring board 10F first surface 10S second surface 13A first conductive layer 13B second conductive layer 20 cavity 20M bottom surface 20K side opening 21 pad 30 groove 34 step portion 34M lower step surface 38 step surface 60 router

Claims (10)

A part of the multilayer wiring board on the side of the first surface, which is one of the front and back surfaces, is removed from the first conductive layer positioned midway in the thickness direction of the multilayer wiring board, and an opening is formed in the first surface. and a multilayer wiring board having a cavity in which the first conductive layer is exposed on the bottom surface,
a side opening that opens the cavity to the first side surface of the multilayer wiring board;
a stepped portion formed by cutting an edge of the bottom surface of the cavity on the side of the side opening,
The conductive layer positioned closest to the bottom surface of the cavity among the conductive layers arranged on the second surface side, which is the other surface of the front and back surfaces of the multilayer wiring board, than the first conductive layer is the stepped portion. It is further away from the first side surface than the stepped surface of the portion. The multilayer wiring board according to claim 1,
Among the conductive layers arranged closer to the second surface than the first conductive layer, the conductive layer closest to the bottom surface of the cavity is closer to the first conductive layer than the stepped surface of the stepped portion. It is separated from the side by 300 μm or more. The multilayer wiring board according to claim 1 or 2,
All the conductive layers arranged closer to the second surface than the first conductive layer are further from the first side surface than the stepped surface of the stepped portion. The multilayer wiring board according to claim 3,
All of the conductive layers arranged closer to the second surface than the first conductive layer are separated from the first side surface by 300 μm or more from the stepped surface of the stepped portion. A multilayer wiring board according to any one of claims 1 to 4,
The lower surface of the stepped portion is located midway in the thickness direction of the insulating layer included in the multilayer wiring board. A multilayer wiring board according to any one of claims 1 to 5,
A machined groove is formed in the outer edge of the bottom surface of the cavity, surrounds the first conductive layer on the bottom surface of the cavity together with the stepped portion, and has a groove bottom surface continuous to the lower surface of the stepped portion. A multilayer wiring board according to any one of claims 1 to 6,
A portion of the first conductive layer exposed on the bottom surface of the cavity forms a component mounting pad. A multilayer wiring board according to any one of claims 1 to 7,
The cavity has a rectangular shape in a plan view, and has the side opening only on one side of the cavity. The router penetrates from the first surface, which is one of the front and back surfaces of the multilayer wiring board, to a position passing through the first conductive layer in the middle of the thickness direction of the multilayer wiring board, and the router draws a closed loop trajectory. After running, a portion closer to the first surface than the first conductive layer in the inner portion of the closed loop is removed to open to the first surface and expose the first conductive layer to the bottom surface and to the bottom surface. A method for manufacturing a multilayer wiring board, comprising forming a cavity having a cut groove in the edge of the multilayer wiring board,
A second conductive layer located closest to the first conductive layer among the conductive layers arranged on the second surface side, which is the other surface of the front and back, than the first conductive layer is a multi-layered structure. arranging at least a first distance from the first side surface of the wiring board;
A portion of the closed loop includes an outer edge of the multilayer wiring board on the side of the first side, and the outer edge is cut to a range within a distance less than the first distance from the first side. running a router to form, in the cavity, a side opening that opens the cavity to the first side; A method for manufacturing a multilayer wiring board according to claim 9,
All the conductive layers arranged closer to the second surface than the first conductive layer are arranged apart from the first side surface by the first distance.

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