JP2022160923A - multichannel clock generator - Google Patents

Abstract

To provide a clock generator capable of generating a plurality of clock signals phase-synchronized with high precision.SOLUTION: A clock generator 100 includes N PLL circuits 200. A phase comparison circuit 210 generates a control signal S1 according to a phase difference between a first clock CLKa input to a first terminal T1 and a second clock CLKb input to a second terminal T2. A loop filter 220 receives the control signal S1 and causes the control signal to pass through a predetermined frequency band. An oscillator 230 oscillates at a frequency corresponding to a control signal S2 that has passed through the loop filter 220. A frequency divider 240 frequency-divides the output clock of the oscillator 230, and outputs the frequency-divided clock signal CLKc from a third terminal T3. A common reference clock is input to the first terminals T1 of the N PLL circuits 200. The third terminal T3 of the i-th (1≤i≤N) PLL circuit 200_i is connected to the second terminal T2 of the (i+1)-th PLL circuit 200_(i+1).SELECTED DRAWING: Figure 2

Description

The present disclosure relates to clock generators.

Devices and devices that require high-speed clock signals of several hundred MHz to several GHz generally generate high-speed clock signals by frequency-multiplying low-speed clock signals using a PLL (Phase Locked Loop) circuit. be.

Japanese Patent Publication No. 2002-540669 Japanese Patent Application Laid-Open No. 2001-036404

It may be desirable to use multiple clock signals that are phase-synchronized with each other. FIG. 1 is a block diagram of a multi-channel clock generator 10R studied by the inventors. The clock generator 10R includes a plurality of N (N≧2) PLL circuits 20_1 to 20_N.

The PLL circuits 20_1 to 20_N receive a common reference clock CLKREF and output clock signals CLK1 to CLKN obtained by multiplying the reference clock CLKREF. PLL circuit 20 includes phase comparator 22 , loop filter 24 , VCO (voltage controlled oscillator) 26 and frequency divider 28 .

The inventor studied the clock generator 10R of FIG. 1 and came to recognize the following problems.

In the configuration of FIG. 1, errors and variations in circuit constants exist among the plurality of PLL circuits 20_1 to 20_N. Phase noise also occurs independently in the plurality of PLL circuits 20_1 to 20_N.

For these reasons, it is difficult for the clock generator 10R of FIG. 1 to synchronize the phases of the plurality of clock signals CLK1 to CLKN with high precision.

The present disclosure has been made in view of such circumstances, and one of the objects of certain aspects thereof is to provide a clock generator capable of generating a plurality of clock signals phase-synchronized with high precision.

A multi-channel clock generator according to one aspect of the present disclosure includes a plurality of N PLL (Phase Locked Loop) circuits. The PLL circuit outputs a control signal corresponding to a phase difference between a first terminal, a second terminal, a third terminal, a first clock input to the first terminal, and a second clock input to the second terminal. a phase comparison circuit that receives a control signal and passes a predetermined frequency band; an oscillator that oscillates at a frequency corresponding to the control signal that has passed through the loop filter; a frequency divider that outputs the clock signal after frequency from a third terminal. A common reference clock is input to the first terminals of the N PLL circuits, and the third terminal of the i-th (1≤i≤N) PLL circuit is connected to the second terminal of the (i+1)-th PLL circuit. Connected.

Arbitrary combinations of the above components, and methods, apparatuses, etc., in which the components and expressions are replaced with each other are also effective as embodiments of the present invention.

According to certain aspects of the present disclosure, multiple clock signals can be phase-synchronized with high accuracy.

1 is a block diagram of a multi-channel clock generator examined by the inventor; FIG. 1 is a block diagram of a clock generator according to an embodiment; FIG. 2 is a block diagram showing a configuration example of a PLL circuit; FIG. 10 is a block diagram of a clock generator according to Modification 1; FIG. FIG. 11 is a block diagram of a clock generator according to Modification 2; FIG. 11 is a block diagram of a clock generator according to Modification 3; FIG. 12 is a block diagram of a clock generator according to Modification 4; FIG. 12 is a block diagram of a clock generator according to Modification 5;

(Overview of embodiment)
SUMMARY OF THE INVENTION Several exemplary embodiments of the disclosure are summarized. This summary presents, in simplified form, some concepts of one or more embodiments, as a prelude to the more detailed description that is presented later, and for the purpose of a basic understanding of the embodiments. The size is not limited. For convenience, "one embodiment" may be used to refer to one embodiment (example or variation) or multiple embodiments (examples or variations) disclosed herein.

This summary is not an extensive overview of all possible embodiments, but is intended to neither identify key or key elements of all embodiments nor delineate the scope of some or all aspects. not. Its sole purpose is to present some concepts of one or more embodiments in a simplified form as a prelude to the more detailed description that is presented later.

(Overview of embodiment)
A multi-channel clock generator according to one embodiment includes a plurality of N PLL (Phase Locked Loop) circuits. The PLL circuit generates a first terminal, a second terminal, a third terminal, and a control signal corresponding to a phase difference between a first clock input to the first terminal and a second clock input to the second terminal. a loop filter that receives a control signal and passes a predetermined frequency band; an oscillator that oscillates at a frequency corresponding to the control signal that has passed through the loop filter; and a frequency divider that outputs a later clock signal from a third terminal. A common reference clock is input to the first terminals of the N PLL circuits, and the third terminal of the i-th (1≤i≤N) PLL circuit is connected to the second terminal of the (i+1)-th PLL circuit. Connected.

According to the above configuration, since the plurality of PLL circuits operate in phase synchronization, it is possible to generate a plurality of phase-synchronized high-speed clock signals. Note that the N-th and the 0-th are treated as equivalent, so the (N+1)-th can be read as the 1-th.

In one embodiment, at least one of the N PLL circuits may further include a first delay circuit provided between the output of the frequency divider and the third terminal. Thereby, the phase difference between the plurality of clock signals can be controlled according to the delay time of the first delay circuit.

In one embodiment, at least one of the N PLL circuits may further include a second delay circuit provided between the output of the oscillator and the input of the frequency divider. Thereby, the phase difference between the plurality of clock signals can be controlled according to the delay time of the second delay circuit.

In one embodiment, at least one of the N PLL circuits may further include a third delay circuit provided between the first terminal and the input of the phase comparator. Thereby, the phase difference between the plurality of clock signals can be controlled according to the delay time of the third delay circuit.

In one embodiment, at least one of the N PLL circuits may further include an offset circuit that is provided before or after the loop filter and superimposes an offset on the control signal. With this configuration, the settling time of the PLL circuit can be shortened.

In one embodiment, the division ratios of the dividers of the N PLL circuits may all be equal.

In one embodiment, the division ratios of the dividers of the N PLL circuits may be independently configurable.

(embodiment)
FIG. 2 is a block diagram of clock generator 100 according to an embodiment. A clock generator 100 receives a reference clock CLKREF and generates clock signals CLK1 to CLKN of N channels (N≧2).

The clock generator 100 includes a plurality of N PLL circuits 200_1-200_N. Each PLL circuit 200 includes a first terminal T1 to a third terminal T3, an output terminal OUT, a phase comparison circuit 210, a loop filter 220, an oscillator 230, and a frequency divider 240.

In each PLL circuit 200_i (1≤i≤N), the phase comparator circuit 210 detects the phase difference between the first clock CLKa input to the first terminal T1 and the second clock CLKb input to the second terminal T2. A control signal S1 is generated. Loop filter 220 filters the output signal of phase comparison circuit 210 . Oscillator 230 oscillates at a frequency corresponding to control signal S2 that has passed through loop filter 220 . The output signal of oscillator 230 is output from output terminal OUT as clock signal CLKi. The frequency divider 240 frequency-divides the clock signal CLK and outputs the frequency-divided clock signal CLKc from the third terminal T3.

A common reference clock CLKREF is input to the first terminals T1 of the N PLL circuits 200_1 to 200_N. Also, the third terminal T3 of the i-th (1≤i≤N) PLL circuit 200_i is connected to the second terminal T2 of the (i+1)-th PLL circuit 200_(i+1). Since the 0th and Nth circuits are treated as equivalent, the third terminal T3 of the Nth PLL circuit 200_N is connected to the second terminal T2 of the first PLL circuit 200_1.

FIG. 3 is a block diagram showing a configuration example of the PLL circuit 200. As shown in FIG. In one embodiment, PLL circuit 200 may comprise an analog PLL circuit. Phase comparator circuit 210 includes a phase frequency detector (Phase Frequency Detector) 212 and a charge pump circuit 214 . Loop filter 220 is an analog filter, and oscillator 230 is a VCO (Voltage Controlled Oscillator). The division ratio (M/N) of frequency divider 240 may be an integer (that is, N=1) or a fraction (N≧2). The frequency of the output CLKc of frequency divider 240 is N/M times the frequency of the output of oscillator 230 .

In one embodiment, PLL circuit 200 may be a digital PLL circuit. In the digital PLL circuit, the phase comparison circuit 210 and frequency divider 240 are composed of digital circuits.

In one embodiment, the PLL circuit 200 may be an AD (All Digital) PLL circuit. In the ADPLL circuit, all the components of the PLL circuit 200 are composed of digital circuits. Specifically, the phase comparison circuit 210 is composed of a TDC (time-to-digital converter) and a counter, the loop filter 220 is composed of a digital filter, and the oscillator 230 is composed of a DCO (Digital Controlled Oscillator).

That is, the configuration of the PLL circuit 200 does not matter whether it is analog or digital.

The above is the configuration of the clock generator 100 . Next, the operation will be explained.

In FIG. 2, it is assumed that the frequency division ratios M/N of frequency dividers 240 in the plurality of PLL circuits 200_1 to 200_N are equal. Also, the frequency of the reference clock CLKREF is assumed to be _fREF . In the clock generator 100, when all the PLL circuits 200 are phase-locked, the multiple clock signals CLK1 to CLKN have the same frequency and are stabilized at f _REF ×M/N.

Moreover, since the plurality of PLL circuits 200_1 to 200_N do not operate independently but form a loop, the phases of all the clock signals CLK1 to CLKN can be synchronized with high accuracy.

The embodiments are examples, and it should be noted that there are various modifications in the combination of each component and each processing process, and such modifications are included in the present disclosure and can constitute the scope of the present invention. It is understood by those skilled in the art. Such modifications will be described below.

FIG. 4 is a block diagram of a clock generator 100A according to Modification 1. As shown in FIG. In Modification 1, the frequency division ratios K (=M/N) of the multiple frequency dividers 240 are different. Others are the same as in FIG.

In Modification 1, if the frequency of the reference clock CLKREF is f _REF and the frequencies of the clock signals CLK1 to CLKN are f ₁ to f _N , the following relational expression holds.
f1* ₁ /K1=f2 _{* 1} /K2=f3* ₁ / _{K3 =} ...= _fN *1/ _KN = _fREF

Therefore, frequencies f ₁ to f _N of the plurality of clock signals CLK1 to CLKN are expressed as follows.
f ₁ =f _REF ×K ₁
f2 _{= fREF *} K2
…
f _N =f _REF ×K _N
Therefore, according to Modification 1, a plurality of clock signals CLK ₁ to CLK _N with different frequencies can be generated.

FIG. 5 is a block diagram of a clock generator 100B according to Modification 2. As shown in FIG. In this modification, the PLL circuit 200 comprises a first delay circuit 250 connected between the output of the frequency divider 240 and the third terminal T3. The division ratios K ₁ to K _N of frequency divider 240 may be equal or different.

According to Modification 2, the phases of the output clocks CLK1 to CLKN can be arbitrarily shifted according to the delay amounts φ ₁ to φ _N of the first delay circuit 250 for each channel.

FIG. 6 is a block diagram of a clock generator 100C according to Modification 3. As shown in FIG. In this variant, PLL circuit 200 comprises a second delay circuit 252 connected between the output of oscillator 230 and the input of frequency divider 240 .

According to Modification 3, the phases of the output clocks CLK1 to CLKN can be arbitrarily shifted according to the delay amounts φ ₁ to φ _N of the second delay circuit 252 for each channel.

FIG. 7 is a block diagram of a clock generator 100D according to Modification 4. As shown in FIG. In this modification, the PLL circuit 200 includes a third delay circuit 254 provided between the first terminal T1 and the phase comparator circuit 210 to delay the clock CLKa.

According to Modification 4, the phases of the output clocks CLK1 to CLKN can be arbitrarily shifted according to the delay amounts φ ₁ to φ _N of the third delay circuit 254 for each channel.

FIG. 8 is a block diagram of a clock generator 100E according to Modification 5. As shown in FIG. In this modification, the PLL circuit 200 includes an offset circuit 260 . The offset circuit 260 is provided before the loop filter 220 and superimposes the output signal of the phase comparison circuit 210 with the offset V _θ .

According to Modification 5, the settling time of the PLL circuit 200 can be shortened by optimizing the offset amount _Vθ . The first delay circuit 250 may be omitted, or a second delay circuit 252 or 254 may be provided instead.

Although all the PLL circuits 200 have the same configuration in the embodiment and modifications 1 to 5, the configurations of the PLL circuits 200 may be different.

Although the present invention has been described based on the embodiments, the embodiments merely show the principle and application of the present invention, and the embodiments deviate from the concept of the present invention defined in the scope of claims. Many variations and arrangement changes are possible within the scope of not doing so.

100 clock generator 200 PLL circuit T1 first terminal T2 second terminal T3 third terminal OUT output terminal 210 phase comparison circuit 220 loop filter 230 oscillator 240 frequency divider 250 first delay circuit 252 second delay circuit 254 third delay circuit

Claims (7)

Equipped with multiple N PLL (Phase Locked Loop) circuits,
The PLL circuit is
a first terminal;
a second terminal;
a third terminal;
a phase comparison circuit that generates a control signal corresponding to a phase difference between a first clock input to a first terminal and a second clock input to a second terminal;
a loop filter that receives the control signal and passes a predetermined frequency band;
an oscillator that oscillates at a frequency corresponding to the control signal that has passed through the loop filter;
a frequency divider that divides the output clock of the oscillator and outputs the frequency-divided clock signal from the third terminal;
including
A common reference clock is input to the first terminals of the N PLL circuits,
The multi-channel clock generator, wherein the third terminal of the i-th (1≤i≤N) PLL circuit is connected to the second terminal of the (i+1)-th PLL circuit. 2. The multi-channel clock generator of claim 1, wherein at least one of the N PLL circuits further includes a first delay circuit provided between the output of the frequency divider and the third terminal. . 3. The multi-channel clock according to claim 1, wherein at least one of the N PLL circuits further includes a second delay circuit provided between the output of the oscillator and the input of the frequency divider. generator. 4. The apparatus according to any one of claims 1 to 3, wherein at least one of said N PLL circuits further includes a third delay circuit provided between said first terminal and an input of said phase comparison circuit. Multi-channel clock generator. 5. The apparatus according to claim 1, wherein at least one of said N PLL circuits further includes an offset circuit which is provided before or after said loop filter and superimposes an offset on said control signal. multi-channel clock generator. 6. The multi-channel clock generator according to claim 1, wherein the division ratios of said frequency dividers of said N PLL circuits are all equal. 6. The multi-channel clock generator according to claim 1, wherein the division ratios of said frequency dividers of said N PLL circuits can be set independently.

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