WO2002027938A2

WO2002027938A2 - High resolution, low jitter frequency synthesizer

Info

Publication number: WO2002027938A2
Application number: PCT/US2001/024648
Authority: WO
Inventors: Sasan Cyrusian
Original assignee: Infineon Technologies North America Corp.
Priority date: 2000-09-28
Filing date: 2001-08-06
Publication date: 2002-04-04
Also published as: WO2002027938A3

Abstract

Systems and methods for synthesizing frequencies with high solution and low jitter are described. In one aspect, a frequency synthesizer (10)for producing a series of output signal pulses spaced-apart by a characteristic period is described. The frequency synthesizer includes a phase-locked looped (11)having a multiphase counter (20) configured to produce a feedback signal pulse shifted in time by a programmable fraction of the output signal period relative to a period corresponding to a programmable number of output signal pulses. In another aspect, a hase shifter is configured to provide an over sampling clock signal with a frequency greater than the frequency of the output signal. In another aspect, the frequency synthesizer includes a phase-locked loop with a charge pump (14)having a pull up current source, a pull down current source, and an equalization circuit programmable to substantially offset mismatch between the pull up current source and the pull down current source.

Description

HIGH RESOLUTION, LOW JITTER FREQUENCY SYNTHESIZER

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to U.S. Application Serial No. 09/675,998, filed on even date herewith, by Sasan Cyrusian, and entitled "Phase Detecting," which is incorporated herein by reference.

TECHNICAL FIELD

This invention relates to systems and methods for synthesizing frequencies with high frequency resolution and low jitter.

BACKGROUND

Frequency synthesizers are used in a wide variety of applications, including wireless communications (e.g., digital cellular communications) and magnetic read/write channels for disk drive applications. Frequency synthesis typically involves generating from a fixed- frequency reference signal a plurality of output signals over a wide range of frequencies. There are two main approaches to frequency synthesis, direct and indirect. In direct frequency synthesis, the fixed-frequency reference signal is processed (e.g., by a frequency divider or a frequency multiplier) to generate an output signal of a desired frequency. In indirect frequency synthesis, a tunable frequency source (e.g., a voltage controlled oscillator (VCO)), which is locked to the fixed-frequency reference signal, generates an output signal of a desired frequency. In a common indirect frequency synthesis approach, a phase-locked loop with a frequency divider in the feedback path tunes the VCO frequency (fvco) to a multiple of the reference frequency (fj -_F)- For example, in one system, divide-by-N logic divides the VCO output signal frequency (fvco) by N to produce a feedback signal with a frequency fvco/N. A phase detector tunes the VCO until the phase of the feedback signal matches the phase of the reference signal. By changing the value of N, the output signal produced by the VCO may be changed in frequency steps equal to the reference frequency (i.e., fvco ⁼ N-f_REF)- Thus, in this approach, in order to increase the frequency resolution of the synthesizer, the frequency of the reference signal must be decreased. However, the bandwidth of the phase-locked loop must decrease to accommodate a lower reference frequency, increasing the time needed to lock to a particular frequency and increasing the noise level (jitter) in the output signal. SUMMARY

The invention features improved systems and methods for synthesizing frequencies with high frequency resolution and low jitter.

In one aspect, the invention features a frequency synthesizer for producing a series of output signal pulses spaced-apart by a characteristic period. The inventive frequency synthesizer comprises a phase-locked loop having a multiphase counter configured to produce a feedback signal pulse shifted in time by a programmable fraction of the output signal period relative to a period corresponding to a programmable number of output signal pulses.

Embodiments may include one or more of the following features.

The phase-locked loop preferably comprises an output signal generator (e.g., a ring oscillator) configured to produce multiple phases of the output signal. The multiphase counter preferably comprises a phase selector coupled to the output signal generator and configured to output a selected phase of the output signal based upon a programmable input value. The phase selector may include a multiplexer coupled to receive the multiple phases produced by the output signal generator. The phase selector also may include a finite state machine coupled to the phase selector and having one state for each of the multiple phases of the output signal. The finite state machine preferably is configured to switch states in response to a pulse of the selected phase of the output signal received from the multiplexer.

The multiphase counter may further include a delay module (e.g., a frequency divider) coupled to the phase selector and configured to produce a feedback signal pulse after a programmable number of output signal pulses have been received from the phase selector. The multiphase counter also may include a controller coupled to the phase selector and configured to selectively enable and disable the phase selector. The controller preferably is configured to enable the phase selector upon receipt of a feedback signal pulse from the delay module, and to disable the phase selector after a programmable number of output signal pulses have been received from the phase selector.

In another aspect of the invention, a phase shifter is coupled to the output signal generator and is configured to provide an over sampling clock signal with a frequency greater than the frequency of the output signal.

In another aspect, the invention features a frequency synthesizer that includes a phase- locked loop with a charge pump having a pull up current source, a pull down current source, and an equalization circuit programmable to substantially offset mismatch between the pull up current source and the pull down current source. The equalization circuit preferably comprises a pull up offset cancellation current source and a pull down offset cancellation current source respectively coupled in parallel with the pull up current source and the pull down current source.

Among the advantages of the invention are the following.

The invention provides a power efficient low jitter frequency synthesizer with a high frequency resolution. The invention allows a higher reference frequency to be used for controlling the output frequency. This feature allows the size of the loop filter in the phase locked loop to be reduced and, consequently, reduces the time needed for the frequency synthesizer to lock to a particular output frequency. The invention also reduces jitter in the charge pump by substantially canceling mismatches between the pull up current source and the pull down current source.

Other features and advantages of the invention will become apparent from the following description, including the drawings and the claims.

DESCRIPTION OF DRAWINGS

FIG. 1 is a block diagram of a frequency synthesizer, including a multiphase VCO, a multiphase counter and a charge pump.

FIG. 2 is a block diagram of the multiphase NCO of FIG. 1.

FIG. 3 is a block diagram of the multiphase counter of FIG. 1.

FIG. 4A is a detailed block diagram of the multiphase counter of FIG. 3.

FIGS. 4B and 4C are state diagrams of two state machines operable in the multiphase counter of FIG. 4A.

FIG. 5 is a block diagram of the charge pump of FIG. 1.

FIG. 6 is a block diagram of the frequency synthesizer of FIG. 1 configured to supply a read clock and a write clock for a magnetic read/write channel.

DETAILED DESCRIPTION

Referring to FIG. 1, in one embodiment, a frequency synthesizer 10 includes a phase- locked loop 11 with a phase detector 12, a charge pump 14, a loop filter 16, a multiphase voltage-controlled oscillator (VCO) 18, and a multiphase counter 20. In operation, phase detector 12 generates frequency adjustment signals V_UP and V_DOWN in response to a detected phase difference between a fixed-frequency reference signal (having a frequency f_REF) and a feedback signal (having a frequency fFEEDB_ACi ), which is produced at the output of multiphase counter 20. The reference signal may be generated by any stable frequency source (e.g., a crystal oscillator). In response to frequency adjustment signal N_UP, charge pump 14 charges a capacitor in loop filter 16 with a current I_PUL_{L UP}- In response to frequency adjustment signal V_DOWΝ, charge pump 14 discharges the loop filter capacitor with a current

IpUL DOWΝ-

As explained in detail below, the resulting voltage (V_CTL) at the output of loop filter 16 controls the frequency (fouτ) of the output signal generated by multiphase NCO 18. Multiphase counter 20 feeds a down-converted version of the output signal back to the input of phase detector 12. In particular, based on the programmable integer parameters Ν and P, multiphase counter generates from the output signal a down-converted feedback signal with a frequency ^F_EEDBA_CK) given by the following equation:

fFEEDBACK = fθUT / (Ν - P/x) ( 1 )

where x is the number of phases of the output signal generated by multiphase VCO 18. By substituting f EF for fFEEDBACK and solving for fouτ, the output signal frequency (fouτ) may be expressed in terms of the reference frequency (fREF) as follows:

fouτ = f_REF - (Ν - P/x) (2)

Thus, by proper selection of parameters Ν and P, a wide variety of output signal frequencies may be generated with a resolution of fκ_E?A a resolution that is x times greater than a conventional divide-by-Ν phase-locked loop frequency synthesizer.

Referring to FIG. 2, in one embodiment, multiphase NCO 18 includes a ring oscillator 30 formed from a plurality of voltage-controlled differential delay cells 32, 34, 36, 38. Each delay cell 32-38 includes a differential input and two outputs (inverting and non-inverting). The delay through each cell 32-38 is substantially the same and is controlled by the control voltage (V_CTL) produced at loop filter 16. Since the overall delay through all of the cells 32- 38 determines the oscillation period of ring oscillator 30, control voltage V_CTL controls the frequency of the signal produced by multiphase VCO 18. By tapping the outputs of each of delay cells 32-38, multiple, equally spaced phases (f₀, fi, . . . , f ) of the output signal may be obtained. One of these phases is selected as the output signal of frequency synthesizer 10.

In other embodiments, multiphase VCO 18 may include any suitable oscillator or delay line that produces multiple phases of the output signal. For example, in one embodiment, multiphase VCO 18 may include a delay-locked loop. Furthermore, a different number of delay cells may be incorporated into ring oscillator 30 to increase or decrease the number of output signal phases generated by multiphase VCO 18.

Referring to FIG. 3, multiphase counter 20 includes a phase selector 40, a frequency divider 42, and a controller 44. Phase selector 40 is coupled to multiphase VCO 18 and is configured to output a selected phase of the output signal based upon a programmable value (P) that is applied to the input of controller 44, which applies a phase selection signal 46 to an input of phase selector 40. Frequency divider 42 divides the frequency of the selected phase by N to produce a feedback signal with a frequency ^_FEEDBACK), which is expressed in terms of the output signal frequency (four) in equation (1) above. Frequency divider 42 may be any type of counter or divider, such as a shift register, a binary counter, or another conventional counter.

Referring to FIGS. 4A, 4B and 4C, in one embodiment, phase selector 40 is implemented by a multiplexer 48 and a finite state machine 50 (FSM1). Multiplexer 48 has an input 52 for receiving each of the phases (f₀, fi, . . . , f ) of the output signal and a single output 54 for outputting a selected one of the output signal phases (f); the selected phase is determined by a phase select signal 55 generated by finite state machine 50. Finite state machine 50 has a state for each of output signal phases (FIG. 5B), with each state producing a respective phase select signal 55. In this embodiment, controller 44 is implemented as a finite state machine 56 (FSM 2) that has two states: an enable FSM 1 state that enables finite state machine 50 to switch states; and a disable FSM 1 state that disables the state switching of finite state machine 50 (FIG. 4C). Finite state machines 50, 56 and frequency divider 42 are clocked by the rising pulse edges of the selected phase produced at output 54 of multiplexer 48. In operation, frequency divider 42 outputs a feedback signal pulse after every N clock pulses of the multiplexer clocking signal. The feedback signal pulse is applied to a reset input of finite state machine 56. Upon receipt of the reset signal, finite state machine 56 switches from the disable FSM 1 state to the enable FSM 1 state. When enabled, finite state machine 50 switches from state-to-state on the rising edge of each multiplexer clock pulse, as shown in FIG. 5B. After P clock pulses have been received from the output of multiplexer 48, finite state machine 56 discontinues the FSM 1 enable control signal 46, fixing the phase produced at output 54 of multiplexer 48. The resulting period (T_FEEDBACK) between frequency divider pulses is given by:

TFEEDBACK ^{= •} TQUTPUT - (P/x) ^* TQUTPUT ⁼ TOUTPUT " (N - P/x) (3) where T_OUTPUT is the period of the output signal produced by multiphase VCO 18, and x is the number of phases of the output signal (e.g., here x has a value of eight). Equation (1) above may be obtained from equation (3) by substituting 1 -FEE_DBACK for T_FEEDBACK. substituting l -_OUTPUT for T_OUTPUT. and solving for fFEEDBACK- By reversing the direction of phase-switching, finite state machine 50 may operate to increase the delay through multiphase counter 20. That is, the following relationship between fouτ and fFEEDB_ACK may be established:

fFEEDBACK = fouT / (N + P/x) (4)

Thus, during each feedback signal period, multiphase counter 20 produces a feedback signal pulse shifted in time by a programmable fraction (P/x) of the output signal period relative to the Nth output signal pulse of that period.

Referring to FIG. 5, in one embodiment, charge pump 14 includes a pull up current source 60, a pull down current source 62, and an equalization circuit 64 that is configured to substantially offset mismatches between pull up current source 60 and pull down current source 62. In particular, equalization circuit 64 includes a pull up offset cancellation current source 66 and a pull down offset cancellation current source 68 respectively coupled in parallel with pull up current source 60 and pull down current source 62. Frequency synthesizer 10 may be calibrated by adjusting an offset control signal (V_OFFSET) - which is applied to the inputs of offset cancellation current sources 66, 68 - until the pull up current (I_PULL UP) substantially equals the pull down current (IPULL DOWN) (c-g-_> when the difference between I_{PULL UP} and I_{PULL DOWN} is within a selected tolerance value). This feature reduces jitter in the output signal generated by multiphase VCO 18 by substantially canceling layout and process related mismatches between up and down charges on loop filter 16.

Referring to FIG. 6, in one embodiment, frequency synthesizer 10 may include output stages 70, 72, which are configured to produce a sampling clock signal 74 (fj) and an over- sampling clock signal 76 (f ), respectively. Output stage 70 includes a frequency divider configured to divide the output signal frequency (fouτ) by (M+l) to produce a frequency fi :

fi = fouτ / (M+l) = f_REF ^• (N - P/x)/(M+l) (5)

In this embodiment, a wide range of frequencies (fi) may be synthesized while, at the same time, significantly reducing the dynamic range of the output signal. For example, in one embodiment, a frequency range of 100 MHz to 800 MHz may be synthesized from an output signals^' with a dynamic range of one octave. In particular, by adjusting the value of M between, 0, 1 and 3, the following frequency ranges may be synthesized:

M FREQUENCY RANGE

0 400-800 MHz 1 200-400 MHz

3 100-200 MHz

Output stage 72 includes a phase shifter 78 that is configured to increase the output frequency by a factor x/(x-l), and a frequency divider 80 that is configured to divide the output signal frequency (fouτ) by (M+l) to produce a frequency f₂:

f₂ = x/(x-l) ^■ [four / (M+l)] = x/(x-l) ^• [f_REF ^• (N - P/x)/(M+l)] (6)

Clock signals 74, 76 may be used in applications where a fixed relationship between fi and f is desired. For example, clock signals 74, 76 may be used to respectively clock a read channel and a write channel for magnetic hard drive applications. Other embodiments are within the scope of the claims.

Claims

WHAT IS CLAIMED IS:

1. A frequency synthesizer (10) for producing a series of output signal pulses spaced- apart by a characteristic period, comprising a phase-locked loop (11) having a multiphase counter (20) configured to produce a feedback signal pulse shifted in time by a programmable fraction of the output signal period relative to a period corresponding to a programmable number of output signal pulses.

2. The frequency synthesizer of claim 1 , wherein the phase-locked loop (11) comprises an output signal generator (18) configured to produce multiple phases of the output signal.

3. The frequency synthesizer of claim 2, wherein the output signal generator (18) comprises a ring oscillator (18).

4. The frequency synthesizer of claim 2, wherein the multiphase counter (20) comprises a phase selector (40) coupled to the output signal generator (18) and configured to output a selected phase of the output signal based upon a programmable input value.

5. The frequency synthesizer of claim 4, wherein the phase selector (40) comprises a multiplexer (48) coupled to receive the multiple phases produced by the output signal generator (18).

6. The frequency synthesizer of claim 4, wherein the phase selector (40) comprises a finite state machine (50) having one state for each of the multiple phases of the output signal.

7. The frequency synthesizer of claim 6, wherein the finite state machine (50) is configured to switch states in response to a pulse of the selected phase of the output signal received from the multiplexer (48).

8. The frequency synthesizer of claim 4, wherein the multiphase counter (20) comprises a delay module (42) coupled to the phase selector (40) and configured to produce a feedback signal pulse after a programmable number of output signal pulses have been received from the phase selector (40).

9. The frequency synthesizer of claim 8, wherein the delay module (42) comprises a frequency divider.

10. The frequency synthesizer of claim 8, wherein the multiphase counter (20) comprises a controller (44) coupled to the phase selector (40) and configured to selectively enable and disable the phase selector (40).

11. The frequency synthesizer of claim 10, wherein the controller (44) is configured to enable the phase selector (40) upon receipt of a feedback signal pulse from the delay module (42).

12. The frequency synthesizer of claim 10, wherein the controller (44) is configured to disable the phase selector (40) after a programmable number of output signal pulses have been received from the phase selector (40).

13. The frequency synthesizer of claim 2, further comprising a phase shifter (50) coupled to the output signal generator (18) and configured to provide an over sampling clock signal with a frequency greater than the frequency of the output signal.

14. The frequency synthesizer of claim 1, wherein the phase-locked loop (11) comprises a charge pump (14) having a pull up current source (60), a pull down current source (62), and an equalization circuit (64) programmable to substantially offset mismatch between the pull up current source (60) and the pull down current source (62).

15. The frequency synthesizer of claim 14, wherein the equalization circuit (64) comprises a pull up offset cancellation current source (66) and a pull down offset cancellation current source (68) respectively coupled in parallel with the pull up and pull down current sources (60, 62).

16. A frequency synthesizer, comprising a phase-locked loop (11) having a charge pump (14) having a pull up current source (60), a pull down current source (62), and an equalization circuit (64) programmable to substantially offset mismatch between the pull up current source (60) and the pull down current source (62).

17. The frequency synthesizer of claim 16, wherein the equalization circuit (64) comprises a pull up offset cancellation current source (66) and a pull down offset cancellation current source (68) respectively coupled in parallel with the pull up current source (60) and the pull down current source (62).

18. A frequency synthesis method for producing a series of output signal pulses spaced-apart by a characteristic period, comprising: generating the output signal pulses based upon a comparison of a reference signal and a feedback signal comprising a series of pulses; and producing a feedback signal pulse shifted in time by a programmable fraction of the output signal period relative to a period corresponding to a programmable number of output signal pulses.

19. The method of claim 18, further comprising producing multiple phases of the output signal.

20. The method of claim 19, further comprising outputting a selected phase of the output signal based upon a programmable input value.

21. The method of claim 20, further comprising producing a feedback signal pulse after a programmable number of output signal pulses have been received.

22. The method of claim 19, further comprising providing an over sampling clock signal with a frequency greater than the frequency of the output signal.

23. The method of claim 18, further comprising substantially offsetting mismatch between a pull up current source (60) and a pull down current source (62) in a charge pump (14).