JP2001036404A - PLL circuit - Google Patents

Abstract

[PROBLEMS] To provide a PLL circuit which suppresses jitter contained in an output signal of a PLL circuit in ASIC, reduces power consumption, reduces a cell area, and shortens a lock-up time. A phase comparison circuit detects a phase difference between a reference signal and a feedback signal based on an output signal of a voltage controlled oscillation circuit, and converts a phase difference detected by the phase comparison circuit into a voltage. And PLL circuits 12 and 13 having the voltage controlled oscillation circuits 3 and 9 for outputting the output signal based on the output voltage.
Is a PLL circuit 14 for inputting a feedback signal of the preceding-stage PLL circuit 12 to the reference signal of
The operation state and the non-operation state of the circuit 13 can be controlled based on a control signal for controlling operation / non-operation.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to an audio AS.
The present invention relates to a PLL circuit mainly applied to ICs and applied to ASICs of various consumer devices, and applied to products such as MD (mini disc) / video camera / digital still camera / DVD (digital vidio disc).

[0002]

2. Description of the Related Art Conventionally, a PLL (ph) used to synchronize a reproduction clock of a video system and a reproduction clock of an audio system has been used.
An ase locked loop circuit is disclosed in Japanese Patent Application Laid-Open No. 9-284126 and Japanese Utility Model Application Laid-Open No. 62-158937. FIG. 3 is a block diagram of a PLL circuit disclosed in Japanese Patent Application Laid-Open No. 9-284126, in which first and second stage PLL circuits are shown.
The circuits 26 and 27 are cascaded, and a programmable 25 is provided on the output side of the second-stage PLL circuit 27.

The first-stage PLL circuit 26 is roughly composed of a prescaler 15, a phase comparator 16, a charge pump 17, a voltage controlled oscillator 18, a frequency divider 19, and the like. The signal is input to the prescaler 15 as a feedback signal and also to the phase comparator 16.

That is, the first-stage PLL circuit 26
A signal obtained by dividing the reference input signal by the prescaler 15 and a feedback signal through the frequency divider 19 are input to the phase comparator 16. Then, the phase comparator 16 calculates
A phase difference is detected from the two input signals, and an error signal of a down pulse and an up pulse is input to the charge pump 17. The signal received by the charge pump 17 is input to a voltage controlled oscillator 18 (hereinafter, referred to as “VCO”). V
In C018, a frequency according to the output voltage from the charge pump 17 is output, and a plurality of cascaded frequency dividers 19 are output.
Divides the pulse oscillated by the VCO 18 into each frequency divider 19
And the phase comparator 1 as a feedback signal.
6 will be input.

[0005] The second-stage PLL circuit 27 has a first stage.
It has a circuit configuration similar to that of the first-stage PLL circuit 26, and the feedback signal from the first-stage VCO 18
After being divided by the prescaler 20 in the second stage, the P
It is configured to be input to the phase comparator 21 as a reference input signal of the LL circuit 27. In this circuit, the input signal frequencies to the phase comparators 16 and 21 and the VCO circuits 18 and 23
By reducing the ratio of the oscillation frequency from the input signal and dividing the input signal frequency into a plurality of PLL circuits so as to amplify the jitter contained in the input signal in one PLL circuit, I have.

FIG. 4 is a block diagram of an oscillator circuit disclosed in Japanese Utility Model Laid-Open Publication No. Sho 62-158937. The PLL circuit 49 shown in FIG. 4 performs a cascade connection using the first-stage PLL circuit 26 of FIG. 3 as a basic configuration circuit, and a low-pass circuit for converting a signal received by the charge pump into a signal for a VCO circuit. Filters 32, 38 and 43 (hereinafter referred to as "LPF") are added. Reference numerals 30, 36, 4
Reference numeral 1 denotes a phase comparator, reference numerals 31, 37, and 42 denote charge pumps, and reference numerals 33, 39, and 44 denote VCO circuits, respectively.

Further, the feedback signal of the same stage is not input to each phase comparator, but the most stable output signal with small jitter from the VCO 44 of the PLL circuit of the final stage is converted into the frequency divider 35, The signals divided by 40 and 45 are input to each circuit as a feedback signal to obtain an output signal with high stability and high accuracy.

[0008]

SUMMARY OF THE INVENTION Japanese Patent Application Laid-Open No. 9-28412
In the PLL circuit disclosed in Japanese Unexamined Patent Application Publication No. 6-114, when a stable signal is input with small jitter, amplification of the jitter is suppressed in this circuit, and a stable output signal can be obtained. However, when there is a large jitter in the input signal, there is a problem that there is no structure for removing the jitter and generating a stable output signal.

[0009] On the other hand, P.
In the LL circuit, since a plurality of PLL circuits are cascaded, even if a signal containing large jitter is input from the input terminal, the magnitude of the jitter is suppressed in each PLL circuit, and the output terminal in the final stage is output. It is possible to obtain an output signal without jitter. However, since a plurality of PLL circuits are always used regardless of the magnitude of the jitter included in the input signal, the ASIC (application specific I / O) is used.
When used in C), all the PLL circuits have to be operated, and there is a problem that power consumption increases and the cell area increases. Further, there is a problem that the lock-up time is longer than when a single-stage PLL circuit is used.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and it is intended to suppress jitter contained in an output signal of a PLL circuit in ASIC, reduce power consumption, reduce cell area, and reduce lock. An object of the present invention is to provide a PLL circuit that reduces the up time.

[0011]

The present invention has the following configuration to achieve the above object. According to a first aspect of the present invention, there is provided a phase comparison circuit for detecting a phase difference between a reference signal and a feedback signal based on an output signal of a voltage controlled oscillator, and converting the phase difference detected by the phase comparison circuit into a voltage. A plurality of PLL units each including a phase difference voltage conversion circuit that converts the voltage, and a voltage control oscillation circuit that outputs the output signal based on the output voltage from the phase difference voltage conversion circuit. The reference signal is a PLL circuit to which a feedback signal of the preceding PLL unit is input, and any or all of the PLL units in the second and subsequent stages are in an operating state and a non-operating state based on a control signal for controlling operation / non-operation. A PLL circuit characterized in that a state can be controlled.

According to a second feature of the present invention, the operation /
P that is operating based on a control signal that controls non-operation
The PLL circuit according to claim 1, further comprising a connection terminal that outputs an output signal of a selected PLL unit among output signals of the LL unit.

According to a third aspect of the present invention, the PLL
A connection terminal for outputting an output signal is provided for each unit, and a plurality of P
2. The PLL circuit according to claim 1, wherein an output signal of the LL unit can be output.

According to a fourth aspect of the present invention, the PLL
4. An external connection terminal for an external capacitor is provided on the input side of the voltage-controlled oscillator of the unit.
The PLL circuit according to any one of the above.

A fifth aspect of the present invention is the PLL circuit according to claim 4, wherein the connection terminal for the external capacitor is provided in a final stage PLL section.

According to a sixth aspect of the present invention, an external connection terminal for connecting an external low-pass filter is provided on the input side of the voltage-controlled oscillator of the last-stage PLL section. P described in any one of Items 1 to 3
LL circuit.

According to a seventh aspect of the present invention, the PLL
7. The PLL circuit according to any one of 1 to 6, wherein the circuit is configured by an ASIC.

According to a first aspect of the present invention, a PLL circuit has a plurality of PLL units, and a feedback signal of a preceding PLL unit is input to a reference signal of a PLL unit of a succeeding or subsequent stage, whereby a PLL of a preceding stage is input. By using the feedback signal with reduced jitter in the PLL section as a reference signal of the subsequent PLL section, it is possible to obtain an output signal with further reduced jitter by the subsequent PLL section. Then, any or all of the PLL units subsequent to the next stage set the optimum number of PLL units to an operation state to suppress the jitter, for example, according to the magnitude of the jitter included in the output signal input to the first stage PLL unit. In addition, since a PLL unit that does not need a subsequent stage is controlled to a non-operation state, it is possible to prevent unnecessary operation of a PLL unit for suppressing jitter included in an output signal, thereby preventing unnecessary increase in power consumption. In. Therefore, it is possible to suppress the jitter included in the output signal with optimal power consumption.

According to a second aspect of the present invention, a PLL which is in an operation state based on a control signal for controlling operation / non-operation is provided.
Since there are connection terminals for selectively outputting output signals among output signals of the unit, the number of connection terminals is small, so that the cell area can be reduced.

According to a third aspect of the present invention, a plurality of stages of P
Since the output signal of the LL section can be obtained, in one application system, when there are a plurality of output supply destinations of the PLL circuit, the high-speed
If the output signal of the LL section requires low jitter, the output signal of the downstream PLL section can be used for general purposes.

According to the fourth aspect of the present invention, the external connection terminal for the external capacitor is provided on the input side of the voltage-controlled oscillator of the PLL section, whereby the jitter contained in the output signal can be further suppressed. When it is desired to obtain a capacitor, it is possible to connect a capacitor to an external capacitor connection terminal.

According to a fifth aspect of the present invention, when an external connection terminal capable of connecting an external capacitor is provided on the input side of the voltage-controlled oscillator of the last-stage PLL unit, jitter cannot be suppressed. Also, by connecting an external capacitor, the jitter contained in the output signal can be suppressed.

According to a sixth aspect of the present invention, an external connection terminal for connecting an external low-pass filter is provided on the input side of the voltage-controlled oscillator of the last-stage PLL section,
Even when the jitter cannot be suppressed, the external low-pass filter can suppress the jitter included in the output signal.

According to the seventh aspect of the present invention, in addition to the above-described functions and effects, by configuring the PLL circuit with an ASIC, it is possible to provide a PLL circuit with low power consumption and a reduced cell area.

[0025]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic block diagram of a PLL circuit configured by an ASIC according to an embodiment of the present invention. As shown in FIG. 1, the ASIC according to the present embodiment
As an example of connecting a plurality of PLL circuits in cascade, a PLL circuit 12 and 13 each constituted by a macro cell are provided in series, and a PLL circuit 12 of the first stage is provided. The feedback signal from the divider 5 at the subsequent stage is input to the phase comparator 1 and is also input as the reference input signal to the phase comparator 6 of the second-stage PLL circuit 13.

The PLL circuit 12 is generally composed of a phase comparator 1, a charge pump 2, an LPF 3, a VCO 4, and four (1/2) frequency dividers 5a to 5d connected in series. The output signal of the device 5d is input to the phase comparator 1 as a feedback signal.

The phase comparator 1 comprises a reference input signal and a frequency divider 5
The phase comparator 1 detects a phase difference from the two input signals, and outputs an error signal of a down pulse and an up pulse to the charge pump 2.
To enter.

The charge pump 2 outputs an output signal corresponding to an up pulse or a down pulse to the LPF 3, and the output signal is applied to the VCO 4 as a control signal after the high frequency component is removed and smoothed by the LPF 3. .

The VC04 outputs a frequency according to the output voltage from the charge pump 2, and a plurality of cascade-connected frequency dividers 5a to 5d divide a pulse oscillated by the VCO 4 by each frequency divider. , As a feedback signal.

The second-stage PLL circuit 13 has a configuration similar to that of the PLL circuit 12, and includes a phase comparator 6, a charge pump 7, an LPF 8, a VCO 9, and four series-connected (1/2) frequency dividers. The devices 10a to 10d correspond to the phase comparator 1, the charge pump 2, the LPF 3, the VCO 4, and the four (1/2) frequency dividers 5a to 5d connected in series, respectively.

The second-stage (final-stage) PLL circuit 13 has an input terminal to which a capacitor component 11, for example, a capacitor can be added externally to the ASIC between the LPF 8 and the VCO 9 (the input side of the VCO 9). T1 is provided, and one end is connected to the input terminal T1 and the other end is grounded. The externally provided capacitor component 11 is provided on the input side of the VCO 9 to achieve the same effect as a low-pass filter, thereby enabling appropriate suppression of jitter. .

The mounting position of the externally mounted capacitor component 11 may be provided in the PLL circuit 12.
4 includes three or more stages of cascade-connected PLL circuits, it may be provided in any of the PLL circuits.
From the viewpoint of reducing the cell area by using the number of L circuits, it is efficient to provide the circuit in the last-stage PLL circuit.

Further, a PLL circuit 14 composed of two stages of PLL circuits 12 and 13 has control connection terminals LPMODE1 and LPMODE1 so that each of the PLL circuits 12 and 13 can independently control the operation / non-operation state. It has two terminals. The control connection terminal LPMODE1 is connected to the phase comparator 1 and the VCO 4 of the PLL circuit 12, and the control connection terminal LPMODE2 is connected to the phase comparator 6 and the VCO of the PLL circuit 13.
For example, by controlling ON / OFF of each starting voltage based on an operation / non-operation control signal from the control unit CON, each of the PLL circuits 12 and 13 is independently controlled to operate / non-operate. Is possible. Note that the first stage P
The control connection terminal LPMODE1 is also provided in the LL circuit 12 so that operation / non-operation can be controlled. When a PLL circuit configured in an ASIC is assumed, all PLL circuits may be stopped depending on an application. Is taken into consideration, and may not be provided. Also, V
The purpose of controlling the input voltage of the CO is to eliminate power consumption due to oscillation.

The control unit CON for outputting an operation / non-operation control signal for selectively controlling the operation / non-operation of the PLL circuits 12 and 13 is not limited to the case where it is provided outside the PLL circuit 14. 14 may be provided.

The second and third (1) of the PLL circuit 12
/ 2) The frequency dividers 5b and 5c are provided with output terminals Tf1 and Tf2 so that signals of different frequencies can be output. Similarly, the second and third (1/1 /
2) Output terminals Tf3 and Tf4 are also provided to the frequency dividers 10b and 10c.
To enable signal output at different frequencies. With the above configuration, in one application system, P
If there are a plurality of LL circuit output destinations, connect to the oscillation output terminals Tf1 and Tf2 of the PLL circuit 12 for those requiring high-speed lockup, and connect the oscillation output terminals of the PLL circuit 13 for those requiring low jitter. By connecting to terminals Tf3 and Tf4, general-purpose use becomes possible.

It should be noted that the output terminals Tf1,
Tf2 and the oscillation output terminals Tf3 and Tf on the PLL circuit 13 side.
A selector circuit (not shown) may be provided before f4 so that only an output signal from any of the PLL circuits can be output. For example, the selector circuit is controlled based on an operation / non-operation control signal from a control connection terminal LPMODE2 that controls the operation / non-operation of the PLL circuits 12 and 13. Thus, according to the effect of reducing the number of terminals and the state of the reference input signal and the output signal in one application system, for example, when the jitter included in the output signal is large, the oscillation output terminal of the PLL circuit 13 on the subsequent stage side is connected to the oscillation output terminal. When the connection is made and the lock time is reduced, it can be used to switch to the output terminal on the PLL circuit 12 side. The frequency dividers 5a to 5d and 10a to 10d provided with output terminals are not limited.

In this embodiment having the above configuration, first, when the feedback signal to the reference input signal is an input signal with small jitter and requires a fast lock-up time, the PLL circuit 13 of the second stage is used. Is stopped, and only the first-stage PLL circuit 12 is operated. Thus, the power consumption of the PLL circuit 13 is eliminated, and the jitter is reduced in a short time in the first-stage PLL circuit 12, so that the oscillation frequency can be output from the output terminals Tf1 and / or Tf2.

When the feedback signal includes jitter with respect to the reference input signal and does not require a fast lock-up time, the first-stage PLL circuit 12 and the second-stage PLL circuit 13 are simultaneously operated. A jitter is more reliably reduced by adopting a configuration for operation and further providing an external capacitor 11 to remove high-frequency components.

This will be described in more detail below. PLL having connection terminal of external capacitor 11 as described above
When the circuit 13 is configured to be cascade-connected to the PLL circuit 12, the feedback signal with small jitter is generated by the first-stage PL signal.
When input to the input terminal of the phase comparator 1 of the L circuit 12, only the first-stage PLL circuit 12 is operated, and output signals of a plurality of oscillation frequencies f1 and f2 are generated from the frequency dividers 5b and 5c. I do. At this time, the second-stage PLL circuit 13
The operation is stopped by an operation / non-operation control signal from the LPMODE2 terminal. As a result, it is possible to output a stable signal with low power consumption, fast lock-up time, and no jitter.

When a signal feedback signal having a large jitter is input to the input terminal of the phase comparator 1, that is, the jitter cannot be completely suppressed by the first-stage PLL circuit 12, and each of the first-stage PLL circuits 12 If the output signal generated from the frequency divider 5d contains jitter, the operation / non-operation control signal input to the control connection terminal LPMODE2 is repeated to operate the second-stage PLL circuit 13. , Second
The configuration is such that output signals are generated from the output terminals of the frequency dividers 10a to 10d in the stage. This is because a signal in which the jitter of the input signal is fed back to the feedback signal of the first-stage PLL circuit 12, so that the signal with reduced jitter is further referenced to the second-stage PLL circuit 13. By inputting as an input signal, the second-stage PLL circuit 13
The output signals from the frequency dividers 10b and 10c are obtained by further suppressing the jitter that could not be suppressed by the first-stage PLL circuit 12.

A feedback signal containing a jitter larger than that described above is input from the input terminal of the phase comparator 1, and the frequency dividers 10b and 10c of the second-stage PLL circuit 13
If the output signal generated from contains jitter,
By externally connecting the capacitor component 11 to the input terminal T1 and grounding one end, the same effect as that of the low-pass filter can be obtained, and the jitter can be further suppressed. Thus, large jitter can be suppressed more accurately by making the capacitor component 11 externally attachable to the PLL circuit 13 composed of macro cells. In this case, the capacitor value and the like need to be changed according to the system used.

As described above, these PLL circuits have independent control connection terminals LPMODE, and control the operation of the PLL circuits according to the magnitude of the jitter contained in the output signal from each PLL circuit. Unused PL
Since the L circuit is controlled to be in the operation stop state, the low power consumption P
It becomes possible to configure an LL circuit.

The VCO 9 of the second-stage PLL circuit 13
Is provided with an input terminal T1 that enables connection of the external capacitor component 11 to the input portion of the PLL circuit 13.
And the external capacitor component 11, it is possible to obtain a stable output signal with suppressed jitter regardless of the magnitude of the jitter included in the input signal of the phase comparator 6.

Also, each independent control connection terminal LPMO
PLL circuits 12 and 13 having DE1 and LPMODE2
Are considered as one macro cell, one system can be created by using a plurality of similar macro cells, and only necessary macro cells can be operated. The effect of shortening the development period is also obtained.

Further, the stable output signal obtained by the present invention is converted to an audio DAC (digital to analogue) such as an MD.
converter), it is possible to suppress deterioration of sound quality due to jitter.

Although the preferred embodiment of the present invention has been described in the above embodiment, it is needless to say that the present invention is not limited to this. For example, in the above embodiment, an output signal including larger jitter is input from the input terminal of the phase comparator 1 and the frequency dividers 10b and 10c of the second-stage PLL circuit 13
The input terminal T1 provided with the external capacitor component 11 to obtain the effect of the low-pass filter with a simple configuration has been described as a means for coping with the case where the output signal generated from the device includes jitter. Of course, the low-pass filter LPF1
The same effect can be obtained even if 1b itself can be externally attached. However, in this case, as shown in FIG.
It is necessary to separate the LPF 8 and the VCO 9 of the PLL circuit 13 of the stage, and to provide connection terminals T2 and T3 for connecting the output side of the LPF 8 and the input side of the VCO 9. In this case, the low-pass filter LP to the connection terminals T2 and T3
To attach F11b, the connection terminals T2 and T3 are connected via a resistor R, and a capacitor C whose other end is grounded is provided between the resistor R and the connection terminal T3. In this case, both the value of the capacitor C and the value of the resistor R need to be changed according to the system used.

[0047]

As described above, according to the first aspect of the present invention, the PLL circuit has a plurality of PLL units, and the feedback signal of the preceding PLL unit is input to the reference signal of the next and subsequent PLL units. By doing so, it is possible to obtain an output signal in which the jitter is further suppressed by the PLL unit in the subsequent stage from the feedback signal in which the jitter is reduced in the previous stage PLL unit. Then, any or all of the PLL units in the next and subsequent stages are controlled so that the optimal number of PLL units for suppressing the jitter are operated, and the other unnecessary PLL units are controlled to the non-operation state. By operating a PLL unit that is unnecessary to suppress jitter contained in a signal, unnecessary power consumption is prevented. Therefore, it was possible to suppress the jitter contained in the output signal with optimal power consumption.

According to the second aspect of the present invention, the cell area can be reduced with a small number of connection terminals.
According to the gist, when there are a plurality of output supply destinations of the PLL circuit, a high-speed lock-up
As for the output signal of the L section, for those requiring low jitter, the output signal of the downstream PLL section can be used for general purpose use.

Further, according to the fourth aspect of the present invention, the effect of suppressing the jitter contained in the output signal can be obtained, and as in the fifth and sixth aspects, the input side of the voltage controlled oscillator of the final stage PLL unit can be provided. By providing an external connection terminal that can connect an external capacitor or an external low-pass filter to
Even when the jitter cannot be suppressed, the jitter included in the output signal can be reliably suppressed by connecting the external capacitor.

Further, according to the seventh aspect of the present invention, in addition to the above-mentioned functions and effects, by configuring the PLL circuit with an ASIC, it is possible to provide a PLL circuit with low power consumption and a reduced cell area.

[Brief description of the drawings]

FIG. 1 is a block diagram of a PLL circuit according to an embodiment of the present invention.

FIG. 2 is a block diagram of an external low-pass filter according to another embodiment of the present invention.

FIG. 3 is a block diagram of a conventional PLL circuit.

FIG. 4 is a block diagram of a conventional oscillation circuit.

[Explanation of symbols]

 1,6 Phase comparator 2,7 Charge pump 3,8 Low-pass filter (LPF) 4,9 Voltage-controlled oscillator (VCO) 5a-5d, 10a-10d Divider 11 External capacitor 11b External low-pass filter 12 First Second-stage PLL circuit 13 Second-stage PLL circuit 14 PLL circuit T1 to T3 Connection terminal LPMODE2 Control connection terminal CON control unit

Claims (7)

[Claims] 1. A phase comparator for detecting a phase difference between a reference signal and a feedback signal based on an output signal of a voltage controlled oscillator, and a phase difference voltage converter for converting the phase difference detected by the phase comparator into a voltage. A plurality of PLL units each including a circuit and the voltage controlled oscillation circuit that outputs the output signal based on an output voltage from the phase difference voltage conversion circuit.
The reference signal of the PLL unit after the first stage is a PLL circuit to which the feedback signal of the previous stage PLL unit is input. Any or all of the PLL units after the second stage are based on a control signal for controlling operation / non-operation. Wherein the operating state and the non-operating state are controllable. 2. A connection terminal for outputting an output signal of a selected PLL unit among output signals of a PLL unit in an operation state based on a control signal for controlling the operation / non-operation. The PLL circuit according to claim 1. 3. The PLL circuit according to claim 1, wherein a connection terminal for outputting an output signal is provided for each of the PLL units, so that output signals of a plurality of stages of PLL units can be output. 4. The PLL according to claim 1, wherein an external connection terminal for an external capacitor is provided on an input side of the voltage controlled oscillator of the PLL unit.
circuit. 5. The PLL circuit according to claim 4, wherein the external connection terminal for the external capacitor is provided in a final stage PLL unit. 6. An external connection terminal to which an external low-pass filter can be connected is provided on the input side of the voltage-controlled oscillator of the last-stage PLL section. 3. The PLL circuit according to 1. 7. The P-type power supply according to claim 1, wherein said PLL circuit is constituted by an ASIC.
LL circuit.