JP2022146601A - Silicon carbide semiconductor device, and method of manufacturing the same - Google Patents

Abstract

To provide a silicon carbide semiconductor device and a method of manufacturing the same capable of suppressing generation of cracks in a Ni plating film.SOLUTION: A silicon carbide semiconductor device has: an electrode formed on a first principal surface of a silicon carbide substrate; a Ni plating film formed on the electrode, containing P; a Pd plating film formed on the Ni plating film; and a Au plating film formed on the Pd plating film. A first P concentration at a first interface with the electrode, of the Ni plating film is higher than a second P concentration at a second interface with the Pd plating film, of the Ni plating film.SELECTED DRAWING: Figure 13

Description

The present disclosure relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device.

In a silicon carbide semiconductor device, a nickel (Ni) plating film, a palladium (Pd) plating film, and a gold (Au) plating film are sequentially formed on electrodes.

JP 2017-128791 A

In a conventional silicon carbide semiconductor device, cracks may occur in the Ni plating film. In particular, cracks are likely to occur in the Ni plating film when unevenness with a large height difference is formed on the upper surface of the electrode.

An object of the present disclosure is to provide a silicon carbide semiconductor device and a method for manufacturing the silicon carbide semiconductor device that can suppress the occurrence of cracks in the Ni plating film.

A silicon carbide semiconductor device of the present disclosure includes an electrode formed on a first main surface of a silicon carbide substrate, a Ni plating film formed on the electrode and containing P, and a Ni plating film formed on the Ni plating film. and an Au-plated film formed on the Pd-plated film, wherein the first P concentration at the first interface between the Ni-plated film and the electrode is equal to the above-mentioned It is higher than the second P concentration at the second interface with the Pd plating film.

According to the present disclosure, it is possible to suppress the occurrence of cracks in the Ni plating film.

FIG. 1 is a cross-sectional view showing a silicon carbide semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view (part) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 3 is a cross-sectional view (part) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 4 is a cross-sectional view (part) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 5 is a cross-sectional view (part) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 6 is a cross-sectional view (part) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 7 is a cross-sectional view (part) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 8 is a cross-sectional view (part) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 9 is a cross-sectional view (part) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 10 is a cross-sectional view (part) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 11 is a cross-sectional view (part) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 12 is a cross-sectional view showing a first example of a method of forming a Ni plating film. FIG. 13 is a cross-sectional view showing a second example of the method of forming the Ni plating film.

The form for carrying out is demonstrated below.

[Description of Embodiments of the Present Disclosure]
First, the embodiments of the present disclosure are listed and described. In the following description, the same or corresponding elements are given the same reference numerals and the same descriptions thereof are not repeated. In the crystallographic descriptions in this specification, individual orientations are indicated by [ ], aggregated orientations by <>, individual planes by ( ), and aggregated planes by { }. In addition, the fact that the crystallographic index is negative is usually expressed by attaching a "-" (bar) above the number, but in this specification, a negative sign is attached before the number. there is

[1] A silicon carbide semiconductor device according to an aspect of the present disclosure includes: an electrode formed on a first main surface of a silicon carbide substrate; a Ni plating film formed on the electrode and containing P; A Pd-plated film formed on a Ni-plated film and an Au-plated film formed on the Pd-plated film, wherein a first P concentration at a first interface between the Ni-plated film and the electrode is , higher than the second P concentration at the second interface between the Ni plating film and the Pd plating film.

Since the first P concentration is higher than the second P concentration, the portion of the Ni plating film on the electrode side provides good coverage, and the portion on the Pd plating film side provides good adhesion to the Pd plating film. . Therefore, excellent flatness is obtained for the Ni plating film, and excellent flatness is also obtained for the Pd plating film. Therefore, it is possible to suppress the permeation of the plating solution used for forming the Au plating film through the Pd plating film and suppress the occurrence of cracks in the Ni plating film.

[2] In [1], the first P concentration may be 12% by mass or more, and the second P concentration may be 4% by mass or less. When the first P concentration is 12% by mass or more, particularly good coverage is obtained, and when the second P concentration is 4% by mass or less, particularly good adhesion to the Pd plating film is obtained.

[3] In [1] or [2], an insulating film formed on the silicon carbide substrate and having a contact hole formed therein is provided, and the electrode is formed on the insulating film through the contact hole. The electrode may be connected to the silicon carbide substrate through the electrode, and the upper surface of the electrode may have unevenness with a height difference of 0.8 μm or more and 1.5 μm. Even if there is an unevenness with a height difference of 0.8 μm or more and 1.5 μm, the Ni plating film has good coverage, so cracking can be suppressed.

[4] In [1] to [3], the first point farthest from the first main surface among the points constituting the first interface and the first point passing through and perpendicular to the first main surface A third P concentration at a central point located at a center of an intersection of the virtual straight line and the second interface may be lower than the first P concentration and higher than the second P concentration. In this case, rapid changes in the P concentration in the Ni plating film can be suppressed.

[5] In [4], the third P concentration may be higher than 4% by mass and lower than 12% by mass. In this case, it is easy to suppress a rapid change in the P concentration in the Ni plating film.

[6] In [4] or [5], the average grain size between the first point and the center point may be smaller than the average grain size between the intersection point and the center point. . Depending on the P concentration of the plating solution used to form the Ni plating film, the average grain size between the first point and the center point may be smaller than the average grain size between the intersection point and the center point.

[7] In [1] to [6], the electrode may contain Al or Cu. In this case, it is easy to reduce the resistance of the electrode.

[8] A method for manufacturing a silicon carbide semiconductor device according to another aspect of the present disclosure includes forming an electrode on a first main surface of a silicon carbide substrate; forming a film, forming a Pd plating film on the Ni plating film, and forming an Au plating film on the Pd plating film, wherein the Ni plating film is formed. The steps include forming a first Ni-plated film using a first plating solution having a first P concentration, and using a second plating solution having a second P concentration lower than the first P concentration on the first Ni-plated film. and forming a second Ni plating film.

By forming the first Ni plating film using the first plating solution, good coverage can be obtained. Further, by forming the second Ni plating film using the second plating solution, it is easy to form the Pd plating film with good adhesion on the Ni plating film. Therefore, it is possible to suppress the permeation of the plating solution used for forming the Au plating film through the Pd plating film and suppress the occurrence of cracks in the Ni plating film.

[9] In [8], the first P concentration may be 12% by mass or more, and the second P concentration may be 4% by mass or less. When the first P concentration is 12% by mass or more, particularly good coverage is obtained, and when the second P concentration is 4% by mass or less, particularly good adhesion to the Pd plating film is obtained.

[10] In [8] or [9], between the step of forming the first Ni-plated film and the step of forming the second Ni-plated film, on the first Ni-plated film, forming a third Ni-plated film using a third plating solution having a third P concentration that is low and higher than the second P concentration, wherein the second Ni-plated film is formed on the third Ni-plated film; good too. In this case, rapid changes in the P concentration in the Ni plating film can be suppressed.

[11] In [10], the third P concentration may be higher than 4% by mass and lower than 12% by mass. In this case, it is easy to suppress a rapid change in the P concentration in the Ni plating film.

[12] In [10] or [11], the thickness of the first Ni plating film is 1.5 μm or more and 2.5 μm or less, and the thickness of the second Ni plating film is 1.0 μm or more and 2.0 μm or less. and the third Ni plating film may have a thickness of 1.0 μm or more and 2.0 μm or less. In this case, it is particularly easy to suppress the occurrence of cracks in the Ni plating film.

[Details of the embodiment of the present disclosure]
Embodiments of the present disclosure will be described in detail below, but the present disclosure is not limited thereto. FIG. 1 is a cross-sectional view showing a silicon carbide semiconductor device according to an embodiment.

As shown in FIG. 1 , silicon carbide semiconductor device 100 according to the embodiment includes silicon carbide substrate 10 , gate insulating film 81 , gate electrode 82 , interlayer insulating film 83 , source electrode 60 and drain electrode 70 . It mainly has

Silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 overlying silicon carbide single crystal substrate 50 . Silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to first main surface 1 . Silicon carbide epitaxial layer 40 forms first main surface 1 , and silicon carbide single-crystal substrate 50 forms second main surface 2 . Silicon carbide single crystal substrate 50 and silicon carbide epitaxial layer 40 are made of hexagonal silicon carbide of polytype 4H, for example. Silicon carbide single-crystal substrate 50 has n-type conductivity, including n-type impurities such as nitrogen (N). A semiconductor element is formed on silicon carbide substrate 10 .

The first main surface 1 is a {0001} plane or a plane in which the {0001} plane is inclined in the off direction by an off angle of 8° or less. Preferably, the first main surface 1 is the (000-1) plane or a plane in which the (000-1) plane is inclined in the off direction by an off angle of 8° or less. The off direction may be, for example, the <11-20> direction or the <1-100> direction. The off angle may be, for example, 1° or more, or may be 2° or more. The off angle may be 6° or less, or may be 4° or less.

In the present embodiment, a field effect transistor is formed on silicon carbide substrate 10 as an example of a semiconductor element. Silicon carbide epitaxial layer 40 mainly has drift region 11 , body region 12 , source region 13 and contact region 18 .

The drift region 11 has an n-type by being doped with an n-type impurity such as nitrogen or phosphorus (P). The doping of the n-type impurity to the drift region 11 is preferably performed by doping the impurity during the epitaxial growth of the drift region 11, not by ion implantation.

Body region 12 is provided on drift region 11 . Body region 12 has a p-type by being doped with a p-type impurity such as aluminum (Al).

Source region 13 is provided on body region 12 so as to be separated from drift region 11 by body region 12 . The source region 13 has an n-type by being doped with an n-type impurity such as nitrogen or phosphorus. Source region 13 constitutes first main surface 1 .

The contact region 18 has a p-type by being doped with a p-type impurity such as aluminum. Contact region 18 constitutes first main surface 1 . Contact region 18 penetrates source region 13 and contacts body region 12 .

A plurality of gate trenches 5 are provided in the first main surface 1 . The gate trenches 5 extend, for example, in a first direction parallel to the first main surface 1, and a plurality of gate trenches 5 are arranged in a line in the second direction. Gate trench 5 has a bottom surface 4 consisting of a drift region 11 . Gate trench 5 has a side surface 3 extending through source region 13 and body region 12 to bottom surface 4 . The bottom surface 4 is, for example, a plane parallel to the second main surface 2 . The angle of the side surface 3 with respect to the plane including the bottom surface 4 is, for example, 50° or more and 65° or less. This angle may be, for example, 55° or more. This angle may be, for example, 60° or less. Side 3 preferably has a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent mobility. The angle of the side surface 3 with respect to the plane containing the bottom surface 4 may be 90°.

A gate insulating film 81 is provided in contact with the side surface 3 and the bottom surface 4 . The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is made of a material containing silicon dioxide, for example. Gate insulating film 81 is in contact with drift region 11 at bottom surface 4 . Gate insulating film 81 is in contact with each of source region 13 , body region 12 and drift region 11 at side surface 3 . Gate insulating film 81 may be in contact with source region 13 on first main surface 1 .

A gate electrode 82 is provided on the gate insulating film 81 . The gate electrode 82 is made of, for example, polysilicon (poly-Si) containing conductive impurities. Gate electrode 82 is arranged inside gate trench 5 .

An interlayer insulating film 83 is provided in contact with the gate electrode 82 and the gate insulating film 81 . The interlayer insulating film 83 is made of a material containing silicon dioxide, for example. Contact holes 90 are formed in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals in the second direction. The contact holes 90 are provided such that the gate trenches 5 are positioned between the contact holes 90 adjacent in the second direction. Contact hole 90 extends in the first direction. Source region 13 and contact region 18 are exposed from interlayer insulating film 83 and gate insulating film 81 through contact hole 90 . For example, the depth of the contact hole 90 is 0.8 μm or more and 1.5 μm or less, and may be 1.0 μm or more and 1.3 μm or less. Further, for example, the diameter of the contact hole 90 is 2.0 μm or more and 5.0 μm or less, and may be 2.5 μm or more and 4.5 μm or less.

A source electrode 60 is provided in contact with the first main surface 1 . Source electrode 60 has contact electrode 61 provided in contact hole 90 and source wiring 62 . Contact electrode 61 is in contact with source region 13 and contact region 18 on first main surface 1 . The contact electrode 61 is made of a material containing nickel silicide (NiSi), for example. Contact electrode 61 may be made of a material containing titanium (Ti), aluminum, and silicon. The contact electrode 61 is in ohmic contact with the source region 13 and contact region 18 . That is, source electrode 60 is connected to silicon carbide substrate 10 through contact hole 90 . The source wiring 62 is made of a material containing aluminum or copper (Cu), for example. Source wiring 62 may be made of a material containing aluminum and copper. Source electrode 60 is electrically insulated from gate electrode 82 by interlayer insulating film 83 . Source electrode 60 may include a barrier metal film such as a titanium nitride (TiN) film between source wire 62 and interlayer insulating film 83 . Source electrode 60 is an example of an electrode.

The upper surface of the source electrode 60 is formed with unevenness reflecting the contact hole 90 . The height difference D1 of the unevenness is approximately the same as the depth of the contact hole 90, and is, for example, 0.8 μm or more and 1.5 μm or less. The unevenness may have a height difference of 1.0 μm or more and 1.3 μm or less. The height difference D1 referred to here is the difference in distance from the first main surface 1 between the concave portion and the convex portion that are adjacent to each other in a cross-sectional view.

A nickel (Ni) plating film 63 containing phosphorus is formed on the source electrode 60 , a palladium (Pd) plating film 64 is formed on the Ni plating film 63 , and a gold (Au) plating film is formed on the Pd plating film 64 . A plated film 65 is formed. The thickness of the Ni plating film 63 is preferably 3.0 μm or more and 7.0 μm or less, more preferably 4.0 μm or more and 6.0 μm or less. The thickness of the Pd plating film 64 is preferably 20 nm or more and 40 nm or less, more preferably 25 nm or more and 35 nm or less. The thickness of the Au plating film 65 is preferably 30 nm or more and 70 nm or less, more preferably 40 nm or more and 60 nm or less. Each thickness of the Ni plating film 63, the Pd plating film 64, and the Au plating film 65 is the thickness of the thickest portion of each film. For example, in the Ni plated film 63 , it is the thickness of the portion of the upper surface of the source electrode 60 that enters the recess.

Ni plated film 63 has a first surface 63A in contact with source electrode 60 and a second surface 63B in contact with Pd plated film 64 . The first P concentration on the first surface 63A is higher than the second P concentration on the second surface 63B. For example, the first P concentration is preferably 12% by mass or more, more preferably 13% by mass or more, and may be 15% by mass or less. Also, the second P concentration is preferably 4% by mass or less, more preferably 3% by mass or less, and may be 2% by mass or more. The P concentration can be measured, for example, by energy dispersive X-ray spectroscopy (EDX). The first surface 63A is an example of a first interface, and the second surface 63B is an example of a second interface.

Further, a first point 91 farthest from the first main surface 1 among the points forming the first surface 63A, an imaginary straight line L1 passing through the first point 91 and perpendicular to the first main surface 1, and the second surface 63B may be lower than the first P concentration and higher than the second P concentration. For example, the P concentration of the Ni plating film 63 at the first point 91 is the first concentration, and the P concentration of the Ni plating film 63 at the intersection point 92 is the second concentration.

Drain electrode 70 is in contact with second main surface 2 . Drain electrode 70 is in contact with silicon carbide single-crystal substrate 50 at second main surface 2 . Drain electrode 70 is electrically connected to drift region 11 . The drain electrode 70 is made of a material containing nickel silicide, for example. Drain electrode 70 may be made of a material containing titanium, aluminum, and silicon. Drain electrode 70 is in ohmic contact with silicon carbide single crystal substrate 50 .

The acceptor concentration and the donor concentration in each impurity region can be determined, for example, by measurement using a scanning capacitance microscope (SCM) or secondary ion mass spectrometry (SIMS). can be measured.

Next, a method for manufacturing silicon carbide semiconductor device 100 according to the embodiment will be described. 2 to 11 are cross-sectional views showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment.

First, as shown in FIG. 2, silicon carbide single crystal substrate 50 is prepared. Next, silicon carbide epitaxial layer 40 is formed on silicon carbide single crystal substrate 50 . For example, silicon carbide single crystal substrate 50 contains an n-type impurity such as nitrogen and has n-type. For example, the silicon carbide epitaxial layer 40 can be formed by epitaxial growth doped with an n-type impurity such as nitrogen. Thus, silicon carbide substrate 10 having first main surface 1 and second main surface 2 is obtained.

Next, as shown in FIG. 3, ion implantation into silicon carbide epitaxial layer 40 is performed. Body region 12, source region 13 and contact region 18 are formed, for example, by ion implantation. The remainder of silicon carbide epitaxial layer 40 functions as drift region 11 . In the ion implantation for forming the body region 12 or the contact region 18, ions of a p-type impurity such as aluminum are implanted. In the ion implantation for forming the source region 13, an n-type impurity such as phosphorus is ion-implanted.

Next, as shown in FIG. 4, a plurality of gate trenches 5 are formed in the source region 13, the body region 12 and the drift region 11. As shown in FIG. The gate trench 5 can be formed as follows.

First, a mask (not shown) having openings over regions where gate trenches 5 are to be formed is formed. Next, using a mask, a portion of the source region 13, a portion of the body region 12, and a portion of the drift region 11 are removed by etching. The etching is, for example, reactive ion etching (RIE). By etching, in the region where the gate trench 5 is to be formed, a side portion substantially perpendicular to the first main surface 1 and a bottom portion provided continuously with the side portion and substantially parallel to the first main surface 1 are formed. is formed.

Thermal etching is then performed in the recess. Thermal etching can be performed in a state in which a mask is formed on first main surface 1, for example, by heating in an atmosphere containing reactive gas having at least one type of halogen atom. The at least one halogen atom includes at least one of chlorine (Cl) and fluorine (F) atoms. The atmosphere includes, for example, chlorine (Cl ₂ ), boron trichloride (BCl ₃ ), sulfur hexafluoride (SF ₆ ) or carbon tetrafluoride (CF ₄ ). For example, a mixed gas of chlorine gas and oxygen (O ₂ ) gas is used as a reaction gas, and thermal etching is performed at a heat treatment temperature of 800° C. or higher and 900° C. or lower. Note that the reaction gas may contain a carrier gas in addition to the chlorine gas and the oxygen gas described above. As the carrier gas, for example, nitrogen (N ₂ ) gas, argon (Ar) gas, helium (He) gas, or the like can be used.

A gate trench 5 is formed in the first main surface 1 by the thermal etching. The gate trench 5 has a bottom surface 4 formed of the drift region 11 and side surfaces 3 extending through the source region 13 and the body region 12 and continuing to the bottom surface 4 . After thermal etching, the mask is removed from first main surface 1 .

Next, as shown in FIG. 5, a gate insulating film 81 is formed. For example, by thermally oxidizing silicon carbide substrate 10, gate insulating film 81 in contact with source region 13, body region 12, drift region 11 and contact region 18 is formed. Specifically, silicon carbide substrate 10 is heated, for example, at a temperature of 1300° C. or more and 1400° C. or less in an atmosphere containing oxygen. As a result, gate insulating film 81 in contact with first main surface 1, side surface 3 and bottom surface 4 is formed. When gate insulating film 81 is formed by thermal oxidation, strictly speaking, part of silicon carbide substrate 10 is taken into gate insulating film 81 . Therefore, in the subsequent processing, it is assumed that first main surface 1, side surface 3 and bottom surface 4 have slightly moved to the interface between gate insulating film 81 and silicon carbide substrate 10 after thermal oxidation.

Next, heat treatment (NO annealing) may be performed on silicon carbide substrate 10 in a nitrogen monoxide (NO) gas atmosphere. In the NO annealing, silicon carbide substrate 10 is held under conditions of, for example, 1100° C. or more and 1400° C. or less for about one hour. Thereby, nitrogen atoms are introduced into the interface region between gate insulating film 81 and body region 12 . As a result, the channel mobility can be improved by suppressing the formation of interface states in the interface region.

Next, as shown in FIG. 6, a gate electrode 82 is formed. A gate electrode 82 is formed on the gate insulating film 81 . The gate electrode 82 is formed by, for example, a low pressure CVD (low pressure-chemical vapor deposition: LP-CVD) method. Gate electrode 82 is formed to face each of source region 13 , body region 12 and drift region 11 .

Next, as shown in FIG. 7, an interlayer insulating film 83 is formed. Specifically, interlayer insulating film 83 is formed to cover gate electrode 82 and to be in contact with gate insulating film 81 . The interlayer insulating film 83 is formed by, for example, the CVD method. The interlayer insulating film 83 is made of a material containing silicon dioxide, for example. A portion of interlayer insulating film 83 may be formed inside gate trench 5 .

Next, as shown in FIG. 8, the interlayer insulating film 83 and the gate insulating film 81 are etched to form contact holes 90 in the interlayer insulating film 83 and the gate insulating film 81 . As a result, the source region 13 and contact region 18 are exposed from the interlayer insulating film 83 and gate insulating film 81 . Next, a metal film (not shown) for contact electrode 61 in contact with source region 13 and contact region 18 is formed on first main surface 1 . A metal film for the contact electrode 61 is formed by, for example, a sputtering method. The metal film for the contact electrode 61 is made of a material containing nickel, for example. Next, alloying annealing is performed. The metal film for the contact electrode 61 is held at a temperature of, for example, 900° C. or higher and 1100° C. or lower for about 5 minutes. Thereby, at least part of the metal film for contact electrode 61 reacts with silicon contained in silicon carbide substrate 10 to be silicided. As a result, the contact electrode 61 that makes ohmic contact with the source region 13 and the contact region 18 is formed. Contact electrode 61 may be made of a material containing titanium, aluminum, and silicon.

Next, as shown in FIG. 9, source wiring 62 is formed. Specifically, the source wiring 62 covering the contact electrode 61 and the interlayer insulating film 83 is formed. The upper surface of the source line 62 is formed with unevenness reflecting the contact hole 90 . The source wiring 62 is formed by sputtering, for example. The source wiring 62 is made of a material containing aluminum or copper, for example. Source wiring 62 may be made of a material containing aluminum and copper. Thus, the source electrode 60 having the contact electrode 61 and the source wiring 62 is formed.

Next, as shown in FIG. 10, a Ni plating film 63 containing phosphorus (P) is formed on the source electrode 60 . The Ni plating film 63 can be formed, for example, by electroless plating. Here, a method for forming the Ni plating film 63 will be described in detail. FIG. 12 is a cross-sectional view showing a first example of a method of forming the Ni plating film 63. As shown in FIG. FIG. 13 is a cross-sectional view showing a second example of the method of forming the Ni plating film 63. As shown in FIG.

In the first example, as shown in FIG. 12, a first plating solution having a first P concentration is used to form a first Ni plating film 101, and then a first Ni plating solution having a concentration lower than the first P is formed on the first Ni plating film 101. A second Ni plating film 102 is formed using a second plating solution having a second P concentration. Preferably, the first Ni plated film 101 is formed with a thickness such that the entire top surface of the first Ni plated film 101 is above the top surface of the source electrode 60 .

The first P concentration is preferably 12% by mass or more, more preferably 13% by mass or more. By using the first plating solution having such a first P concentration, the first Ni plating film 101 with excellent coverage can be formed. That is, the first Ni plated film 101 is embedded in the concave portion existing on the surface of the source electrode 60, and excellent flatness is obtained on the upper surface of the first Ni plated film 101. Next, as shown in FIG. The first P concentration may be 15% by mass or less.

The second P concentration is preferably 4% by mass or less, more preferably 3% by mass or less. By using the second plating solution having such a second P concentration, it is easy to replace Ni with Pd, and it is easy to form the Pd plating film 64 with good adhesion on the Ni plating film 63 . The second P concentration may be 2% by mass or more.

In the second example, as shown in FIG. 13, after forming the first Ni plating film 101 and before forming the second Ni plating film 102, a third plating solution having a third P concentration is applied onto the first Ni plating film 101. is used to form the third Ni plating film 103 . Then, a second Ni plating film 102 is formed on the third Ni plating film 103 . The third P concentration is lower than the first P concentration and higher than the second P concentration. Preferably, the first Ni plated film 101 is formed with a thickness such that the entire top surface of the first Ni plated film 101 is above the top surface of the source electrode 60 . By forming the third Ni-plated film 103, it is possible to suppress a rapid change in the P concentration in the Ni-plated film 63. FIG.

Also in the second example, the first P concentration is preferably 12% by mass or more, more preferably 13% by mass or more, and may be 15% by mass or less. Also, the second P concentration is preferably 4% by mass or less, more preferably 3% by mass or less, and may be 2% by mass or more.

The tertiary P concentration is preferably higher than 4 wt% and lower than 12 wt%, more preferably higher than 6 wt% and lower than 10 wt%. By using the third plating solution having such a 3P concentration, excellent adhesion is ensured between the first Ni plating film 101 and the second Ni plating film 102, and peeling within the Ni plating film 63 is suppressed. Cheap.

After forming the Ni plating film 63, a Pd plating film 64 is formed on the Ni plating film 63, and an Au plating film 65 is formed on the Pd plating film 64, as shown in FIG. The Pd plating film 64 and the Au plating film 65 can be formed, for example, by electroless plating. Further, drain electrode 70 is formed in contact with silicon carbide single crystal substrate 50 on second main surface 2 .

Thus, silicon carbide semiconductor device 100 including a field effect transistor can be manufactured.

In silicon carbide semiconductor device 100 according to the embodiment, Ni plating film 63 includes a portion corresponding to first Ni plating film 101 . Excellent flatness is obtained on the top surface. Therefore, the upper surface of the Pd plating film 64 also has excellent flatness.

When the Au plating film 65 is formed, the plating solution may pass through the Pd plating film 64 and reach the Ni plating film 63 . In particular, when the upper surface of the Pd plating film 64 has unevenness, the plating solution easily reaches the Ni plating film 63 through the concave portions of the Pd plating film 64 . When the plating solution for the Au plating film 65 reaches the Ni plating film 63, the Ni plating film 63 is cracked. On the other hand, in the present embodiment, excellent flatness is obtained on the top surface of the Ni plating film 63 and excellent flatness is also obtained on the top surface of the Pd plating film 64 . Therefore, it is possible to suppress the permeation of the plating solution used for forming the Au plating film 65 through the Pd plating film 64 and suppress the occurrence of cracks in the Ni plating film 63 .

For example, even if the upper surface of the source electrode 60 has unevenness with a height difference D1 of 0.8 μm or more and 1.5 μm or less, the Ni plating film 63 has good coverage, so cracks can be suppressed.

When the Ni plating film 63 is formed according to the first example, the thickness of the first Ni plating film 101 is preferably 1.5 μm or more and 3.5 μm or less, depending on the depth and diameter of the contact hole 90 . , more preferably 1.7 μm or more and 3.3 μm or less. The thickness of the second Ni plating film 102 is preferably 1.0 μm or more and 3.0 μm or less, more preferably 1.2 μm or more and 2.8 μm or less. In this case, it is particularly easy to suppress the occurrence of cracks in the Ni plating film 63 .

When the Ni plating film 63 is formed according to the second example, the thickness of the first Ni plating film 101 is preferably 1.5 μm or more and 2.5 μm or less, depending on the depth and diameter of the contact hole 90. , more preferably 1.7 μm or more and 2.3 μm or less. The thickness of the third Ni plating film 103 is preferably 1.0 μm or more and 2.0 μm or less, more preferably 1.2 μm or more and 1.8 μm or less. The thickness of the second Ni plating film 102 is preferably 1.0 μm or more and 2.0 μm or less, more preferably 1.2 μm or more and 1.8 μm or less. In this case, it is particularly easy to suppress the occurrence of cracks in the Ni plating film 63 .

In the Ni plating film 63, in the first example, the boundary between the first Ni plating film 101 and the second Ni plating film 102 may not be clear. Similarly, in the second example, the boundary between the first Ni plating film 101 and the third Ni plating film 103 may not be clear, and the boundary between the third Ni plating film 103 and the second Ni plating film 102 may not be clear. good.

Further, when forming the Ni plating film 63, the P concentration of the plating solution may be continuously decreased from the initial stage of film formation to the latter stage of film formation. For example, in the early stage of film formation, the P concentration is preferably 12% by mass or more, more preferably 13% by mass or more, and in the late stage of film formation, the P concentration is preferably 4% by mass or less, more preferably 3% by mass. % or less.

In silicon carbide semiconductor device 100 manufactured in this manner, the first P concentration at first surface 63A is higher than the second P concentration at second surface 63B. For example, the first P concentration is preferably 12% by mass or more, more preferably 13% by mass or more, and may be 15% by mass or less. The second P concentration is preferably 4% by mass or less, more preferably 3% by mass or less, and may be 2% by mass or more. In this case, the Ni plated film 63 has a particularly good coverage and a particularly good adhesion to the Pd plated film 64 .

Also, the third P density at the center point 93 positioned between the first point 91 and the intersection point 92 may be lower than the first P density and higher than the second P density. In this case, rapid changes in the P concentration in the Ni plating film 63 are suppressed. In particular, when the third P concentration is higher than 4% by mass and lower than 12% by mass, it is easy to suppress rapid changes in the P concentration in the Ni plating film 63 .

The average grain size between first point 91 and center point 93 may be smaller than the average grain size between intersection point 92 and center point 93 . Between the first point 91 and the center point 93 when the first plating solution and the second plating solution are used, and when the first plating solution, the second plating solution and the third plating solution are used. may be smaller than the average grain size between the intersection point 92 and the center point 93 .

Source electrode 60 preferably contains aluminum or copper. This is because the resistance of the source electrode 60 can be easily reduced. Source electrode 60 may contain aluminum and copper. Source electrode 60 may further contain silicon.

Although the embodiment has been described in detail above, it is not limited to a specific embodiment, and various modifications and changes are possible within the scope described in the claims.

1 first main surface 2 second main surface 3 side surface 4 bottom surface 5 gate trench 10 silicon carbide substrate 11 drift region 12 body region 13 source region 18 contact region 40 silicon carbide epitaxial layer 50 silicon carbide single crystal substrate 60 source electrode 61 contact electrode 62 source wiring 63 Ni plating film 63A first surface 63B second surface 64 Pd plating film 65 Au plating film 70 drain electrode 81 gate insulating film 82 gate electrode 83 interlayer insulating film 90 contact hole 91 first point 92 intersection point 93 central point 100 Silicon carbide semiconductor device 101 first Ni plating film 102 second Ni plating film 103 third Ni plating film L1 imaginary straight line

Claims (12)

an electrode formed on the first main surface of the silicon carbide substrate;
a Ni plating film formed on the electrode and containing P;
a Pd plating film formed on the Ni plating film;
an Au plating film formed on the Pd plating film;
has
A silicon carbide semiconductor device in which a first P concentration at a first interface of the Ni plating film with the electrode is higher than a second P concentration at a second interface of the Ni plating film with the Pd plating film. The first P concentration is 12% by mass or more,
The silicon carbide semiconductor device according to claim 1, wherein said second P concentration is 4% by mass or less. an insulating film formed on the silicon carbide substrate and having a contact hole formed thereon;
the electrode is formed on the insulating film and connected to the silicon carbide substrate through the contact hole;
3. The silicon carbide semiconductor device according to claim 1, wherein an upper surface of said electrode has unevenness with a height difference of 0.8 μm or more and 1.5 μm. a first point farthest from the first main surface among points forming the first interface, and an intersection point between the second interface and a virtual straight line passing through the first point and perpendicular to the first main surface 4 . The silicon carbide semiconductor device according to claim 1 , wherein a third P concentration at a center point located at the center of the silicon carbide semiconductor device is lower than the first P concentration and higher than the second P concentration. The silicon carbide semiconductor device according to claim 4, wherein said third P concentration is higher than 4% by mass and lower than 12% by mass. 6. The silicon carbide semiconductor device according to claim 4, wherein an average crystal grain size between said first point and said center point is smaller than an average crystal grain size between said intersection and said center point. The silicon carbide semiconductor device according to any one of claims 1 to 6, wherein said electrode contains Al or Cu. forming an electrode on the first main surface of the silicon carbide substrate;
forming a Ni plating film containing P on the electrode;
forming a Pd plating film on the Ni plating film;
forming an Au plating film on the Pd plating film;
has
The step of forming the Ni plating film includes
forming a first Ni plating film using a first plating solution having a first P concentration;
forming a second Ni-plated film on the first Ni-plated film using a second plating solution having a second P concentration lower than the first P concentration;
A method for manufacturing a silicon carbide semiconductor device having The first P concentration is 12% by mass or more,
9. The method of manufacturing a silicon carbide semiconductor device according to claim 8, wherein said second P concentration is 4% by mass or less. Between the step of forming the first Ni plating film and the step of forming the second Ni plating, a third P concentration lower than the first P concentration and higher than the second P concentration is formed on the first Ni plating film. forming a third Ni plating film using a third plating solution with a concentration of
10. The method of manufacturing a silicon carbide semiconductor device according to claim 8, wherein said second Ni plating film is formed on said third Ni plating film. 11. The method of manufacturing a silicon carbide semiconductor device according to claim 10, wherein said third P concentration is higher than 4% by mass and lower than 12% by mass. The first Ni plating film has a thickness of 1.5 μm or more and 2.5 μm or less,
The second Ni plating film has a thickness of 1.0 μm or more and 2.0 μm or less,
12. The method of manufacturing a silicon carbide semiconductor device according to claim 10, wherein said third Ni plating film has a thickness of 1.0 [mu]m or more and 2.0 [mu]m or less.

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