JP2019057629A - Silicon carbide semiconductor device - Google Patents

Abstract

To provide a silicon carbide semiconductor device capable of mitigating concentration of an electric field at a bottom of a gate insulation film while reducing on-resistance.SOLUTION: A fourth impurity region includes an overhanging part extending closer to a gate trench than a side end surface in a direction in parallel with a second principal surface. A gate insulation film is in contact with a side surface and a bottom surface. A first electrode is in contact with a first principal surface. A second electrode is in contact with the second principal surface. An impurity concentration in a second impurity region is equal to or higher than 5×10cm. On a cross section perpendicular to the second principal surface, a straight line passing through a first position at which a first impurity region, a second impurity region, and the side surface come into contact with each other and the side end surface's second position closest to the second principal surface is separated from both of the fourth impurity region and a sixth impurity region and is positioned between the fourth impurity region and the sixth impurity region.SELECTED DRAWING: Figure 1

Description

  The present disclosure relates to a silicon carbide semiconductor device.

  For example, in Japanese Unexamined Patent Application Publication No. 2012-64659 (Patent Document 1), Japanese Unexamined Patent Application Publication No. 2013-165197 (Patent Document 2), Japanese Unexamined Patent Application Publication No. 2013-165198 (Patent Document 3), etc. A trench type MOSFET (Metal Oxide Semiconductor Field Effect Transistor) provided with a gate trench is disclosed. A super junction structure in which n-type regions and p-type regions are alternately arranged is provided inside the silicon carbide substrate. International Publication No. 2017/043606 (Patent Document 4) discloses a silicon carbide semiconductor device having a trench current diffusion layer.

JP 2012-64659 A JP 2013-165197 A JP 2013-165198 A International Publication No. 2017/043606

  An object of the present disclosure is to provide a silicon carbide semiconductor device capable of reducing electric field concentration at the bottom of a gate insulating film while reducing on-resistance.

A silicon carbide semiconductor device according to the present disclosure includes a silicon carbide substrate, a gate insulating film, a first electrode, and a second electrode. The silicon carbide substrate has a first main surface and a second main surface opposite to the first main surface. The silicon carbide substrate includes a first impurity region having a first conductivity type, a second impurity region provided on the first impurity region and having a second conductivity type different from the first conductivity type, and separated from the first impurity region. And a third impurity region provided on the second impurity region and having the first conductivity type. The first main surface is provided with a gate trench defined by a side surface penetrating the third impurity region and the second impurity region and reaching the first impurity region, and a bottom surface continuous with the side surface. The silicon carbide substrate is in contact with both the first impurity region and the second impurity region, is located closer to the second main surface than the second impurity region, and has a second conductivity type, and a first impurity region And a fifth impurity region which is in contact with both the fourth impurity region and is closer to the second main surface than the fourth impurity region and has the second conductivity type, and between the bottom surface and the second main surface, It further includes a sixth impurity region opposite to the fifth impurity region and having the second conductivity type across the one impurity region. The fifth impurity region has a side end face facing the sixth impurity region. The fourth impurity region includes an overhanging portion extending toward the gate trench rather than the side end surface in a direction parallel to the second main surface. The gate insulating film is in contact with the side surface and the bottom surface. The first electrode is in contact with the first main surface. The second electrode is in contact with the second main surface. The impurity concentration in the second impurity region is 5 × 10 ¹⁷ cm ⁻³ or more. In a cross section perpendicular to the second main surface, a straight line passing through the first position where the first impurity region, the second impurity region and the side surface are in contact, and the second position of the side end surface closest to the second main surface is The impurity region and the sixth impurity region are spaced apart from each other and located between the fourth impurity region and the sixth impurity region.

  According to the present disclosure, it is possible to provide a silicon carbide semiconductor device that can reduce the electric field concentration at the bottom of the gate insulating film while reducing the on-resistance.

It is a cross-sectional schematic diagram which shows the structure of the silicon carbide semiconductor device which concerns on this embodiment. It is an arrow cross-sectional schematic diagram along the II-II line | wire of FIG. FIG. 3 is a schematic cross-sectional view taken along the line III-III in FIG. 1. It is a cross-sectional schematic diagram which shows the structure of the 1st modification of the silicon carbide semiconductor device which concerns on this embodiment. It is a cross-sectional schematic diagram which shows the structure of the 2nd modification of the silicon carbide semiconductor device which concerns on this embodiment. It is a cross-sectional schematic diagram which shows the 1st process of the manufacturing method of the silicon carbide semiconductor device which concerns on this embodiment. It is a cross-sectional schematic diagram which shows the 2nd process of the manufacturing method of the silicon carbide semiconductor device which concerns on this embodiment. It is a cross-sectional schematic diagram which shows the 3rd process of the manufacturing method of the silicon carbide semiconductor device which concerns on this embodiment. It is a cross-sectional schematic diagram which shows the 4th process of the manufacturing method of the silicon carbide semiconductor device which concerns on this embodiment. It is a cross-sectional schematic diagram which shows the 5th process of the manufacturing method of the silicon carbide semiconductor device which concerns on this embodiment.

[Outline of Embodiment of the Present Disclosure]
First, an overview of an embodiment of the present disclosure will be described.

(1) The silicon carbide semiconductor device 100 according to the present disclosure includes the silicon carbide substrate 10, the gate insulating film 81, the first electrode 60, and the second electrode 70. Silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. Silicon carbide substrate 10 includes a first impurity region 11 having a first conductivity type, a second impurity region 12 provided on first impurity region 11 and having a second conductivity type different from the first conductivity type, It includes a third impurity region 13 provided on second impurity region 12 so as to be separated from impurity region 11 and having the first conductivity type. The first main surface 1 is provided with a gate trench 5 defined by a side surface 3 that penetrates the third impurity region 13 and the second impurity region 12 to reach the first impurity region 11 and a bottom surface 4 that is continuous with the side surface 3. It has been. Silicon carbide substrate 10 is in contact with both first impurity region 11 and second impurity region 12, is located closer to second main surface 2 than second impurity region 12, and has a second conductivity type. A fifth impurity region 15 that is in contact with both the first impurity region 11 and the fourth impurity region 14 and is closer to the second main surface 2 than the fourth impurity region 14 and has the second conductivity type; And a second main surface 2, and further includes a sixth impurity region 16 having the second conductivity type and facing the fifth impurity region 15 with the first impurity region 11 interposed therebetween. The fifth impurity region 15 has a side end face 52 that faces the sixth impurity region 16. The fourth impurity region 14 includes an overhanging portion 41 extending from the side end surface 52 toward the gate trench 5 in a direction parallel to the second main surface 2. The gate insulating film 81 is in contact with the side surface 3 and the bottom surface 4. The first electrode 60 is in contact with the first main surface 1. The second electrode 70 is in contact with the second main surface 2. The impurity concentration in the second impurity region 12 is 5 × 10 ¹⁷ cm ⁻³ or more. In a cross section perpendicular to the second main surface 2, the first position A where the first impurity region 11, the second impurity region 12 and the side surface 3 are in contact, and the second position B of the side end surface 52 closest to the second main surface 2. A straight line L passing through the first impurity region 14 is spaced apart from each of the fourth impurity region 14 and the sixth impurity region 16, and is located between the fourth impurity region 14 and the sixth impurity region 16.

  According to silicon carbide semiconductor device 100 in accordance with (1) above, fourth impurity region 14 extends in a direction parallel to second main surface 2 and extends toward gate trench 5 from side end surface 52. Is included. Thereby, it is possible to suppress the electric field from entering the channel region and the lower portion of the gate trench 5. Therefore, electric field concentration at the bottom of the gate insulating film 81 can be reduced. Further, according to silicon carbide semiconductor device 100 according to (1) above, in a cross section perpendicular to second main surface 2, first position A where first impurity region 11, second impurity region 12, and side surface 3 are in contact with each other, A straight line L passing through the second position B of the side end face 52 closest to the second main surface 2 is separated from each of the fourth impurity region 14 and the sixth impurity region 16, and the fourth impurity region 14 and the It is located between the six impurity regions 16. Thereby, the current from the channel region can be efficiently diffused throughout the first impurity region 11. As a result, the on-resistance of the silicon carbide semiconductor device can be reduced.

  (2) In silicon carbide semiconductor device 100 according to (1) above, fifth impurity region 15 and sixth impurity region 16 may be connected by semiconductor region 19 having the second conductivity type. Thereby, the fifth impurity region 15 and the sixth impurity region 16 can be set to the same potential. As a result, the switching characteristics of silicon carbide semiconductor device 100 can be improved.

  (3) In silicon carbide semiconductor device 100 according to (1) or (2) above, overhanging portion 41 may be in contact with second impurity region 12.

  (4) In silicon carbide semiconductor device 100 according to (1) or (2) above, overhanging portion 41 may be separated from second impurity region 12 by first impurity region 11.

  (5) In the silicon carbide semiconductor device 100 according to (4), the first impurity region 11 includes the first layer 21, the first layer 21, and the sixth layer sandwiched between the overhanging portion 41 and the second impurity region 12. The second layer 22 sandwiched between the impurity regions 16 may be included. The bottom surface 4 may be constituted by the first layer 21.

  (6) In silicon carbide semiconductor device 100 according to (5) above, the impurity concentration of first layer 21 may be lower than the impurity concentration of second layer 22.

  (7) In silicon carbide semiconductor device 100 according to (5) or (6), first impurity region 11 is closer to second main surface 2 than second layer 22, and fifth impurity region 15 and The third layer 23 sandwiched between the six impurity regions 16 may be provided. The impurity concentration of the third layer 23 may be higher than the impurity concentration of the second layer 22.

  (8) In silicon carbide semiconductor device 100 according to any of (1) to (7) above, straight line L may be perpendicular to side surface 3 in the cross section perpendicular to second main surface 2. Thereby, the current from the channel region can be more efficiently diffused throughout the first impurity region 11. As a result, the on-resistance of the silicon carbide semiconductor device can be further reduced.

  (9) In silicon carbide semiconductor device 100 according to any of (1) to (8) above, the angle of side surface 3 with respect to the plane including bottom surface 4 may be not less than 45 ° and not more than 65 °.

  (10) In silicon carbide semiconductor device 100 according to any of (1) to (9) above, fifth impurity region 15 may have lower end surface 53 facing second main surface 2. In the direction perpendicular to the second main surface 2, the distance between the first main surface 1 and the lower end surface 53 may be 2.5 μm or less.

[Details of Embodiment of the Present Disclosure]
Hereinafter, embodiments will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and the description thereof will not be repeated. In the crystallographic description in this specification, the individual orientation is indicated by [], the collective orientation is indicated by <>, the individual plane is indicated by (), and the collective plane is indicated by {}. In addition, a negative crystallographic index is usually expressed by adding a “-” (bar) above a number, but in this specification a negative sign is added before the number. Yes.

  First, the configuration of MOSFET 100 as an example of the silicon carbide semiconductor device according to the present embodiment will be described.

  As shown in FIG. 1, the MOSFET 100 according to the present embodiment includes a silicon carbide substrate 10, a gate insulating film 81, a gate electrode 82, an interlayer insulating film 83, a source electrode 60 (first electrode 60), It mainly has a drain electrode 70 (second electrode 70). Silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 on silicon carbide single crystal substrate 50. Silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to the first main surface 1. Silicon carbide epitaxial layer 40 constitutes first main surface 1, and silicon carbide single crystal substrate 50 constitutes second main surface 2. Silicon carbide single crystal substrate 50 and silicon carbide epitaxial layer 40 are made of, for example, polytype 4H hexagonal silicon carbide. Silicon carbide single crystal substrate 50 includes an n-type impurity such as nitrogen (N) and has an n-type (first conductivity type). The maximum diameter of first main surface 1 of silicon carbide substrate 10 is, for example, 100 mm or more, preferably 150 mm or more.

  The first main surface 1 is a surface in which the {0001} plane or the {0001} plane is inclined by an off angle of 8 ° or less in the off direction. Preferably, the first principal surface 1 is a surface in which the (000-1) plane or the (000-1) plane is inclined by an off angle of 8 ° or less in the off direction. The off direction may be, for example, the <11-20> direction or the <1-100> direction. The off angle may be, for example, 1 ° or more, or 2 ° or more. The off-angle may be 6 ° or less, or 4 ° or less.

  The silicon carbide epitaxial layer 40 includes a drift region 11 (first impurity region 11), a body region 12 (second impurity region 12), a source region 13 (third impurity region 13), a fourth impurity region 14, It mainly includes a fifth impurity region 15, a sixth impurity region 16, and a contact region 18. Drift region 11 includes an n-type impurity such as nitrogen and has an n-type conductivity type. The drift region 11 mainly includes, for example, a first layer 21, a second layer 22, a third layer 23, and a fourth layer 24.

Body region 12 is provided on drift region 11. Body region 12 includes a p-type impurity such as aluminum (Al), for example, and has a p-type (second conductivity type) conductivity type. The concentration of the p-type impurity in the body region 12 is 5 × 10 ¹⁷ cm ⁻³ or more. The short channel effect (punch-through) can occur when a depletion layer extends from the pn junction region into the channel region and the entire channel region becomes a depletion layer. By increasing the concentration of the p-type impurity in the body region 12, the spread of the depletion layer formed in the channel region can be reduced. As a result, even when the thickness of the body region 12 is small, the occurrence of the short channel effect can be suppressed. Therefore, the distance H1 (see FIG. 1) can be reduced. The thickness of body region 12 may be smaller than 0.7 μm, for example. The concentration of the p-type impurity in body region 12 is, for example, about 1 × 10 ¹⁸ cm ⁻³ . The concentration of the p-type impurity in the body region 12 may be higher than the concentration of the n-type impurity in the drift region 11.

Source region 13 is provided on body region 12 so as to be separated from drift region 11 by body region 12. Source region 13 includes an n-type impurity such as nitrogen or phosphorus (P), and has an n-type conductivity type. The source region 13 constitutes the first main surface 1. The concentration of the n-type impurity in the source region 13 may be higher than the concentration of the p-type impurity in the body region 12. The concentration of the n-type impurity in the source region 13 is, for example, about 1 × 10 ¹⁹ cm ⁻³ .

Contact region 18 contains a p-type impurity such as aluminum and has p-type conductivity. The concentration of the p-type impurity in contact region 18 is higher than the concentration of the p-type impurity in body region 12, for example. Contact region 18 passes through source region 13 and contacts body region 12. The contact region 18 constitutes the first main surface 1. The concentration of the p-type impurity in contact region 18 is, for example, 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²⁰ cm ⁻³ or less.

  The first main surface 1 is provided with a gate trench 5 defined by the side surface 3 and the bottom surface 4. Side surface 3 penetrates source region 13 and body region 12 to reach drift region 11. The bottom surface 4 is continuous with the side surface 3. The bottom surface 4 is located in the drift region 11. For example, the bottom surface 4 is a plane parallel to the second main surface 2. The angle θ1 of the side surface 3 with respect to the plane including the bottom surface 4 is, for example, 45 ° or more and 65 ° or less. The angle θ1 may be 50 ° or more, for example. The angle θ1 may be 60 ° or less, for example. For example, the gate trench 5 extends in a stripe shape along a direction parallel to the second main surface 2. The gate trenches 5 may extend in a honeycomb shape or may be scattered in an island shape.

Fourth impurity region 14 includes a p-type impurity such as aluminum (Al), for example, and has a p-type (second conductivity type) conductivity type. The concentration of the p-type impurity in the fourth impurity region 14 is, for example, 3 × 10 ¹⁶ cm ⁻³ or more and 5 × 10 ¹⁸ cm ⁻³ or less. By setting the concentration of the p-type impurity in the fourth impurity region 14 to 5 × 10 ¹⁸ cm ⁻³ or less, it is possible to suppress the fourth impurity region 14 from being completely depleted. The fourth impurity region 14 is in contact with both the first impurity region 11 and the second impurity region 12. The fourth impurity region 14 is closer to the second main surface 2 than the second impurity region 12. For example, the fourth impurity region 14 protrudes from the lower end surface 54 of the second impurity region 12 toward the second main surface 2. In the direction parallel to the second major surface 2, the width of the fourth impurity region 14 may be smaller than the width of the second impurity region 12. In the direction parallel to the second major surface 2, the width of the fourth impurity region 14 may be larger than the width of the fifth impurity region 15.

  For example, the fourth impurity region 14 includes an overhanging portion 41, a second portion 42, and a third portion 43. The overhanging portion 41 extends from the side end surface 52 of the fifth impurity region 15 toward the gate trench 5 in a direction parallel to the second main surface 2. The overhang portion 41 is continuous with the second portion 42. The overhanging portion 41 is located on the gate trench 5 side with respect to the second portion 42. The overhang portion 41 may be separated from the second impurity region 12 by the first impurity region 11.

  The second portion 42 is located between the third portion 43 and the fifth impurity region 15 in the direction perpendicular to the second major surface 2. The second portion 42 is in contact with each of the third portion 43 and the fifth impurity region 15. The third portion 43 is in contact with the second impurity region 12. The third portion 43 is located between the second portion 42 and the second impurity region 12 in the direction perpendicular to the second main surface 2. In the direction parallel to the second major surface 2, the width of the third portion 43 may be larger than the width of the fifth impurity region 15. In the direction parallel to the second major surface 2, the width of the third portion 43 may be smaller than the width of the second impurity region 12. In the direction parallel to the second main surface 2, the width of the third portion 43 may be smaller than the width of the region constituted by the second portion 42 and the overhanging portion 41.

  Fifth impurity region 15 includes a p-type impurity such as aluminum (Al), for example, and has a p-type (second conductivity type) conductivity type. The concentration of the p-type impurity in the fifth impurity region 15 may be substantially the same as the concentration of the p-type impurity in the fourth impurity region 14. The fifth impurity region 15 is in contact with both the first impurity region 11 and the fourth impurity region 14. The fifth impurity region 15 is in contact with the second portion 42. The fifth impurity region 15 is closer to the second main surface 2 than the fourth impurity region 14. The fifth impurity region 15 protrudes from the second portion 42 toward the second main surface 2. The fifth impurity region 15 has a side end face 52 that faces the sixth impurity region 16. The fifth impurity region 15 has a lower end surface 53 that faces the second main surface 2.

  Sixth impurity region 16 includes a p-type impurity such as aluminum (Al), for example, and has a p-type (second conductivity type) conductivity type. The concentration of the p-type impurity in the sixth impurity region 16 may be substantially the same as the concentration of the p-type impurity in the fourth impurity region 14. The sixth impurity region 16 is between the bottom surface 4 of the gate trench 5 and the second main surface 2. The sixth impurity region 16 faces the fifth impurity region 15 with the first impurity region 11 interposed therebetween. For example, the sixth impurity region 16 faces the entire bottom surface 4 of the gate trench 5 and a part of the side surface 3. In a direction parallel to the second main surface 2, the width W <b> 3 of the sixth impurity region 16 may be larger than the width W <b> 1 of the bottom surface 4. In the direction parallel to the second main surface 2, the width W <b> 3 of the sixth impurity region 16 may be smaller than the width W <b> 2 of the opening of the gate trench 5.

The first layer 21 of the drift region 11 is sandwiched between the overhanging portion 41 and the body region 12. The first layer 21 is in contact with each of the body region 12 and the third portion 43. The first layer 21 is on the second main surface 2 side with respect to the body region 12. The first layer 21 is closer to the gate trench 5 than the third portion 43. The bottom surface 4 of the gate trench 5 may be constituted by the first layer 21. A part of the side surface 3 of the gate trench 5 may be constituted by the first layer 21. The concentration of the n-type impurity in the first layer 21 is, for example, 1 × 10 ¹⁶ cm ⁻³ or more and 1 × 10 ¹⁷ cm ⁻³ or less.

  The second layer 22 is sandwiched between the first layer 21 and the sixth impurity region 16. The second layer 22 is in contact with each of the first layer 21 and the sixth impurity region 16. The second layer 22 is closer to the second major surface 2 than the first layer 21. The second layer 22 is located closer to the first main surface 1 than the sixth impurity region 16. The second layer 22 is in contact with the overhang portion 41. The second layer 22 is closer to the gate trench 5 than the overhanging portion 41. In the direction parallel to the second major surface 2, the width of the second layer 22 may be smaller than the width of the first layer 21. The impurity concentration of the first layer 21 may be lower than the impurity concentration of the second layer 22.

The third layer 23 is closer to the second principal surface 2 than the second layer 22. The third layer 23 is continuous with the second layer 22. The third layer 23 is sandwiched between the fifth impurity region 15 and the sixth impurity region 16. The third layer 23 is in contact with each of the fifth impurity region 15 and the sixth impurity region 16. The third layer 23, the fifth impurity region 15, and the sixth impurity region 16 may be located on the same plane parallel to the second main surface 2. The impurity concentration of the third layer 23 may be higher than the impurity concentration of the second layer 22. The concentration of the n-type impurity in the third layer 23 is, for example, 3 × 10 ¹⁶ cm ⁻³ or more and 4 × 10 ¹⁷ cm ⁻³ or less.

  The fourth layer 24 is closer to the second major surface 2 than the third layer 23. The fourth layer 24 is continuous with the third layer 23. The fourth layer 24 is in contact with each of the fifth impurity region 15 and the sixth impurity region 16. The fourth layer 24 is closer to the second main surface 2 than the fifth impurity region 15. The fourth layer 24 is closer to the second major surface 2 than the sixth impurity region 16. The fourth layer 24 may be sandwiched between the third layer 23 and the buffer layer 17. The fourth layer 24 may be continuous with the buffer layer 17. The impurity concentration of the buffer layer 17 may be higher than the impurity concentration of the fourth layer 24.

  As shown in FIG. 1, in a cross section perpendicular to the second main surface 2, the first position A where the first impurity region 11, the second impurity region 12, and the side surface 3 are in contact, and the closest to the second main surface 2. A straight line L passing through the second position B of the side end face 52 is separated from each of the fourth impurity region 14 and the sixth impurity region 16, and between the fourth impurity region 14 and the sixth impurity region 16. positioned. From another viewpoint, the straight line L does not intersect with each of the fourth impurity region 14 and the sixth impurity region 16. The straight line L intersects each of the first layer 21, the second layer 22, the third layer 23, and the fourth layer 24. There is a drift region 11 between the straight line L and the fourth impurity region 14. Similarly, there is a drift region 11 between the straight line L and the sixth impurity region 16.

  The first position A is a contact point between the boundary surface 54 between the body region 12 and the drift region 11 and the side surface 3 of the gate trench 5. The second position B may be an intersection of a straight line along the side end surface 52 of the fifth impurity region 15 and a straight line along the lower end surface 53 of the fifth impurity region 15. As shown in FIG. 1, the straight line L may be perpendicular to the side surface 3 in a cross section perpendicular to the second major surface 2. The cross section may be a direction perpendicular to the extending direction of the gate trench 5. The inclination angle θ2 of the straight line L with respect to the side surface 3 may be, for example, 85 ° or more and 95 ° or less.

  As shown in FIG. 1, in a direction perpendicular to the second main surface 2, the distance H1 between the first main surface 1 and the lower end surface 53 is, for example, 2.5 μm or less. The distance H1 may be 2.0 μm or less, or 1.5 μm or less. In a direction perpendicular to the second main surface 2, the distance H2 between the upper end surface of the sixth impurity region 16 and the first position A is not less than 0.4 μm and not more than 0.8 μm.

  Gate insulating film 81 is, for example, an oxide film. Gate insulating film 81 is made of, for example, a material containing silicon dioxide. The gate insulating film 81 is in contact with the side surface 3 and the bottom surface 4. The gate insulating film 81 is in contact with the first layer 21 at the bottom surface 4. Gate insulating film 81 is in contact with each of source region 13, body region 12, and first layer 21 on side surface 3. Gate insulating film 81 may be in contact with source region 13 on first main surface 1.

  The gate electrode 82 is provided on the gate insulating film 81. The gate electrode 82 is made of, for example, polysilicon containing a conductive impurity. The gate electrode 82 is disposed inside the gate trench 5. A part of the gate electrode 82 may be disposed on the first main surface 1.

  Source electrode 60 is in contact with first main surface 1. The source electrode has a contact electrode 61 and a source wiring 62. The source wiring 62 is on the contact electrode 61. Contact electrode 61 may be in contact with source region 13 and contact region 18 on first main surface 1. Contact electrode 61 is made of a material containing, for example, Ti, Al, and Si. The contact electrode 61 is in ohmic contact with the source region 13. The contact electrode 61 may be in ohmic contact with the contact region 18. Each of fourth impurity region 14, fifth impurity region 15, and sixth impurity region 16 may be grounded to source electrode 60.

  The drain electrode 70 is in contact with the second major surface 2. Drain electrode 70 is in contact with silicon carbide single crystal substrate 50 at second main surface 2. The drain electrode 70 is electrically connected to the drift region 11. The drain electrode 70 is made of a material containing, for example, NiSi or TiAlSi.

  The interlayer insulating film 83 is provided in contact with the gate electrode 82 and the gate insulating film 81. Interlayer insulating film 83 is made of, for example, a material containing silicon dioxide. The interlayer insulating film 83 electrically insulates the gate electrode 82 and the source electrode 60 from each other. A part of the interlayer insulating film 83 may be provided inside the gate trench 5.

  2 is a schematic cross-sectional view taken along the line II-II in FIG. As shown in FIG. 2, the fifth impurity region 15 and the sixth impurity region 16 may be connected by a semiconductor region 19. Semiconductor region 19 includes a p-type impurity such as aluminum (Al), for example, and has a p-type (second conductivity type) conductivity type. The semiconductor region 19 is in contact with the third layer 23. The semiconductor region 19 is in contact with part of the side surface 3 of the fifth impurity region 15 and is in contact with part of the side surface 3 of the sixth impurity region 16. The bottom surface 4 of the gate trench 5 extends in a direction parallel to the second main surface 2. When viewed from a direction perpendicular to the second main surface 2, the bottom surface 4 of the gate trench 5 is, for example, rectangular.

  The fifth impurity region 15 extends, for example, in a direction parallel to the extending direction of the bottom surface 4 of the gate trench 5. When viewed from a direction perpendicular to the second main surface 2, the fifth impurity region 15 has, for example, a rectangular shape. Similarly, the sixth impurity region 16 extends, for example, in a direction parallel to the extending direction of the bottom surface 4 of the gate trench 5. When viewed from a direction perpendicular to the second main surface 2, the sixth impurity region 16 has, for example, a rectangular shape. The extending direction of the fifth impurity region 15 may be the same as the extending direction of the sixth impurity region 16. The fifth impurity region 15 and the sixth impurity region 16 are alternately arranged along a direction (left-right direction in FIG. 2) perpendicular to the extending direction of the bottom surface 4 of the gate trench 5 (up-down direction in FIG. 2). May be.

  3 is a schematic cross-sectional view taken along the line III-III in FIG. For example, the fourth impurity region 14 extends in a direction parallel to the extending direction of the bottom surface 4 of the gate trench 5. When viewed from a direction perpendicular to the second main surface 2, the fourth impurity region 14 has, for example, a rectangular shape. Each of the plurality of fourth impurity regions 14 may be spaced apart from each other in the direction perpendicular to the extending direction of the bottom surface 4 of the gate trench 5. The semiconductor region 19 having the second conductivity type may not be disposed between each of the plurality of fourth impurity regions 14.

Next, the structure of the MOSFET according to the first modification will be described.
As shown in FIG. 4, the overhanging portion 41 may be in contact with the second impurity region 12. In this case, the fourth impurity region 14 includes an overhang portion 41 and a second portion 42. The overhanging portion 41 may be disposed so as to intersect with a plane including the bottom surface 4 of the gate trench 5. A side end surface of the overhang portion 41 may be in contact with the first layer 21. The drift region 11 may be configured by the first layer 21, the third layer 23, and the fourth layer 24. The impurity concentration of the first layer 21 may be lower than the impurity concentration of the third layer 23.

Next, the structure of the MOSFET according to the second modification will be described.
As shown in FIG. 5, the gate trench 5 may be a vertical trench. That is, the angle θ1 of the side surface 3 with respect to the plane including the bottom surface 4 may be 90 °. In this case, the width of the bottom surface 4 of the gate trench 5 is substantially the same as the width of the opening of the gate trench 5 in the direction parallel to the second main surface 2. The inclination angle θ2 of the straight line L with respect to the side surface 3 of the gate trench 5 is larger than 90 °. The vertical trench may be adopted in the MOSFET having the structure of the fourth impurity region 14 shown in FIG. 4 or may be adopted in the MOSFET having the structure of the fourth impurity region 14 shown in FIG. As shown in FIG. 5, in the direction perpendicular to the second main surface 2, the distance H1 between the first main surface 1 and the lower end surface 53 is, for example, 2.5 μm or less. As the distance H1 decreases, the inclination angle θ3 (see FIG. 5) of the straight line L with respect to the lower end surface 54 of the body region 12 decreases. The inclination angle θ3 is, for example, not less than 30 ° and not more than 60 °.

Next, a method for manufacturing the MOSFET 100 according to this embodiment will be described.
First, a step of preparing a silicon carbide substrate is performed. For example, a silicon carbide single crystal substrate 50 is prepared by slicing a silicon carbide ingot (not shown) manufactured by a sublimation method. Next, a step of forming the buffer layer 17 is performed. For example, a silicon carbide single crystal substrate is formed by a CVD (Chemical Vapor Deposition) method using a mixed gas of silane (SiH ₄ ) and propane (C ₃ H ₈ ) as a source gas and using, for example, hydrogen (H ₂ ) as a carrier gas. A buffer layer 17 is formed on 50. During epitaxial growth, n-type impurities such as nitrogen are introduced into the buffer layer 17.

  Next, a step of forming the first epitaxial layer 20 is performed. For example, the first epitaxial layer 20 is formed on the buffer layer 17 by a CVD method using a mixed gas of silane and propane as a source gas and using, for example, hydrogen as a carrier gas (see FIG. 6). During epitaxial growth, an n-type impurity such as nitrogen is introduced into the first epitaxial layer 20. First epitaxial layer 20 has n-type conductivity. The concentration of the n-type impurity in the first epitaxial layer 20 is lower than the concentration of the n-type impurity in the buffer layer 17.

  Next, a step of forming the fifth impurity region 15 and the sixth impurity region 16 is performed. For example, a mask layer (not shown) having an opening is formed on a region where each of fifth impurity region 15 and sixth impurity region 16 is formed. Next, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into first epitaxial layer 20. Thereby, the fifth impurity region 15 and the sixth impurity region 16 are formed (see FIG. 7). Each of fifth impurity region 15 and sixth impurity region 16 is formed inside first epitaxial layer 20 so as not to be exposed on the surface of first epitaxial layer 20. The fifth impurity region 15 and the sixth impurity region 16 may be formed simultaneously or separately.

  Next, a step of forming the fourth impurity region 14 is performed. For example, a mask layer (not shown) having an opening is formed on the region where the fourth impurity region 14 is formed. Next, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into first epitaxial layer 20. Thereby, the fourth impurity region 14 is formed (see FIG. 7). The fourth impurity region 14 is formed so as to be in contact with the fifth impurity region 15 and exposed to the surface of the first epitaxial layer 20.

  Next, a step of implanting n-type impurity ions is performed. For example, n-type impurity ions capable of imparting n-type, such as nitrogen, are implanted into a region between the fifth impurity region 15 and the sixth impurity region 16. Thereby, the third layer 23 is formed. The n-type impurity region above the third layer 23 becomes the second layer 22. The n-type impurity region below the third layer 23 becomes the fourth layer 24 (see FIG. 8). The concentration of the n-type impurity in the third layer 23 is higher than the concentration of the n-type impurity in each of the second layer 22 and the fourth layer 24.

  Next, a step of forming a second epitaxial layer is performed. For example, the second epitaxial layer is formed on the first epitaxial layer 20 by a CVD method using a mixed gas of silane and propane as the source gas and using, for example, hydrogen as the carrier gas. During the epitaxial growth, an n-type impurity such as nitrogen is introduced into the second epitaxial layer. The second epitaxial layer has n-type conductivity.

  Next, a step of implanting p-type impurity ions is performed. For example, a mask layer (not shown) having an opening is formed on the region where the third portion 43 of the fourth impurity region 14 is formed. Next, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into the second epitaxial layer. Thereby, the third portion 43 is formed. The third portion 43 is formed so as to be connected to the second portion 42. Next, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into the entire surface of the second epitaxial layer. Thereby, the body region 12 is formed. In the second epitaxial layer, a region where the body region 12 and the third portion 43 are not formed becomes the first layer 21. The first layer 21, the second layer 22, the third layer 23, and the fourth layer 24 constitute the drift region 11.

  Next, n-type impurities such as phosphorus (P) are ion-implanted into the entire surface of the second epitaxial layer. Thereby, the source region 13 is formed. Next, a mask layer (not shown) having an opening is formed on the region where the contact region 18 is to be formed. Next, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into the source region 13. As a result, a contact region 18 in contact with the source region 13 is formed (see FIG. 9).

  Next, activation annealing is performed to activate the impurity ions implanted into silicon carbide substrate 10. The temperature of activation annealing is preferably 1500 ° C. or higher and 1900 ° C. or lower, for example, about 1700 ° C. The activation annealing time is, for example, about 30 minutes. The atmosphere of activation annealing is preferably an inert gas atmosphere, for example, an Ar atmosphere.

Next, a step of forming the gate trench 5 is performed. For example, a mask 51 having an opening is formed on the first main surface 1 composed of the source region 13 and the contact region 18 at a position where the gate trench 5 (FIG. 1) is formed. Using the mask 51, a part of the source region 13, a part of the body region 12, and a part of the drift region 11 are removed by etching. As an etching method, for example, reactive ion etching, particularly inductively coupled plasma reactive ion etching can be used. Specifically, for example, inductively coupled plasma reactive ion etching using sulfur hexafluoride (SF ₆ ) or a mixed gas of SF ₆ and oxygen (O ₂ ) as a reaction gas can be used. By etching, in a region where the gate trench 5 is to be formed, a side portion substantially perpendicular to the first main surface 1 and a bottom portion provided continuously with the side portion and substantially parallel to the first main surface 1 A recess having the shape is formed.

Next, thermal etching is performed in the recess. The thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas having at least one or more types of halogen atoms in a state where the mask 51 is formed on the first main surface 1. The at least one or more types of halogen atom includes at least one of a chlorine (Cl) atom and a fluorine (F) atom. The atmosphere includes, for example, chlorine (Cl ₂ ), boron trichloride (BCl ₃ ), SF ₆ or carbon tetrafluoride (CF ₄ ). For example, thermal etching is performed using a mixed gas of chlorine gas and oxygen gas as a reaction gas and a heat treatment temperature of, for example, 800 ° C. or more and 900 ° C. or less. Note that the reaction gas may contain a carrier gas in addition to the above-described chlorine gas and oxygen gas. As the carrier gas, for example, nitrogen gas, argon gas or helium gas can be used.

  By the thermal etching, gate trench 5 is formed in first main surface 1 of silicon carbide substrate 10 (see FIG. 10). The gate trench 5 is defined by the side surface 3 and the bottom surface 4. The side surface 3 includes a source region 13, a body region 12, and a drift region 11. The bottom surface 4 is constituted by a drift region 11. The angle θ1 between the side surface 3 and the plane including the bottom surface 4 is, for example, not less than 45 ° and not more than 65 °. Next, the mask 51 is removed from the first main surface 1.

  Next, a step of forming the gate insulating film 81 is performed. For example, by thermally oxidizing silicon carbide substrate 10, gate insulating film 81 in contact with source region 13, body region 12, drift region 11, and contact region 18 is formed. Specifically, silicon carbide substrate 10 is heated at a temperature of, for example, 1300 ° C. or higher and 1400 ° C. or lower in an atmosphere containing oxygen. Thereby, the gate insulating film 81 in contact with the first main surface 1 and the side surface 3 and the bottom surface 4 is formed.

  Next, heat treatment (NO annealing) may be performed on silicon carbide substrate 10 in a nitrogen monoxide (NO) gas atmosphere. In NO annealing, silicon carbide substrate 10 is held for about 1 hour under conditions of, for example, 1100 ° C. or higher and 1400 ° C. or lower. Thereby, nitrogen atoms are introduced into the interface region between the gate insulating film 81 and the body region 12. As a result, the formation of interface states in the interface region is suppressed, so that channel mobility can be improved.

  After the NO annealing, Ar annealing using argon (Ar) as an atmospheric gas may be performed. The heating temperature for Ar annealing is, for example, equal to or higher than the heating temperature for NO annealing. The Ar annealing time is, for example, about 1 hour. Thereby, the formation of interface states in the interface region between the gate insulating film 81 and the body region 12 is further suppressed. Note that other inert gas such as nitrogen gas may be used as the atmospheric gas instead of Ar gas.

  Next, a step of forming a gate electrode is performed. The gate electrode 82 is formed on the gate insulating film 81. The gate electrode 82 is formed by, for example, LP-CVD (Low Pressure Chemical Vapor Deposition). Gate electrode 82 is formed to face each of source region 13, body region 12, and drift region 11.

  Next, a step of forming an interlayer insulating film 83 is performed. Specifically, an interlayer insulating film 83 is formed so as to cover the gate electrode 82 and to be in contact with the gate insulating film 81. The interlayer insulating film 83 is formed by, for example, a CVD method. Interlayer insulating film 83 is a material containing, for example, silicon dioxide. A part of the interlayer insulating film 83 may be formed inside the gate trench 5.

  Next, a step of forming a contact electrode is performed. For example, etching is performed so that openings are formed in the interlayer insulating film 83 and the gate insulating film 81, so that the source region 13 and the contact region 18 are exposed from the interlayer insulating film 83 and the gate insulating film 81 in the openings. To do. Next, contact electrode 61 in contact with source region 13 and contact region 18 is formed on first main surface 1. Contact electrode 61 is formed, for example, by sputtering. Contact electrode 61 is made of, for example, a material containing Ti, Al, and Si.

  Next, alloying annealing is performed. Contact electrode 61 in contact with source region 13 and contact region 18 is held at a temperature of 900 ° C. or higher and 1100 ° C. or lower, for example, for about 5 minutes. Thereby, at least a part of contact electrode 61 reacts with silicon included in silicon carbide substrate 10 to be silicided. As a result, a contact electrode 61 that is in ohmic contact with the source region 13 is formed. The contact electrode 61 may be in ohmic contact with the contact region 18.

  Next, a step of forming a drain electrode is performed. For example, the drain electrode 70 in contact with the second main surface 2 is formed by sputtering. The drain electrode 70 is made of a material containing, for example, NiSi or TiAlSi. Thus, the MOSFET 100 (FIG. 1) according to the present embodiment is completed.

  In the above embodiment, the n-type is the first conductivity type and the p-type is the second conductivity type. However, the p-type may be the first conductivity type and the n-type may be the second conductivity type. . In the above-described embodiment, MOSFET is described as an example of the silicon carbide semiconductor device. However, the silicon carbide semiconductor device may be, for example, an IGBT (Insulated Gate Bipolar Transistor). Further, the concentration of the p-type impurity and the concentration of the n-type impurity in each impurity region can be measured by, for example, SCM (Scanning Capacitance Microscope) or SIMS (Secondary Ion Mass Spectrometry). The position of the boundary surface (that is, the PN interface) between the p-type region and the n-type region can be specified by, for example, SCM or SIMS.

Next, the function and effect of the MOSFET according to this embodiment will be described.
In the MOSFET 100 according to the present embodiment, the fourth impurity region 14 includes the overhanging portion 41 that extends from the side end surface 52 toward the gate trench 5 in a direction parallel to the second main surface 2. Thereby, it is possible to suppress the electric field from entering the channel region and the lower portion of the gate trench 5. Therefore, electric field concentration at the bottom of the gate insulating film 81 can be reduced.

  Further, according to the MOSFET 100 according to the present embodiment, in the cross section perpendicular to the second main surface 2, the first position A where the drift region 11, the body region 12, and the side surface 3 are in contact, and the side closest to the second main surface 2. A straight line L passing through the second position B of the end face 52 is separated from each of the fourth impurity region 14 and the sixth impurity region 16, and is positioned between the fourth impurity region 14 and the sixth impurity region 16. doing. Thereby, the current from the channel region can be efficiently diffused throughout the drift region 11. As a result, the on-resistance of MOSFET 100 can be reduced.

  Furthermore, according to the MOSFET 100 according to the present embodiment, the fifth impurity region 15 and the sixth impurity region 16 may be connected by the semiconductor region 19 having the second conductivity type. Thereby, the fifth impurity region 15 and the sixth impurity region 16 can be set to the same potential. As a result, the switching characteristics of MOSFET 100 can be improved.

  Further, according to the MOSFET 100 according to the present embodiment, the straight line L may be perpendicular to the side surface 3 in a cross section perpendicular to the second main surface 2. Thereby, the current from the channel region can be more efficiently diffused throughout the drift region 11. As a result, the on-resistance of MOSFET 100 can be further reduced.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

DESCRIPTION OF SYMBOLS 1 1st main surface 2 2nd main surface 3 Side surface 4 Bottom surface 5 Gate trench 10 Silicon carbide substrate 11 1st impurity region (drift region)
12 Second impurity region (body region)
13 Third impurity region (source region)
14 4th impurity region 15 5th impurity region 16 6th impurity region 17 Buffer layer 18 Contact region 19 Semiconductor region 20 1st epitaxial layer 21 1st layer 22 2nd layer 23 3rd layer 24 4th layer 40 Silicon carbide epitaxial layer 41 Overhang portion 42 Second portion 43 Third portion 50 Silicon carbide single crystal substrate 51 Mask 52 Side end surface 53 Lower end surface 54 Lower end surface (Boundary surface)
60 First electrode (source electrode)
61 Contact electrode 62 Source wiring 70 Second electrode (drain electrode)
81 Gate Insulating Film 82 Gate Electrode 83 Interlayer Insulating Film 100 Silicon Carbide Semiconductor Device (MOSFET)
A 1st position B 2nd position H1, H2 Distance L Straight line W1, W2, W3 Width

Claims (10)

A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface;
The silicon carbide substrate is
A first impurity region having a first conductivity type;
A second impurity region provided on the first impurity region and having a second conductivity type different from the first conductivity type;
A third impurity region provided on the second impurity region so as to be separated from the first impurity region and having the first conductivity type,
The first main surface is provided with a gate trench that is defined by a side surface that penetrates the third impurity region and the second impurity region to reach the first impurity region, and a bottom surface that is continuous with the side surface. ,
The silicon carbide substrate is
A fourth impurity region that is in contact with both the first impurity region and the second impurity region, is closer to the second main surface than the second impurity region, and has the second conductivity type;
A fifth impurity region that is in contact with both the first impurity region and the fourth impurity region, is closer to the second main surface than the fourth impurity region, and has the second conductivity type;
A sixth impurity region that is between the bottom surface and the second main surface, faces the fifth impurity region with the first impurity region in between, and has the second conductivity type;
The fifth impurity region has a side end surface facing the sixth impurity region,
The fourth impurity region includes an overhanging portion extending toward the gate trench from the side end surface in a direction parallel to the second main surface,
A gate insulating film in contact with the side surface and the bottom surface;
A first electrode in contact with the first main surface;
A second electrode in contact with the second main surface,
The impurity concentration in the second impurity region is 5 × 10 ¹⁷ cm ⁻³ or more,
In a cross section perpendicular to the second main surface, a first position where the first impurity region, the second impurity region and the side surface are in contact with each other, and a second position of the side end surface closest to the second main surface. A silicon carbide semiconductor device, wherein a straight line passing through is spaced from each of the fourth impurity region and the sixth impurity region, and is located between the fourth impurity region and the sixth impurity region.   2. The silicon carbide semiconductor device according to claim 1, wherein the fifth impurity region and the sixth impurity region are connected by a semiconductor region having the second conductivity type.   The silicon carbide semiconductor device according to claim 1, wherein the projecting portion is in contact with the second impurity region.   The silicon carbide semiconductor device according to claim 1, wherein the projecting portion is separated from the second impurity region by the first impurity region. The first impurity region has a first layer sandwiched between the overhanging portion and the second impurity region, and a second layer sandwiched between the first layer and the sixth impurity region,
The silicon carbide semiconductor device according to claim 4, wherein said bottom surface is constituted by said first layer.   The silicon carbide semiconductor device according to claim 5, wherein an impurity concentration of the first layer is lower than an impurity concentration of the second layer. The first impurity region has a third layer that is closer to the second main surface than the second layer and sandwiched between the fifth impurity region and the sixth impurity region,
The silicon carbide semiconductor device according to claim 5, wherein an impurity concentration of the third layer is higher than an impurity concentration of the second layer.   The silicon carbide semiconductor device according to any one of claims 1 to 7, wherein the straight line is perpendicular to the side surface in a cross section perpendicular to the second main surface.   The silicon carbide semiconductor device according to any one of claims 1 to 8, wherein an angle of the side surface with respect to a plane including the bottom surface is not less than 45 ° and not more than 65 °. The fifth impurity region has a lower end surface facing the second main surface,
10. The carbonization according to claim 1, wherein a distance between the first main surface and the lower end surface is 2.5 μm or less in a direction perpendicular to the second main surface. Silicon semiconductor device.

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