JP2023104657A - Silicon carbide semiconductor device - Google Patents

Abstract

To provide a silicon carbide semiconductor device in which the number of times of forming epitaxial layers can be reduced.SOLUTION: In a silicon carbide semiconductor device MOSFET 100, a silicon carbide substrate 10 has a drift region 11 having a first conductivity type, a body region 12 having a second conductivity type, and a source region 13 having the first conductivity type. A gate trench 5 reaching the drift region is provided on a first principal surface 1 of the silicon carbide substrate. The silicon carbide substrate has: a first contact region 18 connected to the body region and having the second conductivity type; a first region 15 overlapping the first contact region 18; a first electric field relaxation region 17 connected to the body region and having the second conductivity type; a second electric field relaxation region 31 surrounding the first region and having the second conductivity type; and a third electric field relaxation region 16 provided between the gate trench and a second principal surface 2 and having the second conductivity type. The peak depth of an effective concentration of a second conductivity type impurities in the third electric field relaxation region with the first principal surface as a reference is 1.0 μm or less.SELECTED DRAWING: Figure 3

Description

The present disclosure relates to silicon carbide semiconductor devices.

As one of silicon carbide semiconductor devices, a MOS field effect transistor (Metal Oxide Semiconductor Field Effect Transistor: MOSFET) having a gate trench penetrating a source region and a body region is disclosed (for example, Patent Documents 1 and 2 ).

JP 2014-41990 A JP 2017-139441 A

In order to manufacture a conventional silicon carbide semiconductor device, it is necessary to form an epitaxial layer multiple times on a silicon carbide single crystal substrate. For cost reduction, it is desirable to reduce the number of epitaxial layer formations.

An object of the present disclosure is to provide a silicon carbide semiconductor device capable of reducing the number of times epitaxial layers are formed.

A silicon carbide semiconductor device of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate having a first conductivity type drift a body region provided on the drift region and having a second conductivity type different from the first conductivity type; and a body region provided on the body region so as to be separated from the drift region and having the first conductivity type. and a gate trench defined by a side surface penetrating the source region and the body region to reach the drift region and a bottom surface continuous with the side surface is provided in the first main surface. The silicon carbide substrate sandwiches the source region between itself and the side surface, is connected to the body region, and has a first contact region having the second conductivity type, and a direction perpendicular to the first main surface. a first electric field provided on the second main surface side of the body region, connected to the body region, and having the second conductivity type; a relaxation region, which surrounds the first region when viewed in plan from a direction perpendicular to the first main surface, is provided closer to the second main surface than the first electric field relaxation region, and is of the second conductivity type; and a third electric field relaxation region having the second conductivity type provided between the gate trench and the second main surface, the first main surface having As a reference, the peak depth of the effective concentration of the impurity of the second conductivity type in the third electric field relaxation region is 1.0 μm or less.

According to the present disclosure, the number of epitaxial layer formations can be reduced.

FIG. 1 is a cross-sectional view (part 1) showing the configuration of the silicon carbide semiconductor device according to the embodiment. FIG. 2 is a cross-sectional view (Part 2) showing the configuration of the silicon carbide semiconductor device according to the embodiment. FIG. 3 is a cross-sectional view (Part 3) showing the configuration of the silicon carbide semiconductor device according to the embodiment. FIG. 4 is a cross-sectional view (part 4) showing the configuration of the silicon carbide semiconductor device according to the embodiment. FIG. 5 is a diagram showing configurations of an interlayer insulating film and a first main surface in the silicon carbide semiconductor device according to the embodiment. FIG. 6 is a cross-sectional view (Part 1) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 7 is a cross-sectional view (Part 2) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 8 is a cross-sectional view (part 3) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 9 is a cross-sectional view (Part 4) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 10 is a cross-sectional view (No. 5) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 11 is a cross-sectional view (No. 6) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 12 is a cross-sectional view (No. 7) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 13 is a cross-sectional view (No. 8) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 14 is a cross-sectional view (No. 9) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 15 is a cross-sectional view (No. 10) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 16 is a cross-sectional view (No. 11) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 17 is a cross-sectional view (No. 12) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 18 is a cross-sectional view (part 13) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 19 is a cross-sectional view (part 14) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 20 is a cross-sectional view (No. 15) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 21 is a cross-sectional view (No. 16) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 22 is a cross-sectional view (No. 17) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 23 is a cross-sectional view (No. 18) showing the method for manufacturing the silicon carbide semiconductor device according to the embodiment. FIG. 24 is a schematic diagram showing the positional relationship among the connection region, the second electric field relaxation region, the third electric field relaxation region, the first contact region, and the second contact region. FIG. 25 is a cross-sectional view showing the configuration of a silicon carbide semiconductor device according to a modification of the embodiment.

The form for carrying out is demonstrated below.

[Description of Embodiments of the Present Disclosure]
First, the embodiments of the present disclosure are listed and described. In the following description, the same or corresponding elements are given the same reference numerals and the same descriptions thereof are not repeated. In the crystallographic descriptions in this specification, individual orientations are indicated by [], aggregated orientations by <>, individual planes by (), and aggregated planes by {}. In addition, the fact that the crystallographic index is negative is usually expressed by attaching a "-" (bar) above the number, but in this specification, a negative sign is attached before the number. there is

[1] A silicon carbide semiconductor device according to an aspect of the present disclosure includes a silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface, the silicon carbide substrate comprising: a drift region having a first conductivity type; a body region provided on the drift region and having a second conductivity type different from the first conductivity type; and a body region provided on the body region so as to be separated from the drift region. , a source region having the first conductivity type, and the first main surface includes a side surface extending through the source region and the body region to reach the drift region, and a bottom surface continuous with the side surface. A defined gate trench is provided, and the silicon carbide substrate sandwiches the source region between the side surface and the first contact region connected to the body region and having the second conductivity type; It has a first region that overlaps with the first contact region when viewed in plan from a direction perpendicular to one main surface, is provided on the second main surface side of the body region, is connected to the body region, and is connected to the second contact region. a first electric field relaxation region having a conductivity type; and a first electric field relaxation region surrounding the first region when viewed in plan from a direction perpendicular to the first main surface and provided closer to the second main surface than the first electric field relaxation region. a second electric field relaxation region having the second conductivity type; and a third electric field relaxation region having the second conductivity type provided between the gate trench and the second main surface. and the peak depth of the effective concentration of the impurity of the second conductivity type in the third electric field relaxation region is 1.0 μm or less with respect to the first main surface.

The peak depth of the effective concentration of the impurity of the second conductivity type in the first electric field relaxation region is 1.0 μm or less with respect to the first main surface. Therefore, the source region, the body region, the drift region, and the first electric field relaxation region can be properly formed without forming epitaxial layers multiple times. Further, when viewed from the direction perpendicular to the first main surface, the first electric field relaxation region has a first region overlapping with the first contact region, and the second electric field relaxation region surrounds the first region. , even if the first contact region contains many crystal defects, it is possible to suppress the drain leak through the crystal defects.

[2] In [1], the second electric field relaxation region and the third electric field relaxation region may be connected in a direction parallel to the first main surface. In this case, the second electric field relaxation region and the third electric field relaxation region are set at the same potential to easily suppress drain leakage.

[3] In [1] or [2], the connection region is connected to the first electric field relaxation region and the second electric field relaxation region and electrically connects the first electric field relaxation region and the second electric field relaxation region. may have In this case, the first electric field relaxation region and the second electric field relaxation region are set at the same potential to easily suppress drain leakage.

[4] In [1] to [3], the second electric field relaxation regions may be arranged periodically in the longitudinal direction of the gate trench. In this case, it is easy to suppress drain leakage while ensuring a sufficient current path for on-current.

[5] In [4], the drift region has a second region between the second electric field relaxation regions adjacent to each other in the longitudinal direction, and the second electric field relaxation region has a first length in the longitudinal direction. The length may be less than or equal to the second length of the second region. In this case, it is easy to secure a current path for an on-current.

[6] In [5], the first length may be 20% or more and 40% or less of the sum of the first length and the second length. In this case, it is particularly easy to achieve both securing of a current path for on-current and suppression of drain leakage.

[7] In [1] to [6], the third electric field relaxation region includes a third region located closer to the second main surface than the bottom surface, and a third region located closer to the first main surface than the bottom surface. and a protruding fourth region, a portion of the drift region being between the fourth region and the body region. In this case, even if a high drain voltage is applied when the device is turned off, it is easy to suppress penetration of an electric field into the body region and drain leakage.

[8] In [1] to [7], the silicon carbide substrate is provided between the source region and the first contact region, is connected to the source region, and has a second contact having the first conductivity type. A region, wherein the second contact region may be thicker than the source region. In this case, it is easy to ohmically contact the source electrode with the contact region.

[9] In [1] to [8], the side surface of the gate trench may include a {0-33-8} plane. Since the side surfaces include the {0-33-8} plane, good mobility can be obtained on the side surfaces of the gate trench, and channel resistance can be reduced.

[Embodiment of the present disclosure]
An embodiment of the present disclosure relates to a so-called vertical MOSFET (silicon carbide semiconductor device). 1 to 4 are cross-sectional views showing the configuration of a silicon carbide semiconductor device according to an embodiment. FIG. 5 is a diagram showing configurations of an interlayer insulating film and a first main surface in the silicon carbide semiconductor device according to the embodiment. FIG. 1 corresponds to a cross-sectional view taken along line II in FIG. FIG. 2 corresponds to a cross-sectional view taken along line II-II in FIG. FIG. 3 corresponds to a cross-sectional view taken along line III-III in FIG. FIG. 4 corresponds to a cross-sectional view taken along line IV-IV in FIG.

As shown in FIGS. 1 to 5, MOSFET 100 according to the present embodiment includes silicon carbide substrate 10, gate insulating film 81, gate electrode 82, interlayer insulating film 83, source electrode 60, and drain electrode 70. , a barrier metal film 84 and a passivation film 85 . Silicon carbide substrate 10 includes a silicon carbide single crystal substrate 50 and a silicon carbide epitaxial layer 40 overlying silicon carbide single crystal substrate 50 . Silicon carbide substrate 10 has a first main surface 1 and a second main surface 2 opposite to first main surface 1 . Silicon carbide epitaxial layer 40 forms first main surface 1 , and silicon carbide single-crystal substrate 50 forms second main surface 2 . Silicon carbide single crystal substrate 50 and silicon carbide epitaxial layer 40 are made of hexagonal silicon carbide of polytype 4H, for example. Silicon carbide single-crystal substrate 50 contains an n-type impurity such as nitrogen (N) and has an n-type conductivity (first conductivity type).

The first main surface 1 is a {0001} plane or a plane in which the {0001} plane is inclined in the off direction by an off angle of 8° or less. Preferably, the first main surface 1 is the (000-1) plane or a plane in which the (000-1) plane is inclined in the off direction by an off angle of 8° or less. The off direction may be, for example, the <11-20> direction or the <1-100> direction. The off angle may be, for example, 1° or more, or may be 2° or more. The off angle may be 6° or less, or may be 4° or less.

Silicon carbide epitaxial layer 40 includes drift region 11 , body region 12 , source region 13 , current diffusion region 14 , third electric field relaxation region 16 , first electric field relaxation region 17 , and first contact region 18 . , a second contact region 19 , a second electric field relaxation region 31 and a connection region 32 .

The drift region 11 contains n-type impurities such as nitrogen or phosphorus (P), and has n-type conductivity. The drift region 11 mainly has, for example, a fifth region 11C, a second region 11D, and a sixth region 11E.

A current spreading region 14 is provided on the drift region 11 . The current diffusion region 14 contains an n-type impurity such as phosphorus and has an n-type conductivity. Current diffusion region 14 is between body region 12 and fifth region 11C in the direction perpendicular to second main surface 2 . The current diffusion region 14 is in contact with the body region 12 and the fifth region 11C. The current diffusion region 14 is closer to the second main surface 2 than the body region 12 is. The current diffusion region 14 is closer to the first main surface 1 than the fifth region 11C. The current spreading region 14 also contacts the side surfaces 3 . The peak value of the effective concentration of the n-type impurity in the current diffusion region 14 is preferably 5×10 ¹⁷ cm ⁻³ or less in order to suppress short-circuit current. The peak value of the effective n-type impurity concentration in the current diffusion region 14 is preferably 2×10 ¹⁷ cm ⁻³ or more in order to suppress the on-resistance. Current spreading region 14 forms part of the drift region.

Body region 12 is provided on current spreading region 14 . Body region 12 contains a p-type impurity such as aluminum (Al) and has p-type conductivity (second conductivity type). Body region 12 is between source region 13 and current spreading region 14 in a direction perpendicular to second main surface 2 . Body region 12 contacts source region 13 and current spreading region 14 . Body region 12 is closer to second main surface 2 than source region 13 is. The body region 12 is closer to the first main surface 1 than the current diffusion region 14 is. Body region 12 also contacts side surface 3 . Body region 12 has a lower end surface 94 that connects to side surface 3 . The lower end surface 94 is in contact with the upper end surface of the current spreading region 14 . A depth D2 of the lower end surface 94 with respect to the first main surface 1 is, for example, 0.2 μm or more and 0.5 μm or less. The effective concentration of the p-type impurity in the body region 12 is, for example, 5×10 ¹⁷ cm ⁻³ or more and 5×10 ¹⁸ cm ⁻³ or less. The peak value of the effective p-type impurity concentration in body region 12 is preferably 2×10 ¹⁸ cm ⁻³ or more. A short-channel effect (punch-through) can occur when a depletion layer spreads from the pn junction region into the channel region and the entire channel region becomes a depletion layer. By increasing the effective concentration of p-type impurities in body region 12, the spread of the depletion layer formed in the channel region can be reduced.

Source region 13 is on body region 12 in a direction perpendicular to second main surface 2 . Source region 13 is in contact with body region 12 . Source region 13 is provided on body region 12 so as to be separated from current spreading region 14 by body region 12 . Source region 13 is closer to first main surface 1 than body region 12 is. Source region 13 is also in contact with side surface 3 . Source region 13 has a lower end surface 97 connected to side surface 3 . The lower end surface 97 contacts the upper end surface of the body region 12 . Source region 13 has a first thickness T1. The first thickness T1 is, for example, 0.1 μm or more and 0.3 μm or less. Source region 13 is covered with gate insulating film 81 . Source region 13 is in direct contact with gate insulating film 81 . The source region 13 contains an n-type impurity such as nitrogen or phosphorus and has an n-type conductivity. Source region 13 constitutes first main surface 1 . The effective concentration of the n-type impurity in the source region 13 is, for example, 5×10 ¹⁸ cm ⁻³ or more and 5×10 ¹⁹ cm ⁻³ or less. The effective concentration of n-type impurities in first main surface 1 of source region 13 is preferably 1×10 ¹⁹ cm ⁻³ or more in order to reduce sheet resistance.

The second contact region 19 contains an n-type impurity such as nitrogen or phosphorus and has an n-type conductivity. The second contact region 19 sandwiches the source region 13 with the side surface 3 . That is, the source region 13 is between the side surface 3 and the second contact region 19 in the direction parallel to the first main surface 1 . The second contact region 19 is on the side farther from the gate trench 5 than the source region 13 is. A second contact region 19 leads to the source region 13 . Second contact region 19 constitutes first main surface 1 . A lower end surface 96 of the second contact region 19 is closer to the second main surface 2 than a lower end surface 97 of the source region 13 . The second contact region 19 is thicker than the source region 13 . The second contact region 19 has a second thickness T2 that is greater than the first thickness T1. The second thickness T2 may be 1.1 to 5.0 times the first thickness T1. The second thickness T2 is, for example, 0.2 μm or more. The second thickness T2 may be 0.2 μm or more and 0.5 μm or less. The effective n-type impurity concentration of the second contact region 19 may be substantially the same as the n-type impurity concentration of the source region 13 . The effective n-type impurity concentration of the second contact region 19 is, for example, 5×10 ¹⁸ cm ⁻³ or more and 5×10 ¹⁹ cm ^{−3 or} less. The second contact region 19 is an example of a contact region having the first conductivity type.

The first contact region 18 contains p-type impurities such as aluminum and has p-type conductivity. The effective concentration of p-type impurities in the first contact region 18 is higher than the effective concentration of p-type impurities in the body region 12, for example. The first contact region 18 penetrates the second contact region 19 and contacts the body region 12 . First contact region 18 constitutes first main surface 1 . The effective concentration of the p-type impurity in the first contact region 18 is, for example, 1×10 ¹⁸ cm ⁻³ or more and 1×10 ²⁰ cm ⁻³ or less.

A gate trench 5 defined by a side surface 3 and a bottom surface 4 is provided in the first main surface 1 . Side surface 3 penetrates source region 13 , body region 12 , current diffusion region 14 and drift region 11 to reach third electric field relaxation region 16 . The bottom surface 4 is continuous with the side surfaces 3 . Bottom surface 4 is located in third electric field relaxation region 16 . The bottom surface 4 is, for example, a plane parallel to the second main surface 2 . An angle θ1 of the side surface 3 with respect to the plane including the bottom surface 4 is, for example, 45° or more and 65° or less. The angle θ1 may be, for example, 50° or more. The angle θ1 may be, for example, 60° or less. Side 3 preferably has a {0-33-8} plane. The {0-33-8} plane is a crystal plane that provides excellent mobility. The gate trenches 5 extend, for example, in stripes along the first direction parallel to the first main surface 1 . A plurality of gate trenches 5 are provided at regular intervals in a second direction perpendicular to the first direction when viewed in plan from a direction perpendicular to the first main surface 1 . A plurality of gate trenches 5 may be provided, for example in an array.

The third electric field relaxation region 16 contains p-type impurities such as aluminum and has p-type conductivity. A third electric field relaxation region 16 is between the current spreading region 14 and the second main surface 2 . When viewed from the direction perpendicular to first main surface 1 , third electric field relaxation region 16 includes a portion overlapping gate trench 5 . For example, the third electric field relaxation region 16 is between the bottom surface 4 of the gate trench 5 and the second main surface 2, and the top surface of the third electric field relaxation region 16 includes the bottom surface 4 of the gate trench 5, for example. A portion of the upper end surface of the third electric field relaxation region 16 faces a portion of the lower end surface of the current diffusion region 14 . The third electric field relaxation region 16 is further away from the gate trench 5 than the first position 91 where the current diffusion region 14 , the body region 12 and the side surface 3 are in contact with each other when viewed from the direction perpendicular to the first main surface 1 . It has a side end face 92 on the facing side. The third electric field relaxation region 16 may be electrically connected to the source electrode 60 . The effective p-type impurity concentration of the third electric field relaxation region 16 is, for example, 5×10 ¹⁷ cm ⁻³ or more and 5×10 ¹⁸ cm ⁻³ or less. A peak depth D1 of the effective concentration of the p-type impurity in the third electric field relaxation region 16 with respect to the first main surface 1 is, for example, 1.0 μm or less. The peak depth D1 may be 0.8 μm or more and 1.0 μm or less. The thickness of the third electric field relaxation region 16 in the direction perpendicular to the first main surface 1 may be 0.4 μm or more and 0.6 μm or less.

Also, the third electric field relaxation region 16 has a third region 16A and a fourth region 16B. Third region 16</b>A is positioned closer to second main surface 2 than bottom surface 4 of gate trench 5 . The fourth region 16B protrudes from the third region 16A toward the first main surface 1 side. The fourth region 16</b>B is between the first position 91 and the side end surface 92 when viewed from the direction perpendicular to the first main surface 1 . The lower end face of the current diffusion region 14 includes a recessed portion toward the first main surface 1 along the fourth region 16B. The fourth region 16B is provided, for example, in the vicinity of the portion of the side end surface 92 that contacts the second region 11D of the drift region 11, and in the vicinity of the portion of the side end surface 92 that contacts the second electric field relaxation region 31: It may not be provided (see FIG. 24).

The first electric field relaxation region 17 contains p-type impurities such as aluminum and has p-type conductivity. The first electric field relaxation region 17 sandwiches the body region 12 with the side surface 3 . That is, body region 12 is between side surface 3 and first electric field relaxation region 17 in the direction parallel to first main surface 1 . The first electric field relaxation region 17 is on the side farther from the gate trench 5 than the body region 12 is. First electric field relaxation region 17 is connected to body region 12 . The first electric field relaxation region 17 is closer to the second main surface 2 than the first contact region 18 and the second contact region 19 are. The first electric field relaxation region 17 has a first region 15 overlapping the first contact region 18 when viewed from the direction perpendicular to the first main surface 1 . The first electric field relaxation region 17 may also overlap the second contact region 19 when viewed from above in a direction perpendicular to the first main surface 1 .

The lower end surface 93 of the first electric field relaxation region 17 is closer to the second main surface 2 than the lower end surface 94 of the body region 12 is. That is, the depth D3 of the lower end surface 93 with respect to the first main surface 1 is greater than the depth D2 of the lower end surface 94 . A lower end surface 93 of the first electric field relaxation region 17 is closer to the first main surface 1 than an upper end surface 95 of the third region 16A of the third electric field relaxation region 16 . That is, the lower end surface 93 of the first electric field relaxation region 17 is closer to the first main surface 1 than the bottom surface 4 of the gate trench 5 . The first electric field relaxation region 17 may penetrate through the current spreading region 14 . The effective concentration of the p-type impurity in the first electric field relaxation region 17 is preferably 1×10 ¹⁸ cm ⁻³ or more and 2×10 ¹⁹ cm ^{−3 or} less. This is to obtain good breakdown voltage and short-circuit resistance. Further, when the effective concentration of the p-type impurity in the first electric field relaxation region 17 is 1×10 ¹⁸ cm ⁻³ or more and 2×10 ¹⁹ cm ⁻³ or less, the current diffusion region 14 can be easily secured.

A fifth region 11</b>C of the drift region 11 is between the current spreading region 14 and the third electric field relaxation region 16 . The fifth region 11C is in contact with the current diffusion region 14 and the third electric field relaxation region 16. As shown in FIG. The fifth region 11C is closer to the second main surface 2 than the current diffusion region 14 is. The fifth region 11C is closer to the first main surface 1 than the third electric field relaxation region 16 is. The effective n-type impurity concentration of the fifth region 11C is, for example, 5×10 ¹⁵ cm ⁻³ or more and 5×10 ¹⁶ cm ^{−3 or} less.

The second region 11D is closer to the second main surface 2 than the fifth region 11C. The second region 11D is continuous with the fifth region 11C. The second region 11D is in contact with the third electric field relaxation region 16 in the direction parallel to the second main surface 2. As shown in FIG. The second region 11</b>D and the third electric field relaxation region 16 may be positioned on the same plane parallel to the second main surface 2 . The effective n-type impurity concentration of the second region 11D may be higher than the effective n-type impurity concentration of the fifth region 11C. The effective n-type impurity concentration of the second region 11D is, for example, 5×10 ¹⁶ cm ⁻³ or more and 5×10 ¹⁷ cm ⁻³ or less.

The sixth region 11E is closer to the second main surface 2 than the second region 11D. The sixth region 11E is continuous with the second region 11D. The sixth region 11E is in contact with the third electric field relaxation region 16. As shown in FIG. The sixth region 11E is closer to the second main surface 2 than the third electric field relaxation region 16 is. Sixth region 11E may be between second region 11D and silicon carbide single-crystal substrate 50 . Sixth region 11E may continue to silicon carbide single-crystal substrate 50 . The effective n-type impurity concentration of the sixth region 11E may be lower than the effective n-type impurity concentration of the second region 11D. The effective n-type impurity concentration of the sixth region 11E is, for example, 5×10 ¹⁵ cm ⁻³ or more and 5×10 ¹⁶ cm ^{−3 or} less.

The gate insulating film 81 is, for example, an oxide film. The gate insulating film 81 is made of a material containing silicon dioxide, for example. Gate insulating film 81 contacts side surface 3 and bottom surface 4 . Gate insulating film 81 is in contact with third electric field relaxation region 16 at bottom surface 4 . Gate insulating film 81 is in contact with each of source region 13 , body region 12 , current diffusion region 14 and fifth region 11</b>C on side surface 3 . Gate insulating film 81 may be in contact with source region 13 on first main surface 1 .

A gate electrode 82 is provided on the gate insulating film 81 . The gate electrode 82 is made of, for example, polysilicon (poly-Si) containing conductive impurities. Gate electrode 82 is arranged inside gate trench 5 . A portion of gate electrode 82 may be arranged on first main surface 1 .

The interlayer insulating film 83 is provided in contact with the gate electrode 82 and the gate insulating film 81 . The interlayer insulating film 83 is made of a material containing silicon dioxide, for example. Interlayer insulating film 83 electrically insulates gate electrode 82 and source electrode 60 . A portion of the interlayer insulating film 83 may be provided inside the gate trench 5 .

Contact holes 86 are formed in the interlayer insulating film 83 and the gate insulating film 81 at regular intervals in the second direction. The contact holes 86 are provided such that the gate trenches 5 are positioned between the contact holes 86 adjacent in the second direction when viewed in plan from the direction perpendicular to the first main surface 1 . Contact hole 86 extends in the first direction. Source region 13 , first contact region 18 and second contact region 19 are exposed from interlayer insulating film 83 and gate insulating film 81 through contact hole 86 . The first contact regions 18 do not have to be arranged all over in the first direction (longitudinal direction of the gate trench 5). For example, they are arranged periodically as shown in FIGS. good.

The second electric field relaxation region 31 contains p-type impurities such as aluminum and has p-type conductivity. The second electric field relaxation region 31 is provided closer to the second main surface 2 than the first electric field relaxation region 17 is. The second electric field relaxation regions 31 are located between the third electric field relaxation regions 16 adjacent in the second direction, and are in contact with both of the third electric field relaxation regions 16 adjacent in the second direction. The second electric field relaxation region 31 and the third electric field relaxation region 16 may be positioned on the same plane parallel to the second main surface 2 . The second electric field relaxation regions 31 are arranged periodically in the first direction. The second electric field relaxation regions 31 are arranged, for example, with the same period as the first contact regions 18 in the first direction. The second electric field relaxation region 31 surrounds the first region 15 when viewed from above in a direction perpendicular to the first main surface 1 . The effective p-type impurity concentration of the second electric field relaxation region 31 may be substantially the same as the effective p-type impurity concentration of the third electric field relaxation region 16 . The effective concentration of the p-type impurity in the second electric field relaxation region 31 is, for example, 1×10 ¹⁷ cm ⁻³ or more and 5×10 ¹⁸ cm ⁻³ or less.

The connection region 32 contains a p-type impurity such as aluminum and has a p-type conductivity. The connection region 32 is located between the second electric field relaxation region 31 and the first electric field relaxation region 17 in the direction perpendicular to the second main surface 2, and is located between the second electric field relaxation region 31 and the first electric field relaxation region 17. bordering on The connection region 32 is located on the second main surface 2 side of the first electric field relaxation region 17 . The connection region 32 is located on the first main surface 1 side of the second electric field relaxation region 31 . The connection regions 32 are arranged periodically in the first direction, similarly to the second electric field relaxation regions 31 . The connection regions 32 are arranged with the same period as the second electric field relaxation regions 31 in the first direction. Two edges of the connection region 32 may be located between two edges of the first contact region 18 in the first direction when viewed in plan from a direction perpendicular to the first main surface 1 . Two edges of the connection region 32 may overlap two edges of the second contact region 19 in the second direction when viewed in plan from a direction perpendicular to the first main surface 1 . The effective concentration of the p-type impurity in the connection region 32 is, for example, 1×10 ¹⁷ cm ⁻³ or more and 5×10 ¹⁸ cm ⁻³ or less.

The first contact region 18 is in contact with the body region 12 , the body region 12 is in contact with the first electric field relaxation region 17 , the first electric field relaxation region 17 is in contact with the connection region 32 , and the connection region 32 is in contact with the second electric field relaxation region 31 . , the connection region 32 is in contact with the third electric field relaxation region 16 . Thus, the third electric field relaxation region 16 is electrically connected to the first contact region 18 .

The barrier metal film 84 covers the upper surface and side surfaces of the interlayer insulating film 83 and the side surfaces of the gate insulating film 81 . Barrier metal film 84 is in contact with each of interlayer insulating film 83 and gate insulating film 81 . The barrier metal film 84 is made of a material containing titanium nitride (TiN), for example.

Source electrode 60 contacts first main surface 1 . The source electrode 60 has a contact electrode 61 and a source wiring 62 . The contact electrode 61 may be in contact with the source region 13 , the first contact region 18 and the second contact region 19 on the first main surface 1 . The contact electrode 61 is made of a material containing nickel silicide (NiSi), for example. Contact electrode 61 may be made of a material containing titanium, aluminum, and silicon. The contact electrode 61 is in ohmic contact with the second contact region 19 . The contact electrode 61 may be in ohmic contact with the first contact region 18 . The source wiring 62 covers the top and side surfaces of the barrier metal film 84 and the top surface of the contact electrode 61 . Source wiring 62 is in contact with each of barrier metal film 84 and contact electrode 61 . The source wiring 62 is made of a material containing aluminum, for example.

A passivation film 85 covers the upper surface of the source line 62 . The passivation film 85 is in contact with the source wiring 62 . The passivation film 85 is made of a material containing polyimide, for example.

Drain electrode 70 is in contact with second main surface 2 . Drain electrode 70 is in contact with silicon carbide single-crystal substrate 50 at second main surface 2 . Drain electrode 70 is electrically connected to drift region 11 . The drain electrode 70 is made of a material containing nickel silicide, for example. Drain electrode 70 may be made of a material containing titanium, aluminum, and silicon. Drain electrode 70 is in ohmic contact with silicon carbide single crystal substrate 50 .

The top surface of the third electric field relaxation region 16 may be separated from the bottom surface 4 in the direction perpendicular to the second main surface 2 . In this case, for example, bottom surface 4 may be located in drift region 11 , and side surface 3 may extend through source region 13 , body region 12 and current diffusion region 14 to drift region 11 . For example, there may be a fifth region 11C between the top surface of the third electric field relaxation region 16 and the bottom surface 4 .

A buffer layer containing n-type impurities such as nitrogen and having n-type conductivity may be provided between silicon carbide single-crystal substrate 50 and sixth region 11E. The effective n-type impurity concentration of the buffer layer may be higher than the effective n-type impurity concentration of the sixth region 11E.

In the present disclosure, the effective concentration of p-type impurities is the difference between the concentration of p-type impurities and the concentration of n-type impurities, and the effective concentration of n-type impurities is the concentration of n-type impurities and the concentration of p-type impurities. is the difference between The effective concentration can be measured, for example, by procedures 1 to 4 below.

(Procedure 1) Identify the element region by observing the surface of the semiconductor device.

(Procedure 2) The semiconductor device is processed so that the cross section of the semiconductor region shown in FIG. 2 appears. For example, a focused ion beam (FIB) device is used to process a cross section of a semiconductor device.

(Procedure 3) Using a scanning electron microscope (SEM), it is determined whether the conductivity type of the impurity-implanted region is p-type or n-type. For example, when SEM observation is performed under the conditions of an acceleration voltage of 3 kV and a magnification of 10000 times, the bright region is the p-type region and the dark region is the n-type region.

(Procedure 4) The impurity concentration of the p-type region and the n-type region in the cross section is measured using a scanning spreading resistance microscopy (SSRM). The concentration of the p-type region is the effective concentration of p-type impurities, and the concentration of the n-type region is the effective concentration of n-type impurities.

Next, a method for manufacturing the MOSFET 100 according to the embodiment will be described. 6 to 23 are cross-sectional views showing the method of manufacturing the MOSFET 100 according to the embodiment. 6 to 8, 10 to 12, 15 to 16, and 18 to 23 correspond to cross-sectional views taken along line I-I in FIG. 5, like FIG. 9, 13 and 17 correspond to cross-sectional views taken along line II-II in FIG. 5, like FIG. 14, like FIG. 4, corresponds to a cross-sectional view taken along line IV-IV in FIG.

First, as shown in FIG. 6, silicon carbide single crystal substrate 50 is prepared. Silicon carbide single crystal substrate 50 is prepared by slicing a silicon carbide ingot (not shown) manufactured by, for example, a sublimation method. A buffer layer (not shown) may be formed on silicon carbide single crystal substrate 50 . The buffer layer is formed by chemical vapor deposition (CVD) using, for example, a mixed gas of silane (SiH ₄ ) and propane (C ₃ H ₈ ) as a source gas and hydrogen (H ₂ ) as a carrier gas. ) method. During the epitaxial growth of the buffer layer, an n-type impurity such as nitrogen may be introduced into the buffer layer.

Next, as also shown in FIG. 6, an epitaxial layer 21 is formed. Epitaxial layer 21 is formed on silicon carbide single crystal substrate 50 by a CVD method using, for example, a mixed gas of silane and propane as a raw material gas and hydrogen, for example, as a carrier gas. During epitaxial growth, an n-type impurity such as nitrogen is introduced into the epitaxial layer 21 . Epitaxial layer 21 has n-type conductivity. The effective n-type impurity concentration of epitaxial layer 21 may be lower than the effective n-type impurity concentration of the buffer layer.

Next, as shown in FIG. 7, a mask layer 150 having openings 151 is formed over regions where the third electric field relaxation region 16 and the second electric field relaxation region 31 are to be formed. The mask layer 150 is made of a material containing silicon dioxide, for example. In the formation of the mask layer 150, after the silicon dioxide film is formed, the silicon dioxide film is etched using a photoresist mask. This etching is performed under the condition that the lower end of the opening 151 has a smaller opening area than the upper end.

Next, as shown in FIGS. 8 and 9, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into the epitaxial layer 21 . Thereby, the third electric field relaxation region 16 and the second electric field relaxation region 31 are formed. Each of the third electric field relaxation region 16 and the second electric field relaxation region 31 is formed inside the epitaxial layer 21 so as not to be exposed on the surface of the epitaxial layer 21 . The third electric field relaxation region 16 and the second electric field relaxation region 31 may be formed simultaneously or separately. The implantation energy of the p-type impurity ions for forming the third electric field relaxation region 16 and the second electric field relaxation region 31 may be 700 keV or more and 1200 keV or less. The peak depth of the effective p-type impurity concentration of the third electric field relaxation region 16 and the second electric field relaxation region 31 with respect to the first main surface 1 may be, for example, 0.8 μm or more and 1.0 μm or less. .

The opening area of the opening 151 of the mask layer 150 used for forming the third electric field relaxation region 16 and the second electric field relaxation region 31 is smaller at the lower end than at the upper end. Therefore, the third electric field relaxation region 16 is likely to be formed shallower than the center of the opening 151 on the second main surface 2 side of the side wall surface of the opening 151, and has the third region 16A and the fourth region 16B. It is formed.

Next, as shown in FIG. 10, body regions 12 are formed. For example, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into the entire surface of the epitaxial layer 21 . Thereby, body region 12 is formed. The implantation energy of p-type impurity ions in forming body region 12 may be set to 200 keV or more and 400 keV or less. The thickness of the body region 12 is, for example, 0.2 μm or more and 0.5 μm or less.

Next, as shown in FIG. 11, current spreading regions 14 are formed. For example, n-type impurity ions capable of imparting n-type, such as phosphorus ions, are implanted into the entire surface of the epitaxial layer 21 . Thereby, a current diffusion region 14 is formed. The implantation energy of the n-type impurity ions for forming the current diffusion region 14 may be 300 keV or more and 800 keV or less.

Next, as shown in FIG. 12, source regions 13 are formed. For example, n-type impurity ions capable of imparting n-type, such as phosphorus ions, are implanted into the entire surface of the epitaxial layer 21 . A source region 13 is thus formed. The implantation energy of the n-type impurity ions in forming the source region 13 may be 50 keV or more and 150 keV or less. The thickness of the source region 13 is, for example, 0.1 μm or more and 0.3 μm or less.

Next, as shown in FIGS. 13, 14 and 24, connection regions 32 are formed. For example, a mask layer (not shown) having openings over the regions where the connection regions 32 are to be formed is formed. Next, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into the drift region 11 . Thereby, the connection region 32 is formed. The implantation energy of the p-type impurity ions in forming the connection region 32 may be 400 keV or more and 900 keV or less. FIG. 24 is a schematic diagram showing the positional relationship among the connection region 32, the second electric field relaxation region 31, the third electric field relaxation region 16, the first contact region 18 and the second contact region 19. FIG. FIG. 13 corresponds to a cross-sectional view taken along line XIII-XIII in FIG. FIG. 14 corresponds to a cross-sectional view taken along line XIV-XIV in FIG.

Next, as shown in FIG. 15, a first electric field relaxation region 17 is formed. For example, a mask layer (not shown) having an opening is formed on the region where the first electric field relaxation region 17 is to be formed. Next, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into the epitaxial layer 21 . Thereby, the first electric field relaxation region 17 is formed. The implantation energy of the p-type impurity ions for forming the first electric field relaxation region 17 may be 300 keV or more and 800 keV or less.

Next, as shown in FIG. 16, second contact regions 19 are formed. For example, a mask layer (not shown) having openings over the regions where the second contact regions 19 are to be formed is formed. Next, n-type impurity ions capable of imparting n-type, such as phosphorus ions, are implanted into the epitaxial layer 21 . Thereby, the second contact region 19 is formed. The implantation energy of the n-type impurity ions in forming the second contact region 19 may be 100 keV or more and 300 keV or less. The mask layer used for forming the first electric field relaxation region 17 may be used for forming the second contact region 19 as it is.

Next, as shown in FIG. 17, first contact regions 18 are formed. For example, a mask layer (not shown) having openings over the regions where the first contact regions 18 are to be formed is formed. Next, p-type impurity ions capable of imparting p-type, such as aluminum ions, are implanted into the second contact region 19 and the body region 12 . Thereby, a first contact region 18 in contact with the body region 12 is formed. The implantation energy of the p-type impurity ions in forming the first contact region 18 may be 50 keV or more and 300 keV or less. Drift region 11 is composed of a portion of epitaxial layer 21 in which impurity ions have not been implanted after formation of epitaxial layer 21 .

Activation annealing is then performed to activate the impurity ions implanted into silicon carbide substrate 10 . The temperature of the activation annealing is preferably 1500°C or higher and 1900°C or lower, for example, about 1700°C. The activation annealing time is, for example, about 30 minutes. The atmosphere for the activation annealing is preferably an inert gas atmosphere such as an argon (Ar) atmosphere.

Next, as shown in FIG. 18, gate trenches 5 are formed. For example, a mask layer (not shown) having openings on positions where the gate trenches 5 are to be formed is formed on the first main surface 1 . Using a mask layer, a portion of source region 13, a portion of body region 12, a portion of current spreading region 14, and a portion of drift region 11 are etched away. As an etching method, for example, reactive ion etching, especially inductively coupled plasma reactive ion etching can be used. Specifically, for example, inductively coupled plasma reactive ion etching using sulfur hexafluoride (SF ₆ ) or a mixed gas of SF ₆ and oxygen (O ₂ ) as a reactive gas can be used. By etching, in the region where the gate trench 5 is to be formed, a side portion substantially perpendicular to the first main surface 1 and a bottom portion provided continuously with the side portion and substantially parallel to the first main surface 1 are formed. A recess (not shown) having a is formed.

A thermal etch is then performed in the recess. Thermal etching can be performed, for example, by heating in an atmosphere containing a reactive gas having at least one type of halogen atom while the mask layer is formed on the first main surface 1 . The at least one halogen atom includes at least one of chlorine (Cl) and fluorine (F) atoms. The atmosphere includes, for example, chlorine (Cl ₂ ), boron trichloride (BCl ₃ ), SF ₆ or carbon tetrafluoride (CF ₄ ). For example, a mixed gas of chlorine gas and oxygen gas is used as a reaction gas, and thermal etching is performed at a heat treatment temperature of, for example, 800° C. or higher and 900° C. or lower. Note that the reaction gas may contain a carrier gas in addition to the chlorine gas and the oxygen gas described above. As the carrier gas, for example, nitrogen gas, argon gas, helium gas, or the like can be used.

Gate trench 5 is formed in first main surface 1 of silicon carbide substrate 10 by the thermal etching described above. Gate trench 5 is defined by side surfaces 3 and a bottom surface 4 . Side surface 3 is composed of source region 13 , body region 12 , current diffusion region 14 and drift region 11 . The bottom surface 4 is composed of a third electric field relaxation region 16 . An angle θ1 between the side surface 3 and the plane including the bottom surface 4 is, for example, 45° or more and 65° or less. The mask layer is then removed from the first major surface 1 .

Next, as shown in FIG. 19, gate insulating film 81 is formed. For example, by thermally oxidizing the silicon carbide substrate 10, the source region 13, the body region 12, the current diffusion region 14, the drift region 11, the third electric field relaxation region 16, the first contact region 18, and the second A gate insulating film 81 is formed in contact with contact region 19 . Specifically, silicon carbide substrate 10 is heated, for example, at a temperature of 1300° C. or more and 1400° C. or less in an atmosphere containing oxygen. As a result, the gate insulating film 81 is formed in contact with the first main surface 1, the side surface 3 and the bottom surface 4. Next, as shown in FIG. When gate insulating film 81 is formed by thermal oxidation, strictly speaking, part of silicon carbide substrate 10 is taken into gate insulating film 81 . Therefore, in the subsequent processing, it is assumed that first main surface 1, side surface 3 and bottom surface 4 have slightly moved to the interface between gate insulating film 81 and silicon carbide substrate 10 after thermal oxidation.

Next, heat treatment (NO annealing) may be performed on silicon carbide substrate 10 in a nitrogen monoxide (NO) gas atmosphere. In the NO annealing, silicon carbide substrate 10 is held under conditions of, for example, 1100° C. or more and 1400° C. or less for about one hour. Thereby, nitrogen atoms are introduced into the interface region between gate insulating film 81 and body region 12 . As a result, the channel mobility can be improved by suppressing the formation of interface states in the interface region.

After the NO anneal, Ar anneal using argon (Ar) as the ambient gas may be performed. The heating temperature for Ar annealing is, for example, higher than the heating temperature for NO annealing. The Ar annealing time is, for example, about one hour. This further suppresses the formation of an interface state in the interface region between gate insulating film 81 and body region 12 . As the atmosphere gas, other inert gas such as nitrogen gas may be used instead of Ar gas.

Next, as shown in FIG. 20, gate electrode 82 is formed. A gate electrode 82 is formed on the gate insulating film 81 . The gate electrode 82 is formed by, for example, a low pressure CVD (Low Pressure-Chemical Vapor Deposition: LP-CVD) method. Gate electrode 82 is formed to face each of source region 13 , body region 12 , current diffusion region 14 and drift region 11 .

Next, as shown in FIG. 21, an interlayer insulating film 83 is formed. Specifically, interlayer insulating film 83 is formed to cover gate electrode 82 and to be in contact with gate insulating film 81 . The interlayer insulating film 83 is formed by, for example, the CVD method. The interlayer insulating film 83 is made of a material containing silicon dioxide, for example. A portion of interlayer insulating film 83 may be formed inside gate trench 5 .

Next, as shown in FIG. 22, contact holes 86 are formed in the interlayer insulating film 83 and the gate insulating film 81 . The first contact region 18 and the second contact region 19 are exposed through the contact hole 86 from the interlayer insulating film 83 and the gate insulating film 81 . Source region 13 preferably remains covered with gate insulating film 81 and interlayer insulating film 83 .

Next, as shown in FIG. 23, barrier metal film 84, contact electrode 61 and drain electrode 70 are formed. For example, a barrier metal film 84 is formed to cover the upper and side surfaces of the interlayer insulating film 83 and the side surfaces of the gate insulating film 81 . Source region 13 is preferably located inside the side end surface of barrier metal film 84 when viewed in plan from a direction perpendicular to first main surface 1 . The barrier metal film 84 is made of a material containing titanium nitride, for example. The barrier metal film 84 is formed by, for example, film formation by sputtering and reactive ion etching (RIE). Next, a metal film (not shown) for the contact electrode 61 in contact with the first contact region 18 and the second contact region 19 is formed on the first main surface 1 . A metal film for the contact electrode 61 is formed by, for example, a sputtering method. The metal film for the contact electrode 61 is made of a material containing nickel, for example. Next, a metal film (not shown) for drain electrode 70 is formed in contact with silicon carbide single crystal substrate 50 on second main surface 2 . A metal film for the drain electrode 70 is formed by, for example, a sputtering method. The metal film for the drain electrode 70 is made of a material containing nickel, for example.

An alloying anneal is then performed. The metal film for the contact electrode 61 and the metal film for the drain electrode 70 are held at a temperature of, for example, 900° C. or more and 1100° C. or less for about 5 minutes. As a result, at least part of the metal film for contact electrode 61 and at least part of the metal film for drain electrode 70 react with silicon contained in silicon carbide substrate 10 to be silicided. Thereby, contact electrode 61 in ohmic contact with second contact region 19 and drain electrode 70 in ohmic contact with silicon carbide single crystal substrate 50 are formed. If the source region 13 is inside the side end surface of the barrier metal film 84 when viewed in plan from the direction perpendicular to the first main surface 1 , the contact electrode 61 is arranged such that the side end surface of the contact electrode 61 is located between the source region 13 and the first main surface 1 . It is formed so as to be separated from the gate trench 5 more than the interface with the two contact regions 19 . Although part of the second contact region 19 is consumed for silicidation, the source region 13 is not consumed because the source region 13 is covered with the gate insulating film 81 and the interlayer insulating film 83 . The contact electrode 61 may be in ohmic contact with the first contact region 18 . Contact electrode 61 may be made of a material containing titanium, aluminum, and silicon. Drain electrode 70 may be made of a material containing titanium, aluminum, and silicon.

Next, source wiring 62 is formed. Specifically, the source wiring 62 covering the contact electrode 61 and the barrier metal film 84 is formed. The source wiring 62 is formed by film formation and RIE, for example, by a sputtering method. The source wiring 62 is made of a material containing aluminum, for example. Thus, the source electrode 60 having the contact electrode 61 and the source wiring 62 is formed.

Next, a passivation film 85 is formed. Specifically, a passivation film 85 covering the source wiring 62 is formed. The passivation film 85 is made of a material containing polyimide, for example. The passivation film 85 is formed by, for example, a coating method.

Thus, the MOSFET 100 according to the embodiment is completed.

Next, the effects of the MOSFET according to this embodiment will be described.

In the MOSFET 100 according to the present embodiment, the peak depth of the effective p-type impurity concentration of the third electric field relaxation region 16 is 1.0 μm or less with respect to the first main surface 1 . Therefore, the source region 13, the body region 12, the current diffusion region 14, the drift region 11, and the third electric field relaxation region 16 can be appropriately formed by ion implantation without forming epitaxial layers multiple times. Further, when viewed in plan from the direction perpendicular to the first main surface 1, the first electric field relaxation region 17 has the first region 15 overlapping with the first contact region 18, and the second electric field relaxation region 31 is the first region. Surrounding area 15 . Therefore, even if the first contact region 18 contains many crystal defects due to high-concentration ion implantation or the like, it is possible to suppress the drain leak through the crystal defects.

When the peak depth D1 is small, it is not necessary to regrow the epitaxial layer after forming the third electric field relaxation region 16, unlike the manufacturing method described above. Therefore, the cost associated with regrowth of the epitaxial layer can be reduced. Also, high-energy ion implantation is not required when forming the third electric field relaxation region 16 . Therefore, it is possible to avoid an increase in cost associated with high-energy ion implantation.

Also, the smaller the first thickness T1 of the source region 13 is, the smaller the drain current at the time of a short circuit is and the more the short circuit resistance can be improved. On the other hand, since the second thickness T2 of the second contact region 19 is larger than the first thickness T1, even if a part of the second contact region 19 is consumed during the formation of the contact electrode 61, the contact electrode 61 is It is easy to ohmically contact the source electrode 60 containing the .

The third electric field relaxation region 16 and the body region 12 are electrically connected to each other via the second electric field relaxation region 31 , the connection region 32 and the first electric field relaxation region 17 . Therefore, the third electric field relaxation region 16 and the body region 12 are set at the same potential to easily suppress drain leakage. Also, the second electric field relaxation regions 31 and the connection regions 32 are periodically arranged in the first direction. Therefore, it is easy to suppress the drain leak while ensuring a sufficient current path for the on-current.

In addition, in the first direction, the first length L1 of the second electric field relaxation region 31 is preferably equal to or less than the second length L2 of the second region 11D of the drift region 11 . This is because it is easy to secure a current path for an on-current. Also, the first length L1 is preferably 20% or more and 40% or less, more preferably 25% or more and 35% or less, of the sum of the first length L1 and the second length L2. This is because it is particularly easy to achieve both securing of a current path for on-current and suppression of drain leakage.

In this embodiment, the third electric field relaxation region 16 includes the fourth region 16B. Therefore, even if a high drain voltage is applied in the off state, it is easy to suppress penetration of an electric field into the body region 12 and drain leakage.

The lower end surface 93 of the first electric field relaxation region 17 may be closer to the first main surface 1 than the upper end surface 95 of the third region 16A of the third electric field relaxation region 16 . Therefore, the current diffusion region 14 and the fifth region 11C of the drift region 11 are sandwiched between the fourth region 16B of the third electric field relaxation region 16 and the first electric field relaxation region 17, and drain leakage is easily suppressed.

The third electric field relaxation region 16 and the first electric field relaxation region 17 are electrically connected to each other through the second electric field relaxation region 31 and the connection region 32 . Therefore, the third electric field relaxation region 16 and the first electric field relaxation region 17 are set at the same potential, so that drain leakage can be easily suppressed.

Further, by increasing the effective concentration of the n-type impurity in the current diffusion region 14, even if the fourth region 16B is provided, an increase in on-resistance can be suppressed.

[Modification]
Next, modifications of the embodiment will be described. The modification differs from the embodiment mainly in the shape of the gate trench. FIG. 25 is a cross-sectional view showing the configuration of a MOSFET (silicon carbide semiconductor device) according to a modification of the embodiment. FIG. 25 shows a section similar to the section along line II in FIG.

As shown in FIG. 25, in the MOSFET 200 according to the modification, the gate trench 5 is a vertical trench. That is, the angle θ1 of the side surface 3 with respect to the plane including the bottom surface 4 may be 90°. Other configurations are the same as in the embodiment.

Such a modified example can also provide the same effects as the embodiment.

In the above embodiments and reference examples, the n-type is the first conductivity type and the p-type is the second conductivity type. good. In the above embodiments and reference examples, a MOSFET is described as an example of a silicon carbide semiconductor device, but the silicon carbide semiconductor device may be, for example, an insulated gate bipolar transistor (IGBT) or the like. The effective concentration of the p-type impurity and the effective concentration of the n-type impurity in each of the impurity regions can be determined, for example, by a scanning capacitance microscope (SCM) method or a secondary ion mass spectrometry (SIMS) method. etc., can be measured. The position of the interface between the p-type region and the n-type region (that is, the pn junction interface) can be specified by, for example, the SCM method or the SIMS method. The distribution of the effective concentration of majority carriers in the current diffusion region can be identified, for example, based on the thickness distribution of the depletion layer generated by the pn junction between the current diffusion region and the body region without measuring the effective concentration. The thickness of the depletion layer can be specified by, for example, the SCM method or the SIMS method.

The gate trenches may extend in a honeycomb shape, or may be scattered like islands.

Although the embodiment has been described in detail above, it is not limited to a specific embodiment, and various modifications and changes are possible within the scope described in the claims.

Reference Signs List 1 first main surface 2 second main surface 3 side surface 4 bottom surface 5 gate trench 10 silicon carbide substrate 11 drift region 11C fifth region 11D second region 11E sixth region 12 body region 13 source region 14 current diffusion region 15 first region 16 third electric field relaxation region 16A third region 16B fourth region 17 first electric field relaxation region 18 first contact region 19 second contact region 21 epitaxial layer 31 second electric field relaxation region 32 connection region 40 silicon carbide epitaxial layer 50 silicon carbide Single crystal substrate 60 source electrode 61 contact electrode 62 source wiring 70 drain electrode 81 gate insulating film 82 gate electrode 83 interlayer insulating film 84 barrier metal film 85 passivation film 86 contact hole 91 first position 92 side end face 93, 94, 96, 97 Lower end surface 95 Upper end surface 100, 200 MOSFET
150 mask layer 151 opening

Claims (9)

A silicon carbide substrate having a first main surface and a second main surface opposite to the first main surface,
The silicon carbide substrate is
a drift region having a first conductivity type;
a body region provided on the drift region and having a second conductivity type different from the first conductivity type;
a source region having the first conductivity type provided on the body region so as to be separated from the drift region;
has
The first main surface is provided with a gate trench defined by a side surface extending through the source region and the body region to the drift region and a bottom surface continuous with the side surface,
The silicon carbide substrate is
a first contact region that sandwiches the source region between itself and the side surface, is connected to the body region, and has the second conductivity type;
a first region overlapping with the first contact region when viewed in plan from a direction perpendicular to the first main surface; provided on the second main surface side of the body region; connected to the body region; a first electric field relaxation region having a second conductivity type;
A second conductive-type second semiconductor device surrounding the first region when viewed in plan from a direction perpendicular to the first main surface, provided closer to the second main surface than the first electric field relaxation region, and having the second conductivity type an electric field relaxation region;
a third electric field relaxation region provided between the gate trench and the second main surface and having the second conductivity type;
further having
The silicon carbide semiconductor device, wherein the peak depth of the effective concentration of the impurity of the second conductivity type in the third electric field relaxation region is 1.0 μm or less with respect to the first main surface. The silicon carbide semiconductor device according to claim 1, wherein said second electric field relaxation region and said third electric field relaxation region are connected in a direction parallel to said first main surface. 3. The device according to claim 1, further comprising a connection region connected to said first electric field relaxation region and said second electric field relaxation region and electrically connecting said first electric field relaxation region and said second electric field relaxation region. Silicon carbide semiconductor device. The silicon carbide semiconductor device according to any one of claims 1 to 3, wherein the second electric field relaxation regions are arranged periodically in the longitudinal direction of the gate trench. the drift region has a second region between the second electric field relaxation regions adjacent to each other in the longitudinal direction;
5. The silicon carbide semiconductor device according to claim 4, wherein a first length of said second electric field relaxation region in said longitudinal direction is equal to or less than a second length of said second region. The silicon carbide semiconductor device according to claim 5, wherein said first length is 20% or more and 40% or less of the sum of said first length and said second length. The third electric field relaxation region is
a third region located closer to the second main surface than the bottom surface;
a fourth region protruding from the third region toward the first main surface;
has
The silicon carbide semiconductor device according to any one of claims 1 to 6, wherein a portion of said drift region is between said fourth region and said body region. The silicon carbide substrate has a second contact region provided between the source region and the first contact region, connected to the source region, and having the first conductivity type,
The silicon carbide semiconductor device according to any one of claims 1 to 7, wherein said second contact region is thicker than said source region. 9. The silicon carbide semiconductor device according to claim 1, wherein said side surface of said gate trench includes a {0-33-8} plane.

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