JP2022128561A - Gallium nitride wafer and method of manufacturing semiconductor chip - Google Patents

Abstract

To provide a method of manufacturing a semiconductor chip, capable of improving productivity.SOLUTION: In preparing a GaN wafer 1 in a method of manufacturing a semiconductor chip, the followings are performed: preparing a bulk wafer 100 that comprises GaN and has a first main surface 100a made as a gallium surface while having a second main surface 100b made as a nitrogen surface, the second main surface being on an opposing side to the first main surface 100a; preparing an auxiliary wafer 110 on which a GaN layer 112 is laminated, on a basic wafer 111 comprising a material different from GaN; separating the GaN layer from the auxiliary wafer 110 and constructing a bonded wafer 114 having a first main surface 114a made as a gallium surface while having a second main surface 114b made as a nitrogen surface, the second main surface being on an opposing side to the first main surface; and preparing a GaN wafer having one surface 1a and the other surface 1b which are made as a gallium surface, by bonding the nitrogen surface of the bulk wafer 110 and the nitrogen surface of the bonded wafer 114.SELECTED DRAWING: Figure 2D

Description

The present invention relates to a method for manufacturing a GaN wafer containing gallium nitride (hereinafter also simply referred to as GaN) and a semiconductor chip.

Conventionally, there has been proposed a manufacturing method for manufacturing semiconductor chips by forming an epitaxial film on a semiconductor wafer to form a processed wafer, forming semiconductor elements on the processed wafer, and then dividing the processed wafer into chip units (for example, See Patent Document 1). Specifically, in this manufacturing method, assuming that the epitaxial film side surface of the processed wafer is one surface and the semiconductor wafer side surface of the processed wafer is the other surface, first, a diffusion layer is formed on one surface side of the processed wafer. A one-surface-side element-constituting portion that constitutes a portion on the one-surface side of a semiconductor element such as a surface electrode or the like is formed. Next, the other surface side of the wafer to be processed is ground to a predetermined thickness, and on the other surface side of the wafer to be processed, the other surface side element forming part constituting the part of the other surface side of the semiconductor element such as the back surface electrode is formed. Form. After that, the wafer to be processed is divided into chips.

JP 2016-207908 A

By the way, the present inventors are studying a semiconductor chip comprising GaN, which has advantages such as a wide bandgap and a high electron saturation velocity. When such a semiconductor chip is manufactured using the manufacturing method described above, it is as follows.

That is, a GaN wafer is prepared as a semiconductor wafer, and an epitaxial film made of GaN is grown on the GaN wafer to form a processed wafer. Then, after forming the element constituting portions on one side of the wafer to be processed, the other side of the wafer to be processed is ground. After that, the element portion on the other side is formed, and the wafer to be processed is divided into chips.

However, in this manufacturing method, the processed wafer is ground from the other side. That is, the GaN wafer is ground. For this reason, it is necessary to prepare a GaN wafer each time a semiconductor chip is manufactured, which may reduce productivity.

SUMMARY OF THE INVENTION An object of the present invention is to provide a method of manufacturing a GaN wafer and a semiconductor chip that can improve productivity.

In claim 1 for achieving the above object, there is provided a method for manufacturing a semiconductor chip having a semiconductor element formed thereon, comprising: By preparing a wafer (1) and forming an epitaxial film (3) on one surface of the GaN wafer, one surface (10a) is on the epitaxial film side and the other surface (10b) is on the GaN wafer side. ), constructing a processed wafer (10) having a plurality of chip forming areas (RA) on one surface side, and forming an element constituting portion (11) on one surface side of a semiconductor element for the plurality of chip forming areas. and forming an altered layer (15) inside the processed wafer along the surface direction of the processed wafer by irradiating the inside of the processed wafer with a laser beam (L) from the other surface side of the processed wafer. dividing the processed wafer into a chip-constituting wafer (30) on one side of the processed wafer and a recycle wafer (40) on the other side of the processed wafer by dividing the processed wafer with the deteriorated layer as a boundary; , taking out the semiconductor chip (S1) from the chip-constituting wafer, and reusing the recycled wafer as a GaN wafer. Then, by preparing a GaN wafer, it is composed of GaN, the first main surface (100a) is a gallium surface, and the second main surface (100b) opposite to the first main surface is a nitrogen surface. providing a bulk wafer (100); providing an auxiliary wafer (110) having a GaN layer (112) laminated on a base wafer (111) composed of GaN and another material; Separating the GaN layer to construct a bonded wafer (114) having a first major surface (114a) as a gallium surface and a second major surface (114b) opposite to the first major surface as a nitrogen surface. and preparing a GaN wafer having a gallium surface on one surface and the other surface by bonding the nitrogen surface of the bulk wafer and the nitrogen surface of the bonded wafer.

According to this method, recycled wafers are reused as GaN wafers. Therefore, it is not necessary to prepare a new GaN wafer each time a semiconductor chip is manufactured, and the GaN wafer can be used effectively. Therefore, the productivity of semiconductor chips can be improved. Also, a GaN wafer having one surface and the other surface made of gallium is prepared. Therefore, it is possible to suppress the formation of fine unevenness on the other surface of the wafer to be processed when each step is performed before the laser beam is irradiated to form the altered layer. Therefore, when the laser beam is irradiated from the other surface of the wafer to be processed, irregular reflection of the laser beam from the other surface of the wafer to be processed is suppressed. As a result, it is possible to suitably form an altered layer inside the wafer to be processed, and further improve productivity.

In claim 5, a GaN wafer made of GaN, comprising one surface (1a) and the other surface (1b) opposite to the one surface, and a bulk wafer (100) arranged on the one surface side and constituting the one surface. , and a bonded wafer (114) disposed on the other side and bonded to the bulk wafer to form the other side, the one side and the other side being gallium surfaces.

According to this, when forming a processed wafer using this GaN wafer and manufacturing a semiconductor chip from the processed wafer, the productivity of the semiconductor chip can be improved by reusing the GaN wafer. Further, when manufacturing a semiconductor chip from a processed wafer, the formation of fine irregularities on the other surface of the processed wafer is suppressed. Diffuse reflection of laser light on the other surface of the wafer to be processed is suppressed. Therefore, the productivity of semiconductor chips can be improved.

It should be noted that the reference numerals in parentheses attached to each component etc. indicate an example of the correspondence relationship between the component etc. and specific components etc. described in the embodiments described later.

4A to 4C are cross-sectional views showing a manufacturing process of the semiconductor chip in the first embodiment; 1B is a cross-sectional view showing the manufacturing process of the semiconductor chip continued from FIG. 1A; FIG. FIG. 1C is a cross-sectional view showing the manufacturing process of the semiconductor chip following FIG. 1B; 1D is a cross-sectional view showing the manufacturing process of the semiconductor chip following FIG. 1C; FIG. 1D is a cross-sectional view showing the manufacturing process of the semiconductor chip following FIG. 1D; FIG. FIG. 1E is a cross-sectional view showing the manufacturing process of the semiconductor chip following FIG. 1E; 1F is a cross-sectional view showing the manufacturing process of the semiconductor chip continued from FIG. 1F; FIG. FIG. 1G is a cross-sectional view showing the manufacturing process of the semiconductor chip following FIG. 1G; FIG. 1H is a cross-sectional view showing the manufacturing process of the semiconductor chip continued from FIG. 1H; FIG. 1I is a cross-sectional view showing the manufacturing process of the semiconductor chip following FIG. 1I; 1J is a cross-sectional view showing the manufacturing process of the semiconductor chip following FIG. 1J; FIG. 1B is a cross-sectional view showing a manufacturing process of the GaN wafer shown in FIG. 1A; FIG. FIG. 2B is a cross-sectional view showing the manufacturing process of the GaN wafer following FIG. 2A; FIG. 2B is a cross-sectional view showing the manufacturing process of the GaN wafer following FIG. 2B; FIG. 2C is a cross-sectional view showing the manufacturing process of the GaN wafer following FIG. 2C; FIG. 10 is a cross-sectional view showing a manufacturing process of a GaN wafer in the second embodiment; 3B is a cross-sectional view showing the manufacturing process of the GaN wafer following FIG. 3A; FIG. FIG. 3C is a cross-sectional view showing the manufacturing process of the GaN wafer following FIG. 3B; FIG. 3C is a cross-sectional view showing the manufacturing process of the GaN wafer following FIG. 3C; FIG. 3C is a cross-sectional view showing the manufacturing process of the GaN wafer following FIG. 3D; FIG. 11 is a cross-sectional view showing a manufacturing process of a GaN wafer in the third embodiment; FIG. 4B is a cross-sectional view showing the manufacturing process of the GaN wafer following FIG. 4A; FIG. 4C is a cross-sectional view showing the manufacturing process of the GaN wafer following FIG. 4B; FIG. 4C is a cross-sectional view showing the manufacturing process of the GaN wafer following FIG. 4C; FIG. 4C is a cross-sectional view showing the manufacturing process of the GaN wafer following FIG. 4D;

An embodiment of the present invention will be described below with reference to the drawings. In addition, in each of the following embodiments, portions that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment will be described with reference to the drawings. Below, the manufacturing method of semiconductor chip S1 comprised using GaN is demonstrated.

First, as shown in FIG. 1A, a GaN wafer 1 in the form of a bulk wafer having one surface 1a and the other surface 1b is prepared. For example, the GaN wafer 1 is doped with silicon, oxygen, germanium, etc., and has an impurity concentration of 5×10 ¹⁷ to 5×10 ¹⁹ cm ⁻³ . However, in the GaN wafer 1 of the present embodiment, the impurity concentration varies discontinuously at predetermined locations in the thickness direction, as will be described later. Although the thickness of the GaN wafer 1 is arbitrary, a wafer with a thickness of about 400 μm, for example, is prepared. The GaN wafer 1 of the present embodiment has one surface 1a as a gallium surface and the other surface 1b as a gallium surface. Further, this GaN wafer 1 is prepared by reusing a recycle wafer 40 shown in FIG. 1K, which will be described later, after performing the manufacturing process of the semiconductor chip S1 described below.

Here, the process of preparing the GaN wafer 1 of this embodiment will be specifically described.

In this embodiment, as shown in FIG. 2A, a bulk wafer 100 made of GaN and having a first principal surface 100a of gallium and a second principal surface 100b of nitrogen is prepared. Then, although not shown, the second main surface 100b is polished or the like as necessary.

2A, an auxiliary wafer 110 having a GaN layer 112 disposed on a base wafer 111 is prepared as shown in FIG. 2B. In this embodiment, the base wafer 111 is composed of a silicon wafer, a sapphire wafer, a silicon carbide wafer, an aluminum nitride polycrystalline wafer, or the like. The GaN layer 112 is formed by epitaxially growing on the base wafer 111 with the buffer layer 113 interposed therebetween. The buffer layer 113 of this embodiment is formed by laminating a second underlayer 113b such as AlGaN on a first underlayer 113a formed of a Si(111) layer or the like. The buffer layer 113 is for improving the crystallinity of the GaN layer 112 and increasing the film thickness.

Next, as shown in FIG. 2C, the GaN layer 112 is separated from the auxiliary wafer 110, the GaN layer 112 is formed, and the first main surface 114a is the gallium surface and the second main surface 114b is the nitrogen surface. A bonded wafer 114 is constructed. The bonded wafer 114 is formed by, for example, grinding or polishing the base wafer 111 or the like to separate the GaN layer 112 . The bonded wafer 114 is formed by separating the GaN layer 112 from the base wafer 111 by, for example, laser slicing.

After that, as shown in FIG. 2D, the second main surface 100b of the bulk wafer 100 and the second main surface 114b of the bonded wafer 114 are bonded by direct bonding or the like. That is, the nitrogen surface of the bulk wafer 100 and the nitrogen surface of the bonded wafer 114 are bonded by direct bonding or the like. Thus, a GaN wafer 1 having one surface 1a and the other surface 1b of gallium is formed.

In addition, direct joining is performed as follows, for example. That is, first, the second main surface 100b of the bulk wafer 100 and the second main surface 114b of the bonded wafer 114 are irradiated with N ₂ plasma, O ₂ plasma, an Ar ion beam, or the like to activate the main surfaces 100b and 114b. . Then, alignment is performed by an infrared microscope or the like using appropriately formed alignment marks, and the second main surface 100b of the bulk wafer 100 and the second main surface 114b of the bonded wafer 114 are bonded together at room temperature to 550.degree. As a result, the bulk wafer 100 and the bonded wafer 114 are directly bonded to form the GaN wafer 1 .

Such a GaN wafer 1 is constructed by bonding two different wafers, a bulk wafer 100 and a bonded wafer 114 . Therefore, this GaN wafer 1 becomes a wafer in which the impurity concentration changes discontinuously at the interface between the bulk wafer 100 and the bonded wafer 114 . Moreover, this GaN wafer 1 is a wafer in which the crystal defect density changes discontinuously at the interface between the bulk wafer 100 and the bonded wafer 114 . In other words, changing discontinuously means that the value changes abruptly.

Next, as shown in FIG. 1B, an epitaxial film 3 made of GaN with a thickness of about 10 to 100 μm is formed on one surface 1a of the GaN wafer 1, thereby forming a processed wafer 10 having a plurality of chip forming regions RA. prepare. In this embodiment, the epitaxial film 3 is formed by sequentially depositing an n ⁺ -type epitaxial layer 3a and an n ⁻ -type epitaxial layer 3b from the GaN wafer 1 side. For example, the n ⁺ -type epitaxial layer 3a is doped with silicon, oxygen, germanium, or the like, and has an impurity concentration of about 5×10 ¹⁷ to 5×10 ¹⁹ cm ⁻³ . The n ⁻ -type epitaxial layer 3b is doped with silicon or the like and has an impurity concentration of approximately 1×10 ¹⁷ to 4×10 ¹⁷ cm ⁻³ .

Note that the n ⁻ -type epitaxial layer 3b is a portion where the one-side element-constituting portion 11 such as a diffusion layer 12, which will be described later, is formed, and has a thickness of, for example, about 8 to 10 μm. The n ⁺ -type epitaxial layer 3a is a portion for ensuring the thickness of the semiconductor chip S1, which will be described later, and has a thickness of about 40 to 100 μm, for example. Further, the thicknesses of the n ⁺ -type epitaxial layer 3a and the n ⁻ -type epitaxial layer 3b are arbitrary, but here, the n ⁺ -type epitaxial layer 3a is replaced with the n ⁻ -type epitaxial layer so as to secure the thickness of the semiconductor chip S1. It is thicker than layer 3b.

Hereinafter, the surface of processed wafer 10 facing epitaxial film 3 is referred to as one surface 10 a of processed wafer 10 , and the surface of processed wafer 10 facing GaN wafer 1 is referred to as second surface 10 b of processed wafer 10 . Further, as described above, in the present embodiment, the one surface 1a and the other surface 10b of the GaN wafer 1 are gallium surfaces. Each chip forming area RA is formed on the one surface 10a side of the wafer 10 to be processed.

Here, in this step, the process temperature for growing the epitaxial film 3 is about 1000.degree. For this reason, when forming each epitaxial film 3, nitrogen is easily gasified and escaped from the processed wafer 10. FIG. Specifically, nitrogen is easily released from the nitrogen surface, which is easily chemically activated. However, the processed wafer 10 of this embodiment has one surface 10a and the other surface 10b made of gallium. Therefore, in the processed wafer 10 of the present embodiment, it is difficult for nitrogen to escape from the processed wafer 10, and formation of minute irregularities on the one surface 10a and the other surface 10b is suppressed.

Next, as shown in FIG. 1C, a surface side process, which is a process for the one surface 10a side of the general semiconductor manufacturing process, is performed. Specifically, ion implantation, vapor deposition, wet processing, and the like are appropriately performed as surface-side processes, and semiconductors such as diffusion layers 12, gate electrodes 13, surface electrodes (not shown), wiring patterns, and passivation films are formed in each chip formation region RA. A step of forming the one-side element-constituting portion 11 of the element is performed. Here, semiconductor elements having various configurations are employed, for example, power devices such as vertical MOS transistors, optical semiconductor elements such as light emitting diodes, semiconductor lasers, and the like are employed. After that, a surface protection film made of resist or the like is formed on the one surface 10a side of the processed wafer 10, if necessary.

Here, in this step, there is a possibility that the chemical solution in the wet process reacts with the processed wafer 10 . Specifically, the chemically active nitrogen surface may react with the chemical solution. However, the processed wafer 10 of this embodiment has one surface 10a and the other surface 10b made of gallium. For this reason, one surface 10a and the other surface 10b of the processed wafer 10 of the present embodiment are less likely to react with the chemical solution, and the formation of fine irregularities on the one surface 10a and the other surface 10b is suppressed.

Subsequently, as shown in FIG. 1D, the holding member 20 is arranged on the one surface 10a side of the wafer 10 to be processed. A dicing tape or the like having a support base 21 and an adhesive 22 is used as the holding member 20, for example. The support base 21 is made of a material that is unlikely to warp during the manufacturing process, such as glass, a silicon substrate, or ceramics. The adhesive 22 is made of a material whose adhesive strength can be changed. For example, a material whose adhesive strength changes depending on temperature or light is used. In this case, the adhesive 22 is composed of, for example, ultraviolet curing resin, wax, double-sided tape, or the like. However, the adhesive 22 is composed of a material that maintains its adhesive force even when forming the other-surface-side element-constituting portion 60 of FIG. 1G, which will be described later.

Next, as shown in FIG. 1E, laser light L is irradiated from the other surface 10b of the processed wafer 10, and along the surface direction of the processed wafer 10, a laser beam L is irradiated from the one surface 10a of the processed wafer 10 to a predetermined depth D. A degraded layer 15 is formed.

Specifically, a laser light source that oscillates laser light L, a dichroic mirror arranged to change the direction of the optical axis of the laser light, that is, the direction of the optical path, a condenser lens for condensing the laser light, and A laser device having a displaceable stage or the like is prepared. Then, when forming the deteriorated layer 15 , the position of the stage or the like is adjusted so that the focal point of the laser beam L is relatively scanned along the surface direction of the processed wafer 10 . As a result, a degraded layer 15 is formed along the surface direction of the processed wafer 10 . More specifically, by irradiating the laser light L, the altered layer 15 is formed by evaporating nitrogen as gas and depositing gallium.

In this case, as described above, even if the processing wafer 10 of the present embodiment is subjected to each step before the irradiation with the laser beam L, fine unevenness is hardly formed on the other surface 10b. Therefore, when the laser beam L is irradiated from the other surface 10b side of the processed wafer 10, the laser beam L is suppressed from being irregularly reflected from the other surface 10b of the processed wafer 10. FIG. Therefore, the deteriorated layer 15 can be preferably formed inside the processed wafer 10 .

Although not particularly limited, in the present embodiment, the laser light L used when forming the altered layer 15 has a wavelength range from infrared to visible light, and the transmittance of the target wafer is (that is, the transmittance of GaN) is used. In the present embodiment, the modified layer 15 is formed by appropriately adjusting the processing point output and pulse width of the laser light L as described above.

The predetermined depth D for forming the deteriorated layer 15 is set according to the ease of handling of the semiconductor chip S1, the withstand voltage, etc., and is about 10 to 200 μm. In this case, the location where the altered layer 15 is formed changes according to the thickness of the epitaxial film 3 , and is either inside the epitaxial film 3 , at the boundary between the epitaxial film 3 and the GaN wafer 1 , or inside the GaN wafer 1 . Crab is formed. Note that FIG. 1E shows an example in which an altered layer 15 is formed at the boundary between epitaxial film 3 and GaN wafer 1 .

However, at least part of the GaN wafer 1 in the processed wafer 10 is reused as a recycled wafer 40, as will be described later. Therefore, degraded layer 15 is preferably formed inside epitaxial film 3 or at the boundary between epitaxial film 3 and GaN wafer 1 . Moreover, when the altered layer 15 is formed inside the GaN wafer 1 , the altered layer 15 is preferably formed on the one surface 1 a side of the GaN wafer 1 . When the degraded layer 15 is formed inside the epitaxial film 3, the degraded layer 15 is formed inside the n ⁺ -type epitaxial layer 3a rather than the n ⁻ -type epitaxial layer 3b constituting the semiconductor device. is preferred.

Hereinafter, the portion of the processed wafer 10 closer to the surface 10a than the degraded layer 15 is referred to as a chip-constituting wafer 30, and the portion of the processed wafer 10 closer to the other surface 10b than the degraded layer 15 is referred to as a recycled wafer 40.

Subsequently, as shown in FIG. 1F, an auxiliary member 50 is arranged on the side of the other surface 10b of the wafer 10 to be processed. The auxiliary member 50 is simplified in FIG. 1F, but is composed of, for example, a base material and an adhesive whose adhesion can be changed. In this case, the base material of the auxiliary member 50 is made of, for example, glass, a silicon substrate, or ceramics, and the adhesive of the auxiliary member 50 is made of, for example, an ultraviolet curable resin, wax, double-sided tape, or the like. Then, a tensile force or the like is applied in the thickness direction of the processed wafer 10 by gripping the supporting table 21 and the auxiliary member 50, and the chip-constituting wafer 30 and the recycled wafer 40 are separated from each other with the deteriorated layer 15 as a boundary (that is, the starting point of branching). To divide.

In the following description, the surface of the chip-constituting wafer 30 on which the one-side element constituting portion 11 is formed is referred to as one surface 30a, and the divided surface of the chip-constituting wafer 30 is referred to as the other surface 30b. The divided surface side of the wafer 40 will be described as one surface 40a. In addition, in each figure after FIG. 1F, the deteriorated layer 15 remaining on the other surface 30b of the chip-constituting wafer 30 and the one surface 40a of the recycle wafer 40 and the like are omitted as appropriate.

After that, as shown in FIG. 1G, as the remaining semiconductor manufacturing process, on the other surface 30b of the chip-constituting wafer 30, the other surface side element constituting portion 60 of the semiconductor element such as the metal film 61 constituting the back surface electrode is formed. The back side process is performed.

Incidentally, before the step of forming the other-side element-constituting portion 60, if necessary, a step of planarizing the other surface 30b of the chip-constituting wafer 30 by CMP (abbreviation of chemical mechanical polishing) method or the like may be performed. can be FIG. 1G shows a diagram in which the other surface 30b of the chip-constituting wafer 30 is flattened. Further, after performing the step of forming the other-side element-constituting portion 60, if necessary, heat treatment such as laser annealing is performed to bring the metal film 61 and the other-side surface 30b of the chip-constituting wafer 30 into ohmic contact. You can do it.

Subsequently, as shown in FIG. 1H, the holding member 51 is placed on the other surface 30b side of the chip-constituting wafer 30, that is, on the metal film 61 side. A dicing tape or the like having a substrate 52 and an adhesive 53 is used as the holding member 51, for example. Note that the adhesive 53 is made of a material whose adhesive strength can be changed, and for example, a material whose adhesive strength changes depending on temperature or light is used.

Thereafter, as shown in FIG. 1I, the support base 21 attached to the one surface 30a of the chip-constituting wafer 30 is peeled off. Here, a process for lowering the adhesive force of the adhesive 22 that adheres the support base 21 to the chip-constituting wafer 30, for example, UV irradiation is performed when the adhesive 22 is composed of a UV resin adhesive.

Subsequently, as shown in FIG. 1J, by singulating the chip-constituting wafer 30 into individual chips using a dicing saw, laser dicing, or the like, each semiconductor chip S1 is formed. At this time, it is preferable to adjust the dicing depth so that the holding member 51 remains connected without being cut while the chip-constituting wafer 30 is divided into chips.

Although the subsequent process for the semiconductor chip S1 is not shown, the holding member 51 is expanded to increase the distance between the semiconductor chips S1 at the dicing cut portions. After that, the adhesive force of the adhesive 53 is weakened by heat treatment, light irradiation, or the like, and the semiconductor chip S1 is picked up. Thereby, the semiconductor chip S1 is manufactured.

Further, as shown in FIG. 1K, one surface 40a of the recycled wafer 40 configured in FIG. 1F is flattened by performing a CMP method using a polishing apparatus 70 or the like. Then, the flattened recycle wafer 40 is used as the GaN wafer 1, and the steps after FIG. 1A are performed again. Thus, the GaN wafer 1 can be used multiple times to construct the semiconductor chip S1.

According to the present embodiment described above, the recycled wafer 40 is reused as the GaN wafer 1 . Therefore, it is not necessary to prepare a new GaN wafer 1 each time the semiconductor chip S1 is manufactured, and the GaN wafer 1 can be effectively used. Therefore, it is possible to improve the productivity of the semiconductor chip S1.

In this embodiment, the GaN wafer 1 is prepared with one surface 1a and the other surface 1b of gallium. Therefore, it is possible to suppress the formation of fine unevenness on the other surface 10b of the processed wafer 10 when each step before forming the altered layer 15 by irradiating the laser beam L is performed. Therefore, when the laser beam L is irradiated from the other surface 10b side of the processed wafer 10, the laser beam L is suppressed from being irregularly reflected from the other surface 10b of the processed wafer 10. FIG. Thereby, the deteriorated layer 15 can be preferably formed inside the processed wafer 10, and the productivity can be further improved.

(1) In this embodiment, the GaN layer 112 is arranged on the base wafer 111 with the buffer layer 113 interposed therebetween. Therefore, it becomes easier to increase the thickness of the GaN layer 112 and to increase the thickness of the bonded wafer 114 composed of the GaN layer 112 . Therefore, it becomes easier to increase the thickness of the GaN wafer 1, and the number of times the GaN wafer 1 can be used effectively can be increased.

(Second embodiment)
A second embodiment will be described. This embodiment differs from the first embodiment in the process of preparing the GaN wafer 1 . Others are the same as those of the first embodiment, so description thereof is omitted here.

In this embodiment, as shown in FIG. 3A, an auxiliary wafer 110 in which a GaN layer 112 is directly arranged on a base wafer 111 is prepared. That is, a wafer without the buffer layer 113 is prepared as the auxiliary wafer 110 . In this embodiment, since the GaN layer 112 is directly arranged on the base wafer 111, the difference in thermal expansion coefficient between the base wafer 111 and the GaN layer 112 makes the auxiliary wafer 110 easy to warp. Therefore, the GaN layer 112 of this embodiment is thinner than the GaN layer 112 of the first embodiment.

Next, as shown in FIG. 3B, a holding substrate 120 is prepared and the GaN layer 112 and the holding substrate 120 are bonded. The holding substrate 120 is for holding the thin GaN layer 112, and is made of, for example, a glass substrate or the like, and is bonded to the GaN layer 112 by direct bonding or the like.

Subsequently, the GaN layer 112 is separated from the auxiliary wafer 110 while the GaN layer 112 is held on the holding substrate 120, as shown in FIG. 3C. Thereby, the bonded wafer 114 having the first main surface 114a of the gallium surface and the second main surface 114b of the nitrogen surface is prepared while being held by the holding substrate 120. FIG. The bonded wafer 114 is formed by, for example, grinding or polishing the base wafer 111 or the like to separate the GaN layer 112 . The bonded wafer 114 is formed by separating the GaN layer 112 from the base wafer 111 by, for example, laser slicing.

Next, as shown in FIG. 3D, the second main surface 100b of the bulk wafer 100 and the second main surface 114b of the bonded wafer 114 are bonded by direct bonding or the like.

Then, as shown in FIG. 3E, the holding substrate 120 is removed by grinding, polishing, laser slicing, wet etching, or the like, thereby preparing the GaN wafer 1 having one surface 1a and the other surface 1b as gallium surfaces.

After that, the semiconductor chip S1 is manufactured by performing the steps after FIG. 1B on each GaN wafer 1. FIG.

According to the present embodiment described above, the GaN wafer 1 has the gallium surface on one side 1a and the other side 1b, so that the same effects as those of the first embodiment can be obtained.

(Third embodiment)
A third embodiment will be described. This embodiment differs from the first embodiment in the process of preparing the GaN wafer 1 . Others are the same as those of the first embodiment, so description thereof is omitted here.

In this embodiment, as shown in FIG. 4A, after the bulk wafer 100 is prepared, a laser beam L is irradiated from the second main surface 100b side to form an altered layer 100C inside. The step of forming the altered layer 100C by irradiating the laser light L is performed under the same conditions as the step of forming the altered layer 15 in FIG. 1E.

Next, as shown in FIG. 4B, the bulk wafer 100 is separated into a first divided bulk wafer 101 and a second divided bulk wafer 102 using the altered layer 100c as a boundary (that is, a starting point of branching). In this step, although not shown, auxiliary members and the like are appropriately arranged on the first main surface 100a and the second main surface 100b of the bulk wafer 100. Next, as shown in FIG. 1F, the bulk wafer 100 is divided into a first divided bulk wafer 101 and a second divided bulk wafer 102 by applying a tensile force or the like in the thickness direction.

Hereinafter, in the first divided bulk wafer 101, the surface that was the first main surface 100a of the bulk wafer 100 will be referred to as the first divided main surface 101a of the first divided bulk wafer 101, and the divided surface will be the second divided bulk wafer 101. It is referred to as a divided main surface 102b. Therefore, in the first divided bulk wafer 101, the first divided main surface 101a is a gallium surface, and the second divided main surface 101b is a nitrogen surface.

Further, in the second divided bulk wafer 102, the divided surface is used as the first divided main surface 102a of the second divided bulk wafer 102, and the surface that was the second main surface 100b of the bulk wafer 100 is used as the second divided bulk wafer 102. Let it be the main surface 102b. Therefore, in the second divided bulk wafer 102, the first divided main surface 102a is a gallium surface, and the second divided main surface 102b is a nitrogen surface.

After that, although not shown, the divided surfaces are planarized by the CMP method or the like while removing the remaining deteriorated layer 100c. Specifically, the second divided main surface 101b of the first divided bulk wafer 101 is flattened, and the first divided main surface 102a of the second divided bulk wafer 102 is flattened.

Also, as shown in FIG. 4C, an auxiliary wafer 110 similar to that shown in FIG. 2B is prepared. However, the auxiliary wafer 110 of this embodiment is a large-diameter substrate having a diameter larger than that of the bulk wafer 100 as compared with the first embodiment. Specifically, the auxiliary wafer 110 has a diameter that allows a plurality of wafers of the same size as the bulk wafer 100 to be obtained in the planar direction.

Next, as shown in FIG. 4D, the GaN layer 112 is separated from the auxiliary wafer 110 to produce a bonded wafer 114 having a gallium surface as the first main surface 114a and a nitrogen surface as the second main surface 114b. Configure. In this case, in this embodiment, two bonded wafers 114 corresponding to the diameters of the first divided bulk wafer 101 and the second divided bulk wafer 102 are formed from the auxiliary wafer 110 . The bonded wafer 114 is formed by, for example, grinding and polishing the base wafer 111 or the like to separate the GaN layer 112 and processing it to have a predetermined diameter. The bonded wafer 114 is formed by, for example, separating the GaN layer 112 from the base wafer 111 by laser slicing or the like and processing it to have a predetermined diameter.

After that, as shown in FIG. 4E, the second divided main surface 101b of the first divided bulk wafer 101 and the second main surface 114b of the bonded wafer 114 are bonded by direct bonding or the like, so that one surface 1a and the other surface 1b are made of gallium. A planarized GaN wafer 1 is constructed. Similarly, by directly bonding the second main surface 102b of the second divided bulk wafer 102 and the second main surface 114b of the bonded wafer 114 by direct bonding or the like, the GaN wafer 1 having one surface 1a and the other surface 1b made of gallium is obtained. configure. That is, in this embodiment, a plurality of GaN wafers 1 are formed simultaneously.

After that, the semiconductor chip S1 is manufactured by performing the steps after FIG. 1B on each GaN wafer 1. FIG.

According to the present embodiment described above, the GaN wafer 1 has the gallium surface on one side 1a and the other side 1b, so that the same effects as those of the first embodiment can be obtained.

(1) In this embodiment, a plurality of GaN wafers 1 can be constructed from one bulk wafer 100 and one auxiliary wafer 110 . Therefore, it is possible to further improve productivity.

(Other embodiments)
Although the present disclosure has been described with reference to embodiments, it is understood that the present disclosure is not limited to such embodiments or structures. The present disclosure also includes various modifications and modifications within the equivalent range. In addition, various combinations and configurations, as well as other combinations and configurations, including single elements, more, or less, are within the scope and spirit of this disclosure.

For example, in each of the embodiments described above, the epitaxial film 3 may consist of only the n ⁻ -type epitaxial layer 3b.

Further, in each of the above-described embodiments, in the process of FIG. 1G, the metal film 61 may be formed without polishing the other surface 30b of the chip-constituting wafer 30 . For example, when an optical semiconductor element or the like is formed as the semiconductor element, it is possible to effectively extract light from the other surface side by forming an uneven structure on the other surface side of the semiconductor chip S1. Immediately after the processed wafer 10 is divided into the chip-constituting wafer 30 and the recycled wafer 40, the other surface 30b of the chip-constituting wafer 30 is in a state in which the deteriorated layer 15 remains, and fine unevenness is formed. It is in a state of Therefore, when optical semiconductor elements are formed, the unevenness of the altered layer 15 may be used without polishing the other surface 30b of the chip-constituting wafer 30. FIG.

Furthermore, in each of the above-described embodiments, an epitaxial film may also be formed on the other surface 1b side of the GaN wafer 1 in the step of forming the epitaxial film 3 in FIG. 1B. According to this, for example, even when the altered layer 15 is formed in the GaN wafer 1, it becomes easy to leave a predetermined thickness or more as the recycled wafer 40, and the number of times of reuse can be increased.

In addition, in the third embodiment, the bulk wafer 100 is divided into three or more bulk wafers, three or more bonded wafers 114 are formed from the auxiliary wafer 110, and three or more GaN wafers 1 are simultaneously formed. You may do so.

Further, each of the above embodiments can be combined as appropriate. For example, by combining the third embodiment with the second embodiment, the auxiliary wafer 110 may be configured by directly disposing the GaN layer 112 on the base wafer 111 .

1a One surface 1b Other surface 1 GaN wafer 3 Epitaxial film 10 Processed wafer 10a One surface 10b Other surface 11 One surface side element constituent part 15 Altered layer 30 Chip constituent wafer 40 Recycled wafer 100 Bulk wafer 100a First principal surface 100b Second principal surface 110 Auxiliary wafer Reference Signs List 111 base wafer 112 GaN layer 114 bonded wafer 114a first main surface 114b second main surface L laser light S1 semiconductor chip

Claims (7)

A method for manufacturing a semiconductor chip on which a semiconductor element is formed, comprising:
preparing a gallium nitride wafer (1) made of gallium nitride and having one side (1a) and the other side (1b) opposite to said one side;
By forming an epitaxial film (3) on the one surface of the gallium nitride wafer, the epitaxial film side surface is one surface (10a) and the gallium nitride wafer side surface is the other surface (10b), and constructing a processed wafer (10) having a plurality of chip formation areas (RA) on one side;
forming a one-side element constituting portion (11) of the semiconductor element in the plurality of chip forming regions;
Forming an altered layer (15) along the surface direction of the processed wafer inside the processed wafer by irradiating the inside of the processed wafer with a laser beam (L) from the other surface side of the processed wafer. When,
By dividing the processed wafer with the deteriorated layer as a boundary, the processed wafer is divided into a chip-constituting wafer (30) on one side of the processed wafer and a recycled wafer (40) on the other side of the processed wafer. splitting and
taking out a semiconductor chip (S1) from the chip-constituting wafer;
reusing the recycled wafer as the gallium nitride wafer;
By preparing the gallium nitride wafer,
Preparing a bulk wafer (100) made of gallium nitride and having a first main surface (100a) of gallium and a second main surface (100b) opposite to the first main surface of nitrogen. When,
providing an auxiliary wafer (110) comprising a gallium nitride layer (112) deposited on a base wafer (111) composed of gallium nitride and another material;
A bonded wafer in which the gallium nitride layer is separated from the auxiliary wafer, and the first main surface (114a) is a gallium surface and the second main surface (114b) opposite to the first main surface is a nitrogen surface. constructing (114);
and preparing the gallium nitride wafer in which the one surface and the other surface are gallium surfaces by bonding the nitrogen surface of the bulk wafer and the nitrogen surface of the bonded wafer. 2. The method of manufacturing a semiconductor chip according to claim 1, wherein preparing the auxiliary wafer includes preparing the auxiliary wafer in which the gallium nitride layer is laminated on the base wafer with a buffer layer (113) interposed therebetween. 3. The method of manufacturing a semiconductor chip according to claim 1, wherein said base wafer is a silicon wafer, a sapphire wafer, a silicon carbide wafer, or an aluminum nitride polycrystalline wafer. After providing the bulk wafer,
irradiating the interior of the bulk wafer with a laser beam (L) to form an altered layer (100c) along the surface direction of the bulk wafer in the interior of the bulk wafer;
By dividing the bulk wafer with the deteriorated layer as a boundary, the bulk wafer is divided so that the surfaces on the first main surface side of the bulk wafer are first divided main surfaces (101a, 102a) and the second main surface side of the bulk wafer is divided. a plurality of divided bulk wafers (101, 102) having the second divided principal surfaces (101b, 102b), the first divided principal surfaces being gallium surfaces, and the second divided principal surfaces being nitrogen surfaces; configuring;
planarizing the divided surfaces of the divided bulk wafers;
preparing the auxiliary wafer having a diameter larger than that of the bulk wafer;
By preparing the bonded wafers, a plurality of bonded wafers having diameters corresponding to the diameters of the divided bulk wafers are prepared,
4. The method of manufacturing a semiconductor chip according to claim 1, wherein preparing the gallium nitride wafer includes bonding the nitrogen surfaces of the plurality of divided bulk wafers and the nitrogen surfaces of the bonded wafers. A gallium nitride wafer made of gallium nitride,
one surface (1a) and the other surface (1b) opposite to the one surface;
a bulk wafer (100) arranged on the one surface side and constituting the one surface;
a bonded wafer (114) disposed on the other side and bonded to the bulk wafer to constitute the other side;
A gallium nitride wafer in which the one surface and the other surface are gallium surfaces. 6. The gallium nitride wafer according to claim 5, wherein the impurity concentration varies discontinuously at the interface between the bulk wafer and the bonded wafer. 7. The gallium nitride wafer according to claim 5, wherein the crystal defect density changes discontinuously at the interface between the bulk wafer and the bonded wafer.

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