JP2022075319A - Semiconductor device, die pad, and manufacturing method for semiconductor device - Google Patents

Abstract

To provide a semiconductor device in which void can be suppressed in a solder between a semiconductor chip and a die pad, and a die pad and a manufacturing method for a semiconductor device.SOLUTION: A semiconductor device according to the present disclosure includes a die pad having a first surface and a second surface on the opposite side of the first surface and including a first concave part on the first surface, and a semiconductor chip. An inner surface of the die pad that forms the first concave part includes a first part for receiving the supply of a solder, a second part where the semiconductor chip is bonded with the solder and a distance from the second surface is smaller in a direction perpendicular to the second surface than the first part, and a coupling part connecting between the first part and the second part, in which the distance from the second surface in the direction perpendicular to the second surface is larger than the first part and smaller than the first surface.SELECTED DRAWING: Figure 2

Description

The present disclosure relates to semiconductor devices, die pads and methods for manufacturing semiconductor devices.

Patent Document 1 discloses a lead frame including a die pad for joining semiconductor chips by soldering. In this lead frame, a recess is formed in the flat upper surface of the die pad where the semiconductor chip is arranged, which is recessed from the upper surface to accommodate the solder. Since the solder is contained in the recess, it does not get wet and spread. Therefore, when the semiconductor chip is joined to the die pad, the thickness of the solder interposed between the die pad and the semiconductor chip can be sufficiently secured.

Japanese Unexamined Patent Publication No. 2012-104709

In Patent Document 1, voids may occur in the solder between the semiconductor chip and the chip mounting area of the die pad.

The present disclosure has been made to solve the above-mentioned problems, and an object of the present invention is to obtain a semiconductor device, a die pad, and a method for manufacturing a semiconductor device capable of suppressing voids in the solder between the semiconductor chip and the die pad.

The semiconductor device according to the first disclosure has a first surface and a second surface which is a surface opposite to the first surface, and a die pad having a first recess formed on the first surface and a semiconductor chip. The inner surface of the die pad forming the first recess is the first portion for receiving the supply of solder and the semiconductor chip is joined with the solder, and the second portion is more than the first portion. A second part having a small distance from the second surface in a direction perpendicular to the surface, and a distance from the second surface in a direction perpendicular to the second surface by connecting the first part and the second part. Has a connecting portion that is larger than the first portion and smaller than the first surface.

The die pad according to the second disclosure is a die pad having a first surface and a second surface which is a surface opposite to the first surface, and a recess is formed in the first surface of the die pad. Of these, the inner surface forming the recess is the first portion for receiving the supply of solder and the second surface in a direction perpendicular to the second surface from the first portion where the semiconductor chip is bonded with the solder. The first part, which connects the first part and the second part with a small distance from the second part, and the distance from the second surface in the direction perpendicular to the second surface is larger than that of the first part. It has a connecting portion that is smaller than the surface.

The method for manufacturing a semiconductor device according to the third disclosure has a first surface and a second surface which is a surface opposite to the first surface, and heats a die pad having a recess formed in the first surface. In this state, solder is supplied to the first portion of the inner surface of the die pad forming the recess, and the second portion of the inner surface forming the recess is perpendicular to the second surface of the first portion. The molten solder is flowed through a connecting portion to a second portion having a small distance from the surface, a semiconductor chip is mounted on the solder that has flowed to the second portion, and the die pad is cooled to cool the semiconductor chip. Is joined to the second portion with the solder, and the connecting portion connects the first portion and the second portion of the inner surface forming the recess, and the second portion in a direction perpendicular to the second surface. The portion where the distance from the two surfaces is larger than the first surface and smaller than the first surface.

According to the semiconductor device according to the first disclosure, the solder supplied to the first portion of the die pad can be flowed to the second portion via the connecting portion. As a result, it is possible to suppress the inflow of voids into the second portion. Therefore, voids can be suppressed in the solder between the semiconductor chip and the die pad.

In the die pad according to the second disclosure, the solder supplied in the first portion can be flowed to the second portion via the connecting portion. As a result, it is possible to suppress the inflow of voids into the second portion. Therefore, voids can be suppressed in the solder between the semiconductor chip and the die pad.

In the method for manufacturing a semiconductor device according to the third disclosure, the solder supplied to the first portion of the die pad can be flowed to the second portion via the connecting portion. As a result, it is possible to suppress the inflow of voids into the second portion. Therefore, voids can be suppressed in the solder between the semiconductor chip and the die pad.

It is a top view of the semiconductor device which concerns on Embodiment 1. FIG. It is sectional drawing obtained by cutting FIG. 1 by the AB straight line. It is a figure explaining the manufacturing method of the semiconductor device which concerns on Embodiment 1. FIG. It is a figure which shows the state which the 2nd recess is filled with solder. It is a figure explaining the process of mounting a semiconductor chip. It is a figure explaining the structure of the die pad which concerns on the 1st comparative example. It is a figure explaining the structure of the die pad which concerns on the 2nd comparative example. It is a figure explaining the structure of the die pad which concerns on Embodiment 1. FIG. It is a figure explaining the process of cooling a semiconductor device. It is a top view of the die pad which concerns on Embodiment 2. FIG. It is sectional drawing of the semiconductor device which concerns on Embodiment 2. FIG. It is sectional drawing of the semiconductor device which concerns on Embodiment 3. FIG. It is a top view of the semiconductor device which concerns on Embodiment 3. FIG.

A method for manufacturing a semiconductor device, a die pad, and a semiconductor device according to each embodiment will be described with reference to the drawings. The same or corresponding components may be designated by the same reference numerals and the description may be omitted.

Embodiment 1.
FIG. 1 is a plan view of the semiconductor device 100 according to the first embodiment. FIG. 2 is a cross-sectional view obtained by cutting FIG. 1 along an AB straight line. The semiconductor device 100 is, for example, a power semiconductor module. The semiconductor device 100 includes a die pad 10 and a semiconductor chip 45. The semiconductor chip 45 is, for example, a power semiconductor chip.

The die pad 10 has a first surface 16 having a plane 13 and a slope 15, and a second surface 11 which is a surface opposite to the first surface 16. A recess 50 is formed on the first surface 16 of the die pad 10. The recess 50 is formed from a first recess 20 and a second recess 30. The die pad 10 has a flat portion 12 and an inclined portion 14. A first recess 20 is formed in the inclined portion 14. A second recess 30 is formed in the flat portion 12.

The inner surface of the die pad 10 forming the recess 50 has a first portion 22, a second portion 32 and a connecting portion 25. The first portion 22 is a portion of the inner surface forming the recess 50 of the die pad 10 that forms the first recess 20. The first portion 22 is a portion for receiving the supply of the solder 40, as will be described later. The second portion 32 is a portion of the inner surface forming the recess 50 of the die pad 10 that forms the second recess 30. A semiconductor chip 45 is joined to the second portion 32 with solder 40. Further, the second portion 32 has a smaller distance from the second surface 11 in the direction perpendicular to the second surface 11 than the first portion 22.

The connecting portion 25 is a portion of the inner surface forming the recess 50 of the die pad 10 that connects the first portion 22 and the second portion 32. The distance of the connecting portion 25 from the second surface 11 in the direction perpendicular to the second surface 11 is larger than that of the first portion 22. That is, the connecting portion 25 connects the first portion 22 and the second portion 32 at a position higher than the bottom of the first portion 22. Further, the distance of the connecting portion 25 from the second surface 11 in the direction perpendicular to the second surface 11 is smaller than that of the plane 13.

The slope 15 which is the portion of the first surface 16 where the first portion 22 is provided is perpendicular to the second surface 11 as it approaches the plane 13 which is the portion of the first surface 16 where the second portion 32 is provided. It is inclined so that the distance from the second surface 11 in the above direction becomes small.

The portion of the second portion 32 provided outside the semiconductor chip 45 when viewed from the direction perpendicular to the second surface 11 is curved so as to be convex toward the outside of the die pad 10. Specifically, of the second portion 32, the side surface 34 around the flat portion 33 directly below the semiconductor chip 45 is curved.

In the semiconductor device 100, the semiconductor chip 45 is bonded to the die pad 10 via the solder 40. The die pad 10 is formed of, for example, metal. Further, the first portion 22 and the second portion 32 may be plated.

Next, a method for manufacturing the semiconductor device 100 will be described. FIG. 3 is a diagram illustrating a method of manufacturing the semiconductor device 100 according to the first embodiment. First, the die pad 10 is mounted on the high temperature plate 70. The die pad 10 is arranged in a furnace in a reduced state (not shown). With the die pad 10 heated in this way, the solder 40 is supplied to the first portion 22. As a result, the molten solder 40 is flowed through the connecting portion 25 in the second portion 32.

In the present embodiment, by providing the first portion 22 on the inclined portion 14, the solder 40 can be efficiently flowed on the second portion 32. Further, the connecting portion 25 is located at a position lower than the plane 13. Therefore, it is possible to prevent the solder 40 from riding on the outside of the second recess 30.

The solder 40 is supplied from the thread solder 42. At this time, the void 60 may be generated by the surface oxide film of the solder thread 42. On the other hand, in the present embodiment, the first portion 22 and the second portion 32 are separated by the connecting portion 25. Therefore, it is possible to prevent the void 60 from flowing to the second portion 32. Therefore, the high-quality solder 40 can be sent to the chip mounting portion, and the void 60 can be suppressed in the solder 40 between the semiconductor chip 45 and the die pad 10.

FIG. 4 is a diagram showing a state in which the second recess 30 is filled with the solder 40. The thickness of the solder 40 in the second recess 30 in this state is preferably 30 um or more when the chip size is small. Here, a general lead-free joining material is assumed as the solder 40. It is desirable that the height difference 80 between the bottom of the first recess 20 and the bottom of the second recess 30 is equal to or larger than the thickness of the solder 40.

Next, the semiconductor chip 45 is mounted on the solder 40 that has flowed to the second portion 32. FIG. 5 is a diagram illustrating a process of mounting the semiconductor chip 45. At this time, as shown by the arrow 81, the semiconductor chip 45 is mounted on the solder 40 while being pushed toward the second portion 32. As a result, as shown by the arrow 82, the solder 82 is discharged from directly below the semiconductor chip 45 to the outside. Along with this, the void 60 can be discharged together with the solder 40 from directly below the semiconductor chip 45 to the outside. After that, the solder 40 in the second recess 30 returns to just below the semiconductor chip 45 due to tension.

FIG. 6 is a diagram illustrating the structure of the die pad 10a according to the first comparative example. The side surface 34a of the second portion 32a of the die pad 10a is a flat slope. At this time, the volume of the outer portion of the semiconductor chip 45 in the second recess is small. Therefore, when the semiconductor chip 45 is pushed in as shown by the arrow 83, the solder 40 tends to crawl up on the semiconductor chip 45. Further, as shown by the arrow 84, the amount of return when the solder 40 returns due to tension becomes large.

FIG. 7 is a diagram illustrating the structure of the die pad 10b according to the second comparative example. The side surface 34b of the second portion 32b of the die pad 10b is a flat surface perpendicular to the flat portion 33. At this time, the volume of the outer portion of the semiconductor chip 45 in the second recess is large. Therefore, when the semiconductor chip 45 is pushed in as shown by the arrow 83, the solder 45 is unlikely to crawl up on the semiconductor chip 45. However, as shown by the arrow 84, the amount of return when the solder 40 returns due to tension is small. Therefore, the thickness of the solder 40 may not be secured.

FIG. 8 is a diagram illustrating the structure of the die pad 10 according to the first embodiment. In the present embodiment, the side surface 34 of the second portion 32 has a curved shape protruding outward. With such a second recess 30, it is possible to prevent the solder 45 from creeping up on the semiconductor chip 45, and to secure the return amount of the solder 40 to secure the thickness of the solder 40. The side surface 34 may be a curved surface or may be configured by connecting a plurality of planes.

FIG. 9 is a diagram illustrating a process of cooling the semiconductor device 100. In this step, the die pad 10 is cooled and the semiconductor chip 45 is bonded to the second portion 32 with solder 40. Cooling is performed, for example, by mounting the die pad 10 on the heat radiating plate 72. The solder 40 is cooled in order from the portion where the distance 85 to the heat sink 72 is smaller. Therefore, the solder 40 provided in the second recess 30 solidifies faster than the solder 40 provided in the first recess 20. As a result, the thickness of the solder 40 in the second recess 30 can be secured.

The solder 40 shrinks as it solidifies. At this time, a cavity may be generated in the portion solidified later by being attracted to the portion solidified earlier. This cavity, also known as Hikesu, contributes to the void. In the present embodiment, the solder 40 directly under the semiconductor chip 45 is closer to the heat sink 72 than the other parts. Therefore, the solder 40 directly under the semiconductor chip 45 solidifies faster than the other parts. Therefore, the void can be suppressed directly under the semiconductor chip 45.

Low thermal resistance is one of the performance required for joints such as soldering. Especially in power semiconductor modules, semiconductor chips tend to be thinner from the viewpoint of improving performance. For example, a semiconductor device equipped with a thin chip of 100 um or less may be incorporated in an inverter or the like as a switching element. At this time, if there is a void directly under the semiconductor chip or directly under the wire bonding portion, the life of the semiconductor device may be shortened due to local heat concentration. Therefore, in order to efficiently dissipate heat in the power semiconductor module, it is desirable that the solder directly under the semiconductor chip has no voids.

In this embodiment, voids are formed in the solder 40 between the semiconductor chip 45 and the die pad 10 during the solder supply shown in FIG. 3, the chip mounting shown in FIG. 5, and the cooling shown in FIG. 60 can be suppressed. Therefore, the life of the semiconductor device 100 can be extended. Further, by controlling the solidification order of the solder 40, the thickness of the solder 40 directly under the semiconductor chip 45 can be secured. As a result, it is possible to suppress shortening of the life due to the generation of a solder portion that is too thin due to the variation in thickness.

The die pad 10 of the present embodiment is provided with an inclined portion 14. As an example of this modification, if the solder 40 can be flowed from the first recess 20 to the second recess 30, the inclined portion 14 may not be provided. Further, the shapes of the first recess 20 and the second recess 30 are not limited to those shown in FIGS. 1 and 2.

Further, the semiconductor chip 45 may be formed of a wide bandgap semiconductor. Wide bandgap semiconductors are, for example, silicon carbide, gallium nitride based materials or diamond. It is conceivable that the semiconductor chip 45 formed of the wide bandgap semiconductor operates at a particularly high temperature. Also in this case, according to the present embodiment, the reliability of the semiconductor device 100 can be improved by suppressing the void 60 and reducing the thermal resistance of the joint portion.

These modifications can be appropriately applied to the semiconductor device, the die pad, and the method for manufacturing the semiconductor device according to the following embodiments. Since the semiconductor device, the die pad, and the method for manufacturing the semiconductor device according to the following embodiments have much in common with the first embodiment, the differences from the first embodiment will be mainly described.

Embodiment 2.
FIG. 10 is a plan view of the die pad 210 according to the second embodiment. FIG. 11 is a cross-sectional view of the semiconductor device 200 according to the second embodiment. FIG. 11 is a cross-sectional view of a portion corresponding to the CD straight line shown in FIG. In the present embodiment, the recess 250 is formed on the first surface 16 of the die pad 210. The recess 250 is formed from a first recess 20 and a second recess 230. The second portion 232 is a portion of the inner surface of the die pad 210 that forms the recess 250 that forms the second recess 230. A slit 234 is formed in the second portion 232. Other configurations are the same as those of the first embodiment.

The plurality of slits 234 are arranged in the lateral direction of the second recess 230 and extend along the longitudinal direction of the second recess 230. The slit 234 has a V-shaped cross section. The slit 234 extends outside the die pad 210 in a direction perpendicular to the second surface 11. Further, the plurality of slits 234 are formed so as to avoid directly below the central portion of the semiconductor chip 45.

In the present embodiment, the void 60 generated by the entrainment of air or the like when the semiconductor chip 45 is mounted can be fastened to the slit 234. In particular, the void 60 can be captured by the slit 234 when the semiconductor chip 45 shown in FIG. 5 is pushed in. Therefore, the void 60 can be suppressed directly under the central portion of the semiconductor chip 45, which tends to have a high temperature, and the increase in thermal resistance can be suppressed. Further, since the slit 234 has a shape that spreads outward, the void 60 can be effectively captured against the movement of the void 60 when the semiconductor chip 45 is mounted.

The width 86 of the slit 234 may be set to be equal to or smaller than the diameter of the void 60 to be suppressed. By capturing the void 60 in the slit 234, the size of the bubble is reduced to a width of 86 or less. Therefore, in the present embodiment, the void 60 can be made smaller than the size which is a problem in the characteristics of the semiconductor device 100, for example.

The number, shape, and size of the slits 234 are not limited to those shown in FIGS. 10 and 11. For example, the slit 234 may have a U-shaped cross section. Further, the slit 234 may be formed so as to avoid directly under a wire (not shown) which is a heat generating portion. In this case as well, the increase in thermal resistance can be suppressed.

Embodiment 3.
FIG. 12 is a cross-sectional view of the semiconductor device 300 according to the third embodiment. FIG. 13 is a plan view of the semiconductor device 300 according to the third embodiment. In the present embodiment, the recess 350 is formed on the first surface 316 of the die pad 310. The recess 350 is formed from a first recess 320 and two second recesses 330. The second recess 330 is arranged on both sides of the first recess 320.

The inner surface of the die pad 310 forming the recess 350 has a first portion 322, a second portion 332 and a connecting portion 325. The first portion 322 is a portion of the inner surface of the die pad 310 that forms the recess 350 that forms the first recess 320. The second portion 332 is a portion of the inner surface of the die pad 310 that forms the recess 350 that forms the second recess 330. A semiconductor chip 45 is bonded to each second portion 332 with solder 40. The second portion 332 has a smaller distance from the second surface 11 in the direction perpendicular to the second surface 11 than the first portion 322. In the present embodiment, a plurality of second portions 332 are provided for one first portion 322.

The connecting portion 325 is a portion of the inner surface forming the recess 50 of the die pad 310 that connects the first portion 322 and the second portion 332. The distance of the connecting portion 325 from the second surface 11 in the direction perpendicular to the second surface 11 is larger than that of the first portion 322. Further, as shown in the height difference 87, the connecting portion 325 has a smaller distance from the second surface 11 in the direction perpendicular to the second surface 11 than the first surface 316.

Immediately below the first portion 322, a recess 352 is formed on the second surface 11. That is, the die pad 310 floats on the mounting surface directly below the first portion 322.

In the present embodiment, for example, the die pad 310 is bent to form the first portion 322 and the connecting portion 325. That is, the die pad 310 is formed by bending the frame. As a result, the volume of the material can be reduced and the cost can be suppressed.

Further, immediately below the first portion 322, the heat sink 72 and the die pad 310 are not in contact with each other. Therefore, the solder 40 provided in the first recess 320 has a larger distance 88 from the heat radiating plate 72 than the solder 40 provided in the second recess 330. Therefore, the solder 40 provided in the second recess 330 solidifies faster than the solder 40 provided in the first recess 320. Therefore, it is possible to suppress voids directly under the semiconductor chip 45 and secure the thickness of the solder 40.

Further, in the present embodiment, a plurality of semiconductor chips 45 can be provided in one first recess 320. Therefore, the mounting area can be reduced as compared with the first embodiment. As a modification of the present embodiment, three or more second recesses 330 may be provided for one first recess 320. Further, the shapes and arrangements of the first recess 320 and the second recess 330 are not limited to those shown in FIGS. 12 and 13. Further, the recess 352 does not have to be formed in the die pad 310.

The technical features described in each embodiment may be used in combination as appropriate.

10, 10a, 10b Die pad, 11 2nd surface, 12 flat part, 13 flat surface, 14 inclined part, 15 inclined surface, 16 1st surface, 20 1st concave part, 22 1st part, 25 connecting part, 30 2nd concave part, 32, 32a, 32b 2nd part, 33 flat part, 34, 34a, 34b side surface, 45 semiconductor chip, 50 recess, 60 void, 70 high temperature plate, 72 heat dissipation plate, 100, 200 semiconductor device, 210 die pad, 230 second Concave part, 232 second part, 234 slit, 250 recess, 300 semiconductor device, 310 die pad, 316 first surface, 320 first recess, 322 first part, 325 connecting part, 330 second recess, 332 second part, 350 , 352 Concave

Claims (14)

A die pad having a first surface and a second surface opposite to the first surface and having a first recess formed on the first surface, and a die pad.
With semiconductor chips
Equipped with
The inner surface of the die pad forming the first recess is
The first part to receive the solder supply and
A second portion in which the semiconductor chip is joined by the solder and the distance from the second surface is smaller in a direction perpendicular to the second surface than the first portion.
A connecting portion that connects the first portion and the second portion and has a distance from the second surface in a direction perpendicular to the second surface that is larger than that of the first portion and smaller than that of the first surface.
A semiconductor device characterized by having. The portion of the first surface provided with the first portion becomes closer to the portion of the first surface provided with the second portion with the second surface in a direction perpendicular to the second surface. The semiconductor device according to claim 1, wherein the semiconductor device is inclined so that the distance between the two is small. The semiconductor device according to claim 1, wherein a plurality of the second portions are provided for one first portion. The semiconductor device according to claim 3, wherein a second recess is formed on the second surface immediately below the first portion. A portion of the second portion provided outside the semiconductor chip when viewed from a direction perpendicular to the second surface is characterized in that it is curved so as to be convex toward the outside of the die pad. The semiconductor device according to any one of claims 1 to 4. The semiconductor device according to any one of claims 1 to 5, wherein a slit is formed in the second portion. The semiconductor device according to claim 6, wherein the slit is formed so as to avoid directly below the central portion of the semiconductor chip. The semiconductor device according to claim 6 or 7, wherein the slit has a V-shaped cross section and extends outside the die pad in a direction perpendicular to the second surface. The semiconductor device according to any one of claims 1 to 8, wherein the semiconductor chip is formed of a wide bandgap semiconductor. The semiconductor device according to claim 9, wherein the wide bandgap semiconductor is silicon carbide, a gallium nitride-based material, or diamond. A die pad having a first surface and a second surface opposite to the first surface, and a recess formed in the first surface.
The inner surface of the die pad forming the recess is
The first part to receive the solder supply and
A second portion in which the semiconductor chip is joined by the solder and the distance from the second surface is smaller in the direction perpendicular to the second surface than the first portion.
A connecting portion that connects the first portion and the second portion and has a distance from the second surface in a direction perpendicular to the second surface that is larger than that of the first portion and smaller than that of the first surface.
A die pad characterized by having. An inner surface of the die pad forming the recess in a state where the die pad having a first surface and a second surface opposite to the first surface and having a recess formed on the first surface is heated. Solder is supplied to the first portion of the above, and the connecting portion is connected to the second portion of the inner surface forming the recess, which is smaller in distance from the second surface in the direction perpendicular to the second surface than the first portion. The molten solder is allowed to flow through the solder.
A semiconductor chip is mounted on the solder that has flowed to the second part, and the semiconductor chip is mounted.
The die pad is cooled and the semiconductor chip is bonded to the second portion with the solder.
The connecting portion connects the first portion and the second portion of the inner surface forming the recess, and the distance from the second surface in the direction perpendicular to the second surface is larger than that of the first portion. A method for manufacturing a semiconductor device, characterized in that the portion is large and smaller than the first surface. The method for manufacturing a semiconductor device according to claim 12, wherein the first portion and the connecting portion are formed by bending the die pad. The method for manufacturing a semiconductor device according to claim 12, wherein the semiconductor chip is mounted on the solder flowing in the second portion while being pushed toward the second portion.

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