JP2022062195A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which has a transistor excellent in electric characteristic, a transistor stable in electric characteristic, and has high integrity.

SOLUTION: A transistor 100 has: a first insulator 102; an oxide layer 104; a second insulator 103; a first conductor 106; a third insulator 108 formed on a side wall of the first conductor; a second conductor 109a and a third conductor 109b contacting an upper surface of the oxide layer, the side surface of the oxide layer, and the side surface of the third insulator; a fourth insulator 110 contacting the side surface of the second conductor and a side surface of the third conductor; and a fifth insulator 111 contacting the fourth insulator, the second conductor and an upper surface of the third conductor. The upper surface of the fourth insulator has an almost flat area. The oxide layer has a first area overlapping the first conductor and a second area having lower resistance than the first area.

SELECTED DRAWING: Figure 1

COPYRIGHT: (C)2022,JPO&INPIT

Description

One aspect of the present invention relates to transistors and semiconductor devices, and methods for manufacturing them.

It should be noted that one aspect of the present invention is not limited to the above technical fields. The technical field of one aspect of the invention disclosed in the present specification and the like relates to a product, a method, or a manufacturing method. Alternatively, one aspect of the invention relates to a process, machine, manufacture, or composition (composition of matter).

In the present specification and the like, the semiconductor device refers to all devices that can function by utilizing the semiconductor characteristics. Display devices (liquid crystal display devices, light emission display devices, etc.), lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, image pickup devices, electronic devices, and the like may have semiconductor devices.

In recent years, transistors using oxide semiconductors have been attracting attention. Since the oxide semiconductor film can be formed by using a sputtering method or the like, it can be used for a transistor constituting a large display device. Further, since the transistor using the oxide semiconductor film has high field effect mobility, it is possible to realize a high-performance display device in which a drive circuit is integrally formed. In addition, since it is possible to improve and use a part of the transistor production equipment using the amorphous silicon film, there is an advantage that the capital investment can be suppressed.

Transistors using oxide semiconductors are known to have extremely low leakage current in a non-conducting state. For example, a low power consumption CPU that applies the characteristic that the leakage current of a transistor using an oxide semiconductor is extremely small is disclosed (see Patent Document 1).

Japanese Unexamined Patent Publication No. 2012-257187

One of the issues is to provide a fine transistor. Alternatively, one of the problems is to provide a transistor having a small parasitic capacitance. Alternatively, one of the problems is to provide a transistor having high frequency characteristics.
One of the challenges is to provide a transistor with good electrical characteristics. Alternatively, one of the problems is to provide a transistor having stable electrical characteristics. Alternatively, one of the challenges is to provide a transistor with low power consumption. Alternatively, one of the challenges is to provide a transistor with good reliability. Alternatively, one of the challenges is to provide a new transistor. Alternatively, one of the challenges is to provide a semiconductor device having at least one of these transistors.

The description of these issues does not preclude the existence of other issues. It should be noted that one aspect of the present invention does not need to solve all of these problems. Issues other than these are self-evident from the description of the description, drawings, claims, etc.
It is possible to extract problems other than these from the drawings, claims, and the like.

One aspect of the present invention is a first insulator, an oxide semiconductor on the first insulator, a second insulator on the oxide semiconductor, and a first conductor on the second insulator. And a third insulator adjacent to the side surface of the first conductor, a second conductor and a third conductor in contact with the side surface of the oxide semiconductor and the side surface of the third insulator, and the first A fourth insulator in contact with the side surface of the second conductor and the side surface of the third conductor, and a fifth insulator in contact with the upper surface of the fourth insulator, the second conductor, and the third conductor. , Is a semiconductor device having. Here, the upper surface of the fourth insulator has a region to be substantially flattened, and the height of the upper ends of the second conductor and the third conductor is approximately the height of the upper end of the fourth insulator. Consistent, the fourth insulator has excess oxygen, and the oxide semiconductor has a first region that overlaps the first conductor and a second region that has a lower resistance than the first region. The first insulator and the fifth insulator have lower oxygen permeability than the fourth insulator.

Here, in the above configuration, the third insulator may be referred to as a side wall insulating layer, a side wall insulating film, or a sidewall. Further, in the above configuration, the semiconductor device preferably has a transistor, the first conductor is the gate electrode of the transistor, and the second conductor and the third conductor are the source electrode or drain of the transistor. As an electrode, the second
It is preferable that the insulator of the above functions as a gate insulator (sometimes referred to as a gate insulating film or a gate insulating layer) of the transistor.

Further, in the above configuration, the fourth insulator has an opening reaching the first insulator, the fifth insulator is arranged in the opening, and the opening is an oxide semiconductor, the second. It is preferable that the insulator and the second conductor are arranged so as to surround the four sides. Further, it is preferable that the fifth insulator has a lower hydrogen permeability than the fourth insulator.

Further, in the above configuration, it is preferable that at least one of the first insulator and the fifth insulator has oxygen and aluminum. Further, in the above configuration, the second
The region of may have a region overlapping with the third insulator. Further, in the above configuration, the second region may contain at least one of tungsten, aluminum, titanium, magnesium, vanadium, antimony, arsenic, and sulfur.

Further, in the above configuration, it is preferable that the semiconductor device has a sixth insulator, the sixth insulator has a convex portion, and the oxide semiconductor is formed in contact with the convex portion. Here, the oxide semiconductor preferably has a first film, a second film in contact with the upper surface of the first film, and a third film in contact with the upper surface of the second film. Here, the electron affinity of the second film is the first film and the third film.
The first conductor has a region facing the side surface of the second film via the second insulator, which is larger than the electron affinity of the film, and the height of the convex portion and the thickness of the first film. The sum of is preferably larger than the sum of the thickness of the third film and the thickness of the second insulator. Further, the second conductor and the third conductor are
It is preferable to touch either the upper surface of the second film or the upper surface of the third film.

Further, in the above configuration, the fourth insulator may have a third region to be mixed with the fifth insulator. Also, the third region may have excess oxygen.

Alternatively, one aspect of the present invention is to form a first insulator on a substrate, then an oxide semiconductor on the first insulator, and then a second insulator on the oxide semiconductor. After forming, the first conductor is formed on the second insulator, and then the first element is added to the oxide semiconductor film.
Then, a third insulator is formed on the first conductor and the oxide semiconductor, and then the third insulator is etched to form the fourth insulator on the side surface of the first electrode. And then
A second conductor is formed on the first conductor and the fourth insulator, and then a fifth insulator is formed on the second conductor, and then a chemical mechanical polishing method is used. By removing the region containing both the first region of the second conductor and the second region of the fifth insulator while flattening the surface of the fifth insulator, the third conductor becomes conductive. The body, the fourth conductor and the sixth insulator are formed, and the first transistor is formed. After that, it is a method of manufacturing a semiconductor device in which a seventh insulator is formed on the sixth insulator. Here, the first region and the second region overlap with the first conductor, and the height of the upper end of the third conductor and the fourth conductor is approximately the height of the upper end of the sixth insulator. Matching, the first conductor functions as the gate electrode of the first transistor, the third conductor and the fourth conductor function as the source or drain electrode of the first transistor, and the first The insulator and the seventh insulator have lower hydrogen permeability than the sixth insulator, and at least one of the first insulator and the seventh insulator has aluminum oxide or silicon nitride.

Here, in the above configuration, the fourth insulator may be referred to as a side wall insulating layer or a side wall insulating film. Further, in the above configuration, the first element may contain at least one of tungsten, aluminum, titanium, magnesium, vanadium, antimony, arsenic, and sulfur.

Alternatively, one aspect of the present invention is to form a first insulator on a substrate, then an oxide semiconductor on the first insulator, and then a second insulator on the oxide semiconductor. It is formed, then a first conductor is formed on the second insulator, then a third insulator is formed on the first conductor, and then one of the third insulators is formed. By removing the part, a fourth insulator is formed, and then
A second conductor is formed by removing a portion of the first conductor, then the first element is added to the oxide semiconductor, and then the fifth insulation on the fourth insulator. A body is formed, and then a part of the fifth insulator is removed to form a sixth insulator on the side wall of the first conductor, and then a third insulator is formed on the sixth insulator. A conductor is formed, and then a seventh conductor is formed on the third conductor, and the third conductor is formed while flattening the surface of the seventh conductor using a chemical mechanical polishing method. By removing the region containing both the first region having and the second region having the seventh insulator, a fourth conductor, a fifth conductor, and an eighth conductor are formed. It is a method for manufacturing a semiconductor device in which a first transistor is formed, and then a ninth insulator is formed on a sixth conductor, a fourth conductor, and a fifth conductor. Here, the first region and the second region overlap with the second conductor, and the first insulator and the ninth insulator have lower hydrogen permeability than the eighth insulator, and the first insulator is used. At least one of the insulator and the ninth insulator preferably has oxygen and aluminum.

Here, in the above configuration, the sixth insulator may be referred to as a side wall insulating layer or a side wall insulating film. Further, in the above configuration, the first element may contain at least one of tungsten, aluminum, titanium, magnesium, vanadium, antimony, arsenic, and sulfur.

It is possible to provide a fine transistor. Alternatively, a transistor having a small parasitic capacitance can be provided. Alternatively, a transistor having high frequency characteristics can be provided. It is possible to provide a transistor having good electrical characteristics. Alternatively, it is possible to provide a transistor having stable electrical characteristics. Alternatively, it is possible to provide a transistor with low power consumption. Alternatively, it is possible to provide a transistor with good reliability. Alternatively, a new transistor can be provided. Alternatively, a semiconductor device having at least one of these transistors can be provided.

The description of these effects does not preclude the existence of other effects. It should be noted that one aspect of the present invention does not have to have all of these effects. It should be noted that the effects other than these are self-evident from the description of the description, drawings, claims, etc., and it is possible to extract the effects other than these from the description of the description, drawings, claims, etc. Is.

Top view and sectional view showing the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the semiconductor device which concerns on one aspect of this invention. The cross-sectional view which shows the semiconductor device which concerns on one aspect of this invention. The cross-sectional view which shows the semiconductor device which concerns on one aspect of this invention. The top view which shows the semiconductor device which concerns on one aspect of this invention. The cross-sectional view which shows the semiconductor device which concerns on one aspect of this invention. The figure which shows the example of the manufacturing method of the semiconductor device which concerns on one aspect of this invention. The figure which shows the example of the manufacturing method of the semiconductor device which concerns on one aspect of this invention. The figure which shows the example of the manufacturing method of the semiconductor device which concerns on one aspect of this invention. The figure which shows the example of the manufacturing method of the semiconductor device which concerns on one aspect of this invention. The figure which shows the example of the manufacturing method of the semiconductor device which concerns on one aspect of this invention. The figure which shows the example of the manufacturing method of the semiconductor device which concerns on one aspect of this invention. The figure which shows the example of the manufacturing method of the semiconductor device which concerns on one aspect of this invention. The figure which shows the example of the manufacturing method of the semiconductor device which concerns on one aspect of this invention. The figure which shows the example of the manufacturing method of the semiconductor device which concerns on one aspect of this invention. The figure which shows the example of the manufacturing method of the semiconductor device which concerns on one aspect of this invention. The figure which shows the example of the manufacturing method of the semiconductor device which concerns on one aspect of this invention. The figure which shows the example of the manufacturing method of the semiconductor device which concerns on one aspect of this invention. The figure which shows the example of the manufacturing method of the semiconductor device which concerns on one aspect of this invention. Top view and sectional view showing the semiconductor device which concerns on one aspect of this invention. The figure explaining the energy band structure. The cross-sectional view which shows the semiconductor device which concerns on one aspect of this invention. The cross-sectional view which shows the semiconductor device which concerns on one aspect of this invention. The cross-sectional view which shows the semiconductor device which concerns on one aspect of this invention. The cross-sectional view which shows the semiconductor device which concerns on one aspect of this invention. The figure which shows the example of the manufacturing method of the semiconductor device which concerns on one aspect of this invention. A Cs-corrected high-resolution TEM image in a cross section of the CAAC-OS, and a schematic cross-sectional view of the CAAC-OS. Cs-corrected high-resolution TEM image in the plane of CAAC-OS. The figure explaining the structural analysis by XRD of CAAC-OS and a single crystal oxide semiconductor. The figure which shows the electron diffraction pattern of CAAC-OS. The figure which shows the change of the crystal part by electron irradiation of In—Ga—Zn oxide. The cross-sectional view which shows the semiconductor device which concerns on one aspect of this invention. The cross-sectional view which shows the semiconductor device which concerns on one aspect of this invention. The cross-sectional view which shows the semiconductor device which concerns on one aspect of this invention. The cross-sectional view which shows the semiconductor device which concerns on one aspect of this invention. The circuit diagram of the semiconductor device which concerns on one aspect of this invention. The circuit diagram of the semiconductor device which concerns on one aspect of this invention. The block diagram which shows the configuration example of CPU. A circuit diagram showing an example of a storage element. The figure explaining an example of an image pickup apparatus. The figure explaining an example of an image pickup apparatus. The figure explaining an example of an image pickup apparatus. The figure explaining the configuration example of a pixel. The figure explaining the configuration example of a pixel. A circuit diagram showing an example of an image pickup device. The cross-sectional view which shows the structural example of the image pickup apparatus. The cross-sectional view which shows the structural example of the image pickup apparatus. A block diagram and a circuit diagram illustrating an example of a display device. A block diagram illustrating an example of a display device. The figure explaining an example of a display device. The figure explaining an example of a display device. The figure explaining an example of a display module. A block diagram illustrating an example of an RF tag. The figure explaining the use example of the RF tag. The perspective view which shows the cross-sectional structure of a package using a lead frame type interposer. The figure explaining an example of an electronic device. Top view showing an example of a film forming apparatus. FIG. 3 is a cross-sectional view showing an example of a film forming apparatus. The cross-sectional view which shows the semiconductor device which concerns on one aspect of this invention. The cross-sectional view which shows the semiconductor device which concerns on one aspect of this invention.

The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that the form and details of the present invention can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention is not construed as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same reference numerals may be used in common among different drawings for the same parts or parts having similar functions, and the repeated description thereof may be omitted.

In addition, the position, size, range, etc. of each configuration shown in the drawings may not represent the actual position, size, range, etc. in order to facilitate the understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings and the like.
For example, in an actual manufacturing process, layers, resist masks, and the like may be unintentionally reduced due to processing such as etching, but they may be omitted for ease of understanding.

Further, in the drawings, the description of some components may be omitted in order to facilitate the understanding of the invention. In addition, some hidden lines may be omitted.

The ordinal numbers such as "first" and "second" in the present specification and the like are attached to avoid confusion of the components, and do not indicate any order or order such as process order or stacking order. In addition, even terms that do not have ordinal numbers in the present specification and the like may be given ordinal numbers within the scope of the claims in order to avoid confusion of the components. Further, even if the terms have ordinal numbers in the present specification and the like, different ordinal numbers may be added within the scope of the claims. Further, even if the terms have ordinal numbers in the present specification and the like, the ordinal numbers may be omitted in the scope of claims.

Further, in the present specification and the like, the terms "electrode" and "wiring" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring" and vice versa. In addition, the terms "electrode" and "wiring" refer to multiple "electrodes" and "wiring."
This includes the case where "wiring" is integrally formed.

In the present specification and the like, the terms "upper" and "lower" do not limit the positional relationship of the components to be directly above or directly below and to be in direct contact with each other. For example, in the case of the expression "electrode B on insulator A", it is not necessary that the electrode B is formed in direct contact with the insulator A.
It does not exclude those containing other components between the insulator A and the electrode B.

In addition, the functions of the source and drain are when using transistors with different polarities, or when using transistors with different polarities.
It is difficult to limit which is the source or the drain because they are interchanged with each other depending on the operating conditions such as when the direction of the current changes in the circuit operation. Therefore, in the present specification, the terms source and drain can be used interchangeably.

Further, in the present specification and the like, when it is explicitly stated that X and Y are connected, the case where X and Y are electrically connected and the case where X and Y function. It is assumed that the case where X and Y are directly connected and the case where X and Y are directly connected are disclosed in the present specification and the like. Therefore, it is not limited to the predetermined connection relationship, for example, the connection relationship shown in the figure or text, and other than the connection relationship shown in the figure or text, it is assumed that the connection relationship is also described in the figure or text.

Further, in the present specification and the like, "electrically connected" includes the case of being connected via "something having some kind of electrical action". Here, the "thing having some kind of electrical action" is not particularly limited as long as it enables the exchange of electric signals between the connection targets. Therefore, even if it is expressed as "electrically connected", in an actual circuit,
In some cases, there is no physical connection and the wiring is just extended.

The channel length is, for example, a region in the top view of the transistor where the semiconductor (or the portion where the current flows in the semiconductor when the transistor is on) and the gate electrode overlap each other, or the region where the channel is formed. (Also referred to as a "channel forming region"), the distance between the source (source region or source electrode) and the drain (drain region or drain electrode). In one transistor, the channel length does not always take the same value in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in the present specification, the channel length is any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

The channel width is, for example, the source and the drain facing each other in the region where the semiconductor (or the part where the current flows in the semiconductor when the transistor is on) and the gate electrode overlap each other, or the region where the channel is formed. The length of the part that is used. In one transistor, the channel width does not always take the same value in all regions. That is,
The channel width of one transistor may not be fixed to one value. Therefore, in the present specification, the channel width is any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

Depending on the structure of the transistor, the channel width in the region where the channel is actually formed (also referred to as "effective channel width") and the channel width shown in the top view of the transistor ("apparent channel width"). Also called.) And may be different. For example, when the gate electrode covers the side surface of the semiconductor film, the effective channel width may be larger than the apparent channel width, and the influence thereof may not be negligible. For example, in a transistor that is fine and has an electrode covering the side surface of the semiconductor, the ratio of the channel region formed on the side surface of the semiconductor may be larger than the ratio of the channel region formed on the upper surface of the semiconductor. In that case, the effective channel width is larger than the apparent channel width.

In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, if the shape of the semiconductor is not known accurately, it is difficult to accurately measure the effective channel width.

Therefore, in the present specification, the apparent channel width is referred to as "enclosure channel width (SCW: S).
It may be called "urrounded Channel Withth)". Further, in the present specification, when simply described as a channel width, it may refer to an enclosed channel width or an apparent channel width. Alternatively, in the present specification, when simply described as channel width,
May refer to the effective channel width. The channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.

When calculating the electric field effect mobility of the transistor, the current value per channel width, or the like, the enclosed channel width may be used for calculation. In that case, the value may be different from the case calculated using the effective channel width.

The semiconductor impurities are, for example, other than the main components constituting the semiconductor. For example, an element having a concentration of less than 0.1 atomic% can be said to be an impurity. Due to the inclusion of impurities, for example
The DOS (Density of State) of the semiconductor may increase, the carrier mobility may decrease, or the crystallinity may decrease. When the semiconductor is an oxide semiconductor, the impurities that change the characteristics of the semiconductor include, for example, Group 1 elements and second elements.
There are group elements, group 13 elements, group 14 elements, group 15 elements, and transition metals other than the main components of oxide semiconductors, and in particular, for example, hydrogen (also contained in water), lithium, sodium, and the like. There are silicon, boron, phosphorus, carbon, nitrogen and so on. In the case of oxide semiconductors, oxygen deficiency may be formed by mixing impurities such as hydrogen. When the semiconductor is silicon, the impurities that change the characteristics of the semiconductor include, for example, Group 1 elements excluding oxygen and hydrogen, Group 2 elements, Group 13 elements, Group 15 elements and the like.

Further, in the present specification, "parallel" means a state in which two straight lines are arranged at an angle of −10 ° or more and 10 ° or less. Therefore, the case of −5 ° or more and 5 ° or less is also included. Also,"
"Approximately parallel" means a state in which two straight lines are arranged at an angle of -30 ° or more and 30 ° or less. Further, "vertical" and "orthogonal" mean a state in which two straight lines are arranged at an angle of 80 ° or more and 100 ° or less. Therefore, the case of 85 ° or more and 95 ° or less is also included. Further, "substantially vertical" means a state in which two straight lines are arranged at an angle of 60 ° or more and 120 ° or less.

In the present specification, etc., when the count value and the measured value are referred to as "same", "same", "equal" or "uniform" (including synonyms thereof), unless otherwise specified. , Plus or minus 20% error shall be included.

Further, in the present specification, when the etching step is performed after the photolithography step, unless otherwise specified, the resist mask formed in the photolithography step is used.
It shall be removed after the etching process is completed.

Further, in the present specification and the like, the high power supply potential VDD (hereinafter, also simply referred to as “VDD” or “H potential”) indicates a power supply potential having a higher potential than the low power supply potential VSS. Further, the low power supply potential VSS (hereinafter, also simply referred to as “VSS” or “L potential”) indicates a power supply potential having a potential lower than that of the high power supply potential VDD. The ground potential can also be used as VDD or VSS. For example, when VDD is the ground potential, VSS is a potential lower than the ground potential.
When VSS is the ground potential, VDD is a potential higher than the ground potential.

The word "membrane" and the word "layer" can be interchanged with each other in some cases or depending on the situation. For example, it may be possible to change the term "conductive layer" to the term "conductive film". Alternatively, for example, it may be possible to change the term "insulating film" to the term "insulating layer".

Further, in the present specification, when the crystal is a trigonal crystal or a rhombohedral crystal, it is represented as a hexagonal system.

(Embodiment 1)
In the present embodiment, a structural example of the semiconductor device according to one aspect of the present invention will be described.

<Configuration example>
FIG. 1A shows a top view of a semiconductor device according to an aspect of the present invention. FIG. 1 (B) is shown in FIG. 1 (A).
), The cross section of the alternate long and short dash line L1-L2 and the cross section of the alternate long and short dash line W1-W2 are shown. FIG. 1 (B)
The semiconductor device shown in the above includes a substrate 101, an insulator 102 on the substrate 101, a transistor 100 on the insulator 102, an insulator 110 covering the transistor 100, and an insulator 111 on the insulator 110.

The transistor 100 includes an oxide layer 104 on the insulator 103, an insulator 105 on the oxide layer 104, a conductor 106 on the insulator 105, and an insulator 108 formed on the side wall of the conductor 106. It has a conductor 109a and a conductor 109b in contact with the side surface of the oxide layer 104 and the side surface of the insulator 108. The insulator 108 is preferably adjacent to the side surface of the conductor 106.

The conductor 106 functions as a first gate electrode of the transistor 100, the conductor 109a and the conductor 109b function as a source electrode or a drain electrode of the transistor 100, and the insulator 105 functions as a gate insulator of the transistor 100. Is preferable.

Here, the oxide layer 104 can be formed of a single layer or a plurality of layers. For example, FIG.
As shown in (B), the oxide layer 104 is preferably formed by three layers of an oxide layer 104a, an oxide layer 104b, and an oxide layer 104c. The oxide layer 104b is the oxide layer 104a.
The oxide layer 104c is formed in contact with the oxide layer 104b.

The oxide layer 104a and the oxide layer 104c are closer to the insulator than the oxide layer 104b.
Therefore, when a gate voltage is applied, the oxide layer 104a, the oxide layer 104b, and the oxide layer 10 are applied.
Of the 4c, channels are likely to be formed in the oxide layer 104b. Therefore, in the present specification and the like, the oxide layer 104a and the oxide layer 104c may be referred to as insulators.

The transistor 100 shown in FIG. 1B includes an oxide layer 104a on the insulator 103, an oxide layer 104b in contact with the upper surface of the oxide layer 104a, and an oxide layer 104c in contact with the upper surface of the oxide layer 104b. It has an insulator 105 on the oxide layer 104c. Further, the insulator 108 has a region in contact with the upper surface of the insulator 105. Further, the lower surface of the insulator 108 is a conductor 106.
Approximately coincides with the bottom surface of. Further, the conductor 109a and the conductor 109b have an oxide layer 104.
It has a region in contact with the upper surface of b.

Further, the transistor 100 has a region in the oxide layer 104 that overlaps with the insulator 108.
The region overlapping the conductor 109a and the conductor 109b contains a metal element 131 different from the main component of the oxide layer 104. The metal element 131 may also be contained in a part of the insulator 105, the oxide layer 104, and the insulator 103. The end of the region 135 containing the metal element 131 is shown by a broken line in FIG. 1B as an example. In FIG. 1B, the region 135 is formed above the broken line indicating the end of the region 135.

In the oxide layer 104, the region 135 can function as a source region or a drain region of the transistor 100. Therefore, the region sandwiched between the regions 135 of the oxide layer 104 can function as the channel forming region.

As shown in FIG. 1 (B), it is preferable that the height of the upper end of the insulator 110 and the height of the upper ends of the conductor 109a and the conductor 109b are substantially the same. Further, the insulator 110 and the conductor 1
The upper surfaces of 09a, the conductor 109b, the insulator 108, and the insulator 107 preferably form a continuous flat flat surface, on which the insulator 111 is formed.

Further, in FIG. 1 and the like, the oxide layer 104 may have a structure that does not have either the oxide layer 104a or the oxide layer 104c.

As shown in FIG. 1 (B), the insulator 103 may have a convex portion. In that case, it is preferable that the oxide layer 104 is formed in contact with the upper part of the convex portion. Here, the characteristics of the transistor 100 are improved by making the sum of the height of the convex portion and the thickness of the oxide layer 104a larger than the sum of the thickness of the oxide layer 104c and the thickness of the oxide layer 104b. You may be able to.

FIG. 59 (A) shows a modification of the cross section shown in FIG. 1 (B) in the cross section corresponding to the alternate long and short dash line L1-L2. The semiconductor device of one aspect of the present invention does not have to have the insulator 107 on the conductor 106 as in the example shown in FIG. 59 (A). Further, it is more preferable to have the insulator 107 on the conductor 106 as shown in FIG. 1 (B) and the like. Since the transistor 100 has the insulator 107, it may be possible to stabilize the manufacturing process of the transistor 100. By stabilizing the manufacturing process, the characteristics of the transistor 100 can be improved.

Further, the transistor 100 includes the insulator 118 and the conductor 117 on the insulator 102.
May have. In the example shown in FIG. 1 (B), the conductor 117 is formed so as to fill the insulator 118. The insulator 103 is formed so as to fill the insulator 118, and the insulator 103 is the insulator 1.
Formed on 18. Here, it is preferable that the conductor 117 functions as a second gate electrode of the transistor 100. The potential of the second gate electrode may be the same potential as that of the first game of the transistor 100, or may be a ground potential (GND potential) or an arbitrary potential. Further, by changing the potential of the second gate electrode independently without interlocking with the first gate electrode,
The threshold voltage of the transistor can be changed.

By providing the conductor 106 and the conductor 117 with the oxide layer 104 interposed therebetween, and further setting the conductor 106 and the conductor 117 at the same potential, the region where the carrier flows in the oxide layer 104 is in the film thickness direction. As it becomes larger in, the amount of carrier movement increases. As a result, the on-current of the transistor 100 increases and the field effect mobility increases.

Therefore, the transistor 100 is a transistor having a large on-current with respect to the occupied area. That is, the occupied area of the transistor 100 can be reduced with respect to the required on-current. Therefore, it is possible to realize a semiconductor device having a high degree of integration.

Further, since the first gate electrode and the second gate electrode are formed by the conductive layer, the function of preventing the electric field generated outside the transistor from acting on the semiconductor layer on which the channel is formed (particularly, the electric field against static electricity or the like). Has a shielding function). By forming the second gate electrode larger than the semiconductor layer and covering the semiconductor layer with the second gate electrode, the electric field shielding function can be enhanced.

Since the conductor 106 and the conductor 117 each have a function of shielding an electric field from the outside, charges such as charged particles generated above the conductor 106 and below the conductor 117 are charged in the channel forming region of the oxide layer 104. Does not affect. As a result, deterioration of the stress test (for example, applying a negative charge to the gate-GBT (Gate Bias-Temperature) stress test) is suppressed. Further, the conductor 106 and the conductor 117 can be cut off so that the electric field generated from the drain electrode does not act on the semiconductor layer. Therefore, it is possible to suppress fluctuations in the rising voltage of the on-current due to fluctuations in the drain voltage. It should be noted that this effect is remarkable when the electric potential is supplied to the conductor 106 and the conductor 117.

The BT stress test is a kind of accelerated test, and can evaluate the change in transistor characteristics (secular variation) caused by long-term use in a short time. In particular, the fluctuation amount of the threshold voltage of the transistor before and after the BT stress test is an important index for examining the reliability. It can be said that the smaller the fluctuation amount of the threshold voltage is before and after the BT stress test, the higher the reliability of the transistor.

Further, it has a conductor 106 and a conductor 117, and also has a conductor 106 and a conductor 117.
By setting the potentials to the same potential, the fluctuation amount of the threshold voltage is reduced. Therefore, the variation in electrical characteristics among the plurality of transistors is also reduced at the same time.

Further, the transistor having the second gate electrode applies a positive charge to the gate + GB.
The fluctuation of the threshold voltage before and after the T stress test is also smaller than that of the transistor having no second gate electrode.

Further, when light is incident from the second gate electrode side, the light is incident on the semiconductor layer from the second gate electrode side by forming the second gate electrode with a conductive film having a light-shielding property. Can be prevented. Therefore, it is possible to prevent photodegradation of the semiconductor layer and prevent deterioration of electrical characteristics such as a shift of the threshold voltage of the transistor.

Further, among the cross sections shown in FIG. 1 (B), in the cross section corresponding to the alternate long and short dash line L1-L2,
The end 315 of the insulator 108 is located outside the end 316 of the conductor 117, although FIG.
As shown in 0 (A), the positions of the end portion 315 and the end portion 316 may be substantially the same. or,
As shown in FIG. 60 (B), the end portion 315 may be located inside the end portion 316.

Further, the semiconductor device according to one aspect of the present invention includes the insulator 112 on the insulator 111 and the insulator 11.
0, contact plug 113 formed to fill insulator 111 and insulator 112
It may have a, a contact plug 113b, and a contact plug 113c, and a conductor 114a, a conductor 114b, and a conductor 114c on the insulator 112. Conductor 114
The a, the conductor 114b, and the conductor 114c can be used, for example, for wiring or the like.

Further, the semiconductor device according to one aspect of the present invention may have a semiconductor element or the like between the substrate 101 and the insulator 102.

FIG. 2A shows a top view of the semiconductor device according to one aspect of the present invention. FIG. 2 (B) is shown in FIG. 2 (A).
), The cross section of the alternate long and short dash line L1-L2 and the cross section of the alternate long and short dash line W1-W2 are shown. In FIG. 2, the semiconductor device has a transistor 100. In the semiconductor device shown in FIG. 2, the structure of the insulator 108 included in the transistor 100 is different from that in FIG. In FIG. 1B, the lower surface of the insulator 108 substantially coincides with the lower surface of the conductor 106, whereas in FIG. 2B, the lower surface of the insulator 108 substantially coincides with the lower surface of the oxide layer 104c. do. Further, in FIG. 1B, the insulator 108 is in contact with the upper surface of the insulator 105, whereas in FIG. 2B, the insulator 108 is in contact with the upper surface of the oxide layer 104b. Further, the ends of the oxide layer 104c and the insulator 105 substantially coincide with the ends of the insulator 108 in FIG. 1 (B), whereas the ends thereof substantially coincide with the ends of the conductor 106 in FIG. 2 (B). do.

Here, as shown in FIG. 2B, the transistor 100 may have an insulator 108b in contact with the side surface of the oxide layer 104b or the like.

Further, as shown in FIG. 3A, the end portion of the oxide layer 104c may be located outside the end portion of the insulator 108. In the transistor 100 shown in FIG. 3A, the oxide layer 1
The end of 04c is located outside the end of insulator 108. Further, the end portion of the oxide layer 104c is located outside the end portion of the conductor 109a and the conductor 109b.

Further, as shown in FIG. 59B, the end portion of the oxide layer 104c and the end portion of the insulator 105 may be located outside the end portions of the conductor 109a and the conductor 109b. .. Further, the end portion of the oxide layer 104c and the end portion of the insulator 105 may be substantially aligned or may not be aligned as shown in FIG. 59 (B).

Further, as shown in FIG. 59 (C), the end portion of the insulator 105 may be located outside the insulator 108, and may be located inside the conductor 109a or the end portion of the conductor 109b. .. Further, FIG. 59 (C) shows an example in which the end portion of the oxide layer 104c is located outside the end portions of the conductor 109a and the conductor 109b, but may be located inside.

Further, the end portion of the oxide layer 104c may be located outside the end portion of the conductor 109a and the end portion of the conductor 109b. In this case, the conductor 109a and the conductor 109b are
It has an oxide layer 104c between it and the insulator 103.

Further, as shown in FIG. 4, the end portion of the oxide layer 104c may substantially coincide with the oxide layer 104b.

<Explanation of components>

[Oxide layer 104]
The oxide layer 104 preferably has a structure in which the oxide layer 104a, the oxide layer 104b, and the oxide layer 104c are laminated.

As the oxide layer 104, for example, it is preferable to use an oxide semiconductor containing indium (In). When the oxide semiconductor contains, for example, indium, the carrier mobility (electron mobility) becomes high. Further, the oxide semiconductor preferably contains the element M.

The element M is preferably aluminum, gallium, yttrium, tin or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium and the like. However, as the element M, a plurality of the above-mentioned elements may be combined in some cases. The element M is, for example, an element having a high binding energy with oxygen. The element M is, for example, an element having a function of increasing the energy gap of the oxide semiconductor. Further, the oxide semiconductor preferably contains zinc. Oxide semiconductors may be easily crystallized if they contain zinc.

However, the oxide layer 104 is not limited to the oxide containing indium. Oxide layer 104
May be, for example, an oxide containing zinc, an oxide containing gallium, an oxide containing tin, etc., which does not contain indium, such as zinc tin oxide, gallium tin oxide, and gallium oxide.

For the oxide layer 104, for example, an oxide semiconductor having a large energy gap is used. The energy gap of the oxide semiconductor used for the oxide layer 104 is, for example, 2.5 eV or more.
2 eV or less, preferably 2.8 eV or more and 3.8 eV or less, more preferably 3 eV or more 3
.. It is 5 eV or less.

Oxide semiconductors are prepared by sputtering method, CVD (Chemical Vapor Dep).
Osition) method (MOCVD (Metalorganic Chemical V)
apor Deposition) method, ALD (Atomic Layer Depos)
Ition) method, thermal CVD method or PECVD (Plasma Enhanced Ch)
(Includes, but is not limited to, the electrical Vapor Deposition) method),
MBE (Molecular Beam Epitaxy) method or PLD (Pulse)
The film may be formed by using the d Laser Deposition) method. The plasma CVD method can obtain a high quality film at a relatively low temperature. When a film forming method that does not use plasma at the time of film formation, such as a MOCVD method, an ALD method, or a thermal CVD method, is used, the surface to be formed is less likely to be damaged, and a film having few defects can be obtained.

The CVD method and the ALD method are different from the film forming method in which particles emitted from a target or the like are deposited, and are film forming methods in which a film is formed by a reaction on the surface of an object to be treated. Therefore, it is a film forming method that is not easily affected by the shape of the object to be treated and has good step coverage. In particular, the ALD method has excellent step covering property and excellent thickness uniformity, and is therefore suitable for covering the surface of an opening having a high aspect ratio. However, since the ALD method has a relatively slow film forming speed, it may be preferable to use it in combination with another film forming method such as a CVD method having a high film forming speed.

In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of the raw material gas. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the raw material gas. Further, for example, in the CVD method and the ALD method, a film having a continuously changed composition can be formed by changing the flow rate ratio of the raw material gas while forming the film. When forming a film while changing the flow rate ratio of the raw material gas, the time required for film formation can be shortened by the amount of time required for transport and pressure adjustment, as compared with the case of forming a film using multiple film forming chambers. can. Therefore, it may be possible to increase the productivity of transistors and semiconductor devices.

For example, when an InGaZNOX ( _X > 0) film is formed as the oxide layer 104 by a thermal CVD method, trimethylindium (In (CH ₃ ) ₃ ) and trimethylgallium (Ga (Ga (
CH ₃ ) ₃ ) and dimethylzinc (Zn (CH ₃ ) ₂ ) are used. Further, the combination is not limited to these, and instead of trimethylgallium, triethylgallium (Ga (C ₂ H ₅ )) is used.
) ₃ ) can also be used, and instead of dimethylzinc, diethylzinc (Zn (C ₂ H ₅ ) ₂ )
Can also be used.

For example, when an InGaZnO _X (X> 0) film is formed as the oxide layer 104 by the ALD method, In (CH ₃ ) ₃ gas and O ₃ gas are sequentially and repeatedly introduced to form an InO ₂ layer. Then, Ga (CH ₃ ) ₃ gas and O ₃ gas are sequentially and repeatedly introduced to form a GaO layer, and then Zn (CH ₃ ) ₂ gas and O ₃ gas are sequentially and repeatedly introduced to form a ZnO layer. do. The order of these layers is not limited to this example. Also, using these gases, InGa
A mixed compound layer such as an _{O2 layer, an InZNO 2 layer} , a GaInO layer, a ZnInO layer, and a GaZNO layer may be formed. In addition, H ₂ which was bubbled with an inert gas such as Ar instead of O ₃ gas.
O gas may be used _, but it is preferable to use O3 gas that does not contain H. Also, In (C)
H ₃ ) In (C ₂ H ₅ ) ₃ gas or tris (acetylacetonato) indium may be used instead of ₃ gas. Indium (acetylacetonato) is In (aca).
c) Also called ₃ . Further, Ga (C ₂ H ₅ ) ₃ gas or tris (acetylacetonato) gallium may be used instead of Ga (CH ₃ ) ₃ gas. In addition, tris (acetylacetonato) gallium is also referred to as Ga (acac) ₃ . Further, Zn (CH ₃ ) ₂ gas or zinc acetate may be used. It is not limited to these gas species.

When forming an oxide semiconductor by a sputtering method, it is preferable to use a target containing indium in order to reduce the number of particles. Further, when an oxide target having a high atomic number ratio of the element M is used, the conductivity of the target may be low. When a target containing indium is used, the conductivity of the target can be increased, and DC discharge and AC discharge become easy, so that it becomes easy to cope with a large area substrate. Therefore, the productivity of the semiconductor device can be increased.

When the oxide semiconductor is formed by the sputtering method, the atomic number ratio of the target is I.
n: M: Zn is 3: 1: 1, 3: 1: 2, 3: 1: 4, 1: 1: 0.5, 1: 1: 1, 1
It may be 1: 2, 1: 4: 4, 4: 2: 4.1, or the like.

When an oxide semiconductor is formed by a sputtering method, an oxide semiconductor having an atomic number ratio deviating from the target atomic number ratio may be formed. In particular, zinc may have a smaller atomic number ratio of the film formed than the target atomic number ratio. Specifically, the atomic number ratio of zinc contained in the target may be 40 atomic% or more and 90atomic% or less.

The oxide layer 104a and the oxide layer 104c are preferably formed of a material containing one or more of the same metal elements among the elements other than oxygen constituting the oxide layer 104b. When such a material is used, it is possible to make it difficult for an interface state to occur at the interface between the oxide layer 104a and the oxide layer 104b and the interface between the oxide layer 104c and the oxide layer 104b. Therefore, it is possible to improve the electric field effect mobility of the transistor by preventing the scattering and capture of carriers at the interface. In addition, it is possible to reduce the variation in the threshold voltage of the transistor. Therefore, it is possible to realize a semiconductor device having good electrical characteristics.

The thickness of the oxide layer 104a and the oxide layer 104c is 3 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less. The thickness of the oxide layer 104b is 3 nm or more and 2
00 nm or less, preferably 3 nm or more and 100 nm or less, more preferably 3 nm or more and 50
It should be nm or less.

Further, the oxide layer 104b is an In—M—Zn oxide (an oxide containing In, elements M and Zn).
When the oxide layer 104a and the oxide layer 104c are also In—M—Zn oxides,
The oxide layer 104a and the oxide layer 104c are In: M: Zn = x ₁ : y ₁ : z ₁ [atomic number ratio], and the oxide layer 104b is In: M: Zn = x ₂ : y ₂ : z ₂ [ Atomic number ratio], y
Select an oxide layer 104a, an oxide layer 104c, and an oxide layer 104b in which ₁ / x ₁ is larger than y ₂ / x ₂ . Preferably, an oxide layer 104a, an oxide layer 104c, and an oxide layer 104b in which y ₁ / x ₁ is 1.5 times or more larger than y ₂ / x ₂ are selected. More preferably, the oxide layer 104a, in which y ₁ / x ₁ is more than twice as large as y ₂ / x ₂ .
The oxide layer 104c and the oxide layer 104b are selected. More preferably, the oxide layer 104a, the oxide layer 104c and the oxide layer 104b in which y ₁ / x ₁ is three times or more larger than y ₂ / x ₂ are selected. At this time, in the oxide layer 104b, it is preferable that y ₁ is x ₁ or more because stable electrical characteristics can be imparted to the transistor. However, when y ₁ becomes 3 times or more of x ₁ , the field effect mobility of the transistor decreases, so that y ₁ is preferably less than 3 times x ₁ . By having the oxide layer 104a and the oxide layer 104c as described above, the oxide layer 104a and the oxide layer 104c can be made into a layer in which oxygen deficiency is less likely to occur than the oxide layer 104b.

When the oxide layer 104a is an In—M—Zn oxide, the sum of In and M is 100a.
When it is set to tomic%, In is preferably less than 50atomic% and M is 50atom.
Higher than ic%, more preferably In is less than 25 atomic%, M is 75 atomi
Make it higher than c%. When the oxide layer 104b is an In—M—Zn oxide and the sum of In and M is 100 atomic%, In is preferably higher than 25 atomic%, M is less than 75 atomic%, and In is more preferably 34 atomic. % And M is less than 66 atomic%. Further, when the oxide layer 104c is an In—M—Zn oxide and the sum of In and M is 100 atomic%, In is preferably 50a.
Less than tomic%, M is higher than 50atomic%, more preferably In is 25 at
Less than omic%, M is higher than 75atomic%. The oxide layer 104c may use an oxide of the same type as the oxide layer 104a.

For example, as the oxide layer 104a containing In or Ga and the oxide layer 104c containing In or Ga, In: Ga: Zn = 1: 3: 2, 1: 3: 4, 1: 3: 6, 1: 1. 6:
In-Ga-Zn oxide formed using a target with an atomic number ratio such as 4, or 1: 9: 6, or a target with an atomic number ratio such as In: Ga = 1: 9 or 7:93 is used. In-Ga oxide formed in the above can be used. Further, as the oxide layer 104b, for example,
In—Ga—Zn oxide formed using a target having an atomic number ratio such as In: Ga: Zn = 1: 1: 1 or 3: 1: 2 can be used. The atomic number ratios of the oxide layer 104a and the oxide layer 104b are, respectively, plus or minus 20 of the above atomic number ratios as errors.
Includes% fluctuation.

As the oxide layer 104b, an oxide having a higher electron affinity than the oxide layer 104a and the oxide layer 104c is used. For example, the oxide layer 104b has an electron affinity of 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV, as compared with the oxide layer 104a and the oxide layer 104c.
An oxide larger than 0.7 eV or more, more preferably 0.15 eV or more and 0.4 eV or less is used. The electron affinity is the difference between the vacuum level and the energy at the lower end of the conduction band.

Indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, it is preferable that the oxide layer 104c contains indium gallium oxide. The gallium atom ratio [Ga / (In + Ga)] is, for example, 70% or more, preferably 80% or more.
More preferably, it is 90% or more.

However, the oxide layer 104a and / and the oxide layer 104c may be gallium oxide. For example, when gallium oxide is used as the oxide layer 104c, the leakage current generated between the electrode 105a or the electrode 105b and the conductor 106 can be reduced. That is, the off-current of the transistor 100 can be reduced.

The oxide layer 104a and the oxide layer 104c are closer to an insulator than the oxide layer 104b because they have a smaller electron affinity than, for example, the oxide layer 104b. Therefore, when a gate voltage is applied, the oxide layer 104b among the oxide layer 104a, the oxide layer 104b, and the oxide layer 104c is applied.
Channels are likely to be formed.

Further, in order to impart stable electrical characteristics to a transistor (also referred to as "OS transistor") using an oxide semiconductor in the semiconductor layer on which a channel is formed, impurities and oxygen deficiency in the oxide semiconductor are reduced. It is preferable that the oxide layer 104b is made into an oxide semiconductor which can be regarded as genuine or substantially genuine. For example, by supplying excess oxygen to the oxide layer 104b, oxygen deficiency may be reduced. Also, at least the oxide layer 1
It is preferable to use an oxide semiconductor in which the channel forming region in 04b can be regarded as genuine or substantially genuine.

Further, among the oxide layers 104, at least the oxide layer 104b has CAAC-OS (CA).
xis Defined Crystalline Oxide Semiconduc
It is preferable to use tor). The CAAC-OS will be described in detail in a later embodiment.

Here, the region other than the region not CAAC or the region having c-axis orientation is preferably at least 20% or less of the entire oxide semiconductor film used for the oxide layer 104b.

CAAC-OS has dielectric anisotropy. Specifically, CAAC-OS has a larger dielectric constant in the c-axis direction than the dielectric constant in the a-axis direction and the b-axis direction. A transistor in which the gate electrode is arranged in the c-axis direction by using CAAC-OS on the semiconductor film on which the channel is formed has a large dielectric constant in the c-axis direction, so that the electric field generated from the gate electrode easily reaches the entire CAAC-OS. ..
Therefore, the subthreshold swing value (S value) can be reduced. Further, in a transistor using CAAC-OS for a semiconductor film, an increase in S value due to miniaturization is unlikely to occur.

Further, since the CAAC-OS has a small dielectric constant in the a-axis direction and the b-axis direction, the influence of the electric field generated between the source and the drain is alleviated. Therefore, the channel length modulation effect and the short channel effect are less likely to occur, and the reliability of the transistor can be improved.

Here, the channel length modulation effect refers to a phenomenon in which the depletion layer expands from the drain side and the effective channel length becomes shorter when the drain voltage is higher than the threshold voltage. The short-channel effect is a phenomenon in which the electrical characteristics are deteriorated, such as a decrease in the threshold voltage, due to the shortening of the channel length. The finer the transistor, the more likely it is that the electrical characteristics will deteriorate due to these phenomena.

[Energy band structure of oxide semiconductor film]
Here, the function and effect of the oxide layer 104 composed of the laminated oxide layer 104a, the oxide layer 104b, and the oxide layer 104c will be described with reference to the energy band structure diagram shown in FIG. 21 (A). do. 21 (A) shows the energy band structure of the portion shown by the alternate long and short dash line of A1-A2 in FIG. 1 (B). That is, FIG. 21A shows the energy band structure of the channel formation region of the transistor 100.

In FIG. 21 (A), Ec382, Ec383a, Ec383b, Ec383c, Ec38
6 is an insulator 103, an oxide layer 104a, an oxide layer 104b, and an oxide layer 104, respectively.
c, shows the energy at the lower end of the conduction band of the insulator 105. Further, FIG. 21B shows an example in the case where the oxide layer 104a is not used.

Here, the electron affinity is a value obtained by subtracting the energy gap from the difference between the vacuum level and the energy at the upper end of the valence band (also referred to as “ionization potential”). The energy gap is the spectroscopic ellipsometer (HORIBA JOBIN YVON UT-300).
) Can be measured. In addition, the energy difference between the vacuum level and the upper end of the valence band is determined by UV photoelectron spectroscopy (UPS).
It can be measured using a roscopy) device (PHI VersaProbe).

In-formed using a target having an atomic number ratio of In: Ga: Zn = 1: 3: 2.
The energy gap of Ga—Zn oxide is about 3.5 eV, and the electron affinity is about 4.5 eV. In addition, In formed by using a target having an atomic number ratio of In: Ga: Zn = 1: 3: 4.
The energy gap of the -Ga-Zn oxide is about 3.4 eV, and the electron affinity is about 4.5 eV. Further, I formed by using a target having an atomic number ratio of In: Ga: Zn = 1: 3: 6.
The energy gap of n-Ga-Zn oxide is about 3.3 eV, and the electron affinity is about 4.5 eV.
Is. Further, the energy gap of the In—Ga—Zn oxide formed by using a target having an atomic number ratio of In: Ga: Zn = 1: 6: 2 is about 3.9 eV, and the electron affinity is about 4.3 e.
It is V. Further, the energy gap of the In—Ga—Zn oxide formed by using a target having an atomic number ratio of In: Ga: Zn = 1: 6: 8 is about 3.5 eV, and the electron affinity is about 4.4.
It is an eV. Further, the energy gap of the In—Ga—Zn oxide formed by using a target having an atomic number ratio of In: Ga: Zn = 1: 6: 10 is about 3.5 eV, and the electron affinity is about 4.
.. It is 5 eV. Further, the energy gap of the In—Ga—Zn oxide formed by using a target having an atomic number ratio of In: Ga: Zn = 1: 1: 1 is about 3.2 eV, and the electron affinity is about 4.7 eV. Further, the energy gap of the In—Ga—Zn oxide formed by using a target having an atomic number ratio of In: Ga: Zn = 3: 1: 2 is about 2.8 eV, and the electron affinity is about 5.0 eV.

Since the insulator 103 and the insulator 105 are insulators, Ec382 and Ec386 are Ec3.
Closer to vacuum level (less electron affinity) than 83a, Ec383b, and Ec383c.

Further, Ec383a is closer to the vacuum level than Ec383b. Specifically, Ec383
It is preferable that a is 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, and more preferably 0.15 eV or more and 0.4 eV or less closer to the vacuum level than Ec383b.

Further, Ec383c is closer to the vacuum level than Ec383b. Specifically, Ec383
c is preferably 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, and more preferably 0.15 eV or more and 0.4 eV or less closer to the vacuum level than Ec383b.

Here, between the oxide layer 104a and the oxide layer 104b, there may be a mixed region of the oxide layer 104a and the oxide layer 104b. Further, the oxide layer 104b and the oxide layer 104
There may be a mixed region of the oxide layer 104b and the oxide layer 104c between the c and the oxide layer 104b.
The interface state density is low in the mixed region. Therefore, the oxide layer 104a and the oxide layer 104b
The laminate of the oxide layer 104c and the oxide layer 104c has a band structure in which the energy continuously changes (also referred to as continuous bonding) in the vicinity of each interface.

At this time, the electrons mainly move in the oxide layer 104b, not in the oxide layer 104a and the oxide layer 104c. Therefore, the oxide layer 104a and the oxide layer 104b
By lowering the interface state density at the interface of the above and the interface state density at the interface between the oxide layer 104b and the oxide layer 104c, the movement of electrons in the oxide layer 104b is less likely to be hindered, and the transistor 100 is used. The on-current of the can be increased.

Further, the interface between the oxide layer 104a and the insulator 103, and the oxide layer 104c and the insulator 10
Although trap levels 390 due to impurities and defects may be formed near the interface of 5.
The presence of the oxide layer 104a and the oxide layer 104c can keep the oxide layer 104b away from the trap level.

When the transistor 100 has an s-channel structure, the oxide layer 104b
Channels are formed throughout. Therefore, the thicker the oxide layer 104b, the larger the channel region. That is, the thicker the oxide layer 104b, the higher the on-current of the transistor 100 can be. For example, the oxide layer 104b having a region having a thickness of 20 nm or more, preferably 40 nm or more, more preferably 60 nm or more, and more preferably 100 nm or more.
And it is sufficient. However, since the productivity of the semiconductor device having the transistor 100 may decrease, for example, it is 300 nm or less, preferably 200 nm or less, and more preferably 1.
The oxide layer 104b having a region having a thickness of 50 nm or less may be used.

Further, in order to increase the on-current of the transistor 100, it is preferable that the thickness of the oxide layer 104c is small. For example, the oxide layer 104c having a region of less than 10 nm, preferably 5 nm or less, more preferably 3 nm or less may be used. On the other hand, the oxide layer 104c is
Elements other than oxygen constituting an insulator adjacent to the oxide layer 104b on which channels are formed (
It has a function to block hydrogen, silicon, etc. from entering. Therefore, the oxide layer 104c preferably has a certain thickness. For example, the oxide layer 104c having a region having a thickness of 0.3 nm or more, preferably 1 nm or more, more preferably 2 nm or more.
And it is sufficient.

Further, in order to increase the reliability, it is preferable that the oxide layer 104a is thick and the oxide layer 104c is thin. For example, 10 nm or more, preferably 20 nm or more, more preferably 4
The oxide layer 104a having a region having a thickness of 0 nm or more, more preferably 60 nm or more may be used. By increasing the thickness of the oxide layer 104a, the adjacent insulator and the oxide layer 104 can be increased.
The distance from the interface with a to the oxide layer 104b on which the channel is formed can be increased.
However, since the productivity of the semiconductor device having the transistor 100 may decrease, for example, the oxide layer 104a having a region having a thickness of 200 nm or less, preferably 120 nm or less, and more preferably 80 nm or less may be used.

Silicon in the oxide semiconductor may be a carrier trap or a carrier generation source. Therefore, the lower the silicon concentration of the oxide layer 104b, the more preferable. For example, between the oxide layer 104b and the oxide layer 104a, for example, secondary ion mass spectrometry (SIMS::
In Secondary Ion Mass Spectrometry), 1 × 1
It has a region having a silicon concentration of less than 0 ¹⁹ atoms / cm ³ , preferably less than 5 × 10 ¹⁸ atoms / cm ³ , more preferably less than 2 × 10 ¹⁸ atoms / cm ³ .
Further, in SIMS between the oxide layer 104b and the oxide layer 104c, 1 × 10 ¹⁹
It has a region having a silicon concentration of less than atoms / cm ³ , preferably less than 5 × 10 ¹⁸ atoms / cm ³ , more preferably less than 2 × 10 ¹⁸ atoms / cm ³ .

Further, in order to reduce the hydrogen concentration of the oxide layer 104b, it is preferable to reduce the hydrogen concentration of the oxide layer 104a and the oxide layer 104c. Oxide layer 104a and oxide layer 104c
Is 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ in SIMS.
It has a region having a hydrogen concentration of atoms / cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ³ or less, still more preferably 5 × 10 ¹⁸ atoms / cm ³ or less. also,
In order to reduce the nitrogen concentration of the oxide layer 104b, the oxide layer 104a and the oxide layer 104
It is preferable to reduce the nitrogen concentration of c. The oxide layer 104a and the oxide layer 104c are SI.
In MS, less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms
It has a region having a nitrogen concentration of s / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, still more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

If copper is mixed in the oxide semiconductor, an electron trap may be generated. In the electronic trap, the threshold voltage of the transistor may fluctuate in the positive direction. Therefore, the lower the copper concentration on the surface or inside of the oxide layer 104b, the more preferable. For example, the oxide layer 104b, the copper concentration is 1 × 10 ¹⁹ atoms / cm ³ or less, and 5 × 10 ¹⁸ atoms.
It is preferable to have a region of / cm ³ or less, or 1 × 10 ¹⁸ atoms / cm ³ or less.

The above-mentioned three-layer structure is an example. For example, a two-layer structure without the oxide layer 104a or the oxide layer 104c may be used. Alternatively, above or below the oxide layer 104a, or above or below the oxide layer 104c, the oxide layer 104a, the oxide layer 104b, and the oxide layer 104
A four-layer structure having any one of the semiconductors exemplified as c may be used. Alternatively, the oxide layer 104a, the oxide layer 104b, and the oxide layer may be located at one of two or more locations, above the oxide layer 104a, below the oxide layer 104a, above the oxide layer 104c, and below the oxide layer 104c. 104
An n-layer structure having any one of the semiconductors exemplified as c (n is an integer of 5 or more) may be used.

In particular, in the transistor 100 exemplified in this embodiment, the upper surface and the side surface of the oxide layer 104b are in contact with the oxide layer 104c and the lower surface of the oxide layer 104b is in contact with the oxide layer 104a in the channel width direction. (See FIG. 1 (C)). Thus, the oxide layer 104
By covering b with the oxide layer 104a and the oxide layer 104c, the influence of the trap level can be further reduced.

Further, the band gaps of the oxide layer 104a and the oxide layer 104c are set to the oxide layer 10.
It is preferably wider than the bandgap of 4b.

According to one aspect of the present invention, it is possible to realize a transistor having little variation in electrical characteristics. Therefore, it is possible to realize a semiconductor device having little variation in electrical characteristics. According to one aspect of the present invention, a transistor with good reliability can be realized. Therefore, it is possible to realize a semiconductor device with good reliability.

Further, since the band gap of the oxide semiconductor is 2 eV or more, the transistor using the oxide semiconductor for the semiconductor film on which the channel is formed can make the off-current extremely small. Specifically, when the voltage between the source and drain is 3.5 V and the room temperature (25 ° C) is normal, the off current per 1 μm of channel width is less than 1 × ^{10-20 A, 1 × 10-22 A} , or 1 It can be less than × ^10-24A . That is, the on / off ratio is 20 digits or more and 15
It can be 0 digits or less.

According to one aspect of the present invention, a transistor with low power consumption can be realized. Therefore, it is possible to realize a semiconductor device with low power consumption.

[Insulator 102]
The insulator 102 includes aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum nitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon nitride nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, and lanthanum oxide. , Neodim oxide, Hafnium oxide, Tantalum oxide, Aluminum silicate, etc. are used in a single layer or in a laminated manner. Further, among the oxide material, the nitride material, the oxide nitride material, and the nitride oxide material, a material obtained by mixing a plurality of materials may be used.

In the present specification, the nitride oxide refers to a compound having a higher nitrogen content than oxygen. Further, the oxidative nitride refers to a compound having a higher oxygen content than nitrogen. The content of each element is, for example, Rutherford Backscattering Method (RBS: Rutherford Ba).
It can be measured using ckscattering Spectrometry) or the like.

In particular, the insulator 102 is preferably formed by using an insulating material having a low permeability of impurities. For example, low oxygen permeability is preferred. Further, for example, it is preferable that the permeability of hydrogen is low. For example, insulating materials containing boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lantern, neodymium, hafnium or tantalum, in a single layer or It may be used in lamination. For example, aluminum oxide, aluminum nitride, aluminum nitride, aluminum nitride, aluminum nitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide are examples of insulating materials with low permeability of impurities. , Silicon nitride and the like. Further, as the insulator 102, indium tin oxide (In—Sn—Zn oxide) having high insulating properties may be used.

The insulator 102 may have an oxide having indium. Insulator 10
2 may have an oxide having indium and zinc. Further, the insulator 102 may have an oxide having indium, zinc, and the element M. Oxygen permeability may be reduced by having the insulator 102 having an oxide having indium, an oxide having indium and zinc, or an oxide having indium, zinc, and the element M.

The method for forming the insulator 102 is not particularly limited, and various forming methods such as a sputtering method, a CVD method, an MBE method or a PLD method, an ALD method, and a spin coating method can be used. The thickness of the insulator 102 and the insulator 110 is 10 nm or more and 500 nm or less, preferably 50.
It may be nm or more and 300 nm or less.

For example, when aluminum oxide is formed as the insulator 102 by using the thermal CVD method, a raw material gas obtained by vaporizing a liquid (TMA or the like) containing a solvent and an aluminum precursor compound and H ₂ O as an oxidizing agent are used. Two types of gas are used. The chemical formula of trimethylaluminum is Al (CH ₃ ) ₃ . Examples of other material liquids include tris (dimethylamide) aluminum, triisobutylaluminum, and aluminum tris (2,2,6,6-tetramethyl-3,5-heptanedionate).

By using an insulating material having low impurity permeability for the insulator 102, it is possible to suppress the diffusion of impurities from the substrate 101 side and improve the reliability of the transistor. By using an insulating material having low impurity permeability for the insulator 111, it is possible to suppress the diffusion of impurities from the insulator 112 side and improve the reliability of the transistor.

As the insulator 102, a plurality of insulators formed of these materials may be laminated and used.

[Insulator 111 and Insulator 110b]
Further, it is preferable that the insulator 111 and the insulator 110b are formed by using an insulating material having a low permeability of impurities. For example, the insulator 111 and the insulator 110b preferably have low oxygen permeability. Further, for example, it is preferable that the insulator 111 and the insulator 110b have low hydrogen permeability. Further, for example, it is preferable that the insulator 111 and the insulator 110b have low water permeability. Materials that can be used for insulator 111 and insulator 110b,
For the method of manufacturing the insulator 111 and the insulator 110b, the description of the insulator 102 can be referred to.

Due to the low oxygen permeability of the insulator 111 and the insulator 110b, the oxide layer 104b
It may be possible to prevent the excess oxygen supplied to the surface from diffusing outward.

[Insulator 103]
Examples of the insulator 103 include silicon oxide, silicon nitriding, silicon nitride, and the like.
Silicon nitride, aluminum oxide, aluminum nitride nitride, aluminum nitride, aluminum nitride or the like may be used, and the material may be laminated or formed in a single layer. Sputtering method, CVD method (thermal CVD method, MOCVD method, PEC) are used to form the insulator 402 and the insulator 412.
The VD method and the like), the MBE method, the ALD method, the PLD method and the like can be used. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method, because the covering property can be improved. Also, to reduce the damage caused by plasma, heat CV
The D method, MOCVD method or ALD method is preferable.

Further, the insulator 103 may have a charge capture layer. For example, as shown in FIG. 4B, the insulator 103 has a laminated structure of the insulator 103a, the insulator 103b, and the insulator 103c.
By using hafnium oxide, aluminum oxide, tantalum oxide, aluminum silicate, or the like as the insulator 103b, the insulator 103b may be used as the charge capture layer. As the insulator 103a and the insulator 103c, for example, silicon oxide, silicon nitride nitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum nitride nitride, aluminum nitride, aluminum nitride and the like can be used. By injecting electrons into the insulator 103b, it is possible to change the threshold voltage of the transistor. For the injection of electrons into the insulator 103b, for example, the tunnel effect may be used. By applying a positive voltage to the conductor 117, tunnel electrons can be injected into the insulator 103b.

Insulator 103 can be formed using the same materials and methods as insulator 102. Further, it is preferable to reduce the hydrogen concentration of the insulator 103 in order to prevent an increase in the hydrogen concentration in the oxide layer 104. Specifically, the hydrogen concentration in the insulator 103 is set to 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ in SIMS.
Below, more preferably 1 × 10 ¹⁹ atoms / cm ³ or less, still more preferably 5 × 10
¹⁸ atoms / cm ³ or less. Further, in order to prevent an increase in the nitrogen concentration in the oxide semiconductor, it is preferable to reduce the nitrogen concentration in the insulator 103. Specifically, the insulator 103
In SIMS, the nitrogen concentration in the medium is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm.
³ or less, more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

Further, the insulator 103 is preferably formed by using an insulator (also referred to as an "insulator containing excess oxygen") in which oxygen is released by heating. Specifically, in TDS analysis, the amount of oxygen desorbed in terms of oxygen atoms is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 3.
.. It is preferable to use an insulator having 0 × 10 ²⁰ atoms / cm ³ or more.

Further, the insulator containing excess oxygen can also be formed by subjecting the insulator to a treatment of adding oxygen. The treatment of adding oxygen can be performed by heat treatment under an oxygen atmosphere, or by using an ion implantation device, an ion doping device, or a plasma processing device. As the gas for adding oxygen, oxygen gas such as ¹⁶ O ₂ or ¹⁸ O ₂ , nitrous oxide gas, ozone gas, or the like can be used. In addition, in this specification, the process of adding oxygen is also referred to as "oxygen doping process". The process of adding oxygen is, for example, after the film formation of the insulator 118, and then the insulator 103.
This may be performed after the film formation of the oxide layer 104e and before the film formation of the oxide layer 104e. Further, high-density plasma treatment or the like may be performed. The high-density plasma may be generated by using microwaves. In the high-density plasma treatment, for example, an oxidizing gas such as oxygen or nitrous oxide may be used. Alternatively, a mixed gas of an oxidizing gas and a rare gas such as He, Ar, Kr, and Xe may be used. In high density plasma processing, a bias may be applied to the substrate. As a result, oxygen ions and the like in the plasma can be drawn into the substrate side. The high-density plasma treatment may be performed while heating the substrate. For example, when high-density plasma treatment is performed instead of the heat treatment, the same effect can be obtained at a temperature lower than the temperature of the heat treatment. The high-density plasma treatment may be performed, for example, after the film formation of the insulator 118, the film formation of the insulator 103, and the film formation of the oxide layer 104e.

Here, for example, a so-called multi-chamber device having a processing chamber for forming an insulator 103, a processing chamber for performing high-density plasma processing, and a substrate processing chamber for transporting between each chamber. Is preferable because the film formation of the insulator 103 and the high-density plasma treatment can be continuously performed without exposing to the atmosphere, thereby reducing the mixing of impurities in the film and at the interface. In addition, the process time can be shortened, which may lead to cost reduction. In addition, the process can be simplified and the yield may be improved. Here, for example, the substrate processing chamber may have a reduced pressure atmosphere.

Similarly, for example, a treatment chamber for forming the insulator 103, a treatment chamber for forming the oxide layer 104d, a treatment chamber for forming the oxide layer 104e, and a high-density plasma treatment are performed. By using a multi-chamber device having a processing chamber for performing and a substrate transport chamber for transporting between the processing chambers, the film formation of the insulator 103, the high-density plasma treatment, and the oxide layer 104d are performed. The film formation of the oxide layer 104e and the film formation of the oxide layer 104e can be continuously performed without being exposed to the atmosphere, which is preferable.

The thickness of the insulator 103 is preferably 1 nm or more and 50 nm or less, more preferably 3 nm or more and 30 nm or less, and further preferably 5 nm or more and 10 nm or less. Oxygen doping treatment may be performed after the formation of the oxide layer 104f. Further, oxygen doping treatment may be performed after the insulator 103 is formed. Further, the heat treatment may be performed after the insulator 103 is formed. In this embodiment,
For example, silicon oxide is formed as the insulator 103.

<Structure example 2>
FIG. 5A is a top view of the semiconductor device. Further, FIG. 6A shows the alternate long and short dash line L shown in FIG.
FIG. 6B shows a cross section of 1-L2, and FIG. 6B shows a cross section of the alternate long and short dash line W1-W2 shown in FIG. 5A. The semiconductor device shown in FIGS. 5 (A), 6 (A) and (B) is a transistor 10.
Insulator 111 located above 0 and insulator 102 located below transistor 100
And an insulator 110b that surrounds the four sides of the transistor 100. The insulator 102, the insulator 111, and the insulator 110b surround the transistor 100 on six sides. Further, in FIG. 6A, the insulator 110b is the contact plug 113a or the contact plug 1.
It is located outside 13b. Further, in FIG. 6B, the insulator 110b is located outside the contact plug 113c and the contact plug 113d. Here, the outside means, for example, a longer distance from the transistor 100 with the transistor 100 as the center.

Further, as shown in FIG. 5B, the insulator 102, the insulator 111, and the insulator 110b
May have a structure that surrounds a plurality of transistors 100. On the upper surface of the semiconductor device shown in FIG. 5B, two transistors 100 are surrounded by an insulator 110b. Further, although not shown, in the cross section of the semiconductor device, the insulator 111 is above the two transistors 100.
And has an insulator 102 below. Therefore, the two transistors 100 are the insulator 1.
02, insulator 111 and insulator 110b surround on six sides. Further, it is preferable that the insulator 110b has a closed shape on the upper surface of the semiconductor device. Closed shapes include, for example, polygons, circles, ellipses, and closed curves that connect curves and straight lines. For example, it may be a quadrangle as shown in FIG. 5 (A), or it may be a quadrangle as shown in FIG. 5 (B).
The quadrangle may have rounded corners.

The characteristics of the transistor 100 may fluctuate with the movement of water, hydrogen, or oxygen. Since the insulator 102, the insulator 111, and the insulator 110b surround the transistor 100 on all sides, hydrogen and hydrogen are mixed into the transistor 100 from the outside of the enclosed area, and the transistor 100 is outside the enclosed area. It is possible to suppress the release of oxygen. Therefore, fluctuations in the characteristics of the transistor 100 can be suppressed.

In the present embodiment, one aspect of the present invention has been described. Alternatively, in another embodiment, one aspect of the present invention will be described. However, one aspect of the present invention is not limited to these. That is, since various aspects of the invention are described in this embodiment and other embodiments, one aspect of the present invention is not limited to a specific aspect. For example, as one aspect of the present invention, an example is shown in which a channel forming region, a source / drain region, and the like of a transistor such as a transistor 100 have an oxide semiconductor, but one aspect of the present invention is not limited thereto. In some cases, or depending on the circumstances, the various transistors in one aspect of the present invention, the channel formation region of the transistor, the source / drain region of the transistor, and the like may have various semiconductors. In some cases, or depending on the circumstances, various transistors, transistor channel forming regions, or, depending on the circumstances, in one aspect of the invention.
The source / drain region of the transistor may have at least one such as silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor. Or, for example, in some cases or, depending on the circumstances, the various transistors in one aspect of the invention, the channel formation region of the transistor, the source / drain region of the transistor, etc., even if they do not have an oxide semiconductor. good.

(Embodiment 2)
In this embodiment, a method for manufacturing the semiconductor device shown in the first embodiment will be described.

<Manufacturing method>
A method for manufacturing the semiconductor device shown in FIG. 1 will be described with reference to FIGS. 7 to 14.

An insulator 102 is formed on the substrate 101. Next, the insulator 118 is formed on the insulator 102. Next, the mask 301 is formed on the insulator 118 (see FIG. 7A).

The material used as the substrate 101 is not largely limited, but it is required to have at least heat resistance enough to withstand the subsequent heat treatment. For example, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used.

Further, as the substrate 101, a single crystal semiconductor substrate made of silicon, silicon carbide, or the like as a material,
A polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium or the like may be used. Further, it is also possible to use an SOI substrate or a semiconductor device in which a semiconductor element such as a strain transistor or a FIN type transistor is formed on the semiconductor substrate. Alternatively, a high electron mobility transistor (HEMT: High Electron Mobility Transis)
You may use gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide, silicon germanium and the like applicable to tor). That is, the substrate 101 is not limited to a simple support substrate, but may be a substrate on which a device such as another transistor is formed. In this case, at least one of the gate, source, or drain of the transistor 100 may be electrically connected to the other device.

A flexible substrate (flexible substrate) may be used as the substrate 101. When a flexible substrate is used, a transistor, a capacitive element, or the like may be directly manufactured on the flexible substrate, or a transistor, a capacitive element, or the like may be manufactured on another manufactured substrate, and then the flexible substrate is formed. It may be peeled off or transposed. It is preferable to form a peeling layer between the manufacturing substrate and a transistor, a capacitive element, or the like in order to peel and transfer from the manufacturing substrate to the flexible substrate.

As the flexible substrate, for example, metal, alloy, resin or glass, fibers thereof, or the like can be used. The flexible substrate used for the substrate 101 is preferable because the lower the coefficient of linear expansion, the more the deformation due to the environment is suppressed. As the flexible substrate used for the substrate 101, for example, a material having a linear expansion coefficient of 1 × 10 ^-3 / K or less, 5 × 10 ^-5 / K or less, or 1 × 10 ^-5 / K or less may be used. .. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic resin and the like. In particular, aramid has a low coefficient of linear expansion and is therefore suitable as a flexible substrate.

The mask 301 may be manufactured by a lithography method using, for example, a resist. Further, a hard mask made of an inorganic film or a metal film may be formed. The resist mask can be formed by appropriately using a photolithography method, a printing method, an inkjet method, or the like.
If the resist mask is formed by a printing method, an inkjet method, or the like, the photomask is not used, so that the manufacturing cost can be reduced.

The resist mask is formed by the photolithography method by irradiating the photosensitive resist with light through the photomask and removing the resist in the exposed portion (or the non-exposed portion) with a developing solution. The light irradiating the photosensitive resist is KrF excimer laser light, Ar.
There are F excimer laser light, EUV (Extreme Ultraviolet) light and the like. Further, an immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens for exposure. Further, instead of the above-mentioned light, an electron beam or an ion beam may be used. When an electron beam or an ion beam is used, a photomask is not required. The resist mask can be removed by a dry etching method such as ashing or a wet etching method using a special peeling liquid or the like. Both the dry etching method and the wet etching method may be used.

Next, using the mask 301, a part of the insulator 118 is removed to form the opening 306 (see FIG. 7B). For removing the insulator 118, for example, dry etching may be used.

Next, a conductor 117d is formed on the upper surface of the insulator 118 and in the opening 306 (FIG. 7 (FIG. 7).
See C). ).

Next, the conductor 117 is formed by removing a part of the conductor 117d (FIG. 7 (FIG. 7).
D) See. ). To remove the conductor 117d, for example, chemical mechanical polishing (Chemical)
It is preferable to use a polishing method such as the Mechanical Polishing (CMP) method. Alternatively, dry etching may be used. For example, a method such as etch back may be used.

Here, the CMP method is a method of flattening the surface of a work piece by a combined chemical and mechanical action. Generally, a polishing cloth is attached on the polishing stage, and the polishing stage and the work piece are rotated or swung while supplying a slurry (abrasive) between the work piece and the work piece to make the slurry. This is a method of polishing the surface of a work piece by a chemical reaction between the surface of the work piece and the surface of the work piece and the action of mechanical polishing between the polishing cloth and the work piece.

Next, the insulator 103, the oxide layer 104d, and the oxide layer 104e are formed on the insulator 118 and the conductor 117 in this order.

Next, in order to further reduce impurities such as water or hydrogen contained in the oxide layer 104d and the oxide layer 104e and to purify the oxide layer 104d and the oxide layer 104e.
It is preferable to perform heat treatment.

For example, the amount of water measured under a reduced pressure atmosphere, an inert atmosphere such as nitrogen or a rare gas, an oxidizing atmosphere, or an ultra-dry air (CRDS (cavity ring-down laser spectroscopy)) dew point meter is used. The oxide layer 104d and the oxide layer 10 under an atmosphere of 20 ppm (-55 ° C. in terms of dew point) or less, preferably 1 ppm or less, preferably 10 ppb or less).
Heat treatment is applied to 4e. The oxidizing atmosphere means an atmosphere containing 10 ppm or more of an oxidizing gas such as oxygen, ozone or oxygen nitride. The inert atmosphere means an atmosphere in which the above-mentioned oxidizing gas is less than 10 ppm and is filled with nitrogen or a noble gas.

Further, by performing the heat treatment, oxygen contained in the insulator 103 is diffused into the oxide layer 104d and the oxide layer 104e at the same time as the release of impurities, and the oxygen deficiency contained in the oxide semiconductor layer is reduced. Can be done. After the heat treatment in an atmosphere of an inert gas, the heat treatment may be performed in an atmosphere containing 10 ppm or more and 1% or more or 10% or more of an oxidizing gas in order to supplement the desorbed oxygen. The heat treatment was performed on the oxide layer 104d and the oxide layer 10.
It may be performed at any time after the formation of 4e. For example, the oxide layer 104a and the oxide layer 10
Heat treatment may be performed after the formation of 4b. Further, it may be performed after the formation of the oxide layer 104c which is performed later.

The heating device used for the heat treatment is not particularly limited, and may be a device that heats the object to be treated by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, an electric furnace or L
RTA (Lamp Rapid Thermal Anneal) device, GRTA (Ga)
RTA (Rapid The) such as s Rapid Thermal Anneal) equipment
An rmal Anneal) device can be used. The LRTA device is a device that heats an object to be processed by radiation of light (electromagnetic waves) emitted from lamps such as halogen lamps, metal halide lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, and high-pressure mercury lamps. The GRTA device is a device that performs heat treatment using a high-temperature gas.

The heat treatment may be performed at 250 ° C. or higher and 650 ° C. or lower, preferably 300 ° C. or higher and 500 ° C. or lower. The processing time shall be within 24 hours. Heat treatment for more than 24 hours is not preferable because it causes a decrease in productivity.

The oxygen doping treatment may be performed after the formation of the oxide layer 104d or after the formation of the oxide layer 104e.

Next, the mask 302 is formed on the oxide layer 104e (see FIG. 8A). Mask 3
For 02, refer to mask 301. Then, using the mask 302, the oxide layer 104
e, a part of each of the oxide layer 104d and the insulator 103 is removed to form the oxide layer 104a and the oxide layer 104b (see FIG. 8B). Oxide layer 104e, oxide layer 104
For example, dry etching or wet etching can be used to remove d and the insulator 103.

When etching a conductor, a semiconductor, or an insulator by a dry etching method, a gas containing a halogen element can be used as the etching gas. Examples of gases containing halogen elements include chlorine (Cl ₂ ), boron trichloride (BCl ₃ ), and silicon tetrachloride (SiCl ₄ ).
) Or carbon tetrachloride (CF ₄ ), a chlorine-based gas typified by carbon tetrachloride (CCl ₄ ), etc.
), Sulfur hexafluoride (SF ₆ ), nitrogen trifluoride (NF ₃ ) or trifluoromethane (C)
Fluorine-based gas such as HF ₃ ), hydrogen bromide (HBr) or oxygen can be appropriately used. Further, an inert gas may be added to the etching gas to be used. In addition, methane (CH ₄ ) and ethane (C ₂ ) are used as etching gases for etching oxide semiconductors.
A mixed gas of a hydrocarbon gas such as H ₆ ), propane (C ₃ H ₈ ), or butane (C ₄ H ₁₀ ) and an inert gas may be used.

As a dry etching method, a parallel plate type RIE (Reactive Ion) is used.
Etching) method and ICP (Inductively Coupled Plasma)
a: Inductively coupled plasma) method, DF-CCP (Dual Frequency Capa)
Citivery Coupled Plasma: dual frequency excitation capacitive coupled plasma) method or the like can be used. Etching conditions (for example, the amount of power applied to the coil-shaped electrode, the amount of power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.) may be appropriately adjusted so that the etching can be performed to a desired processing shape. ..

Next, the oxide layer 104f, the insulator 105d, the conductor 106d, and the insulator 107d are placed on the upper surface and the side surface of the oxide layer 104b, the side surface of the oxide layer 104a, and the insulator 103.
Are formed in order. After that, a mask 303 is formed on the upper surface of the insulator 107d (FIG. 8C).
reference. ). For the mask 303, refer to the mask 301.

Next, a part of the insulator 107d and the conductor 106d is removed by dry etching or the like using the mask 303 to form the insulator 107 and the conductor 106 (FIG. 9 (FIG. 9).
A) See. ).

Examples of the conductive material for forming the conductor 106 include aluminum, chromium, copper, and silver.
Materials containing one or more metal elements selected from gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, berylium and the like can be used. Further, a semiconductor having high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, and a silicide such as nickel silicide may be used. As the conductor 106, a plurality of conductive layers formed of these materials may be laminated and used.

Further, indium tin oxide (ITO: Indium Tin Oxi) is added to the conductor 106.
de), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide containing silicon It is also possible to apply a conductive material containing oxygen such as, and a conductive material containing nitrogen such as titanium nitride and tantalum nitride. Further, it is also possible to form a laminated structure in which the above-mentioned material containing a metal element and a conductive material containing oxygen are combined. Further, it is also possible to form a laminated structure in which the above-mentioned material containing a metal element and a conductive material containing nitrogen are combined. Further, it is also possible to form a laminated structure in which the above-mentioned material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined. The thickness of the conductor 106 is preferably 10 nm or more and 500 nm or less, preferably 20 nm or more and 300.
It is more preferably nm or less, and further preferably 30 nm or more and 200 nm or less. In this embodiment, a laminate of titanium nitride and tungsten is used as the conductive layer 126. Specifically, tungsten nitride having a thickness of 150 nm is formed on titanium nitride having a thickness of 10 nm.

The method for forming the conductor 106 is not particularly limited, and various forming methods such as a vapor deposition method, a CVD method, and a sputtering method can be used.

[Metallic element 131]
Next, the metal element 131 is introduced using the conductor 106 and the insulator 107 as masks (see FIG. 9C). In FIG. 9C, the metal element 131 is indicated by an arrow. The metal element 131 can be introduced by using an ion implantation method, a plasma doping method, or the like. In FIG. 9C, the end portion of the region 135 into which the metal element 131 is introduced is shown by a broken line. The depth of the region 135 into which the metal element is introduced and the concentration of the metal element contained in the region 135 can be determined by treatment conditions such as an ion implantation method and a plasma doping method.

As the metal element 131, it is preferable to use one or more metal elements. For example, as the metal element 131, tungsten, aluminum, titanium, magnesium, vanadium, etc.
One or more of the elements such as antimony, arsenic, and sulfur can be used.
The dose amount of the metal element 131 is 1 × 10 ¹² ions / cm ² or more and 1 × 10 ¹⁶ ions.
/ Cm ² or less, preferably 1 × 10 ¹³ ions / cm ² or more 1 × 10 ¹⁵ ions / c
It may be m ² or less. The acceleration voltage at the time of introducing the metal element 131 may be 5 kV or more and 50 kV or less, preferably 10 kV or more and 30 kV or less. In this embodiment, tungsten is used as the metal element 131. When the metal element 131 is introduced using the conductor 106 and the insulator 107 as masks, the region 135 can be formed adjacent to the channel forming region by self-alignment.

Here, when the metal element 131 is formed of a material that easily binds to oxygen such as tungsten or titanium, the oxide of the metal element 131 is formed, so that the metal element 131 is introduced into the oxide layer 104 in the oxide layer 104. Oxygen deficiency (also referred to as "Vo") may increase. When hydrogen is bonded to Vo to form VoH, the carrier density in the region increases and the resistivity decreases.

After the introduction of the metal element 131, heat treatment may be performed. The heat treatment is preferably 200 ° C.
More than 500 ° C or less, more preferably 300 ° C or more and 450 ° C or less, still more preferably 350 ° C.
It may be carried out at ° C. or higher and 400 ° C. or lower. When hydrogen is bonded to Vo by the heat treatment to form VoH, the carrier density in the region is further increased and the resistivity is further reduced.

Therefore, the region 135 in the oxide layer 104 has a higher carrier density and a lower resistivity than the region (channel forming region) that overlaps with the conductor 106 of the oxide layer 104. Therefore, the region 135 in the oxide layer 104 may have a lower resistance than the region (channel forming region) that overlaps with the conductor 106 of the oxide layer 104.

In this embodiment, tungsten is used as the metal element 131. Further, it is introduced into a part of the oxide layer 104 by an ion implantation method. By introducing tungsten, a region containing tungsten oxide is formed in the oxide layer 104.

Next, the insulator 108d is formed on the insulator 105d and on the insulator 107 (FIG. 9 (FIG. 9).
See C). ).

Next, the insulator 108d is etched by an anisotropic dry etching method, and the conductor 10 is used.
Insulator 108 is formed on the side wall of 6. At this time, the region of the insulator 105d that does not overlap with either the insulator 108 or the conductor 106 is also etched to form the insulator 105.
Further, the region of the oxide layer 104f that does not overlap with either the insulator 108 or the conductor 106 is also etched to form the oxide layer 104c. Therefore, a part of the oxide layer 104b is exposed when the insulator 108 is formed.

At this time, a part of the exposed oxide layer 104b is etched, and the oxide layer 1 having a convex portion 1
04b may be formed. Here, FIGS. 20 (A) and 20 (B) show a transistor 100 having a convex portion formed on the oxide layer 104b. FIG. 20A is a plan view of the transistor 100. Further, FIG. 20 (B) shows the alternate long and short dash line L1 shown in FIG. 20 (A).
It is sectional drawing in -L2 and the alternate long and short dash line W1-W2.

[Insulator 107 and Insulator 108]
Here, when a part of the insulator 108d is etched by an anisotropic dry etching method to form the insulator 108, it is preferable that the insulator 107 is not etched. Alternatively, the etching rate of the insulator 107 is preferably slower than the etching rate of the insulator 108d. Therefore, it is preferable that the insulator 107 has a main element different from that of the insulator 108, for example. Alternatively, for example, the insulator 107 is, for example, the insulator 10.
It is preferable that the composition is different from that of 8. The thickness of the insulator 107 is preferably 5 nm or more and 100 nm or less, and more preferably 10 nm or more and 50 nm or less.

Here, as an example, silicon oxide or silicon nitride is used as the insulator 108, and silicon nitride or silicon nitride is used as the insulator 107. By making the nitrogen atomic number ratio of the insulator 107 higher than that of the insulator 108, it may be possible to slow down the etching rate of the insulator 107 at the time of etching the insulator 108.

Further, as a further example, there is a case where silicon oxide, silicon nitride, silicon nitride or silicon nitride can be used as the insulator 108, and aluminum nitride, aluminum oxide, aluminum nitride oxide, or aluminum nitride can be used as the insulator 107. be.

Further, as a further example, when silicon oxide, silicon nitride nitride, silicon nitride oxide or silicon nitride is used as the insulator 108, the oxide layer 104 is used as the insulator 107.
In some cases, a material that can be used as a material is preferable.

Here, by etching the insulator 108d by the anisotropic dry etching method, an insulator may be formed in addition to the side wall of the conductor 106. For example, the oxide layer 104
An insulator may be formed on the side wall of b or the like.

Next, the conductor 109d on the insulator 103, the oxide layer 104b, and the insulator 107
(See FIG. 10 (B)). Here, it is preferable that the conductor 109d covers the side surface of the insulator 108. The thickness of the conductor 109d is preferably 5 nm or more and 500 nm or less, and 1
It is more preferably 0 nm or more and 200 nm or less, and further preferably 15 nm or more and 100 nm or less. In this embodiment, tungsten having a thickness of 20 nm is used as the conductor 109d.

Alternatively, as the conductor 109d, titanium oxide having a thickness of 5 nm and a thickness of 20 on titanium oxide are used.
A three-layer laminate of tungsten at nm and titanium oxide having a thickness of 5 nm on tungsten may be used.

Next, a part of the conductor 109d is removed using a mask to form the conductor 109e (see FIG. 10C). Then, the insulator 110d is formed into a film (see FIG. 11A).

[Conductor 109a and Conductor 109b]
Next, the insulator 110d and the conductor 109 so as to make the upper surface flat with respect to the substrate 101.
By removing a part of e, the conductor 109a and the conductor 109b are formed (FIG. 1).
See 1 (B). ). Here, by removing a part of the conductor 109e, the conductor 109d
Of these, the conductor 109e can be separated by removing the region overlapping with the conductor 106, and the conductor 109a and the conductor 109b can be formed.

Here, a polishing method such as the CMP method can be used to remove the insulator 110d and the conductor 109e. Alternatively, dry etching may be used. For example, a method such as etch back may be used.

When a polishing method such as the CMP method is used to remove the insulator 110d or the conductor 109e, the polishing speed of the conductor 109d or the insulator 110d may have a distribution in the plane of the sample. In this case, the exposure time of the insulator 107 may be long in a place where the polishing speed is high. It is preferable that the polishing speed of the insulator 107 is slower than the polishing speed of the conductor 109e and the insulator 110d. Due to the slow polishing speed of the insulator 107, the insulator 585 can serve as a polishing stopper film in the polishing process of the conductor 109d and the insulator 110d.

Here, in one aspect of the present invention, for example, when a mask is formed by using lithography, the position where the mask is formed may be displaced depending on the accuracy of the apparatus for lithography. In such a case, a distance is generated between the end portions of the conductor 109a and the conductor 109b and the end portions of the insulator 108. On the other hand, in one aspect of the present invention, the conductor 1
It is not necessary to use a mask or the like when forming the 09a and the conductor 109b. Therefore, the area of the transistor 100 seen from the upper surface can be made smaller. By reducing the area of the transistor 100, it is possible to realize the integration of the circuit of the semiconductor device.

Further, the upper surfaces of the insulator 110, the conductor 109a, the conductor 109b, the insulator 108, and the insulator 107 form a continuous flat flat surface. By forming the insulator 111 on the plane, for example, the coverage of the insulator 111 may be improved and the hydrogen permeability may be lowered, which is preferable. Further, since the blocking capacity of the insulator 111 is improved, the insulator 111 may be made thinner. By making the insulator 111 thinner, for example, when the insulator 111 is provided with an opening by dry etching or the like, the etching time can be shortened. If the etching time is too long, for example, the mask width may be reduced and the opening may be enlarged, which makes miniaturization difficult. By shortening the etching time, for example, a finer opening can be provided, which is preferable.

As the conductor 109a and the conductor 109b, for example, a highly implantable conductive material such as tungsten or polysilicon can be used. Further, the side surfaces and the bottom surface of the material may be covered with a titanium layer, a titanium nitride layer, or a barrier layer (diffusion prevention layer) composed of a laminate thereof. Further, for example, as shown in FIG. 3B, the conductor 109a is the conductor 109j, the conductor 109k and the conductor 109l are three layers, the conductor 109b is the conductor 109m, and the conductor 1
It may be a laminated structure of three layers of 09n and the conductor 109o. Here, the conductor 109j
And it is preferable to use the conductor 109m as a barrier layer. Further, the conductor 109l and the conductor 109o may be used as the barrier layer. Here, when the conductor 109a and the conductor 109b function as electrodes, they may be referred to as electrodes including the barrier layer.

The conductors 109a and 109b are made of, for example, tungsten or titanium.
When formed of a material having the property of extracting oxygen from the oxide layer 104, Vo in the oxide layer 104 in contact with the conductor 109a and the conductor 109b increases. Therefore, the oxide layer 104
Of the regions 135 formed in the above, the carrier density of the regions in contact with the conductors 109a and 109b increases, and the resistivity decreases. When hydrogen is bonded to Vo to form VoH, the carrier density in the region is further increased and the resistivity is further reduced.

Therefore, in the oxide layer 104, the carrier density in the region overlapping with the insulator 108 is higher than the carrier density.
The carrier density in the region where the conductor 109a and the conductor 109b are in contact may be high. Further, in the oxide layer 104, the conductor 10 is more than the resistivity in the region overlapping with the insulator 108.
The resistivity in the region where 9a and the conductor 109b are in contact may be reduced. Further, in the oxide layer 104, the resistance in the region where the conductor 109a and the conductor 109b are in contact may be lower than the resistance in the region overlapping the insulator 108.

Next, the insulator 111 is formed on the insulator 110, the conductor 109a, the conductor 109b, and the like (see FIG. 12A).

In the present embodiment, aluminum oxide is formed as the insulator 111 by a sputtering method. Further, a gas containing oxygen is used as the sputtering gas. When the insulator 111 is formed by the sputtering method, a mixed layer in which both are mixed is formed at the interface between the insulator 111 and the surface to be formed of the insulator 111 and its vicinity thereof. Specifically, the mixed layer 145 is formed at the interface between the insulator 110 and the insulator 111 and in the vicinity thereof.

Further, the mixed layer 145 contains a part of the sputtering gas. In this embodiment, since a gas containing oxygen is used as the sputtering gas, oxygen is contained in the mixed layer 145.
Therefore, the mixed layer 145 has excess oxygen.

Next, heat treatment is performed. The heat treatment may be preferably carried out at 200 ° C. or higher and 500 ° C. or lower, more preferably 300 ° C. or higher and 450 ° C. or lower, and further preferably 350 ° C. or higher and 400 ° C. or lower. The temperature of the heat treatment performed at this time is set to be equal to or lower than the temperature of the heat treatment performed after the introduction of the metal element 131.

Oxygen contained in the mixed layer 145 is diffused by the heat treatment. Here, the excess oxygen contained in the mixed layer 145 diffuses into the oxide layer 104a, the oxide layer 104b, and the oxide layer 104c via the insulator 110, the insulator 103, the insulator 108, the insulator 105, and the like. Insulator 1
By using a material that does not easily allow oxygen to permeate as the insulator 102 and the insulator 102, the excess oxygen contained in the mixed layer 145 can be effectively diffused into the oxide layer 104b via the insulator 110, the insulator 103, and the like. Can be done. FIG. 1 shows how excess oxygen contained in the mixed layer 145 diffuses.
2 (B) is indicated by an arrow.

Next, the insulator 112 is formed on the insulator 111. After that, the insulator 112 and the insulator 11
An opening 307 that reaches the conductor 109a and the like is formed in 1 and the insulator 110 (FIG. 13 (FIG. 13).
A) See. ).

Next, a conductor is formed on the insulator 112 and in the opening 307, and a part of the conductor is removed so as to make the upper surface flat with respect to the substrate 101, thereby causing the contact plug 113.
a, the contact plug 113b, and the contact plug 113c are formed (FIG. 13 (FIG. 13).
B) See. ). For example, the CMP method can be used to remove the conductor.

Contact plug 113a, contact plug 113b, and contact plug 11
As 3c, for example, a conductive material having high embedding property such as tungsten and polysilicon can be used. Further, although not shown, the side surfaces and the bottom surface of the material may be covered with a titanium layer, a titanium nitride layer, or a barrier layer (diffusion prevention layer) composed of a laminate thereof. In this case, it may be called an electrode including the barrier layer.

The insulator 112 can be formed by the same material and method as the insulator 103. also,
As the insulator 112, an organic material having heat resistance such as polyimide, acrylic resin, benzocyclobutene resin, polyamide, and epoxy resin can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials), siloxane-based resins, PSG (phosphorus glass), BPSG (phosphorus glass) and the like can be used. The insulator 112 may be formed by laminating a plurality of insulators made of these materials.

The siloxane-based resin is Si—O— formed from a siloxane-based material as a starting material.
It corresponds to a resin containing a Si bond. As the substituent of the siloxane-based resin, an organic group (for example, an alkyl group or an aryl group) or a fluoro group may be used. Further, the organic group may have a fluoro group.

The method for forming the insulator 112 is not particularly limited, and a sputtering method or SOG can be used depending on the material thereof.
A method, spin coating, dip, spray coating, droplet ejection method (inkjet method, etc.), printing method (screen printing, offset printing, etc.) may be used. By combining the firing step of the insulator 112 and another heat treatment step, it is possible to efficiently manufacture a transistor.

Next, the surface of the sample is chemically mechanically polished (CMP).
Polishing) processing (also referred to as “CMP processing”) is performed (see FIG. 11 (A)). By performing the CMP treatment, the unevenness of the sample surface can be reduced, and the covering property of the insulator and the conductive layer formed after that can be improved.

Then, by forming the conductor 114a, the conductor 114b, and the conductor 114c on the insulator 112, the semiconductor device shown in FIG. 1 can be manufactured (see FIG. 14).

The film formation of the insulator 118, the insulator 105d, the insulator 110d and the insulator 112 is
You can refer to the film forming method of the insulator 103. Insulator 118, insulator 105,
For the insulator 110 and the insulator 112, the materials and configurations shown as the insulator 103 can be used.

Further, for the film formation of the conductor 117d, the conductor 109d, the contact plugs 113a to c, and the conductors 114a to 114a, the conductor 106d can be referred to. Also, the conductor 1
17, the materials and configurations shown as the conductor 106 can be used for the conductor 109a, the conductor 109b, the contact plugs 113a to c, and the conductors 114a to 114a to c.

Here, in FIG. 9B, the metal element 131 was added before forming the insulator 108, but as shown in FIG. 15A, the metal element 131 was added after FIG. 9A. Before
The insulator 108d is formed as shown in FIG. 5 (A), then the insulator 108 is formed as shown in FIG. 15 (B), and then the metal element 131 is added as shown in FIG. 15 (C). You may. After that, the insulator 110, the conductor 109a, the conductor 109b, the insulator 111, and the insulator 11
2. The semiconductor device shown in FIG. 16 can be manufactured by forming the contact plug 113a, the conductor 114a, and the like. Here, in FIG. 16, as compared to the region under the insulator 108,
In the outer region, the concentration of the metal element 131 may be high.

<Manufacturing method 2>
Next, a method for manufacturing the semiconductor device shown in FIG. 2 will be described with reference to FIGS. 17 to 19.

Insulator 102, insulator 118, conductor 117, insulator 103, oxide layer 104a, oxide layer 104b, oxidation on the substrate 101 using the methods shown in FIGS. 7 (A) to 9 (A). The material layer 104f, the insulator 105d, the conductor 106, and the insulator 107 are formed. Then, using the conductor 106 as a mask, a part of the insulator 105d and the oxide layer 104f is removed, and the insulator 1 is removed.
05 and the oxide layer 104c are formed (see FIG. 17 (A)). In FIG. 17A, it is preferable that the side surfaces of the oxide layer 104c, the insulator 105, the conductor 106, and the insulator 107 substantially coincide with each other.

Next, the metal element 131 is introduced using the conductor 106 and the insulator 107 as masks (see FIG. 17B). In FIG. 17B, the metal element 131 is indicated by an arrow, and the metal element 1 is shown.
The end of the region 135 into which 31 is introduced is indicated by a broken line.

Next, the insulator 108d is formed on the oxide layer 104b, the insulator 103, and the insulator 107 (see FIG. 17C). Then, the conductor 10 is subjected to the anisotropic dry etching method.
Insulator 108 is formed on the side wall of No. 6 (see FIG. 18 (A)). Here, by etching the insulator 108d by the anisotropic dry etching method, an insulator may be formed in addition to the side wall of the conductor 106. FIG. 18A shows an example in which the insulator 108b is formed on the side wall of the oxide layer 104b.

Next, the conductor 109a, the conductor 109b, the insulator 110, and the insulator 111 are formed by using the methods shown in FIGS. 10 (B) to 12 (A) (see FIG. 18 (B)). ..

In the present embodiment, aluminum oxide is formed as the insulator 111 by a sputtering method. Further, a gas containing oxygen is used as the sputtering gas. When the insulator 111 is formed by the sputtering method, a mixed layer in which both are mixed is formed at the interface between the insulator 111 and the surface to be formed of the insulator 111 and its vicinity thereof. Specifically, the mixed layer 145 is formed at the interface between the insulator 110 and the insulator 111 and in the vicinity thereof.

Further, the mixed layer 145 contains a part of the sputtering gas. In this embodiment, since a gas containing oxygen is used as the sputtering gas, oxygen is contained in the mixed layer 145.
Therefore, the mixed layer 145 is a layer having excess oxygen.

Next, heat treatment is performed. The heat treatment may be preferably carried out at 200 ° C. or higher and 500 ° C. or lower, more preferably 300 ° C. or higher and 450 ° C. or lower, and further preferably 350 ° C. or higher and 400 ° C. or lower. The temperature of the heat treatment performed at this time is set to be equal to or lower than the temperature of the heat treatment performed after the introduction of the metal element 131.

Oxygen contained in the mixed layer 145 is diffused by the heat treatment. Here, the excess oxygen contained in the mixed layer 145 is passed through the insulator 110, the insulator 103, the insulator 108, and the like to the oxide layer 10.
It diffuses into 4a, the oxide layer 104b, and the oxide layer 104c. By using a material that does not easily allow oxygen to permeate as the insulator 111 and the insulator 102, excess oxygen contained in the mixed layer 145 is efficiently diffused into the oxide layer 104b via the insulator 110, the insulator 103, and the like. be able to. The state in which the excess oxygen contained in the mixed layer 145 diffuses is shown by an arrow in FIG. 19 (A).

After that, an insulator 112, a contact plug 113a, a conductor 114a, etc. are formed, and FIG. 2
The semiconductor device shown in the above can be manufactured (see FIG. 19B).

<Structure 300>
In the formation of the conductor 109a and the conductor 109b shown in FIG. 11B, the substrate 101
A part of the insulator 110d and the conductor 109e is removed so as to make the upper surface flat. When a polishing method such as the CMP method is used to remove the insulator 110d or the conductor 109e, the polishing rate may have a distribution in the plane of the sample. In such a case, excessive polishing may occur in a place where the polishing speed is high, and a part of the insulator 108, the insulator 107, and the conductor 106 may be removed. Here, it is preferable that the structure such as the conductor 106 is densely arranged so that excessive polishing can be suppressed.

FIG. 22A shows an example of a cross section in the channel length direction of the semiconductor device having the structure 100d which becomes the transistor 100. Here, in FIG. 22A, in the insulator 110d, the difference in the height of the upper surface between the region where the structure 100d is provided and the region where the structure 100d is not provided is defined as the length 311. Here, it is more preferable that the length 311 is small. Length 311
In some cases, the flatness of the surface of the insulator 110 obtained after the formation of the conductor 109a and the conductor 109b can be improved by reducing the size.

The semiconductor device shown in FIG. 22B has a structure 100d as a transistor 100 and a structure 300d as a structure 300. The structure 300d is adjacent to the structure 100d. It is preferable that the semiconductor device has the structure 300 because it may be possible to suppress excessive polishing in the step of removing the insulator 110d and the conductor 109d.

The structure 100d preferably has a conductor 106. Structure 300 (Structure 30)
0d) may have the same structure as the transistor 100 (structure 100d). or,
The structure 300 (structure 300d) may have only a part of the components of the transistor 100 (structure 100d). In the example shown in FIG. 23, the structure 300d has the conductor 109e, the conductor 106, the insulator 108, the insulator 107, and the insulator 1 among the components of the structure 100d.
05, it has an oxide layer 104c and does not have an oxide layer 104b and an oxide layer 104a.

Further, in FIG. 23, the structure 300d shows an example in which the insulator 103 does not have a convex portion. Alternatively, the convex portion of the insulator 103 of the structure 300d is the insulator 103 of the structure 100d.
The height may be smaller than the convex part of the. Here, in FIG. 23, the insulator 110
In d, the difference in the height of the upper surface between the region where the structure 100d is provided and the region where the structure 300d is provided is defined as the length 314. Since the semiconductor device has the structure 300d, the length 314 can be shorter than the length 311 shown in FIG. 22 (A), which is preferable.

The distance between the conductor 106 of the structure 100d and the conductor 106 of the structure 300d is set to the length 312. Here, for example, the length 312 is 0.5 times or more and 10 times or less, or 1 time or more and 5 times or less the length 313 of the oxide layer 104b in the cross section of the transistor 100 in the channel direction.

Further, the structure 300 does not have to function as a semiconductor element in the semiconductor device.
For example, the structure 300 does not have to be connected to the wiring. Further, in the circuit of the semiconductor device, the signal input to the circuit may not be electrically connected to the structure 300. The structure 300 may be referred to as a dummy pattern or a dummy element.

FIG. 24A shows an example of a semiconductor device having two structures 100d. FIG. 24 (A)
By removing a part of the insulator 110d and the conductor 109d in FIG. 24 (B).
), Two transistors 100 are obtained.

Here, in FIG. 24A, when the two structures 100d are sparsely present, by removing a part of the insulator 110d and the conductor 109d, as shown in FIG. 24C, 2 A recess may be formed in the insulator 110 between the two transistors 100. At this time, excessive polishing may occur and a part of the insulator 108, the insulator 107, and the conductor 106 may be removed.

By forming one or more structures 300d adjacent to the structure 100d as shown in FIG. 25 (A), excessive polishing can be suppressed when the conductors 109a, 109b and the insulator 110 are formed. Therefore, it is preferable (see FIG. 25 (B)). Further, it is preferable because the surface of the insulator 110 can be made flatter. Further, the upper surface of the insulator 110 and the conductor 1
In some cases, it may be possible to roughly match the upper end of 09a and the conductor 109b, which is preferable.

Further, in FIG. 25C, the structure 300 has a conductor 109a, a conductor 109b, and a conductor 1.
An example is shown which has 06, an insulator 108, an insulator 107, an insulator 105, and an oxide layer 104c, and does not have the oxide layer 104b and the oxide layer 104a. It is preferable to form one or a plurality of structures 300d because excessive polishing can be suppressed when the conductors 109a, 109b and the insulator 110 are formed.

<Manufacturing method 3>
Next, a method for manufacturing the semiconductor device shown in FIG. 6 will be described with reference to FIG. 26.

As shown in FIGS. 7A to 11B, the insulator 102 and the conductor 11 are placed on the substrate 101.
7. Insulator 118, Insulator 103, Oxide Layer 104a, Oxide Layer 104b, Oxide Layer 10
4c, an insulator 105, a conductor 106, an insulator 107, an insulator 108, a conductor 109e, an insulator 110, and the like are formed (see FIG. 26A).

Next, an opening 308 reaching the insulator 102 is formed in the insulator 110, the insulator 103, and the insulator 118 (see FIG. 26B).

Next, an insulator to be the insulator 110b is formed on the insulator 110 and in the opening 308. Then, the upper surface of the insulator 110 is removed so as to be parallel to the substrate 101 so that the upper surface of the insulator 110 is exposed, and the insulator 110b is formed. After that, as shown in FIG. 26C, the semiconductor device shown in FIG. 6 can be manufactured by forming the insulator 111 on the insulator 110 and the insulator 110b.

This embodiment can be carried out in combination with at least a part thereof as appropriate in combination with other embodiments described in the present specification.

(Embodiment 3)
Oxide semiconductors are divided into single crystal oxide semiconductors and other non-single crystal oxide semiconductors. Examples of the non-single crystal oxide semiconductor include CAAC-OS, polycrystalline oxide semiconductor, and nc-O.
S (nanocrystalline Oxide Semiconductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous like Oxid)
eSemiconductor), amorphous oxide semiconductors, etc.

From another viewpoint, the oxide semiconductor is divided into an amorphous oxide semiconductor and other crystalline oxide semiconductors. As crystalline oxide semiconductors, single crystal oxide semiconductors, CAAC-
There are OS, polycrystalline oxide semiconductor, nc-OS and the like.

As a definition of an amorphous structure, it is generally known that it is not immobilized in a metastable state, and that it is isotropic and does not have an anisotropic structure. In addition, it can be rephrased as a structure in which the coupling angle is flexible and the structure has short-range order but does not have long-range order.

On the contrary, in the case of an essentially stable oxide semiconductor, it is completely amorphous.
(Terry amorphous) It cannot be called an oxide semiconductor. Further, an oxide semiconductor that is not isotropic (for example, having a periodic structure in a minute region) cannot be called a completely amorphous oxide semiconductor. However, although the a-like OS has a periodic structure in a minute region, it has a void (also referred to as “void”) and has an unstable structure. Therefore, it can be said that the physical characteristics are close to those of an amorphous oxide semiconductor.

<CAAC-OS>
CAAC-OS is one of oxide semiconductors having a plurality of c-axis oriented crystal portions (also referred to as "pellets").

Transmission Electron Microscope (TEM: Transmission Electron Microscope)
By oscope), a composite analysis image of the bright field image of CAAC-OS and the diffraction pattern ("
Also called "high resolution TEM image". ) Can be observed to confirm multiple pellets. On the other hand, in the high-resolution TEM image, the boundary between pellets, that is, the crystal grain boundary (also referred to as "grain boundary") cannot be clearly confirmed. Therefore, it can be said that CAAC-OS is unlikely to cause a decrease in electron mobility due to grain boundaries.

The CAAC-OS observed by TEM will be described below. FIG. 27 (A) shows a high-resolution TEM image of a cross section of CAAC-OS observed from a direction substantially parallel to the sample surface.
For observation of high-resolution TEM images, spherical aberration correction (Spherical Aberration)
The nDirector) function was used. A high-resolution TEM image using the spherical aberration correction function is particularly called a Cs-corrected high-resolution TEM image. Acquisition of Cs-corrected high-resolution TEM image is, for example,
It can be performed by an atomic resolution analysis electron microscope JEM-ARM200F manufactured by JEOL Ltd.

FIG. 27 (B) shows a Cs-corrected high-resolution TEM image in which the region (1) of FIG. 27 (A) is enlarged. From FIG. 27 (B), it can be confirmed that the metal atoms are arranged in layers in the pellet. The arrangement of each layer of metal atoms reflects the unevenness of the surface (also referred to as "formed surface") or upper surface on which the CAAC-OS film is formed, and is parallel to the formed surface or upper surface of CAAC-OS. ..

As shown in FIG. 27 (B), CAAC-OS has a characteristic atomic arrangement. FIG. 27 (C
) Shows the characteristic atomic arrangement with auxiliary lines. 27 (B) and 27 (C)
), It can be seen that the size of one pellet is 1 nm or more and 3 nm or more, and the size of the gap generated by the inclination between the pellet and the pellet is about 0.8 nm.
Therefore, the pellets can also be referred to as nanocrystals (nc: nanocrystals). In addition, CAAC-OS can be used as CANC (C-Axis Aligned nanocr).
It can also be called an oxide semiconductor having ystals).

Here, if the arrangement of the CAAC-OS pellets 5100 on the substrate 5120 is schematically shown based on the Cs-corrected high-resolution TEM image, the structure is as if bricks or blocks were stacked (FIG. 27 (D)). reference.). The portion where the inclination occurs between the pellets observed in FIG. 27 (C) corresponds to the region 5161 shown in FIG. 27 (D).

Further, in FIG. 28 (A), C of the plane of CAAC-OS observed from a direction substantially perpendicular to the sample surface.
The s-corrected high-resolution TEM image is shown. Area (1), area (2) and area (3) of FIG. 28 (A)
) Is enlarged and shown in FIGS. 28 (B), 28 (C) and 28 (D), respectively. From FIGS. 28 (B), 28 (C) and 28 (D), it can be confirmed that the metal atoms are arranged in a triangular shape, a square shape or a hexagonal shape in the pellet. However, there is no regularity in the arrangement of metal atoms between different pellets.

Next, C analyzed by X-ray diffraction (XRD: X-Ray Diffraction).
AAC-OS will be described. For example, CAAC-O having crystals of InGaZnO ₄ .
When structural analysis is performed on S by the out-of-plane method, a peak may appear in the vicinity of the diffraction angle (2θ) of 31 ° as shown in FIG. 29 (A). This peak is InGa
Since it is attributed to the (009) plane of the ZnO ₄ crystal, it is confirmed that the CAAC-OS crystal has c-axis orientation and the c-axis is oriented substantially perpendicular to the surface to be formed or the upper surface. can.

In the structural analysis of CAAC-OS by the out-of-plane method, 2θ is 31.
In addition to the peak in the vicinity of °, a peak may appear in the vicinity of 2θ at 36 °. 2θ is 36 °
Near peaks indicate that some of the CAAC-OS contains crystals that do not have c-axis orientation. In a more preferable CAAC-OS, in the structural analysis by the out-of-plane method, 2θ shows a peak near 31 ° and 2θ does not show a peak near 36 °.

On the other hand, in-pla in which X-rays are incident on CAAC-OS from a direction substantially perpendicular to the c-axis.
When the structural analysis by the ne method is performed, a peak appears in the vicinity of 2θ at 56 °. This peak is I
It is attributed to the (110) plane of the crystal of nGaZnO ₄ . In the case of CAAC-OS, 2θ is 5
Even if the sample is fixed near 6 ° and the analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), no clear peak appears as shown in FIG. 29 (B). .. On the other hand, in the case of a single crystal oxide semiconductor of InGaZnO ₄ , 2θ is fixed in the vicinity of 56 ° and φ.
When scanned, as shown in FIG. 29 (C), six peaks attributed to the crystal plane equivalent to the (110) plane are observed. Therefore, from the structural analysis using XRD, it can be confirmed that the orientation of the a-axis and the b-axis of CAAC-OS is irregular.

Next, the CAAC-OS analyzed by electron diffraction will be described. For example, InGa
The probe diameter is 300 nm parallel to the sample surface with respect to CAAC-OS having ZnO ₄ crystals.
When the electron beam of No. 30 is incident, a diffraction pattern as shown in FIG. 30 (A) (also referred to as a “limited field transmission electron diffraction pattern”) may appear. This diffraction pattern includes InGaZn.
A spot due to the (009) plane of the crystal of _O4 is included. Therefore, it can be seen from the electron diffraction that the pellets contained in CAAC-OS have c-axis orientation and the c-axis is oriented substantially perpendicular to the surface to be formed or the upper surface. On the other hand, FIG. 30B shows a diffraction pattern when an electron beam having a probe diameter of 300 nm is incident on the same sample perpendicularly to the sample surface.
From FIG. 30B, a ring-shaped diffraction pattern is confirmed. Therefore, it can be seen that the a-axis and b-axis of the pellets contained in CAAC-OS do not have orientation even by electron diffraction. The first ring in FIG. 30B is a crystal of InGaZnO ₄ (010).
It is considered to be caused by the surface, the (100) surface, and the like. Further, it is considered that the second ring in FIG. 30 (B) is caused by the (110) plane or the like.

As described above, CAAC-OS is a highly crystalline oxide semiconductor. Since the crystallinity of an oxide semiconductor may decrease due to the inclusion of impurities or the generation of defects, CAAC-OS can be said to be an oxide semiconductor having few impurities and defects (oxygen deficiency, etc.) from the opposite viewpoint.

Impurities are elements other than the main components of oxide semiconductors, such as hydrogen, carbon, silicon, and transition metal elements. For example, an element such as silicon, which has a stronger bond with oxygen than a metal element constituting an oxide semiconductor, deprives the oxide semiconductor of oxygen, disturbs the atomic arrangement of the oxide semiconductor, and lowers the crystallinity. It becomes a factor. Also, heavy metals such as iron and nickel, argon,
Since carbon dioxide and the like have a large atomic radius (or molecular radius), they disturb the atomic arrangement of the oxide semiconductor and cause a decrease in crystallinity.

When an oxide semiconductor has impurities or defects, its characteristics may fluctuate due to light, heat, or the like. For example, impurities contained in an oxide semiconductor may be a carrier trap or a carrier generation source. In addition, oxygen deficiency in the oxide semiconductor may become a carrier trap or a carrier generation source by capturing hydrogen.

CAAC-OS, which has few impurities and oxygen deficiency, is an oxide semiconductor having a low carrier density. Specifically, it is less than 8 × 10 ¹¹ pieces / cm ³ , preferably less than 1 × 10 ¹¹ / cm ³ , more preferably less than 1 × 10 ¹⁰ pieces / cm ³ , and 1 × ^10-9 pieces / cm ³ . It can be an oxide semiconductor having the above carrier density. Such oxide semiconductors are referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. CAAC-OS has a low impurity concentration and a low defect level density. That is, it can be said that it is an oxide semiconductor having stable characteristics.

<Nc-OS>
The nc-OS has a region in which a crystal portion can be confirmed and a region in which a clear crystal portion cannot be confirmed in a high-resolution TEM image. The crystal portion contained in nc-OS is often 1 nm or more and 10 nm or less, or 1 nm or more and 3 nm or less in size. An oxide semiconductor having a crystal portion larger than 10 nm and 100 nm or less may be referred to as a microcrystalline oxide semiconductor. In the nc-OS, for example, in a high-resolution TEM image, the crystal grain boundaries may not be clearly confirmed. It should be noted that the nanocrystals may have the same origin as the pellets in CAAC-OS. Therefore, in the following, the crystal portion of nc-OS may be referred to as a pellet.

The nc-OS has periodicity in the atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). In addition, nc-OS has no regularity in crystal orientation between different pellets. Therefore, no orientation is observed in the entire film. Therefore, the nc-OS may be indistinguishable from the a-like OS and the amorphous oxide semiconductor depending on the analysis method. For example, when X-rays having a diameter larger than that of pellets are used for nc-OS, the peak showing the crystal plane is not detected by the analysis by the out-of-plane method. Also, for nc-OS, the probe diameter is larger than the pellet (for example, 50).
When electron diffraction using an electron beam of nm or more) is performed, a diffraction pattern such as a halo pattern is observed. On the other hand, when nanobeam electron diffraction is performed on nc-OS using an electron beam having a probe diameter close to or smaller than the pellet size, spots are observed. also,
When nanobeam electron diffraction is performed on nc-OS, a region with high brightness (ring-shaped) may be observed in a circular motion. Furthermore, multiple spots may be observed in the ring-shaped region.

In this way, since the crystal orientation does not have regularity between pellets (nanocrystals), nc
-The OS is an oxide semiconductor having RANC (Random Aligned nanocrystals) or NANC (Non-Aligned nanocrystals).
It can also be called an oxide semiconductor having s).

The nc-OS is an oxide semiconductor having higher regularity than the amorphous oxide semiconductor. Therefore, the defect level density of nc-OS is lower than that of a-like OS and amorphous oxide semiconductors. However, in nc-OS, there is no regularity in crystal orientation between different pellets. Therefore, the defect level density of nc-OS is higher than that of CAAC-OS.

<A-like OS>
The a-like OS is an oxide semiconductor having a structure between nc-OS and an amorphous oxide semiconductor. In a-like OS, voids may be observed in high-resolution TEM images. In addition, in the high-resolution TEM image, the area where the crystal part can be clearly confirmed and the area where the crystal part can be clearly confirmed,
It has a region where the crystal part cannot be confirmed.

Due to the presence of voids, the a-like OS has an unstable structure. In the following, a-lik
e To show that the OS has an unstable structure as compared with CAAC-OS and nc-OS, the structural change due to electron irradiation is shown.

As a sample to be irradiated with electrons, a-like OS (referred to as sample A) and nc-OS.
(Indicated as Sample B) and CAAC-OS (indicated as Sample C) are prepared. Both samples are In-Ga-Zn oxides.

First, a high-resolution cross-sectional TEM image of each sample is acquired. From the high-resolution cross-sectional TEM image, it can be seen that each sample has a crystal portion.

It should be noted that the determination as to which portion is regarded as one crystal portion may be performed as follows. For example, the unit cell of a crystal of InGaZnO ₄ may have a structure in which a total of 9 layers are stacked in a layered manner in the c-axis direction, having 3 In—O layers and 6 Ga—Zn—O layers. Are known. The distance between these adjacent layers is about the same as the grid plane distance (also referred to as “d value”) of the (009) plane, and the value is determined to be 0.29 nm from the crystal structure analysis. Therefore, the portion where the interval between the plaids is 0.28 nm or more and 0.30 nm or less can be regarded as the crystal portion of InGaZnO ₄ . The plaids correspond to the ab planes of the InGaZnO ₄ crystal.

FIG. 31 is an example of investigating the average size of the crystal portions (22 to 45 locations) of each sample. However, the length of the above-mentioned plaid is defined as the size of the crystal portion. From FIG. 31, a-li
It can be seen that in the ke OS, the crystal portion becomes larger according to the cumulative irradiation amount of electrons. Specifically, as shown by (1) in FIG. 31, the crystal portion (also referred to as "initial nucleus") having a size of about 1.2 nm at the initial stage of observation by TEM is the cumulative irradiation amount of electrons. Is 4.2 × 10
It can be seen that at ⁸ e ⁻ / nm ² , it has grown to a size of about 2.6 nm. On the other hand, in nc-OS and CAAC-OS, the cumulative amount of electron irradiation is 4.2 × from the start of electron irradiation.
It can be seen that there is no change in the size of the crystal part in the range of 10 ⁸ e ⁻ / nm ² . Specifically, as shown by (2) and (3) in FIG. 31, n regardless of the cumulative irradiation amount of electrons.
The size of the crystal part of c-OS and CAAC-OS is about 1.4 nm and 2.
It can be seen that it is about 1 nm.

As described above, in the a-like OS, growth of the crystal portion may be observed by electron irradiation. On the other hand, it can be seen that in nc-OS and CAAC-OS, almost no growth of the crystal portion due to electron irradiation is observed. That is, the a-like OS is nc-OS and CAAC-
It can be seen that the structure is unstable compared to the OS.

Further, since it has a void, the a-like OS has a structure having a lower density than that of nc-OS and CAAC-OS. Specifically, the density of a-like OS is 78.6% or more and less than 92.3% of the density of a single crystal having the same composition. Also, the density of nc-OS and CAA
The density of C-OS is 92.3% or more and less than 100% of the density of a single crystal having the same composition. It is difficult to form an oxide semiconductor having a density of less than 78% of a single crystal.

For example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic number ratio],
The density of the single crystal InGaZnO ₄ having a rhombohedral crystal structure is 6.357 g / cm ³ . Therefore, for example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic number ratio], the density of a-like OS is 5.0 g / cm ³ or more and less than 5.9 g / cm ³ . .. Further, for example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic number ratio], the density of nc-OS and the density of CAAC-OS are 5.9 g / cm ³ or more and 6.3 g /. cm
It will be less than ³ .

In some cases, a single crystal having the same composition does not exist. In that case, the density corresponding to the single crystal in the desired composition can be estimated by combining the single crystals having different compositions at an arbitrary ratio. The density corresponding to a single crystal having a desired composition may be estimated by using a weighted average with respect to the ratio of combining single crystals having different compositions. However, it is preferable to estimate the density by combining as few types of single crystals as possible.

As described above, oxide semiconductors have various structures, and each has various characteristics.
The oxide semiconductor may be, for example, an amorphous oxide semiconductor, a-like OS, nc-OS.
, CAAC-OS may be a laminated film having two or more kinds.

This embodiment can be implemented in combination with the configurations described in other embodiments as appropriate.

(Embodiment 4)
In this embodiment, an example of a semiconductor device using a transistor disclosed in the present specification and the like will be described.

<< Structural example of semiconductor device >>
32 (A) to 32 (C) are sectional views of the semiconductor device 400. Semiconductor device 40
0 has a transistor 100 and a transistor 281. The transistor 100 can be replaced with another transistor shown in the above embodiment. 32 (A) is a cross-sectional view of the transistor 100 and the transistor 281 in the channel length direction, and FIG. 32 (B) is a cross-sectional view of the transistor 100 and the transistor 281 in the channel width direction. 32 (C) shows the transistor 28 in FIG. 32 (A).
It is an enlarged view of 1.

The semiconductor device 400 uses an n-type semiconductor as the substrate 401. Transistor 281
Channel formation region 283, high-concentration p-type impurity region 285, insulator 286, conductor 287,
It has a structure 288. In addition, it has a low-concentration p-type impurity region 284 in a region that overlaps with the structure 288 via the insulator 286. The insulator 286 can function as a gate insulating layer. The conductor 287 can function as a gate electrode. Transistor 281 is a channel forming region 283.
Is formed on a part of the substrate 401.

The low-concentration p-type impurity region 284 can be formed by introducing an impurity element using the conductor 287 as a mask after the conductor 287 is formed and before the structure 288 is formed. That is, the low-concentration p-type impurity region 284 can be formed by self-alignment. After the structure 288 is formed, a high-concentration p-type impurity region 285 is formed. The low-concentration p-type impurity region 284 has the same conductive type as the high-concentration p-type impurity region 285, and the concentration of impurities imparting the conductive type is lower than that of the high-concentration p-type impurity region 285. In addition, the low-concentration p-type impurity region 284 is
It may not be provided depending on the situation.

The transistor 281 is electrically separated from other transistors by the element separation layer 414. The formation of the element separation region is performed by LOCOS (Local Oxidation of S).
ilicon) method and STI method (Shallow Trench Isolation)
Etc. can be used.

The transistor 281 can function as a p-channel type transistor. Further, an insulator 403 is formed on the transistor 282, and an insulator 404 is formed on the insulator 403. The insulator 403 and the insulator 404 can be formed by the same material and method as the insulator 111. The insulator 403 and the insulator 404 are preferably formed by using an insulating material having a function of preventing the diffusion of impurities such as oxygen, hydrogen, water, alkali metal, and alkaline earth metal. Either one of the insulator 403 and the insulator 404 may be omitted, or the insulating layer may be further laminated.

Further, the semiconductor device 400 has an insulator 405 having a flat surface on the insulator 404. The insulator 405 can be formed by the same material and method as the insulator 112. Further, the surface of the insulator 405 may be subjected to CMP treatment.

Further, on the insulator 405, the conductor 413a, the conductor 413b, and the conductor 413c
Is formed. The conductor 413a, the conductor 413b, and the conductor 413c can be manufactured by the same material and method as the conductor 109a.

Further, the conductor 413a has a high concentration p-type impurity region 28 via the contact plug 406a.
It is electrically connected to one of the five. The conductor 413b is electrically connected to the other of the high-concentration p-type impurity region 285 via the contact plug 406b. The conductor 413c is electrically connected to the conductor 287 via the contact plug 406c.

Further, the insulator 407 covers the conductor 413a, the conductor 413b, and the conductor 413c.
Is formed. The insulator 407 can be formed by the same material and method as the insulator 405. Further, the surface of the insulator 407 may be subjected to CMP treatment.

Further, the insulator 102 is formed on the insulator 407. The transistor 100 is formed on the insulator 102. An insulator 111 is formed on the transistor 100. The configuration of the layer above the insulator 407 can be understood by considering the above embodiment. Therefore, detailed description in this embodiment will be omitted. Further, the conductor 109b is electrically connected to the conductor 413b via the contact plug 112d.

<Modification 1>
An n-channel transistor may be provided on the substrate 401. 33 (A) and 33 (B) are sectional views of the semiconductor device 410. The semiconductor device 410 is a semiconductor device 40.
It has a configuration in which an n-channel type transistor 282 is added to 0. 33 (A) is a cross-sectional view of the transistor 100, the transistor 281 and the transistor 282 in the channel length direction, and FIG. 33 (B) is an enlarged view of the transistor 281.

In the transistor 282, the channel forming region 1283 is formed in the well 220. Further, the transistor 282 has a channel forming region 1283, a high concentration n-type impurity region 1285, and the like.
It has an insulator 286, a conductor 287, and a structure 288. Further, a low-concentration n-type impurity region 1284 is provided in a region overlapping the structure 288 via the insulator 286.

The low-concentration n-type impurity region 1284 can be formed by introducing an impurity element using the conductor 287 as a mask after the conductor 287 is formed and before the structure 288 is formed.
That is, the low-concentration n-type impurity region 1284 can be formed by self-alignment. After the structure 288 is formed, a high concentration n-type impurity region 1285 is formed. The low-concentration n-type impurity region 1284 has the same conductive type as the high-concentration n-type impurity region 1285, and the concentration of impurities imparting the conductive type is lower than that of the high-concentration n-type impurity region 1285. Further, the low-concentration n-type impurity region 1284 may not be provided depending on the situation.

<Modification 2>
A transistor 100 may be further provided above the transistor 100. FIG. 34 shows
It is sectional drawing of the semiconductor device 420. The semiconductor device 420 has a transistor 100a having a configuration similar to that of the transistor 100 on the semiconductor device 410. Also, transistor 1
An insulator 111a is provided on 00.

The transistor 100a is provided on the insulator 112 via the insulator 407a. also,
Although not shown in FIG. 34, the insulator 112 and the insulator 103 included in the transistor 100a are included.
An insulator 102a may be provided between the a and the insulator 102a. Insulator 407a, Insulator 103a, Insulator 1
The 02a and the insulator 111a can be provided by the same materials and methods as the insulator 407, the insulator 103, the insulator 102 and the insulator 111, respectively. Also, transistor 1
00a can be manufactured in the same manner as the transistor 100.

Further, the semiconductor device 420 has a capacitive element 141 and a capacitive element 142. One of the conductors 413c constituting the capacitive element 141 can be provided on the same layer as the conductors 413a and 413b by using a part of the conductive layer for forming the conductors 413a and 413b. Further, the other conductor 109c constituting the capacitive element 141 is the conductor 10.
A part of the conductive layer for forming the conductor 109a and the conductor 109b can be provided in the same layer as the conductor 109a and the conductor 109b. The insulating layer sandwiched between the conductor 109c and the conductor 413c can function as a dielectric layer of the capacitive element 141.

<Modification 3>
35 (A) to 35 (C) are cross-sectional views of the semiconductor device 430. Semiconductor device 430
Has a configuration in which the transistor 281 of the semiconductor device 400 is replaced with the Fin type transistor 291. By making the transistor a Fin type, the effective channel width can be increased and the on-characteristics of the transistor can be improved. Further, since the contribution of the electric field of the gate electrode to the channel forming region can be increased, the off characteristic of the transistor can be improved.

Further, the semiconductor device 430 is different from the semiconductor device 400 in that the capacitive element 413 is provided above the transistor. The capacitive element 413 includes a conductor 114b, a second conductor, and the like.
It has a conductor 114 and an insulator sandwiched between the second conductors. The conductor 114b is an insulator 1
It is provided on 12. Further, the conductor 114b is connected to the conductor 109b which functions as a drain electrode or a source electrode of the transistor 100 via a contact plug 113b.
The conductor 109b is connected to the conductor 287 that functions as a gate electrode of the transistor 291 via the insulator 407, the insulator 102, the contact plug provided in the opening of the insulator 118, the conductor 413b, and the like.

[Semiconductor circuit]
The transistors disclosed in the present specification and the like include logic circuits such as OR circuits, AND circuits, NAND circuits, and NOR circuits, inverter circuits, buffer circuits, shift register circuits, flip-flop circuits, encoder circuits, decoder circuits, and amplification circuits. It can be used in various semiconductor circuits such as analog switch circuits, integrator circuits, differential circuits, and memory elements.

In this embodiment, FIGS. 36 (A) to 36 (E) are used to show an example of a CMOS circuit or the like that can be used for a peripheral circuit and a pixel circuit. In the circuit diagram and the like which are referred to in this specification and the like, "OS" is added to the circuit symbol of the transistor to which the OS transistor is preferably applied.

The CMOS circuit shown in FIG. 36A shows a configuration example of an inverter circuit in which a p-channel type transistor 281 and an n-channel type transistor 282 are connected in series and each gate is connected.

The CMOS circuit shown in FIG. 36B shows a configuration example of an analog switch circuit in which a p-channel type transistor 281 and an n-channel type transistor 282 are connected in parallel.

The CMOS circuit shown in FIG. 36C has a transistor 281a and a transistor 281b.
A configuration example of a NAND circuit using the transistor 282a and the transistor 282b is shown. In the NAND circuit, the output potential changes depending on the combination of the potentials input to the input terminal IN_A and the input terminal IN_B.

〔Storage device〕
The circuit shown in FIG. 37 (A) shows a configuration example of a storage device in which one of the source and drain of the transistor 289 is connected to one electrode of the gate of the transistor 1281 and the capacitive element 257. Further, the circuit shown in FIG. 37B shows a configuration example of a storage device in which one of the source and drain of the transistor 289 is connected to one electrode of the capacitive element 257.

The circuit shown in FIGS. 37 (A) and 37 (B) can hold the charge input from either the source or the drain of the transistor 289 at the node 256. By using the OS transistor for the transistor 289, the charge of the node 256 can be retained for a long period of time.

In FIG. 37 (A), a p-channel type transistor is shown as the transistor 1281, but an n-channel type transistor may be used. For example, the transistor 281 or the transistor 282 may be used as the transistor 1281. Further, an OS transistor may be used as the transistor 1281.

Here, regarding the semiconductor device (storage device) shown in FIGS. 37 (A) and 37 (B),
I will explain in detail.

The semiconductor device shown in FIG. 37 (A) includes transistors 1281 and a second semiconductor using the first semiconductor.
It has a transistor 289 using the semiconductor of the above and a capacitive element 257.

The transistor 289 is an OS transistor disclosed in the above embodiment. Due to the small off-current of the transistor 289, it is possible to retain the stored contents in a specific node of the semiconductor device for a long period of time. That is, since the refresh operation is not required or the frequency of the refresh operation can be extremely reduced, the semiconductor device has low power consumption.

In FIG. 37 (A), the wiring 251 is electrically connected to one of the source or drain of the transistor 1281 and the wiring 252 is electrically connected to the other of the source or drain of the transistor 1281. Further, the wiring 253 is electrically connected to either the source or the drain of the transistor 289, and the wiring 254 is electrically connected to the gate of the transistor 289. Then, the gate of the transistor 1281, the other of the source or drain of the transistor 289, and one of the electrodes of the capacitive element 257 are electrically connected to the node 256. Further, the wiring 255 is electrically connected to the other of the electrodes of the capacitive element 257.

The semiconductor device shown in FIG. 37 (A) has a characteristic of being able to hold the electric charge given to the node 256, so that information can be written, held, and read out as shown below.

[Write operation, hold operation]
Writing and retaining information will be described. First, the potential of the wiring 254 is set to the potential at which the transistor 289 is turned on. As a result, the potential of the wiring 253 becomes the node 256.
Given to. That is, a predetermined charge is given to the node 256 (writing). here,
It is assumed that either of the charges that give two different potential levels (hereinafter, referred to as "Low level charge" and "High level charge") is given. After that, the electric charge is held in the node 256 by setting the potential of the wiring 254 to the potential in which the transistor 289 is turned off.

The High level charge is a charge that gives a higher potential to the node 256 than the Low level charge. When a p-channel type transistor is used for the transistor 1281, the high level charge and the low level charge are both charges that give a potential higher than the threshold voltage of the transistor. Further, when an n-channel type transistor is used for the transistor 1281, both the high level charge and the low level charge have potentials lower than the threshold voltage of the transistor. That is, High level charge and L
The ow level charge is a charge that gives a potential for turning off the transistor.

Since the off-current of the transistor 289 is extremely small, the charge of the node 256 is retained for a long period of time.

[Read operation]
Next, reading information will be described. When a read potential _VR is applied to the wiring 255 in a state where a predetermined potential (constant potential) different from the potential of the wiring 252 is applied to the wiring 251, the node 25 is applied.
The information held in 6 can be read out.

Assuming that the potential given by the High level charge is V _H and the potential given by the Low level charge is _VL , the read potential _VR is {(Vth-V _H ) + (Vth + _VL )} /.
It may be 2. The potential of the wiring 255 when no information is read out is higher than V _H when a p-channel type transistor is used for the transistor 1281, and lower than _VL when an n-channel type transistor is used for the transistor 1281. It may be an electric potential.

For example, when a p-channel type transistor is used for the transistor 1281, if the Vth of the transistor 1281 is -2V, the V _H is 1V, and the _VL is -1V, the V _R is -2.
It may be V. When the potential written to the node 256 is V _H , when _VR is given to the wiring 255, _VR + V _H , that is, -1 V is applied to the gate of the transistor 1281. Since -1V is higher than Vth, the transistor 1281 is not turned on. Therefore, the potential of the wiring 252 does not change. Further, when the potential written to the node 256 is _VL , when _VR is applied to the wiring 255, _VR + _VL , that is, -3V is applied to the gate of the transistor 1281. Since -3V is lower than Vth, the transistor 1281 is turned on. Therefore, the potential of the wiring 252 changes.

When an n-channel type transistor is used for the transistor 1281, if the Vth of the transistor 1281 is 2V, the _VH is 1V, and the _VL is -1V, the _VR may be 2V. When the potential written to the node 256 is V _H , when _VR is given to the wiring 255, _VR + V _H , that is, 3 V is applied to the gate of the transistor 1281. Since 3V is higher than Vth, the transistor 1281 is turned on. Therefore, the potential of the wiring 252 changes. Further, when the potential written to the node 256 is _VL , V is applied to the wiring 255.
When _R is given, _VR + _VL , that is, 1V is applied to the gate of the transistor 1281. Since 1V is lower than Vth, the transistor 1281 is not turned on. Therefore, the potential of the wiring 252 does not change.

By discriminating the potential of the wiring 252, the information held in the node 256 can be read out.

The semiconductor device shown in FIG. 37 (B) does not have the transistor 1281 in FIG. 37 (A).
It is different from the semiconductor device shown in. In this case as well, information can be written and held by the same operation as that of the semiconductor device shown in FIG. 37 (A).

Reading information in the semiconductor device shown in FIG. 37 (B) will be described. Wiring 25
When the potential for turning on the transistor 289 is given to 4, the wiring 25 in a floating state
3 and the capacitive element 257 are conducted, and the electric charge is redistributed between the wiring 253 and the capacitive element 257. As a result, the potential of the wiring 253 changes. The amount of change in the potential of the wiring 253 is the node 256.
It takes different values depending on the potential of (or the charge stored in the node 256).

For example, assuming that the potential of the node 256 is V, the capacitance of the capacitance element 257 is C, the capacitance component of the wiring 253 is CB, and the potential of the wiring 253 before the charge is redistributed is VB0, after the charge is redistributed. The potential of the wiring 253 is (CB × VB0 + C × V) / (CB + C). Therefore, assuming that the potential of the node 256 takes two states of V1 and V0 (V1> V0) as the state of the memory cell, the potential of the wiring 253 when the potential V1 is held (= (CB).
It can be seen that × VB0 + C × V1) / (CB + C)) is higher than the potential of the wiring 253 (= (CB × VB0 + C × V0) / (CB + C)) when the potential V0 is held.

Then, the information can be read out by comparing the potential of the wiring 253 with a predetermined potential.

The semiconductor device shown above can retain the stored contents for a long period of time by applying a transistor using an oxide semiconductor and having an extremely small off-current. That is, the refresh operation becomes unnecessary, or the frequency of the refresh operation can be made extremely low, so that a semiconductor device having low power consumption can be realized. Further, even when there is no power supply (however, it is preferable that the potential is fixed), it is possible to retain the stored contents for a long period of time.

Further, since the semiconductor device does not require a high voltage for writing information, deterioration of the element is unlikely to occur. For example, unlike the conventional non-volatile memory, electrons are not injected into the floating gate or extracted from the floating gate, so that the problem of deterioration of the insulator does not occur at all. That is, the semiconductor device according to one aspect of the present invention is a semiconductor device in which the number of rewritable times, which is a problem in the conventional non-volatile memory, is not limited, and the reliability is dramatically improved. Further, since information is written depending on the conduction state and the non-conduction state of the transistor, high-speed operation is possible.

[CPU]
In this embodiment, a CPU will be described as an example of a semiconductor device using the above-mentioned transistor. FIG. 38 is a block diagram showing a configuration example of a CPU using the above-mentioned transistor as a part.

The CPU shown in FIG. 38 has an ALU 1191 (ALU: Arisme) on the substrate 1190.
Tic logic unit, arithmetic circuit), ALU controller 1192, instruction decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198 (Bus I / F), rewritable ROM 1199, and ROM interface 1189. It has (ROM I / F). The substrate 1190 is a semiconductor substrate, SOI.
Use a substrate, glass substrate, etc. ROM 1199 and ROM interface 1189
May be provided on another chip. Of course, the CPU shown in FIG. 38 is only an example showing a simplified configuration thereof, and an actual CPU has a wide variety of configurations depending on its use. For example, the configuration including the CPU or the arithmetic circuit shown in FIG. 38 may be one core, and a plurality of the cores may be included so that the cores operate in parallel. The number of bits that the CPU can handle in the internal arithmetic circuit or data bus is, for example, 8 bits, 16 bits, 32 bits, or 6.
It can be 4 bits or the like.

Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.

The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. Further, the interrupt controller 1194 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or the mask state during the execution of the CPU program. The register controller 1197 generates the address of the register 1196, and reads or writes the register 1196 according to the state of the CPU.

Further, the timing controller 1195 includes an ALU 1191 and an ALU controller 11.
92, instruction decoder 1193, interrupt controller 1194, and register controller 1197 generate signals to control the timing of operation. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal based on the reference clock signal, and supplies the internal clock signal to the above-mentioned various circuits.

In the CPU shown in FIG. 38, a memory cell is provided in the register 1196. As the memory cell of the register 1196, the above-mentioned transistor, storage device, or the like can be used.

In the CPU shown in FIG. 38, the register controller 1197 selects the holding operation in the register 1196 according to the instruction from the ALU 1191. That is, register 1
In the memory cell of the 196, it is selected whether to hold the data by the flip-flop or the data by the capacitive element. When data retention by flip-flop is selected, the power supply voltage is supplied to the storage element in the register 1196. When the retention of data in the capacitive element is selected, the data is rewritten to the capacitive element, and the supply of the power supply voltage to the memory cell in the register 1196 can be stopped.

FIG. 39 is an example of a circuit diagram of a storage element that can be used as a register 1196. The storage element 730 includes a circuit 701 in which the stored data is volatilized when the power is cut off, a circuit 702 in which the stored data is not volatilized when the power is cut off, a switch 703, a switch 704, and a logic element 706.
And a capacitive element 707 and a circuit 720 having a selection function. The circuit 702 includes a capacitive element 708, a transistor 709, and a transistor 710. The storage element 730 may further have other elements such as a diode, a resistance element, and an inductor, if necessary.

Here, the above-mentioned storage device can be used for the circuit 702. When the supply of the power supply voltage to the storage element 730 is stopped, the ground potential (0V) or the potential at which the transistor 709 is turned off continues to be input to the gate of the transistor 709 of the circuit 702. For example, the gate of the transistor 709 is grounded via a load such as a resistor.

The switch 703 is configured by using a one-conductive type (for example, n-channel type) transistor 713, and the switch 704 is configured by using a conductive type (for example, p-channel type) transistor 714 opposite to the transistor 713. An example is shown. Here, the first terminal of the switch 703 corresponds to one of the source and drain of the transistor 713, the second terminal of the switch 703 corresponds to the other of the source and drain of the transistor 713, and the switch 703 corresponds to the gate of the transistor 713. The control signal RD input to is selected to conduct or not conduct (that is, the on or off state of the transistor 713) between the first terminal and the second terminal. The first terminal of the switch 704 corresponds to one of the source and drain of the transistor 714, the second terminal of the switch 704 corresponds to the other of the source and drain of the transistor 714, and the switch 704 is input to the gate of the transistor 714. The control signal RD selects conduction or non-conduction between the first terminal and the second terminal (that is, the on or off state of the transistor 714).

One of the source and drain of the transistor 709 is electrically connected to one of the pair of electrodes of the capacitive element 708 and the gate of the transistor 710. Here, the connection portion is referred to as a node M2. One of the source and drain of the transistor 710 is electrically connected to a wiring (eg, GND wire) capable of supplying a low power potential, and the other is a switch 703.
Is electrically connected to the first terminal (one of the source and drain of the transistor 713).
The second terminal of the switch 703 (the other of the source and drain of the transistor 713) is electrically connected to the first terminal of the switch 704 (the other of the source and drain of the transistor 714). Second terminal of switch 704 (the other of the source and drain of transistor 714)
Is electrically connected to a wire that can supply the power potential VDD. The second terminal of the switch 703 (the other of the source and drain of the transistor 713) and the first of the switch 704.
Terminal (one of the source and drain of the transistor 714), the input terminal of the logic element 706, and one of the pair of electrodes of the capacitive element 707 are electrically connected. Here, the connection portion is referred to as a node M1. The other of the pair of electrodes of the capacitive element 707 can be configured to receive a constant potential. For example, low power potential (GND, etc.) or high power potential (GND, etc.)
It can be configured so that VDD etc.) is input. The other of the pair of electrodes of the capacitive element 707 is electrically connected to a wiring (eg, GND wire) capable of supplying a low power potential. The other of the pair of electrodes of the capacitive element 708 can be configured to receive a constant potential. For example, a configuration in which a low power supply potential (GND or the like) or a high power supply potential (VDD or the like) is input can be used. The other of the pair of electrodes of the capacitive element 708 is electrically connected to a wiring (eg, GND wire) capable of supplying a low power potential.

The capacitive element 707 and the capacitive element 708 can be omitted by positively utilizing the parasitic capacitance of the transistor and the wiring.

A control signal WE is input to the gate electrode of the transistor 709. The switch 703 and the switch 704 have a first terminal and a second terminal by a control signal RD different from the control signal WE.
The conduction state or non-conduction state between the terminals of the switch is selected, and the first terminal and the second terminal of one switch are selected.
When the terminals of the switch are in a conductive state, the first terminal and the second terminal of the other switch are in a non-conducting state.

A signal corresponding to the data held in the circuit 701 is input to the other of the source and drain of the transistor 709. FIG. 39 shows an example in which the signal output from the circuit 701 is input to the other of the source and drain of the transistor 709. The signal output from the second terminal of the switch 703 (the other of the source and drain of the transistor 713) is the logic element 7.
The logical value is inverted by 06 to become an inverted signal, which is input to the circuit 701 via the circuit 720.

In FIG. 39, the signal output from the second terminal of the switch 703 (the other of the source and drain of the transistor 713) is the circuit 70 via the logic element 706 and the circuit 720.
An example of inputting to 1 is shown, but the present invention is not limited to this. The signal output from the second terminal of the switch 703 (the other of the source and drain of the transistor 713) may be input to the circuit 701 without inverting the logical value. For example, when there is a node in the circuit 701 that holds a signal in which the logical value of the signal input from the input terminal is inverted, the switch 70
A signal output from the second terminal of 3 (the other of the source and drain of the transistor 713) can be input to the node.

The transistor 709 in FIG. 39 is the transistor 15 exemplified in the first embodiment.
0 can be used. Further, the control signal WE can be input to the gate electrode, and the control signal WE2 can be input to the back gate electrode. The control signal WE2 may be a signal having a constant potential. For the constant potential, for example, a ground potential GND or a potential smaller than the source potential of the transistor 709 is selected. The control signal WE2 is a potential signal for controlling the threshold voltage of the transistor 709, and the drain current of the transistor 709 when the gate voltage is 0 V can be further reduced. As the transistor 709, a transistor that does not have a second gate can also be used.

Further, in FIG. 39, among the transistors used in the storage element 730, the transistors other than the transistor 709 are layers or substrates 1190 made of semiconductors other than oxide semiconductors.
It can be a transistor in which a channel is formed. For example, it can be a transistor in which a channel is formed on a silicon layer or a silicon substrate. Further, the memory element 7
All the transistors used in 30 may be transistors whose channels are formed of an oxide semiconductor layer. Alternatively, the storage element 730 combines a transistor other than the transistor 709 with a transistor having a channel formed of an oxide semiconductor layer and a transistor having a channel formed on a layer made of a semiconductor other than the oxide semiconductor or a substrate 1190. You may use it.

For the circuit 701 in FIG. 39, for example, a flip-flop circuit can be used.
Further, as the logic element 706, for example, an inverter, a clocked inverter, or the like can be used.

In the semiconductor device according to one aspect of the present invention, the data stored in the circuit 701 can be held in the node M2 by the capacitive element 708 provided in the circuit 702 while the power supply voltage is not supplied to the storage element 730. ..

Further, as described above, the off-current of the transistor in which the channel is formed in the oxide semiconductor layer is extremely small. For example, the off-current of a transistor in which a channel is formed in an oxide semiconductor layer is significantly lower than the off-current of a transistor in which a channel is formed in crystalline silicon. Therefore, by using the transistor as the transistor 709, the signal held by the capacitive element 708 is maintained for a long period of time even when the power supply voltage is not supplied to the storage element 730. In this way, the storage element 730 can retain the stored contents (data) even when the supply of the power supply voltage is stopped.

Further, by providing the switch 703 and the switch 704, it is possible to shorten the time until the circuit 701 holds the original data again after the power supply voltage supply is restarted.

Further, in the circuit 702, the signal held in the node M2 is input to the gate of the transistor 710. Therefore, after the supply of the power supply voltage to the storage element 730 is resumed, the signal held in the node M2 can be converted into the state (on state or off state) of the transistor 710 and read out from the circuit 702. .. Therefore, even if the potential corresponding to the signal held in the node M2 fluctuates to some extent, the original signal can be accurately read out.

By using such a storage element 730 for a storage device such as a register or a cache memory possessed by the CPU, it is possible to prevent data loss in the storage device due to a stop supply of the power supply voltage. Further, after restarting the supply of the power supply voltage, it is possible to return to the state before the power supply is stopped in a short time. Therefore, it is possible to stop the power supply for a short period of time in the entire CPU or one or a plurality of logic circuits constituting the CPU, and the frequency of power supply stoppages can be increased, so that power consumption can be suppressed.

In this embodiment, the storage element 730 has been described as an example of using the storage element 730 for the CPU, but the storage element 7 has been described.
30 is a DSP (Digital Signal Processor), custom LS.
LSI, RF such as I, PLD (Programmable Logic Device), etc.
It can also be applied to a (Radio Frequency) tag.

[Image pickup device]
An image pickup device will be described as an example of the semiconductor device using the above-mentioned transistor.

<Configuration example of image pickup device 600>
FIG. 40A is a plan view showing a configuration example of the image pickup apparatus 600. The image pickup apparatus 600 includes a pixel unit 621, a first circuit 260, a second circuit 270, a third circuit 280, and a fourth circuit 290. In this specification and the like, the first circuit 260 to the fourth circuit 29
0 and the like may be referred to as a "peripheral circuit" or a "drive circuit". For example, the first circuit 26
It can be said that 0 is a part of the peripheral circuit.

FIG. 40B is a diagram showing a configuration example of the pixel unit 621. The pixel unit 621 has p columns and q rows (
p and q have a plurality of pixels 622 (image sensor) arranged in a matrix of two or more natural numbers). In FIG. 40 (B), n is a natural number of 1 or more and p or less, and m is a natural number of 1 or more and q or less.

For example, by arranging the pixels 622 in a matrix of 1920 × 1080, it is possible to realize an image pickup apparatus 600 capable of taking an image at a so-called full high-definition (also referred to as “2K resolution”, “2K1K”, “2K”, etc.) resolution. Can be done. Also, for example, 40 pixels 622
When arranged in a 96 × 2160 matrix, an image pickup device 6 capable of taking an image at a so-called ultra-high definition (also referred to as “4K resolution”, “4K2K”, “4K”, etc.) resolution 6
00 can be realized. Further, for example, when the pixels 622 are arranged in a matrix of 8192 × 4320, so-called super high definition (“8K resolution”, “8K4K”,
Also known as "8K". ) Can be realized as an image pickup apparatus 600 capable of taking an image. By increasing the number of display elements, it is possible to realize an image pickup apparatus 600 capable of taking an image at a resolution of 16K or 32K.

The first circuit 260 and the second circuit 270 have a function of connecting to a plurality of pixels 622 and supplying a signal for driving the plurality of pixels 622. Further, the first circuit 260 may have a function of processing an analog signal output from the pixel 622. Further, the third circuit 280 may have a function of controlling the operation timing of the peripheral circuit. For example, it may have a function of generating a clock signal. Further, it may have a function of converting the frequency of a clock signal supplied from the outside. Further, the third circuit 280 may have a function of supplying a reference potential signal (for example, a lamp wave signal or the like).

The peripheral circuit has at least one of a logic circuit, a switch, a buffer, an amplifier circuit, or a conversion circuit. Further, the transistor and the like used in the peripheral circuit are the pixel drive circuit 6 described later.
It may be formed by using a part of the semiconductor formed for manufacturing 10. Further, a part or all of the peripheral circuit may be mounted by a semiconductor device such as an IC.

As the peripheral circuit, at least one of the first circuit 260 to the fourth circuit 290 may be omitted. For example, the function of one of the first circuit 260 or the fourth circuit 290 is added to the other of the first circuit 260 or the fourth circuit 290, and the first circuit 260 or the fourth circuit 290 is added.
One of the circuits 290 of the above may be omitted. Further, for example, the function of one of the second circuit 270 or the third circuit 280 may be added to the other of the second circuit 270 or the third circuit 280.
Either the second circuit 270 or the third circuit 280 may be omitted. Also, for example, the first
By adding the function of another peripheral circuit to any one of the circuit 260 to the fourth circuit 290, the other peripheral circuit may be omitted.

Further, as shown in FIG. 41, the first circuit 260 to the fourth circuit 290 may be provided along the outer circumference of the pixel portion 621. Further, in the pixel unit 621 of the image pickup apparatus 600, the pixel 6
22 may be tilted and arranged. By arranging the pixels 622 at an angle, the pixel spacing (pitch) in the row direction and the column direction can be shortened. As a result, the quality of the image captured by the image pickup apparatus 600 can be further improved.

Further, as shown in FIG. 42, the pixel portion 621 may be provided above the first circuit 260 to the fourth circuit 290. FIG. 42A is a top view of the image pickup apparatus 600 in which the pixel portion 621 is formed so as to be superimposed on the first circuit 260 to the fourth circuit 290. Further, FIG. 42 (B)
Is a perspective view for explaining the configuration of the image pickup apparatus 600 shown in FIG. 42 (A).

By providing the pixel unit 621 on top of the first circuit 260 to the fourth circuit 290, the pixel unit 621 is provided.
The area occupied by the pixel unit 621 with respect to the size of the image pickup apparatus 600 can be increased. Therefore, the light receiving sensitivity of the image pickup apparatus 600 can be improved. In addition, the dynamic range of the image pickup apparatus 600 can be improved. In addition, the resolution of the image pickup apparatus 600 can be improved. In addition, the reproducibility of the image taken by the image pickup apparatus 600 can be improved. In addition, the degree of integration of the image pickup apparatus 600 can be improved.

[Color filters, etc.]
By using the pixel 622 of the image pickup apparatus 600 as a sub-pixel and providing a filter (color filter) that transmits light in a different wavelength range to each of the plurality of pixels 622, information for realizing a color image display is acquired. be able to.

FIG. 43A is a plan view showing an example of pixels 623 for acquiring a color image.
FIG. 43 (A) shows a pixel 62 provided with a color filter that transmits light in the wavelength range of red (R).
2 (hereinafter, also referred to as “pixel 622R”), pixel 622 (hereinafter, also referred to as “pixel 622G”) provided with a color filter that transmits light in the green (G) wavelength range, and blue (B) wavelength range. It has a pixel 622 (hereinafter, also referred to as “pixel 622B”) provided with a color filter that transmits the light of the above. Pixel 622R, pixel 622G, and pixel 622B are combined into one pixel 623.
To function as.

The color filter used for the pixel 623 is not limited to red (R), green (G), and blue (B), and is a color filter that transmits light of cyan (C), yellow (Y), and magenta (M). May be used. Pixel 6 that detects light in at least three different wavelength ranges in one pixel 623
By providing 22, a full-color image can be acquired.

FIG. 43 (B) shows a color filter that transmits yellow (Y) light in addition to the pixel 622 provided with a color filter that transmits red (R), green (G), and blue (B) light, respectively. Illustrates a pixel 623 having a pixel 622 provided with. FIG. 43 (C) shows a color filter that transmits blue (B) light in addition to a pixel 622 provided with a color filter that transmits cyan (C), yellow (Y), and magenta (M) light, respectively. Illustrates a pixel 623 having a pixel 622 provided with. By providing the pixel 622 for detecting four or more kinds of light in different wavelength ranges in one pixel 623, the color reproducibility of the acquired image can be further improved.

Further, the pixel number ratio (or light receiving area ratio) of the pixels 622R, the pixels 622G, and the pixels 622B does not necessarily have to be 1: 1: 1. As shown in FIG. 43 (D), the pixel number ratio (
A Bayer array may be used in which the light receiving area ratio) is red: green: blue = 1: 2: 1. Further, the pixel number ratio (light receiving area ratio) may be red: green: blue = 1: 6: 1.

The number of pixels 622 used for the pixel 623 may be one, but two or more are preferable. For example, by providing two or more pixels 622 that detect light in the same wavelength range, redundancy can be increased and the reliability of the image pickup apparatus 600 can be improved.

Further, by using an IR (IR: Infrared) filter that absorbs or reflects light having a wavelength equal to or lower than the wavelength of visible light and transmits infrared light as a filter, an image pickup device 600 that detects infrared light is realized. can do. Further, as a filter, UV (UV: Ultra Vio) that absorbs or reflects light having a wavelength equal to or higher than that of visible light and transmits ultraviolet light is transmitted.
By using a let) filter, it is possible to realize an image pickup apparatus 600 that detects ultraviolet light. Further, by using a scintillator that converts radiation into ultraviolet light or visible light as a filter, the image pickup device 600 can be made to function as a radiation detector that detects X-rays, γ-rays, and the like.

Further, when an ND (ND: Neutral Density) filter (neutral density filter) is used as a filter, a phenomenon that the output is saturated (hereinafter referred to as "output", which occurs when a large amount of light is incident on the photoelectric conversion element (light receiving element). It is also called "saturation"). By using a combination of ND filters with different amounts of dimming, the dynamic range of the image pickup device can be increased.

Further, in addition to the filter described above, a lens may be provided in the pixel 622. Here, FIG. 44
An arrangement example of the pixel 622, the filter 624, and the lens 625 will be described with reference to the cross-sectional view of. By providing the lens 625, the incident light can be efficiently received by the photoelectric conversion element.
Specifically, as shown in FIG. 44 (A), the light 660 is transferred to the photoelectric conversion element 601 through a lens 625 formed on the pixel 622, a filter 624 (filter 624R, filter 624G, filter 624B), a pixel drive circuit 610, and the like. It can be a structure that is incident on the lens.

However, as shown in the area surrounded by the alternate long and short dash line, a part of the light 660 indicated by the arrow is the wiring group 62.
It may be shielded from light by a part of No. 6, a transistor, and / or a capacitive element. Therefore, as shown in FIG. 44B, a lens 625 and a filter 624 may be formed on the photoelectric conversion element 601 side so that the incident light is efficiently received by the photoelectric conversion element 601. By incident light 660 from the photoelectric conversion element 601 side, it is possible to provide an image pickup device 600 having high light receiving sensitivity.

45 (A) to 45 (C) show a pixel drive circuit 6 that can be used for the pixel unit 621.
An example of 10 is shown. The pixel drive circuit 610 shown in FIG. 45A has a transistor 602, a transistor 604, and a capacitive element 606, and is connected to a photoelectric conversion element 601. One of the source or drain of the transistor 602 is electrically connected to the photoelectric conversion element 601 and the other of the source or drain of the transistor 602 is electrically connected to the gate of the transistor 604 via the node 607 (charge storage unit). There is.

It is preferable to use an OS transistor for the transistor 602. Since the OS transistor can make the off current extremely small, the capacitive element 606 can be made small. Alternatively, as shown in FIG. 45B, the capacitive element 606 can be omitted.
Further, when an OS transistor is used as the transistor 602, the potential of the node 607 is unlikely to fluctuate. Therefore, it is possible to realize an image pickup device that is not easily affected by noise. An OS transistor may be used for the transistor 604.

As the photoelectric conversion element 601, a diode element in which a pn-type or pin-type junction is formed on a silicon substrate can be used. Alternatively, a pin-type diode element using an amorphous silicon film, a microcrystalline silicon film, or the like may be used. Alternatively, a diode-connected transistor may be used. Further, a variable resistor or the like utilizing the photoelectric effect may be formed by using silicon, germanium, selenium or the like.

Further, the photoelectric conversion element may be formed by using a material capable of absorbing radiation and generating electric charges. Materials capable of absorbing radiation and generating electric charges include lead iodide, mercury iodide, gallium arsenide, CdTe, and CdZn.

The pixel drive circuit 610 shown in FIG. 45 (C) has a transistor 602 and a transistor 603.
, Transistor 604, transistor 605, and capacitive element 606, which are connected to the photoelectric conversion element 601. The pixel drive circuit 610 shown in FIG. 45C shows a case where a photodiode is used as the photoelectric conversion element 601. One of the source or drain of the transistor 602 is electrically connected to the cathode of the photoelectric conversion element 601 and the other is electrically connected to the node 607. The anode of the photoelectric conversion element 601 is the wiring 611.
Is electrically connected to. One of the source or drain of the transistor 603 is electrically connected to the node 607 and the other is electrically connected to the wiring 608. The gate of transistor 604 is electrically connected to node 607, one of the source or drain is electrically connected to wiring 609, and the other is electrically connected to one of the source or drain of transistor 605. The other of the source or drain of the transistor 605 is wiring 60
It is electrically connected to 8. One electrode of the capacitive element 606 is electrically connected to the node 607 and the other electrode is electrically connected to the wiring 611.

The transistor 602 can function as a transfer transistor. The transfer signal TX is supplied to the gate of the transistor 602. The transistor 603 can function as a reset transistor. A reset signal RST is supplied to the gate of the transistor 603. The transistor 604 can function as an amplification transistor. The transistor 605 can function as a selection transistor. A selection signal SEL is supplied to the gate of the transistor 605. Further, VDD is supplied to the wiring 608, and VSS is supplied to the wiring 611.

Next, the operation of the pixel drive circuit 610 shown in FIG. 45 (C) will be described. First, the transistor 603 is turned on and VDD is supplied to the node 607 (reset operation). After that, when the transistor 603 is turned off, VDD is held in the node 607. Next, when the transistor 602 is turned on, the potential of the node 607 changes according to the amount of light received by the photoelectric conversion element 601 (accumulation operation). After that, when the transistor 602 is turned off, the potential of the node 607 is maintained. Next, when the transistor 605 is turned on, the potential corresponding to the potential of the node 607 is output from the wiring 609 (selection operation). Wiring 60
By detecting the potential of 9, the amount of light received by the photoelectric conversion element 601 can be known.

It is preferable to use an OS transistor for the transistor 602 and the transistor 603. As described above, since the OS transistor can make the off current extremely small, the capacitive element 606 can be made small. Alternatively, the capacitive element 606 can be omitted. Further, when the OS transistor is used as the transistor 602 and the transistor 603, the potential of the node 607 is unlikely to fluctuate. Therefore, it is possible to realize an image pickup device that is not easily affected by noise.

Pixel 6 using any of the pixel drive circuits 610 shown in FIGS. 45 (A) to 45 (C).
By arranging the 22 in a matrix, an image pickup device with high resolution can be realized.

For example, when the pixel drive circuit 610 is arranged in a matrix of 1920 × 1080, so-called full high-definition (also referred to as “2K resolution”, “2K1K”, “2K”, etc.).
It is possible to realize an image pickup device capable of taking an image at the same resolution. Further, for example, the pixel drive circuit 6
By arranging the 10s in a matrix of 4096 × 2160, it is possible to realize an image pickup apparatus capable of taking an image at a so-called ultra-high definition (also referred to as “4K resolution”, “4K2K”, “4K”, etc.) resolution. Further, for example, the pixel drive circuit 610 is 8192 × 43.
When arranged in a matrix of 20, so-called Super Hi-Vision (" 8K resolution", "
It is also called "8K4K" or "8K". ) Can be realized as an image pickup device capable of taking an image. By increasing the number of display elements, it is possible to realize an image pickup device capable of taking an image at a resolution of 16K or 32K.

FIG. 46 shows a structural example of the pixel 622 using the above-mentioned transistor. FIG. 46 shows the pixel 62.
2 is a partial cross-sectional view of 2.

The pixel 622 shown in FIG. 46 uses an n-type semiconductor as the substrate 401. In addition, the substrate 4
A p-type semiconductor 221 of the photoelectric conversion element 601 is provided in 01. Further, a part of the substrate 401 functions as an n-type semiconductor 223 of the photoelectric conversion element 601.

Further, the transistor 604 is provided on the substrate 401. Transistor 604 is n
It can function as a channel type transistor. Further, a p-type semiconductor well 220 is provided in a part of the substrate 401. The well 220 can be provided in the same manner as in the formation of the p-type semiconductor 221. Further, the well 220 and the p-type semiconductor 221 can be formed at the same time. As the transistor 604, for example, the above-mentioned transistor 282 can be used.

Further, an insulator 403 and an insulator 40 are placed on the photoelectric conversion element 601 and the transistor 604.
4, and the insulator 405 are formed. Substrate 401 of insulator 403 to insulator 405
An opening 224 is formed in a region overlapping the (n-type semiconductor 223), and the insulator 403 to the insulator 4 is formed.
An opening 225 is formed in a region overlapping the p-type semiconductor 221 of 05. Also, the opening 224
A contact plug 406 is formed in the opening 225 and the opening 225. Contact plug 40
6 can be provided in the same manner as the contact plug 113a described above. In addition, opening 22
There are no particular restrictions on the number or arrangement of the 4 and the opening 225. Therefore, it is possible to realize an image pickup device having a high degree of freedom in layout.

Further, a conductor 421, a conductor 422, and a conductor 429 are formed on the insulator 405. The conductor 421 is electrically connected to the n-type semiconductor 223 (board 401) via a contact plug 406 provided in the opening 224. Further, the conductor 429 is electrically connected to the p-type semiconductor 221 via a contact plug 406 provided in the opening 225. The conductor 422 can function as one electrode of the capacitive element 606.

Further, the insulator 407 is formed so as to cover the conductor 421, the conductor 429, and the conductor 422. The insulator 407 can be formed by the same material and method as the insulator 405. Further, the surface of the insulator 407 may be subjected to CMP treatment. By performing the CMP treatment, the unevenness of the sample surface can be reduced, and the covering property of the insulating layer and the conductive layer formed after that can be improved. The conductor 421, the conductor 422, and the conductor 429 are the conductor 114a described above.
It can be formed by the same material and method as above.

Further, the insulator 102 is formed on the insulator 407, and the conductor 427 is formed on the insulator 102.
, Conductor 119, and electrode 273 are formed. The conductor 427 is electrically connected to the conductor 429 via a contact plug. The conductor 119 is a transistor 602.
Can function as a back gate for. The electrode 273 can function as the other electrode of the capacitive element 606. As the transistor 602, for example, the above-mentioned transistor 100 can be used.

Further, the conductor 109a is electrically connected to the conductor 427 via a contact plug.

<Modification 1>
FIG. 47 shows a configuration example of the pixel 622 different from that of FIG. 46. FIG. 47 is a cross-sectional view of a part of the pixel 622.

The pixel 622 shown in FIG. 47 has a transistor 604 and a transistor 605 on the substrate 401.
Is provided. The transistor 604 can function as an n-channel type transistor. The transistor 605 can function as a p-channel type transistor. As the transistor 604, for example, the above-mentioned transistor 282 can be used. As the transistor 605, for example, the above-mentioned transistor 281 can be used.

Conductors 413a to 413d are formed on the insulator 405. Conductor 41
3a is electrically connected to one of the source and drain of the transistor 604, and the conductor 4
13b is electrically connected to the other of the source or drain of the transistor 604.
The conductor 413c is electrically connected to the gate of the transistor 604. Conductor 41
3b is electrically connected to one of the source and drain of the transistor 605, and the conductor 4
13d is electrically connected to the other of the source or drain of the transistor 605.

The conductor 109b and the conductor 413c are electrically connected via the contact plug 112d. Further, the insulator 4 is placed on the conductor 114a, the conductor 114b, and the insulator 112.
15 is formed. The insulator 415 can be formed by the same material and method as the insulator 111.

Further, in the pixel 622 shown in FIG. 47, a photoelectric conversion element 601 is provided on the insulator 415. Further, an insulator 442 is provided on the photoelectric conversion element 601 and a conductor 488 is provided on the insulator 442. The insulator 442 can be formed by the same material and method as the insulator 415.

The photoelectric conversion element 601 shown in FIG. 47 has a photoelectric conversion layer 681 between a conductor 686 formed of a metal material or the like and a translucent conductive layer 682. FIG. 47 shows a form in which a selenium-based material is used for the photoelectric conversion layer 681. The photoelectric conversion element 601 using a selenium-based material has a characteristic of high external quantum efficiency with respect to visible light. The photoelectric conversion element can be a highly sensitive sensor in which the amplification of electrons with respect to the amount of light incident by the avalanche phenomenon is large.
Further, since the selenium-based material has a high light absorption coefficient, it has an advantage that the photoelectric conversion layer 681 can be easily thinned.

As the selenium-based material, amorphous selenium or crystalline selenium can be used. As an example, crystalline selenium can be obtained by forming an amorphous selenium into a film and then heat-treating it. By making the crystal grain size of the crystal selenium smaller than the pixel pitch, it is possible to reduce the variation in characteristics for each pixel. Further, crystalline selenium has characteristics having higher spectral sensitivity to visible light and a light absorption coefficient than amorphous selenium.

Although the photoelectric conversion layer 681 is shown as a single layer, gallium oxide or cerium oxide is provided as a hole injection blocking layer on the light receiving surface side of the selenium-based material, and oxidation is performed as an electron injection blocking layer on the conductor 686 side. It is also possible to provide nickel, antimony sulfide, or the like.

Further, the photoelectric conversion layer 681 may be a layer containing a compound (CIS) of copper, indium and selenium. Alternatively, it may be a layer containing a compound (CIGS) of copper, indium, gallium, and selenium. In CIS and CIGS, it is possible to form a photoelectric conversion element that can utilize the avalanche phenomenon as in the case of a single layer of selenium.

Further, CIS and CIGS are p-type semiconductors, and cadmium sulfide, zinc sulfide, or the like of n-type semiconductors may be provided in contact with each other in order to form a junction.

In order to generate the avalanche phenomenon, a relatively high voltage (for example, 1) is applied to the photoelectric conversion element.
It is preferable to apply 0 V or more). Since the OS transistor has a characteristic of having a higher drain withstand voltage than the Si transistor, it is easy to apply a relatively high voltage to the photoelectric conversion element. Therefore, by combining an OS transistor having a high drain withstand voltage and a photoelectric conversion element having a selenium-based material as a photoelectric conversion layer, it is possible to obtain a highly sensitive and highly reliable image pickup device.

The translucent conductive layer 682 contains, for example, indium tin oxide, indium tin oxide containing silicon, indium oxide containing zinc, zinc oxide, zinc oxide containing gallium, zinc oxide containing aluminum, tin oxide, and fluorine. Tin oxide containing tin oxide, tin oxide containing antimony, graphene and the like can be used. Further, the translucent conductive layer 682 is not limited to a single layer, and may be a laminate of different films. Further, in FIG. 47, the translucent conductive layer 682 and the wiring 487 are the conductor 48.
Although the configuration is shown in which electrical connection is made via the 8 and the contact plug 489, the translucent conductive layer 682 and the wiring 487 may be in direct contact with each other.

Further, the conductor 686, the wiring 487, and the like may have a configuration in which a plurality of conductive layers are laminated. For example, the conductor 686 has two layers of the conductor 686a and the conductor 686b, and the wiring 487.
Can be made into two layers of the conductor 487a and the conductor 487b. Also, for example, the conductor 6
The 86a and the conductor 487a may be formed by selecting a metal or the like having a low resistance, and the conductor 686b and the conductor 487b may be formed by selecting a metal or the like having good contact characteristics with the photoelectric conversion layer 681. With such a configuration, the electrical characteristics of the photoelectric conversion element can be improved. In addition, some metals may cause electrolytic corrosion when they come into contact with the translucent conductive layer 682. Even when such a metal is used for the conductor 487a, electrolytic corrosion can be prevented by passing through the conductor 487b.

For the conductor 686b and the conductor 487b, for example, molybdenum or tungsten can be used. Further, for the conductor 686a and the conductor 487a, for example, aluminum, titanium, or a laminate in which aluminum is sandwiched between titanium can be used.

Further, the insulator 442 may have a multi-layer structure. The partition wall 477 can be formed by using an inorganic insulator, an insulating organic resin, or the like. Further, the partition wall 477 may be colored black or the like in order to block light from the transistor or the like and / or to determine the area of the light receiving portion per pixel.

Further, the photoelectric conversion element 601 uses an amorphous silicon film, a microcrystalline silicon film, or the like.
An in-type diode element or the like may be used. The photodiode has a structure in which an n-type semiconductor layer, an i-type semiconductor layer, and a p-type semiconductor layer are laminated in this order. It is preferable to use amorphous silicon for the i-type semiconductor layer. Further, as the p-type semiconductor layer and the n-type semiconductor layer, amorphous silicon or microcrystalline silicon containing a dopant that imparts the respective conductive type can be used. A photodiode having amorphous silicon as a photoelectric conversion layer has high sensitivity in the wavelength region of visible light and can easily detect weak visible light.

The pn-type or pin-type diode element is preferably provided so that the p-type semiconductor layer serves as a light receiving surface. By using the p-type semiconductor layer as the light receiving surface, the output current of the photoelectric conversion element 601 can be increased.

The photoelectric conversion element 601 formed by using the above-mentioned selenium-based material, amorphous silicon, or the like is
It can be manufactured by using a general semiconductor manufacturing process such as a film forming process, a lithography process, and an etching process.

[Display device]
A display device will be described as an example of the semiconductor device using the above-mentioned transistor.
A display device (liquid crystal display device, light emitting display device, etc.), which is a device having a display element, may use various forms or may have various elements.

Display devices include, for example, EL (electroluminescence) elements (EL elements containing organic and inorganic substances, organic EL elements, inorganic EL elements), LED chips (white LED chips, red LED chips, green LED chips, blue LED chips, etc.). , Transistor (transistor that emits light according to current), electron emitting element, display element using carbon nanotube, liquid crystal element, electronic ink, electrowetting element, electrophoresis element, MEMS (micro electro mechanical system) Display elements used (eg, grating light valve (GLV), digital micromirror device (DMD), DMS (digital micro shutter), MIRASOL®, IMOD (interference modulation) element, shutter type MEMS display element, optical interference type ME
It has at least one such as an MS display element, a piezoelectric ceramic display, etc.), or a quantum dot.

In addition to these, the display device can be used for contrast, brightness, by electrical or magnetic action.
It may have a display medium in which the reflectance, transmittance and the like change. For example, the display device may be a plasma display (PDP).

An EL display or the like is an example of a display device using an EL element. As an example of a display device using an electron emitting element, a field emission display (FED) or an SED type planar display (SED: Surface-conduction)
Electron-emitter Display) and the like.

An example of a display device using quantum dots for each pixel is a quantum dot display. The quantum dots may be provided not as a display element but as a part of a backlight used in a liquid crystal display device or the like. By using quantum dots, it is possible to display with high color purity.

As an example of a display device using a liquid crystal element, a liquid crystal display device (transmissive liquid crystal display,
Semi-transmissive liquid crystal display, reflective liquid crystal display, direct-view liquid crystal display, projection type liquid crystal display) and the like.

In the case of realizing a semi-transmissive liquid crystal display or a reflective liquid crystal display, a part or all of the pixel electrodes may have a function as a reflective electrode. For example, a part or all of the pixel electrodes may have aluminum, silver, or the like. Further, in that case, it is also possible to provide a storage circuit such as SRAM under the reflective electrode. Thereby, the power consumption can be further reduced.

An example of a display device using electronic ink, electronic powder fluid (registered trademark), or an electrophoretic element is electronic paper.

When an LED chip is used as a display element or the like, graphene or graphite may be arranged under the electrode of the LED chip or the nitride semiconductor. Graphene and graphite may be formed by stacking a plurality of layers to form a multilayer film. By providing graphene or graphite in this way, a nitride semiconductor, for example, an n-type GaN semiconductor layer having crystals can be easily formed on the graphene. Further, a p-type GaN semiconductor layer having crystals or the like can be provided on the p-type GaN semiconductor layer to form an LED chip. In addition, with graphene and graphite,
An AlN layer may be provided between the n-type GaN semiconductor layer having crystals. The GaN semiconductor layer of the LED chip may be formed by MOCVD. However, by providing graphene, the GaN semiconductor layer of the LED chip can be formed by a sputtering method.

Further, in the display element using MEMS, the space in which the display element is sealed (for example, between the element substrate on which the display element is arranged and the facing substrate arranged to face the element substrate). A desiccant may be placed in the. By arranging the desiccant, it is possible to prevent MEMS and the like from becoming difficult to move due to moisture and easily deteriorating.

<Pixel circuit configuration example>
Next, a more specific configuration example of the display device will be described with reference to FIG. 48. FIG. 48 (A
) Is a block diagram for explaining the configuration of the display device 3100. The display device 3100 has a display area 3131, a circuit 3132, and a circuit 3133. The circuit 3132 functions as, for example, a scanning line drive circuit. Further, the circuit 3133 functions as, for example, a signal line drive circuit.

Further, the display device 3100 is arranged substantially parallel to each of the m scanning lines 3135 whose potential is controlled by the circuit 3132, and each is arranged substantially parallel to the circuit 3133.
It has n signal lines 3136 whose potential is controlled by. Furthermore, the display area 313
1 has a plurality of pixels 3130 arranged in a matrix of m rows and n columns. Both m and n are natural numbers of 2 or more.

In the display area 3131, each scanning line 3135 is electrically connected to n pixels 3130 arranged in any row of the pixels 3130. Further, each signal line 3136 is electrically connected to m pixels 3130 arranged in any row of the pixels 3130.

Further, as shown in FIG. 49 (A), the circuit 3152 may be provided at a position facing the circuit 3132 with the display area 3131 interposed therebetween. Further, as shown in FIG. 49 (B), the display area 31
The circuit 3153 may be provided at a position facing the circuit 3133 with the 31 in between. FIG. 49 (A)
) And FIG. 49 (B) show an example in which the circuit 3152 is connected to the scanning line 3135 in the same manner as the circuit 3132. However, the present invention is not limited to this, for example, the circuit 3 connected to the scanning line 3135.
The 132 and the circuit 3152 may be changed every few lines. FIG. 49B shows an example of connecting the circuit 3153 to the signal line 3136 in the same manner as the circuit 3133. However, the present invention is not limited to this, and for example, the circuit 3133 and the circuit 3153 connected to the signal line 3136 may be changed every few lines.
Further, the circuit 3132, the circuit 3133, the circuit 3152 and the circuit 3153 have pixels 3130.
It may have a function other than driving.

Further, the circuit 3132, the circuit 3133, the circuit 3152 and the circuit 3153 may be referred to as a drive circuit unit. Pixel 3130 includes a pixel circuit 3137 and a display element. The pixel circuit 3137 is a circuit for driving a display element. The transistor included in the drive circuit unit can be formed at the same time as the transistor constituting the pixel circuit 3137. Further, a part or all of the drive circuit unit may be formed on another substrate and electrically connected to the display device 3100. For example, a part or all of the drive circuit unit is formed using a single crystal substrate, and the display device 3100 is used.
May be electrically connected to.

48 (B) and 48 (C) show a circuit configuration that can be used for the pixel 3130 of the display device 3100.

<< An example of a pixel circuit for a light emitting display device >>
FIG. 48B shows an example of a pixel circuit that can be used in a light emission display device. FIG. 48 (B
), The pixel circuit 3137 includes a transistor 3431, a capacitive element 3233, a transistor 3232, and a transistor 3434. Further, the pixel circuit 3137 is electrically connected to a light emitting element 3125 that can function as a display element.

One of the source electrode and the drain electrode of the transistor 3431 is electrically connected to the signal line 3136 (hereinafter referred to as signal line DL_n) in the nth row to which the data signal is given. Further, the gate electrode of the transistor 3431 is the scanning line 3 on the mth line to which the gate signal is given.
It is electrically connected to 135 (hereinafter referred to as scanning line GL_m).

The transistor 3431 has a function of controlling the writing of the data signal to the node 3435.

One of the pair of electrodes of the capacitive element 3233 is electrically connected to the node 3435 and the other is electrically connected to the node 3437. Further, the other of the source electrode and the drain electrode of the transistor 3431 is electrically connected to the node 3435.

The capacitance element 3233 has a function as a holding capacitance for holding the data written in the node 3435.

One of the source electrode and the drain electrode of the transistor 3232 is a potential supply line VL_a.
The other is electrically connected to node 3437. Further, the gate electrode of transistor 3232 is electrically connected to node 3435.

One of the source electrode and the drain electrode of the transistor 3434 is a potential supply line VL_c.
The other is electrically connected to node 3437. Further, the gate electrode of the transistor 3434 is electrically connected to the scanning line GL_m.

One of the anode and cathode of the light emitting device 3125 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the node 3437.

As the light emitting element 3125, for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used. However, the present invention is not limited to this, and for example, an inorganic EL element made of an inorganic material may be used.

For example, the potential supply line VL_a has a function of supplying VDD. In addition, the potential supply line VL
_B has a function of supplying VSS. Further, the potential supply line VL_c has a function of supplying VSS.

Here, an operation example of the display device having the pixel circuit 3137 of FIG. 48 (B) will be described. First, the pixel circuit 3137 of each row is sequentially selected by the circuit 3132, and the transistor 3 is selected.
The data signal (potential) is written to the node 3435 with the 431 turned on. Next, the transistor 3434 is turned on and the potential of the node 3437 is set to VSS.

After that, the transistor 3431 is turned off and the data signal written to the node 3435 is held. Next, the transistor 3434 is turned off. Transistor 3232
The amount of current flowing between the source and drain of is determined by the data signal written to the node 3435. Therefore, the light emitting element 3125 emits light with a brightness corresponding to the amount of flowing current. By doing this sequentially line by line, the image can be displayed.

Further, a color image can be displayed by using a plurality of pixels 3130 as sub-pixels and emitting light in different wavelength ranges from each sub-pixel. For example, a pixel 3130 that emits light in the red wavelength region, a pixel 3130 that emits light in the green wavelength region, and a pixel 3130 that emits light in the blue wavelength region are used as one pixel.

The wavelength range of the light to be combined is not limited to red, green, and blue, and may be cyan, yellow, and magenta. A color image can be displayed by providing one pixel with sub-pixels that emit light in at least three different wavelength ranges.

In addition, one or more of yellow, cyan, magenta, white, etc. may be added to red, green, and blue. For example, in addition to red, green, and blue, sub-pixels that emit light in the yellow wavelength range may be added. Also, one or more reds, greens, blues, whites, etc. may be added to cyan, yellow, and magenta. For example, in addition to cyan, yellow, and magenta, subpixels that emit light in the blue wavelength range may be added. By providing sub-pixels that emit light in four or more different wavelength ranges in one pixel,
The color reproducibility of the displayed image can be further improved.

Further, the pixel number ratio (or emission area ratio) of red, green, and blue used for one pixel does not necessarily have to be 1: 1: 1. For example, the pixel number ratio (emission area ratio) is red: green: blue = 1: 1:
It may be 2. Further, the pixel number ratio (light receiving area ratio) may be red: green: blue = 1: 2: 3.

It is also possible to realize color display by combining a sub-pixel that emits white light with a color filter such as red, green, or blue. Further, a color filter that transmits light in the red, green, or blue wavelength range may be combined with each of the sub-pixels that emit light in the red, green, or blue wavelength range.

However, the present invention is not limited to the display device for color display, and can be applied to the display device for monochrome display.

<< An example of a pixel circuit for a liquid crystal display device >>
FIG. 48C shows an example of a pixel circuit that can be used in a liquid crystal display device. FIG. 48 (C
), The pixel circuit 3137 includes a transistor 3431 and a capacitive element 3233. Further, the pixel circuit 3137 is electrically connected to the liquid crystal element 3432 that can function as a display element.

The potential of one of the pair of electrodes of the liquid crystal element 3432 is appropriately set according to the specifications of the pixel circuit 3137. The alignment state of the liquid crystal included in the liquid crystal element 3432 is set by the data written in the node 3436. A common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 3432 included in each of the plurality of pixel circuits 3137.

Examples of the mode of the liquid crystal element 3432 include a TN mode, an STN mode, a VA mode, and an ASM (Axially Symmetrically Aligned Micro-cel).
l) Mode, OCB (Optically Compensated Birefrin)
gent) mode, FLC (Ferroelectric Liquid Crystal)
al) mode, AFLC (AntiFerroelectric Liquid Cry)
stal) mode, MVA mode, PVA (Patterned Vertical A)
lignment) mode, IPS mode, FFS mode, or TBA (Transv)
The erse Bend Alignment) mode and the like may be used. Also, as another example, ECB (Electrically Controlled Birefring)
element) mode, PDLC (Polymer Dispersed Liquid C)
rystal) mode, PNLC (Polymer Network Liquid C)
There are rystal) mode, guest host mode, etc. However, the present invention is not limited to this, and various modes can be used.

Further, the liquid crystal element 3432 may be configured by a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent. The liquid crystal display showing the blue phase has a response speed of 1 mse.
Since it is as short as c or less and is optically isotropic, no orientation treatment is required and the viewing angle dependence is small.

In the pixel circuit 3137 in the m-th row and n-th column, one of the source electrode and the drain electrode of the transistor 3431 is electrically connected to the signal line DL_n, and the other is electrically connected to the node 3436. The gate electrode of the transistor 3431 is electrically connected to the scanning line GL_m. The transistor 3431 has a function of controlling the writing of a data signal to the node 3436.

One of the pair of electrodes of the capacitive element 3233 is electrically connected to a wiring to which a specific potential is supplied (hereinafter, also referred to as “capacitive line CL”), and the other is electrically connected to a node 3436. .. Further, the other of the pair of electrodes of the liquid crystal element 3432 is electrically connected to the node 3436. The potential value of the capacitance line CL is appropriately set according to the specifications of the pixel circuit 3137. The capacitance element 3233 has a function as a holding capacitance for holding the data written in the node 3436.

Here, an operation example of the display device having the pixel circuit 3137 of FIG. 48C will be described. First, the pixel circuit 3137 of each row is sequentially selected by the circuit 3132, the transistor 3431 is turned on, and the data signal is written to the node 3436.

Next, the data signal written to the node 3436 is held with the transistor 3431 turned off. The amount of transmitted light of the liquid crystal element 3432 is determined according to the data signal written to the node 3436. By sequentially performing this line by line, an image can be displayed in the display area 3131.

<Display device configuration example>
Using the transistor shown in the above embodiment, a part or the whole of the drive circuit including the transistor can be integrally formed on the same substrate as the pixel portion to form a system on panel. A configuration example of a display device capable of using the transistor shown in the above embodiment will be described with reference to FIGS. 50 and 51.

[Liquid crystal display and EL display]
As an example of the display device, a display device using a liquid crystal element and a display device using an EL element will be described. In FIG. 50 (A), the pixel portion 40 provided on the first substrate 4001.
A sealing material 4005 is provided so as to surround the 02, and is sealed by the second substrate 4006. In FIG. 50A, a signal line formed of a single crystal semiconductor or a polycrystalline semiconductor on a separately prepared substrate in a region different from the region surrounded by the sealing material 4005 on the first substrate 4001. A drive circuit 4003 and a scanning line drive circuit 4004 are mounted. Further, the signal line drive circuit 4003, the scan line drive circuit 4004, or the pixel unit 4002.
Various signals and potentials given to FPC (Flexible printed cil)
It is supplied from cut) 4018a and FPC4018b.

In FIGS. 50 (B) and 50 (C), the pixel portion 4 provided on the first substrate 4001.
A sealing material 4005 is provided so as to surround the 002 and the scanning line drive circuit 4004. Further, a second substrate 4006 is provided on the pixel unit 4002 and the scanning line drive circuit 4004. Therefore, the pixel unit 4002 and the scanning line drive circuit 4004 are connected to the first substrate 400.
It is sealed together with the display element by 1, the sealing material 4005, and the second substrate 4006. In FIGS. 50B and 50C, the sealing material 4005 on the first substrate 4001
A signal line drive circuit 4003 formed of a single crystal semiconductor or a polycrystalline semiconductor is mounted on a separately prepared substrate in a region different from the region surrounded by. In FIGS. 50B and 50C, various signals and potentials given to the signal line drive circuit 4003, the scan line drive circuit 4004, or the pixel unit 4002 are supplied from the FPC 4018.

Further, FIGS. 50B and 50C show an example in which the signal line drive circuit 4003 is separately formed and mounted on the first substrate 4001, but the configuration is not limited to this. The scanning line drive circuit may be separately formed and mounted, or only a part of the signal line driving circuit or a part of the scanning line driving circuit may be separately formed and mounted.

The method of connecting the separately formed drive circuit is not particularly limited, and wire bonding, COG (Chip On Glass), and TCP (Tape Carrier) are not particularly limited.
Package), COF (Chip On Film) and the like can be used.
FIG. 50 (A) is an example of mounting the signal line drive circuit 4003 and the scanning line drive circuit 4004 by COG, and FIG. 50 (B) is an example of mounting the signal line drive circuit 4003 by COG. (C) is an example of mounting the signal line drive circuit 4003 by TCP.

Further, the display device may include a panel in which the display element is sealed and a module in which an IC or the like including a controller is mounted on the panel.

Further, the pixel portion and the scanning line drive circuit provided on the first substrate have a plurality of transistors, and the transistors shown in the above embodiment can be applied.

51 (A) and 51 (B) are cross-sectional views showing a cross-sectional structure of a portion shown by a chain line of N1-N2 in FIG. 50 (B). The display device shown in FIGS. 51 (A) and 51 (B) has an electrode 40.
15, and the electrode 4015 has a terminal of the FPC 4018 and an anisotropic conductive layer 4019.
It is electrically connected via. Further, the electrode 4015 has an insulating layer 4112 and an insulating layer 4.
It is electrically connected to the wiring 4014 at the openings formed in the 111 and the insulating layer 4110.

The electrode 4015 is formed of the same conductive layer as the first electrode layer 4030, and the wiring 4014 is
It is formed of the same conductive layer as the transistor 4010 and the source and drain electrodes of the transistor 4011.

Further, the pixel unit 4002 and the scanning line drive circuit 4004 provided on the first substrate 4001 are
It has a plurality of transistors, and in FIGS. 51 (A) and 51 (B), the transistor 4010 included in the pixel unit 4002 and the transistor 40 included in the scanning line drive circuit 4004.
11 is illustrated. In FIG. 51 (A), the transistor 4010 and the transistor 4
An insulating layer 4112, an insulating layer 4111, and an insulating layer 4110 are provided on 011 with reference to FIG.
In 1 (B), the partition wall 4510 is formed on the insulating layer 4112.

Further, the transistor 4010 and the transistor 4011 are provided on the insulating layer 4102. Further, the transistor 4010 and the transistor 4011 have an insulating layer 410.
It has an electrode 4017 formed on the electrode 4017, and an insulating layer 4103 is formed on the electrode 4017.
The electrode 4017 can function as a backgate electrode.

As the transistor 4010 and the transistor 4011, the transistor shown in the above embodiment can be used. The transistor exemplified in the above embodiment has suppressed fluctuations in electrical characteristics and is electrically stable. Therefore, the display device of the present embodiment shown in FIGS. 51 (A) and 51 (B) can be a highly reliable display device.

Note that FIGS. 51 (A) and 51 (B) illustrate the case where a transistor having the same structure as the transistor 160 shown in the above embodiment is used as the transistor 4010 and the transistor 4011.

Further, the display device shown in FIGS. 51 (A) and 51 (B) has a capacitive element 4020. The capacitive element 4020 has a region in which a part of one of the source electrode or the drain electrode of the transistor 4010 and the electrode 4021 overlap with each other via the insulating layer 4103. The electrode 4021 is
It is formed of the same conductive layer as the electrode 4017.

Generally, the capacitance of the capacitive element provided in the display device is set so as to be able to retain the electric charge for a predetermined period in consideration of the leakage current of the transistor arranged in the pixel portion and the like. The capacitance of the capacitive element may be set in consideration of the off current of the transistor and the like.

For example, by using an OS transistor in the pixel portion of the liquid crystal display device, the capacity of the capacitive element can be reduced to 1/3 or less or 1/5 or less of the liquid crystal capacity. By using an OS transistor, it is possible to omit the formation of a capacitive element.

The transistor 4010 provided in the pixel unit 4002 is electrically connected to the display element. FIG. 51 (A) is an example of a liquid crystal display device using a liquid crystal element as a display element. FIG. 51 (A
), The liquid crystal element 4013, which is a display element, includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. In addition, an insulating layer 4032 and an insulating layer 4033 that function as an alignment film are provided so as to sandwich the liquid crystal layer 4008. Second electrode layer 4031
Is provided on the side of the second substrate 4006, and the first electrode layer 4030 and the second electrode layer 4031 are superimposed via the liquid crystal layer 4008.

Further, the spacer 4035 is a columnar spacer obtained by selectively etching the insulating layer, and is provided to control the distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. There is. A spherical spacer may be used.

When a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low molecular weight liquid crystal, a polymer liquid crystal, a polymer dispersion type liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials show a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase and the like depending on the conditions.

Further, a liquid crystal showing a blue phase without using an alignment film may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the temperature of the cholesteric liquid crystal is raised. Since the blue phase is expressed only in a narrow temperature range, a liquid crystal composition mixed with 5% by weight or more of a chiral agent is used for the liquid crystal layer in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response speed of 1 msec or less, is optically isotropic, does not require an orientation treatment, and has a small viewing angle dependence. In addition, since it is not necessary to provide an alignment film, the rubbing process is not required, so that electrostatic breakdown caused by the rubbing process can be prevented, and defects and breakage of the liquid crystal display device during the manufacturing process can be reduced. .. Therefore, it is possible to improve the productivity of the liquid crystal display device.

Further, it is possible to use a method called multi-domain or multi-domain design, in which a pixel is divided into several areas (sub-pixels) and the molecules are tilted in different directions.

The intrinsic resistance of the liquid crystal material is 1 × 10 ⁹ Ω · cm or more, preferably 1 × 10 ¹
It is ¹ Ω · cm or more, more preferably 1 × 10 ¹² Ω · cm or more. The value of the intrinsic resistance in the present specification is a value measured at 20 ° C.

The OS transistor used in this embodiment can reduce the current value (off current value) in the off state. Therefore, the holding time of an electric signal such as an image signal can be lengthened, and the writing interval can be set long when the power is on. Therefore, the frequency of the refresh operation can be reduced, which has the effect of suppressing power consumption.

Further, since the OS transistor can obtain a relatively high field effect mobility, it can be driven at high speed. Therefore, by using the above-mentioned transistor in the pixel portion of the display device, it is possible to provide a high-quality image. Further, since the drive circuit unit or the pixel unit can be manufactured separately on the same substrate, the number of parts of the display device can be reduced.

Further, in the display device, an optical member (optical substrate) such as a black matrix (light-shielding layer), a polarizing member, a retardation member, and an antireflection member may be appropriately provided. For example, circular polarization using a polarizing substrate and a retardation substrate may be used. Further, a backlight, a side light or the like may be used as the light source.

Further, as a display element included in the display device, a light emitting element using electroluminescence can be applied. A light emitting device that utilizes electroluminescence is distinguished by whether the light emitting material is an organic compound or an inorganic compound, and the former is generally called an organic EL element and the latter is called an inorganic EL element.

In the organic EL element, by applying a voltage to the light emitting element, electrons and holes are injected from the pair of electrodes into the layer containing the luminescent organic compound, and a current flows. Then, when those carriers (electrons and holes) are recombined, the luminescent organic compound forms an excited state, and when the excited state returns to the ground state, it emits light. Due to such a mechanism, such a light emitting device is called a current excitation type light emitting device.

The inorganic EL element is classified into a dispersed inorganic EL element and a thin film type inorganic EL element according to the element configuration. The dispersed inorganic EL element has a light emitting layer in which particles of a light emitting material are dispersed in a binder, and the light emitting mechanism is a donor using a donor level and an acceptor level.
It is an acceptor recombination type emission. The thin film type inorganic EL element has a structure in which a light emitting layer is sandwiched between a dielectric layer and further sandwiched between electrodes, and the light emitting mechanism is localized light emission utilizing the inner-shell electron transition of metal ions. Here, an organic EL element will be used as the light emitting element.

The light emitting element may have at least one of a pair of electrodes transparent in order to extract light. Then, a top emission (top emission) structure in which a transistor and a light emitting element are formed on the substrate and light emission is taken out from the surface opposite to the substrate, and a bottom injection (bottom emission) structure in which light emission is taken out from the surface on the substrate side. , There is a light emitting element having a double-sided emission (dual emission) structure that extracts light emission from both sides, and any light emitting element having an injection structure can be applied.

FIG. 51B is an example of a light emitting display device (also referred to as “EL display device”) using a light emitting element as a display element. The light emitting element 4513, which is a display element, is electrically connected to the transistor 4010 provided in the pixel unit 4002. The configuration of the light emitting element 4513 is a laminated structure of the first electrode layer 4030, the light emitting layer 4511, and the second electrode layer 4031, but is not limited to this configuration. The configuration of the light emitting element 4513 can be appropriately changed according to the direction of the light extracted from the light emitting element 4513 and the like.

The partition wall 4510 is formed by using an organic insulating material or an inorganic insulating material. In particular, it is preferable to use a photosensitive resin material to form an opening on the first electrode layer 4030 so that the side surface of the opening becomes an inclined surface formed with a continuous curvature.

The light emitting layer 4511 may be composed of a single layer or may be configured such that a plurality of layers are laminated.

A protective layer may be formed on the second electrode layer 4031 and the partition wall 4510 so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light emitting element 4513. As the protective layer, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum nitride, aluminum nitride, DLC (Diamond Like Carbon) and the like can be formed. Further, the first substrate 4001, the second substrate 4006, and the sealing material 4
A filler 4514 is provided and sealed in the space sealed by 005. As described above, it is preferable to package (enclose) with a protective film (bonded film, ultraviolet curable resin film, etc.) or a cover material having high airtightness and less degassing so as not to be exposed to the outside air.

As the filler 4514, in addition to an inert gas such as nitrogen or argon, an ultraviolet curable resin or a thermosetting resin can be used, and PVC (polyvinyl chloride), acrylic resin, etc. can be used.
Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV
A (ethylene vinyl acetate) can be used. For example, nitrogen may be used as the filler.

If necessary, a polarizing plate or a circular polarizing plate (including an elliptical polarizing plate) is used on the ejection surface of the light emitting element.
, A retardation plate (λ / 4 plate, λ / 2 plate), an optical film such as a color filter may be appropriately provided. Further, an antireflection film may be provided on the polarizing plate or the circular polarizing plate. For example, it is possible to apply an anti-glare treatment that can diffuse the reflected light due to the unevenness of the surface and reduce the reflection.

A first electrode layer and a second electrode layer (pixel electrode layer, common electrode layer,
In the counter electrode layer and the like), the translucency and the reflectivity may be selected according to the direction of the light to be taken out, the place where the electrode layer is provided, and the pattern structure of the electrode layer.

The first electrode layer 4030 and the second electrode layer 4031 include indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, and indium containing titanium oxide. A translucent conductive material such as tin oxide, indium zinc oxide, and indium tin oxide to which silicon oxide is added can be used.

Further, the first electrode layer 4030 and the second electrode layer 4031 are tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (
Metals such as Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag). , Or an alloy thereof, or a metal nitride thereof, using one or more.

Further, the first electrode layer 4030 and the second electrode layer 4031 can be formed by using a conductive composition containing a conductive polymer (also referred to as a conductive polymer). As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene or its derivatives,
Alternatively, a derivative thereof may be mentioned.

Further, since the transistor is easily destroyed by static electricity or the like, it is preferable to provide a protection circuit for protecting the drive circuit. The protection circuit is preferably configured by using a non-linear element.

By using the transistor shown in the above embodiment, a reliable display device can be provided. Further, by using the transistor shown in the above embodiment, it is possible to provide a display device capable of increasing the definition and the area and having good display quality. Further, it is possible to provide a display device with reduced power consumption.

[Display module]
A display module will be described as an example of a semiconductor device using the above-mentioned transistor. The display module 6000 shown in FIG. 52 has an upper cover 6001 and a lower cover 60.
It has a touch sensor 6004 connected to the FPC6003, a display panel 6006 connected to the FPC6005, a backlight unit 6007, a frame 6009, a printed circuit board 6010, and a battery 6011. The backlight unit 6007,
The battery 6011, the touch sensor 6004, and the like may not be provided.

The semiconductor device according to one aspect of the present invention is, for example, a touch sensor 6004 and a display panel 6006.
, Can be used for integrated circuits mounted on the printed circuit board 6010 and the like. For example, the display device described above can be used for the display panel 6006.

The shape and dimensions of the upper cover 6001 and the lower cover 6002 can be appropriately changed according to the size of the touch sensor 6004, the display panel 6006, and the like.

As the touch sensor 6004, a resistance film type or a capacitance type touch sensor can be used by superimposing it on the display panel 6006. It is also possible to add a touch sensor function to the display panel 6006. For example, it is possible to provide a touch sensor electrode in each pixel of the display panel 6006 and add a capacitance type touch panel function. Alternatively, it is also possible to provide an optical sensor in each pixel of the display panel 6006 and add the function of an optical touch sensor.

The backlight unit 6007 has a light source 6008. A light source 6008 may be provided at the end of the backlight unit 6007, and a light diffusing plate may be used. Further, when a light emitting display device or the like is used for the display panel 6006, the backlight unit 6007 can be omitted.

The frame 6009 has a function as an electromagnetic shield for blocking electromagnetic waves generated from the printed circuit board 6010 side, in addition to the protective function of the display panel 6006. Further, the frame 6009 may have a function as a heat sink.

The printed circuit board 6010 includes a power supply circuit, a signal processing circuit for outputting a video signal, a clock signal, and the like. Battery 6011 is used as a power source to supply power to the power supply circuit.
It may be a commercial power source. When a commercial power source is used as the power source, the battery 6011 can be omitted.

Further, members such as a polarizing plate, a retardation plate, and a prism sheet may be added to the display module 6000.

It should be noted that this embodiment can be appropriately combined with other embodiments and examples shown in the present specification.

[RF tag]
An RF tag will be described as an example of a semiconductor device using the above-mentioned transistor.

The RF tag according to one aspect of the present invention has a storage circuit (storage device) inside, stores information in the storage circuit, and exchanges information with the outside by using non-contact means, for example, wireless communication. be.
Due to these characteristics, the RF tag can be used in an individual authentication system or the like that identifies an article by reading individual information of the article or the like. High reliability is required for use in these applications.

The configuration of the RF tag will be described with reference to FIG. 53. FIG. 53 is a block diagram showing a configuration example of the RF tag.

As shown in FIG. 53, the RF tag 800 has an antenna 804 that receives a radio signal 803 transmitted from an antenna 802 connected to a communication device 801 (also referred to as an interrogator, a reader / writer, etc.). The above-mentioned transistor may be used for the communication device 801. RF tag 8
00 has a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a storage circuit 810, and a ROM 811. As the semiconductor of the transistor having a rectifying action included in the demodulation circuit 807, for example, an oxide semiconductor capable of sufficiently suppressing a reverse current may be used. As a result, it is possible to suppress a decrease in the rectifying action due to the reverse current and prevent the output of the demodulation circuit from being saturated. That is, the output of the demodulation circuit can be made linear with respect to the input of the demodulation circuit. There are three major data transmission formats: an electromagnetic coupling method in which a pair of coils are arranged facing each other and communication is performed by mutual induction, an electromagnetic induction method in which communication is performed by an induced electromagnetic field, and a radio wave method in which communication is performed using radio waves. Be separated. The RF tag 800 can be used in any of the methods.

Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving a radio signal 803 to and from the antenna 802 connected to the communication device 801. Further, the rectifier circuit 805 rectifies the input AC signal generated by receiving the radio signal at the antenna 804, for example, half-wave double pressure rectification, and smoothes the rectified signal by the capacitive element in the subsequent stage. This is a circuit for generating an input potential. A limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. The limiter circuit has a large amplitude of the input AC signal.
This is a circuit for controlling so that power exceeding a certain power is not input to the subsequent circuit when the internally generated voltage is large.

The constant voltage circuit 806 is a circuit for generating a stable power supply voltage from an input potential and supplying it to each circuit. The constant voltage circuit 806 may have a reset signal generation circuit inside. The reset signal generation circuit utilizes the rising edge of the stable power supply voltage to make the logic circuit 8
It is a circuit for generating a reset signal of 09.

The demodulation circuit 807 is a circuit for generating a demodulated signal by demodulating the input AC signal by detecting the envelope. Further, the modulation circuit 808 is a circuit for performing modulation according to the data output from the antenna 804.

The logic circuit 809 is a circuit for analyzing and processing the demodulated signal. The storage circuit 810 is a circuit that holds the input information, and has a row decoder, a column decoder, a storage area, and the like. Further, the ROM 811 is a circuit for storing a unique number (ID) and the like and outputting according to processing.

In addition, each circuit mentioned above can be discarded as appropriate.

The above-mentioned storage device can be used for the storage circuit 810. The storage device according to one aspect of the present invention is suitable for RF tags because it can retain information even when the power supply is cut off. Further, the storage device according to one aspect of the present invention does not cause a difference in the maximum communication distance between reading and writing data because the power (voltage) required for writing data is lower than that of the conventional non-volatile memory. It is also possible. Further, it is possible to suppress the occurrence of malfunction or erroneous writing due to insufficient power when writing data.

Further, since the storage device according to one aspect of the present invention can be used as a non-volatile memory, it can also be applied to ROM 811. In that case, it is preferable that the producer separately prepares a command for writing the data to the ROM 811 so that the user cannot freely rewrite the data. By shipping the product after the producer writes the unique number before shipping, it is possible to assign the unique number only to the non-defective product to be shipped, instead of assigning the unique number to all the RF tags produced. The unique number of the product after shipment does not become discontinuous, and customer management corresponding to the product after shipment becomes easy.

An example of using the RF tag according to one aspect of the present invention will be described with reference to FIG. 54. RF tags have a wide range of uses, such as banknotes, coins, securities, bearer bonds, certificates such as driver's licenses and resident cards (see Fig. 54 (A)), recording media such as DVD software and video tapes (see Fig. 54 (A)). (See FIG. 54 (B)), containers such as plates, cups and bottles (see FIG. 54 (C)), packaging supplies such as wrapping paper, boxes and ribbons, moving objects such as bicycles (see FIG. 54 (D)). .), Personal items such as bags and glasses, plants, animals, human bodies, clothing, daily necessities, medical products containing chemicals and drugs, or electronic devices (eg, liquid crystal display devices, EL display devices, television devices, or mobile phones. It can be used by being provided on an article such as a telephone) or a tag attached to each article (see FIGS. 54 (E) and 54 (F)).

The RF tag 800 according to one aspect of the present invention is fixed to an article by being attached to or embedded in a surface. For example, if it is a book, it is embedded in paper, and if it is a package made of organic resin, it is embedded inside the organic resin and fixed to each article. Since the RF tag 800 according to one aspect of the present invention realizes small size, thinness, and light weight, the design of the article itself is not impaired even after being fixed to the article. Further, an authentication function can be given to banknotes, coins, securities, bearer bonds, certificates, etc. by the RF tag 800 according to one aspect of the present invention, and if this authentication function is utilized, counterfeiting can be prevented. Can be done. Further, by attaching the RF tag 800 according to one aspect of the present invention to a packaging container, a recording medium, personal belongings, clothing, daily necessities, an electronic device, etc., the efficiency of a system such as an inspection system can be improved. .. also,
By attaching the RF tag 800 according to one aspect of the present invention to the moving body, it is possible to enhance the security against theft and the like. As described above, the RF tag 800 according to one aspect of the present invention can be used for each of the above-mentioned uses.

This embodiment can be implemented in combination with the configurations described in other embodiments as appropriate.

(Embodiment 5)
<Package using lead frame type interposer>
FIG. 55 (A) shows a perspective view showing a cross-sectional structure of a package using a lead frame type interposer. In the package shown in FIG. 55 (A), the chip 551 corresponding to the semiconductor device according to one aspect of the present invention is connected to the terminal 552 on the interposer 550 by a wire bonding method. The terminal 552 is arranged on the surface on which the chip 551 of the interposer 550 is mounted. The chip 551 may be sealed with the mold resin 553, but the chip 551 is sealed with a part of each terminal 552 exposed.

FIG. 55 (B) shows a configuration example of an electronic device in which a package is mounted on a circuit board. The electronic device shown in FIG. 55 (B) is mounted on, for example, a mobile phone. In the electronic device shown in FIG. 55 (B), a package 562 and a battery 564 are mounted on a printed wiring board 561. Further, the printed wiring board 561 is FP on the panel 560 provided with the display element.
It is implemented by C563.

It should be noted that this embodiment can be appropriately combined with other embodiments and examples shown in the present specification.

(Embodiment 6)
In this embodiment, an example of an electronic device using a semiconductor device according to one aspect of the present invention will be described.

As an electronic device using a semiconductor device according to one aspect of the present invention, it is stored in a display device such as a television or a monitor, a lighting device, a desktop or notebook personal computer, a word processor, and a recording medium such as a DVD (Digital Versaille Disc). Image playback devices, portable CD players, radios, tape recorders, headphone stereos, stereos, table clocks, wall clocks, cordless telephone handsets, transceivers, car phones, mobile phones, personal digital assistants, tablets High-frequency heating of fixed-type game machines such as personal computers, portable game machines, pachinko machines, calculators, electronic notebooks, electronic book terminals, electronic translators, voice input devices, video cameras, digital still cameras, electric shavers, microwave ovens, etc. Equipment, electric rice cooker, electric washing machine, electric vacuum cleaner, water heater, fan, hair dryer,
Air conditioners such as air conditioners, humidifiers, dehumidifiers, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerators, freezers for storing DNA,
Examples include flashlights, tools such as chainsaws, smoke detectors, medical devices such as dialysis machines, and the like.
Further examples include industrial equipment such as guide lights, traffic lights, conveyor belts, elevators, escalator, industrial robots, power storage systems, power leveling and power storage devices for smart grids. Further, an engine using fuel and a moving body propelled by an electric motor using electric power from a storage body may also be included in the category of electronic devices. Examples of the moving body include an electric vehicle (EV), a hybrid electric vehicle (HEV) having an internal combustion engine and an electric motor, a plug-in hybrid electric vehicle (PHEV), and a tracked vehicle in which these tire wheels are changed to an infinite track.
Motorized bicycles including electrically power assisted bicycles, motorcycles, electric wheelchairs, golf carts,
Small or large vessels, submarines, helicopters, aircraft, rockets, artificial satellites, space probes and planetary explorers, spacecraft, etc. may be mentioned.

The portable game machine 2900 shown in FIG. 56A has a housing 2901, a housing 2902, a display unit 2903, a display unit 2904, a microphone 2905, a speaker 2906, and an operation key 290.
It has 7 mag. The portable game machine shown in FIG. 25A has two display units 2903 and a display unit 2904, but the number of display units is not limited to this. Display 2903
Is provided with a touch screen as an input device and can be operated by a stylus 2908 or the like.

The information terminal 2910 shown in FIG. 56B has a display unit 2912 and a microphone 2 in the housing 2911.
It has a speaker unit 2914, a camera 2913, an external connection unit 2916, an operation button 2915, and the like. The display unit 2912 includes a display panel and a touch screen using a flexible substrate. The information terminal 2910 can be used as, for example, a smartphone, a mobile phone, a tablet-type information terminal, a tablet-type personal computer, an electronic book terminal, or the like.

The notebook personal computer 2920 shown in FIG. 56 (C) has a housing 2921, a display unit 2922, a keyboard 2923, a pointing device 2924, and the like.

The video camera 2940 shown in FIG. 56 (D) has a housing 2941, a housing 2942, and a display unit 2.
It has 943, an operation key 2944, a lens 2945, a connection portion 2946, and the like. The operation key 2944 and the lens 2945 are provided in the housing 2941, and the display unit 2943 is provided in the housing 2942. The housing 2941 and the housing 2942 are connected to each other at the connection portion 2946.
The angle between the housing 2941 and the housing 2942 can be changed by the connecting portion 2946. Depending on the angle of the housing 2942 with respect to the housing 2941, the orientation of the image displayed on the display unit 2943 can be changed, and the display / non-display of the image can be switched.

FIG. 56 (E) shows an example of a bangle-type information terminal. The information terminal 2950 has a housing 295.
It has 1 and a display unit 2952 and the like. The display unit 2952 is supported by a housing 2951 having a curved surface. Since the display unit 2952 is provided with a display panel using a flexible substrate, it is possible to provide a flexible, light and easy-to-use information terminal 2950.

FIG. 56F shows an example of a wristwatch-type information terminal. The information terminal 2960 has a housing 2961.
, Display unit 2962, band 2963, buckle 2964, operation button 2965, input / output terminal 2966, and the like. The information terminal 2960 can execute various applications such as mobile phone, e-mail, text viewing and creation, music playback, Internet communication, and computer games.

The display surface of the display unit 2962 is curved, and display can be performed along the curved display surface. Further, the display unit 2962 is provided with a touch sensor and can be operated by touching the screen with a finger or a stylus. For example, the application can be started by touching the icon 2967 displayed on the display unit 2962. In addition to setting the time, the operation button 2965 can have various functions such as power on / off operation, wireless communication on / off operation, execution / cancellation of manner mode, execution / cancellation of power saving mode, and the like. .. For example, by the operating system built into the information terminal 2960, the operation button 296
It is also possible to set the functions of 5.

In addition, the information terminal 2960 can execute short-range wireless communication standardized for communication. For example, by communicating with a headset capable of wireless communication, it is possible to make a hands-free call. Further, the information terminal 2960 is provided with an input / output terminal 2966, and data can be directly exchanged with another information terminal via a connector. Input / output terminal 29
Charging can also be done via 66. The charging operation may be performed by wireless power supply without going through the input / output terminal 2966.

FIG. 56 (G) shows an electric refrigerator as an example of household electric appliances. The electric refrigerator 2970 has a housing 2971, a refrigerator door 2972, a freezing room door 2973, and the like.

FIG. 56 (H) is an external view showing an example of an automobile. The car 2980 has a body 2981
, Wheels 2982, dashboard 2983, and lights 2984 and the like.

The electronic device shown in this embodiment is equipped with the above-mentioned transistor, the above-mentioned semiconductor device, or the like.

This embodiment can be implemented in combination with the configurations described in other embodiments as appropriate.

(Embodiment 7)
In this embodiment, a film forming apparatus (sputtering apparatus) having a film forming chamber in which a target for sputtering can be installed will be described. The film forming apparatus shown in this embodiment is
It can be used for a parallel plate type sputtering device, a facing target type sputtering device, or the like.

In film formation using a facing target type sputtering device, damage to the surface to be formed can be reduced, so that it is easy to obtain a film having high crystallinity. That is, it may be preferable to use a facing target type sputtering device for film formation such as CAAC-OS.

A film forming method using a parallel plate sputtering device is used in PESP (Parallel).
It can also be called Electrode Sputtering). In addition, VDSP (Vapor Depositi) is a film formation method using a facing target sputtering device.
It can also be called on Sputtering).

First, the configuration of the film forming apparatus in which impurities are less likely to be mixed in the film at the time of film forming will be described with reference to FIGS. 57 and 58.

FIG. 57 schematically shows a top view of the single-wafer multi-chamber film forming apparatus 2700. The film forming apparatus 2700 has an atmospheric pressure side substrate supply chamber 2701 including a cassette port 2761 for accommodating the substrate and an alignment port 2762 for aligning the substrate, and an atmospheric pressure side substrate for transporting the substrate from the atmospheric pressure side substrate supply chamber 2701. The transport chamber 2702 and the load lock chamber 2703a that carries in the substrate and switches the pressure in the room from atmospheric pressure to atmospheric pressure, or from reduced pressure to atmospheric pressure, and carries out the substrate and reduces the pressure in the room from reduced pressure to atmospheric pressure. Alternatively, the unload lock chamber 2703b for switching from atmospheric pressure to decompression and the transport chamber 2 for transporting the substrate in vacuum.
It has a substrate heating chamber 2705 for heating the substrate, a film forming chamber 2706a on which a target is arranged and forming a film, a film forming chamber 2706b, and a film forming chamber 2706c. The film formation chamber 2706a, the film formation chamber 2706b, and the film formation chamber 2706c can take into consideration the above-mentioned configuration of the film formation chamber.

Further, the atmospheric board transport chamber 2702 is connected to the load lock chamber 2703a and the unload lock chamber 2703b, and the load lock chamber 2703a and the unload lock chamber 270 are connected.
3b is connected to the transport chamber 2704, and the transport chamber 2704 is a substrate heating chamber 2705 and a film forming chamber 2.
It is connected to 706a, the film forming chamber 2706b and the film forming chamber 2706c.

A gate valve 2764 is provided at the connection portion of each chamber, and the atmospheric side substrate supply chamber 2 is provided.
Except for 701 and the atmosphere side substrate transfer chamber 2702, each chamber can be independently maintained in a vacuum state. Further, the atmospheric side substrate transport chamber 2702 and the transport chamber 2704 are the transport robot 276.
3 and can convey the substrate.

Further, it is preferable that the substrate heating chamber 2705 also serves as a plasma processing chamber. Film forming equipment 2700
Can transport the substrate between treatments without exposing it to the atmosphere, so that it is possible to suppress the adsorption of impurities on the substrate. In addition, the order of film formation and heat treatment can be freely constructed. The number of the transport chamber, the film forming chamber, the load lock chamber, the unload lock chamber, and the substrate heating chamber is not limited to the above number, and an optimum number can be appropriately provided according to the installation space and process conditions.

Next, FIG. 58 shows a cross section corresponding to the alternate long and short dash line X1-X2, the alternate long and short dash line Y2-Y3 of the film forming apparatus 2700 shown in FIG. 57.

FIG. 58 (A) shows a cross section of the substrate heating chamber 2705 and the transfer chamber 2704, and the substrate heating chamber 2705 has a plurality of heating stages 2765 capable of accommodating the substrate. The substrate heating chamber 2705 is connected to the vacuum pump 2770 via a valve.
As the vacuum pump 2770, for example, a dry pump, a mechanical booster pump, or the like can be used.

Further, as the heating mechanism that can be used in the substrate heating chamber 2705, for example, a heating mechanism that heats using a resistance heating element or the like may be used. Alternatively, it may be a heating mechanism that heats by heat conduction or heat radiation from a medium such as a heated gas. For example, GRTA, L
RTA such as RTA can be used.

Further, the substrate heating chamber 2705 is a refiner 27 via a mass flow controller 2780.
Connected to 81. The mass flow controller 2780 and the refiner 2781 are provided as many as the number of gas types, but only one is shown for ease of understanding. Substrate heating chamber 2705
As the gas introduced into, a gas having a dew point of −80 ° C. or lower, preferably −100 ° C. or lower can be used, and for example, oxygen gas, nitrogen gas, and a rare gas (argon gas or the like) are used.

The transfer chamber 2704 has a transfer robot 2763. The transfer robot 2763 can transfer the substrate to each room. Further, the transfer chamber 2704 is connected to the vacuum pump 2770 and the cryopump 2771 via a valve. With such a configuration, the transfer chamber 2704 is exhausted from atmospheric pressure to low vacuum or medium vacuum (about 0.1 to several hundred Pa) using a vacuum pump 2770, and the valve is switched to switch from medium vacuum to high vacuum. Vacuum or ultra-high vacuum (0.1 Pa to 1 × 10 ^-7 Pa) is exhausted using the cryopump 2771.

Further, for example, two or more cryopumps 2771 may be connected in parallel to the transport chamber 2704. With such a configuration, even if one cryopump is being regenerated, it is possible to exhaust using the remaining cryopumps. The above-mentioned regeneration refers to a process of releasing molecules (or atoms) stored in a cryopump. Cryopumps have reduced exhaust capacity if they store too many molecules (or atoms).
Regeneration is done regularly.

FIG. 58 (B) shows a film forming chamber 2706b, a transport chamber 2704, and a load lock chamber 2703a.
The cross section of is shown.

Here, the details of the film forming chamber (sputtering chamber) will be described with reference to FIG. 58 (B). The film forming chamber 2706b shown in FIG. 58 (B) has a target 2766a and a target 276.
It has 6b, a target shield 2767a, a target shield 2767b, a magnet unit 2790a, a magnet unit 2790b, a substrate holder 2768, and a power supply 2791. Not shown, target 2766a and target 276
Each of the 6b is fixed to the target holder via the backing plate. Further, a power supply 2791 is electrically connected to the target 2766a and the target 2766b. The magnet unit 2790a and the magnet unit 2790b are arranged on the back surface of the target 2766a and the target 2766b, respectively. The target shield 2767a and the target shield 2767b are the targets 2766, respectively.
It is arranged so as to surround the ends of a and the target 2766b. Here, the substrate 2769 is supported by the substrate holder 2768. The board holder 2768 is a variable member 27.
It is fixed to the film forming chamber 2706b via 84. Target 2 by variable member 2784
The substrate holder 2768 can be moved to the region between the 766a and the target 2766b (also referred to as the inter-target region). For example, by arranging the substrate holder 2768 that supports the substrate 2769 in the inter-target region, damage due to plasma may be reduced. Further, although not shown, the substrate holder 2768 may include a substrate holding mechanism for holding the substrate 2769, a heater for heating the substrate 2769 from the back surface, and the like.

In addition, the target shield 2767 can prevent particles sputtered from the target 2766 from accumulating in unnecessary regions. The target shield 2767 is
It is desirable to process the accumulated spatter particles so that they do not peel off. For example, a blast treatment that increases the surface roughness, or the surface of the target shield 2767 may be provided with irregularities.

Further, the film forming chamber 2706b has a mass flow controller 2 via a gas heating mechanism 2782.
Connected to 780, the gas heating mechanism 2782 is connected to the refiner 2781 via a mass flow controller 2780. The gas heating mechanism 2782 can heat the gas introduced into the film forming chamber 2706b to 40 ° C. or higher and 400 ° C. or lower, preferably 50 ° C. or higher and 200 ° C. or lower. The gas heating mechanism 2782, the mass flow controller 2780, and the refiner 2781 are provided as many as the number of gas types, but only one is shown for ease of understanding. As the gas introduced into the film forming chamber 2706b, a gas having a dew point of −80 ° C. or lower, preferably −100 ° C. or lower can be used, and for example, oxygen gas, nitrogen gas, and a rare gas (argon gas or the like) can be used. Use.

When a refiner is provided immediately before the gas introduction port, the length of the pipe from the refiner to the film forming chamber 2706b is 10 m or less, preferably 5 m or less, and more preferably 1 m or less. By setting the length of the pipe to 10 m or less, 5 m or less, or 1 m or less, the influence of the gas released from the pipe can be reduced according to the length. Further, for the gas pipe, it is preferable to use a metal pipe whose inside is coated with iron fluoride, aluminum oxide, chromium oxide or the like. The above-mentioned piping is, for example, SUS.
Compared with the 316L-EP pipe, the amount of gas containing impurities is small, and the entry of impurities into the gas can be reduced. In addition, high-performance ultra-compact metal gasket joints (UPG) are used for piping joints.
It is good to use a joint). Further, it is preferable that all the pipes are made of metal because the influence of the generated gas and external leak can be reduced as compared with the case of using a resin or the like.

Further, the film forming chamber 2706b is connected to the turbo molecular pump 2772 and the vacuum pump 2770 via a valve.

Further, the film forming chamber 2706b is provided with a cryotrap 2751.

The cryotrap 2751 is a mechanism capable of adsorbing a molecule (or atom) having a relatively high melting point such as water. The turbo molecular pump 2772 is excellent in productivity because it stably exhausts large-sized molecules (or atoms) and the frequency of maintenance is low, but it has a low hydrogen and water exhaust capacity. Therefore, in order to increase the exhaust capacity for water and the like, the cryotrap 2751 is connected to the film forming chamber 2706b. Cryotrap 2751
The temperature of the refrigerator is 100K or less, preferably 80K or less. Further, when the cryotrap 2751 has a plurality of refrigerators, it is preferable to change the temperature for each refrigerator because efficient exhaust can be achieved. For example, the temperature of the first stage refrigerator is set to 100K or less, and 2
The temperature of the refrigerator at the stage may be set to 20 K or less. In some cases, a higher vacuum can be achieved by using a titanium sublimation pump instead of the cryotrap. Further, it may be possible to further increase the vacuum by using an ion pump instead of the cryopump or the turbo molecular pump.

The exhaust method of the film forming chamber 2706b is not limited to this, and may have the same configuration as the exhaust method (exhaust method of the cryopump and the vacuum pump) shown in the above-mentioned transport chamber 2704. Of course, the exhaust method of the transport chamber 2704 may be the same as that of the film forming chamber 2706b (exhaust method of the turbo molecular pump and the vacuum pump).

The back pressure (total pressure) of the transport chamber 2704, the substrate heating chamber 2705, and the film forming chamber 2706b described above, and the partial pressure of each gas molecule (atom) are preferably as follows. In particular, since impurities may be mixed in the formed film, the back pressure of the film forming chamber 2706b,
In addition, it is necessary to pay attention to the partial pressure of each gas molecule (atom).

The back pressure (total pressure) of each of the above-mentioned chambers is 1 × 10 ^-4 Pa or less, preferably 3 × 10 ^-5 Pa.
Below, it is more preferably 1 × 10 ^-5 Pa or less. Mass-to-charge ratio of each chamber described above (m /
The partial pressure of the gas molecule (atom) in which z) is 18 is 3 × 10 ^-5 Pa or less, preferably 1 × 1.
It is ^0-5 Pa or less, more preferably 3 × 10 ^-6 Pa or less. Further, the partial pressure of the gas molecule (atom) having an m / z of 28 in each of the above-mentioned chambers is 3 × 10 ^-5 Pa or less, preferably 1 ×.
It is ^10-5 Pa or less, more preferably 3 × ^10-6 Pa or less. Further, the partial pressure of the gas molecule (atom) having an m / z of 44 in each of the above-mentioned chambers is 3 × 10 ^-5 Pa or less, preferably 1
It is × ^10-5 Pa or less, more preferably 3 × ^10-6 Pa or less.

The total pressure and partial pressure in the vacuum chamber can be measured using a mass spectrometer. For example, ULVAC, Inc. quadrupole mass spectrometer (also called Q-mass) Qu
Lee CGM-051 may be used.

Further, it is desirable that the transport chamber 2704, the substrate heating chamber 2705, and the film forming chamber 2706b described above have a configuration in which there are few external leaks or internal leaks.

For example, the leak rates of the transport chamber 2704, the substrate heating chamber 2705, and the film forming chamber 2706b described above are 3 × 10 ^-6 Pa · m ³ / s or less, preferably 1 × 10 ^-6 Pa · m ³ /.
It is less than or equal to s. In addition, the leak rate of gas molecules (atoms) with m / z of 18 is 1 × 10 ⁻ .
⁷ Pa · m ³ / s or less, preferably 3 × 10 ^-8 Pa · m ³ / s or less. Also, m /
The leak rate of the gas molecule (atom) in which z is 28 is 1 × 10 ^-5 Pa · m ³ / s or less, preferably 1 × 10 ^-6 Pa · m ³ / s or less. Further, gas molecules having an m / z of 44 (
The leak rate of (atom) is 3 × 10 ^-6 Pa · m ³ / s or less, preferably 1 × 10 ^-6 Pa.
-M ³ / s or less.

The leak rate may be derived from the total pressure and partial pressure measured using the above-mentioned mass spectrometer.

The leak rate depends on external and internal leaks. An external leak is a gas flowing in from outside the vacuum system due to a minute hole or a defective seal. The internal leak is caused by a leak from a partition such as a valve in the vacuum system or a gas released from an internal member. In order to keep the leak rate below the above value, it is necessary to take measures from both external and internal leaks.

For example, the opening / closing portion of the film forming chamber 2706b may be sealed with a metal gasket. As the metal gasket, it is preferable to use a metal coated with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets have higher adhesion than O-rings and can reduce external leaks. Further, by using the passivation of the metal coated with iron fluoride, aluminum oxide, chromium oxide or the like, the released gas containing impurities released from the metal gasket can be suppressed and the internal leak can be reduced.

Further, as a member constituting the film forming apparatus 2700, aluminum, chromium, titanium, zirconium, nickel or vanadium containing impurities and having a small amount of emitted gas is used. Further, the above-mentioned member may be used by coating it with an alloy containing iron, chromium, nickel and the like. Alloys containing iron, chromium, nickel, etc. are rigid, heat resistant and suitable for processing. Here, if the surface unevenness of the member is reduced by polishing or the like in order to reduce the surface area, the released gas can be reduced.

Alternatively, the member of the film forming apparatus 2700 described above may be coated with iron fluoride, aluminum oxide, chromium oxide or the like.

The member of the film forming apparatus 2700 is preferably made of only metal as much as possible. For example, even when a viewing window made of quartz or the like is installed, the surface of the film forming apparatus 2700 is made of iron fluoride in order to suppress the emitted gas.
It is advisable to coat it thinly with aluminum oxide, chromium oxide, etc.

Since the adsorbent existing in the film forming chamber is adsorbed on the inner wall or the like, it does not affect the pressure in the film forming chamber, but it causes outgassing when the film forming chamber is exhausted. Therefore, although there is no correlation between the leak rate and the exhaust speed, it is important to use a pump with a high exhaust capacity to remove the adsorbent existing in the film forming chamber as much as possible and exhaust it in advance. The film forming chamber may be baked in order to promote the detachment of the adsorbent. By baking, the desorption rate of the adsorbent can be increased by about 10 times. Baking may be performed at 100 ° C. or higher and 450 ° C. or lower. At this time, if the adsorbent is removed while the inert gas is introduced into the film forming chamber, the desorption rate of water or the like, which is difficult to desorb only by exhausting the gas, can be further increased. By heating the introduced inert gas to the same temperature as the baking temperature, the desorption rate of the adsorbent can be further increased. Here, it is preferable to use a rare gas as the inert gas. Further, depending on the type of film to be formed, oxygen or the like may be used instead of the inert gas. For example, when forming an oxide, it may be preferable to use oxygen as a main component. It is preferable that baking is performed using a lamp.

Alternatively, it is preferable to increase the pressure in the film forming chamber by introducing an inert gas such as a heated rare gas or oxygen, and to exhaust the film forming chamber again after a lapse of a certain period of time. By introducing the heated gas, the adsorbent in the film forming chamber can be desorbed, and the impurities existing in the film forming chamber can be reduced. It should be noted that this treatment is performed 2 times or more and 30 times or less, preferably 5 times or more and 15 times.
It is effective to repeat it within the range of less than once. Specifically, by introducing an inert gas or oxygen having a temperature of 40 ° C. or higher and 400 ° C. or lower, preferably 50 ° C. or higher and 200 ° C. or lower, the pressure in the film forming chamber is 0.1 Pa or higher and 10 kPa or lower, preferably 10 kPa or lower. The pressure may be 1 Pa or more and 1 kPa or less, more preferably 5 Pa or more and 100 Pa or less, and the pressure holding period may be 1 minute or more and 300 minutes or less, preferably 5 minutes or more and 120 minutes or less. After that, the film formation chamber was opened for 5 minutes or more and 300.
Exhaust for a period of minutes or less, preferably 10 minutes or more and 120 minutes or less.

Further, the desorption rate of the adsorbent can be further increased by forming a dummy film. Dummy film formation is a film formation on a dummy substrate by a sputtering method or the like, so that a film is deposited on the dummy substrate and the film formation chamber wall, and impurities in the film formation chamber and adsorbents on the film formation chamber wall are filmed. It means to confine it inside. The dummy substrate is preferably a substrate having a small amount of emitted gas. By forming a dummy film, it is possible to reduce the concentration of impurities in the film to be formed later. The dummy film formation may be performed at the same time as baking.

Next, the transport chamber 2704 and the load lock chamber 2703a shown in FIG. 58 (B), and FIG. 5
The details of the atmospheric side substrate transport chamber 2702 and the atmospheric side substrate supply chamber 2701 shown in 8 (C) will be described below. Note that FIG. 58C shows a cross section of the atmospheric side substrate transport chamber 2702 and the atmospheric side substrate supply chamber 2701.

For the transport chamber 2704 shown in FIG. 58 (B), the description of the transport chamber 2704 shown in FIG. 58 (A) is referred to.

The load lock chamber 2703a has a substrate transfer stage 2752. The load lock chamber 2703a raises the pressure from the decompressed state to the atmosphere, and when the pressure in the load lock chamber 2703a reaches atmospheric pressure, the transfer robot 27 provided in the atmospheric side substrate transfer chamber 2702
The board is received from 63 to the board delivery stage 2752. After that, the road lock room 27
After the 03a is evacuated to a reduced pressure state, the transfer robot 2763 provided in the transfer chamber 2704 receives the substrate from the substrate transfer stage 2752.

Further, the load lock chamber 2703a is connected to the vacuum pump 2770 and the cryopump 2771 via a valve. Vacuum pump 2770, and cryopump 27
Since the exhaust system connection method of 71 can be connected by referring to the connection method of the transport chamber 2704, the description thereof is omitted here. The unload lock chamber 2703b shown in FIG. 57 can have the same configuration as the load lock chamber 2703a.

The atmospheric board transfer chamber 2702 has a transfer robot 2763. Transfer robot 2763
As a result, the substrate can be transferred between the cassette port 2761 and the load lock chamber 2703a. Further, a HEPA filter (High Efficiency Particulate A) is placed above the atmospheric side substrate transport chamber 2702 and the atmospheric side substrate supply chamber 2701.
A mechanism for purifying dust or particles such as ir Filter) may be provided.

The atmosphere side substrate supply chamber 2701 has a plurality of cassette ports 2761. The cassette port 2761 can accommodate a plurality of substrates.

The target has a surface temperature of 100 ° C. or lower, preferably 50 ° C. or lower, more preferably about room temperature (typically 25 ° C.). Sputtering equipment for large area substrates often uses large area targets. However, it is difficult to seamlessly produce a target having a size corresponding to a large area. In reality, multiple targets are arranged so that there are as few gaps as possible to form a large shape, but a slight gap is inevitably created. As the surface temperature of the target rises from such a small gap, zinc and the like may volatilize and the gap may gradually widen. If the gap is widened, the backing plate and the metal of the bonding material used for joining the backing plate and the target may be sputtered, which causes an increase in the impurity concentration. Therefore, it is preferable that the target is sufficiently cooled.

Specifically, as a backing plate, a metal having high conductivity and high heat dissipation (specifically, as a backing plate
Specifically, copper) is used. Further, by forming a water channel in the backing plate and flowing a sufficient amount of cooling water through the water channel, the target can be efficiently cooled.

When the target contains zinc, plasma damage is reduced by forming a film in an oxygen gas atmosphere, and an oxide in which zinc is less likely to volatilize can be obtained.

By using the film forming apparatus described above, the hydrogen concentration can be determined by secondary ion mass spectrometry (SIMS: S).
(econdary Ion Mass Spectrometry), 2 × 10
²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ³ or less, still more preferably 5 × 10 ¹⁸ atom.
An oxide semiconductor having an s / cm ³ or less can be formed.

Further, the nitrogen concentration in SIMS is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 1 × 10 ¹⁹ atoms / cm ³ or less, and more preferably 5 × 10 ¹⁸ atoms / c.
It is possible to form an oxide semiconductor having m ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less.

Further, the carbon concentration in SIMS is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, and more preferably 1 × 10 ¹⁸ atoms / c.
It is possible to form an oxide semiconductor having m ³ or less, more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

In addition, temperature desorption gas spectroscopy (TDS: Thermal Desorption Gas spectroscopy) (TDS: Thermal Desorption Gas Spectroscopy)
Gas molecules (atoms) whose m / z is 2 (hydrogen molecules, etc.) by ctroscopy) analysis,
Gas molecules (atoms) with m / z of 18, gas molecules (atoms) with m / z of 28 and m /
It is possible to form an oxide semiconductor in which the emission amount of gas molecules (atoms) having z of 44 is 1 × 10 ¹⁹ / cm ³ or less, preferably 1 × 10 ¹⁸ / cm ³ or less, respectively.

By using the above film forming apparatus, it is possible to suppress the mixing of impurities into the oxide semiconductor. Further, by forming a film in contact with the oxide semiconductor by using the above-mentioned film forming apparatus, it is possible to prevent impurities from being mixed into the oxide semiconductor from the film in contact with the oxide semiconductor.

This embodiment can be implemented in combination with the configurations described in other embodiments as appropriate.

100 Conductor 100a Conductor 100d Structure 101 Substrate 102 Insulator 102a Insulator 103 Insulator 103a Insulator 103b Insulator 103c Insulator 104 Oxide layer 104a Oxide layer 104b Oxide layer 104c Oxide layer 104d Oxide layer 104e Oxide Layer 104f Oxide layer 105 Insulator 105a Electrode 105b Electrode 105d Insulation 106 Conductor 106d Conductor 107 Insulation 107d Insulation 108 Insulation 108b Insulation 108d Insulation 109a Conductor 109b Conductor 109c Conductor 109d Conductor 109e Conductive Body 109j Conductor 109k Conductor 109l Conductor 109m Conductor 109n Conductor 109o Conductor 110 Insulation 110b Insulation 110d Insulation 111 Insulation 111a Insulation 112 Insulation 112d Contact plug 113a Contact plug 113b Contact plug 113c Contact plug 113d Contact plug 114 Conductor 114a Conductor 114b Conductor 114c Conductor 117 Conductor 117d Conductor 118 Insulator 119 Conductor 126 Conductive layer 131 Metal element 135 Region 141 Capacitant element 142 Capacitive element 145 Mixed layer 150 Transistor 160 Transistor 220 Well 221 p-type semiconductor 223 n-type semiconductor 224 opening 225 opening 251 wiring 252 wiring 253 wiring 254 wiring 255 wiring 256 node 257 capacitive element 260 circuit 270 circuit 273 electrode 280 circuit 281 conductor 281a conductor 281b transistor 282 conductor 282a conductor 283 284 Low-concentration p-type impurity region 285 High-concentration p-type impurity region 286 Insulator 287 Conductor 288 Structure 289 Transistor 290 Circuit 291 Transistor 300 Structure 300d Structure 301 Mask 302 Mask 303 Mask 306 Opening 307 Opening 308 Opening 311 Length 312 Length 313 Length 314 Length 315 End 316 End 382 Ec
383a Ec
383b Ec
383c Ec
386 Ec
390 Trap Level 400 Semiconductor Device 401 Board 402 Insulator 403 Insulator 404 Insulator 405 Insulator 406 Contact Plug 406a Contact Plug 406b Contact Plug 406c Contact Plug 407 Insulator 407a Insulator 410 Insulator 410 Insulator 413 Insulator 413 Capacitive Element 413a Conductive Body 413b Conductor 413c Conductor 413d Conductor 414 Insulator Separation Layer 415 Insulator 420 Semiconductor Device 421 Conductor 422 Conductor 427 Conductor 429 Conductor 430 Semiconductor Device 442 Insulator 477 Insulator 487 Insulator 487 Wiring 487a Conductor 487b Conductor 488 Conductor Body 489 Contact Plug 550 Interposer 551 Chip 552 Terminal 552 Mold Resin 560 Panel 561 Printed Wiring Board 562 Package 563 FPC
564 Battery 585 Insulator 600 Image pickup device 601 Photoelectric conversion element 602 Transistor 603 Transistor 604 Transistor 605 Transistor 606 Capacitive element 607 Node 608 Wiring 609 Wiring 610 Pixel drive circuit 611 Wiring 621 Pixel part 622 Pixel 622B Pixel 622G Pixel 622R Pixel 623 624B Filter 624G Filter 624R Filter 625 Lens 626 Wiring group 660 Optical 681 Photoelectric conversion layer 682 Transistor conductive layer 686 Conductor 686a Conductor 686b Conductor 701 Circuit 702 Circuit 703 Switch 704 Switch 706 Logic element 707 Capacitant element 708 Capacitive element 709 Transistor 710 Transistor 713 Transistor 714 Transistor 720 Circuit 730 Storage element 800 RF tag 801 Communicator 802 Antenna 803 Wireless signal 804 Antenna 805 Rectification circuit 806 Constant voltage circuit 807 Demodulation circuit 808 Modulation circuit 809 Logic circuit 810 Storage circuit 81 ROM
1189 ROM interface 1190 board 1191 ALU
1192 ALU controller 1193 Instruction decoder 1194 Interrupt controller 1195 Timing controller 1196 Register 1197 Register controller 1198 Bus interface 1199 ROM
1281 Transistor 1283 Channel formation region 1284 Low concentration n-type impurity region 1285 High-concentration n-type impurity region 2700 Film deposition equipment 2701 Atmospheric side substrate supply room 2702 Atmospheric side substrate transfer chamber 2703a Load lock chamber 2703b Unload lock chamber 2704 Transport chamber 2705 Substrate Heating chamber 2706a Formation chamber 2706b Formation chamber 2706c Formation chamber 2751 Cryotrap 275 Stage 2761 Cassette port 2762 Alignment port 2763 Conveying robot 2763 Gate valve 2765 Heating stage 2766 Target 2766a Target 2766b Target 2767 Target shield 2767b Target shield 2768 Board holder 2769 Board 2770 Vacuum pump 2771 Cryo pump 2772 Turbo molecular pump 2780 Mass flow controller 2781 Purifier 2782 Gas heating mechanism 2784 Variable member 2790a Magnet unit 2790b Magnet unit 2791 Power supply 2900 Portable game machine 2901 Housing 2902 Housing 2903 Display 2904 Display 2905 Microphone 2906 Speaker 2907 Operation key 2908 Stylus 2910 Information terminal 2911 Housing 2912 Display 2913 Camera 2914 Speaker 2915 Button 2916 External connection 2917 Microphone 2920 Notebook personal computer 2921 Housing 2922 Display 2923 Keyboard 2924 Pointing device 2940 Video camera 2941 Housing 2942 Housing 2943 Display 2944 Operation key 2945 Lens 2946 Connection 2950 Information terminal 2951 Housing 2952 Display 2960 Information terminal 2961 Housing 2962 Display 2963 Band 2964 Buckle 2965 Operation button 2966 Input / output terminal 2967 Icon 2970 Electric refrigerator 2971 Housing 2792 Refrigerating room door 2973 Freezer room door 2980 Automobile 2891 Body 2982 Wheels 2983 Dashboard 2984 Light 3100 Display device 3125 Light emitting element 3130 Pixel 3131 Display area 3132 Circuit 3133 Circuit 3135 Scan line 3136 Signal line 3137 Pixel Circuit 3152 Circuit 3153 Circuit 3232 Transistor 3233 Capacitive element 3431 Transistor 3432 Liquid crystal element 3434 Transistor 3435 Node 3436 Node 3437 Node 4001 Substrate 4002 Pixel part 4003 Signal line drive circuit 4004 Scanning line drive circuit 4005 Sealing material 4006 Substrate 4008 Liquid crystal layer 4010 Transistor 4011 Transistor 4013 Liquid crystal element 4014 Wiring 4015 Electrode 4017 Electrode 4018 FPC
4018b FPC
4019 Anisotropic conductive layer 4020 Capacitive element 4021 Electrode 4030 Electrode layer 4031 Electrode layer 4032 Insulation layer 4033 Insulation layer 4035 Spacer 4102 Insulation layer 4103 Insulation layer 4110 Insulation layer 4111 Insulation layer 4112 Insulation layer 4510 Partition wall 4511 Light emitting layer 4513 Light emitting element 4514 Material 5100 Pellet 5120 Board 5161 Area 6000 Display module 6001 Top cover 6002 Bottom cover 6003 FPC
6004 Touch sensor 6005 FPC
6006 Display panel 6007 Backlight unit 6008 Light source 6009 Frame 6010 Printed circuit board 6011 Battery

Claims (3)

It has a first transistor and a second transistor provided below the first transistor.
The first transistor has an oxide semiconductor in the channel forming region and has an oxide semiconductor.
The second transistor has silicon in the channel forming region and has silicon.
The first transistor has a first gate electrode below the oxide semiconductor and a second gate electrode above the oxide semiconductor.
The second gate electrode has a region lower than the lower surface of the channel forming region of the oxide semiconductor and does not overlap with the oxide semiconductor in the channel width direction.
A semiconductor device in which the length of the region of the first gate electrode overlapping with the oxide semiconductor in the channel length direction is longer than the length of the region of the second gate electrode overlapping with the oxide semiconductor. Has a first transistor,
The first transistor has an oxide semiconductor in the channel forming region and has an oxide semiconductor.
The first transistor has a first gate electrode below the oxide semiconductor and a second gate electrode above the oxide semiconductor.
The second gate electrode has a region lower than the lower surface of the channel forming region of the oxide semiconductor and does not overlap with the oxide semiconductor in the channel width direction.
A semiconductor device in which the length of the region of the first gate electrode overlapping with the oxide semiconductor in the channel length direction is longer than the length of the region of the second gate electrode overlapping with the oxide semiconductor. In claim 1 or 2,
The oxide semiconductor is a semiconductor device having In, Gz, and Zn.

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