JP2020115556A - Semiconductor device - Google Patents

Abstract

To provide a transistor having an excellent electric characteristic, a transistor having a stable electric characteristic, and a semiconductor device having a high integration degree.SOLUTION: A semiconductor device comprises: a substrate 101; an insulator 102 on the substrate; a transistor 100 on the insulator 102; an insulator 110 covering the transistor; and an insulator 111 on the insulator 110. The transistor includes: an oxide layer 104 on an insulator 103; an insulator 105 on the oxide layer 104; a conductor 106 on the insulator 105; an insulator 108 formed for a side wall of the conductor 106; and a conductor 109a and a conductor 109b contacting a side surface of the oxide layer 104 and a side surface of the insulator 108. The insulator 108 is adjacent to a side surface of the conductor 106. The conductor 106 functions as a first gate electrode of the transistor, the conductor 109a and the conductor 109b function as a source electrode or a drain electrode of the transistor, and the insulator 105 functions as a gate insulator of the transistor.SELECTED DRAWING: Figure 1

Description

One embodiment of the present invention relates to a transistor, a semiconductor device, and a manufacturing method thereof.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).

Note that in this specification and the like, a semiconductor device generally means a device that can function by utilizing semiconductor characteristics. A display device (a liquid crystal display device, a light-emitting display device, or the like), a lighting device, an electro-optical device, a power storage device, a storage device, a semiconductor circuit, an imaging device, an electronic device, or the like may include a semiconductor device.

In recent years, a transistor including an oxide semiconductor has attracted attention. Since the oxide semiconductor film can be formed by a sputtering method or the like, it can be used for a transistor included in a large-sized display device. In addition, since a transistor including an oxide semiconductor film has high field-effect mobility, a highly functional display device in which a driver circuit is formed can be realized. Further, since it is possible to improve and use a part of production equipment of a transistor using an amorphous silicon film, there is also an advantage that equipment investment can be suppressed.

It is known that a transistor including an oxide semiconductor has an extremely small leak current in a non-conducting state. For example, a low power consumption CPU or the like is disclosed in which the characteristics of a transistor including an oxide semiconductor, which has extremely low leakage current, are applied (see Patent Document 1).

JP 2012-257187 A

Another object is to provide a minute transistor. Another object is to provide a transistor having a small parasitic capacitance. Another object is to provide a transistor with high frequency characteristics.
Another object is to provide a transistor with favorable electric characteristics. Another object is to provide a transistor with stable electric characteristics. Another object is to provide a transistor with low power consumption. Another object is to provide a highly reliable transistor. Another object is to provide a new transistor. Another object is to provide a semiconductor device including at least one of these transistors.

Note that the description of these problems does not prevent the existence of other problems. Note that one embodiment of the present invention does not need to solve all of these problems. The problems other than these are obvious from the description of the specification, drawings, claims, etc.
Problems other than these can be extracted from the drawings, claims, and the like.

One embodiment of the present invention is a first insulator, an oxide semiconductor over the first insulator, a second insulator over the oxide semiconductor, and a first conductor over the second insulator. A third insulator adjacent to the side surface of the first conductor, a second conductor and a third conductor in contact with the side surface of the oxide semiconductor and the side surface of the third insulator, A fourth insulator in contact with the side surface of the second conductor and the side surface of the third conductor, and a fifth insulator in contact with the upper surfaces of the fourth insulator, the second conductor and the third conductor. , A semiconductor device having. Here, the upper surface of the fourth insulator has a region to be substantially flattened, and the heights of the upper ends of the second conductor and the third conductor are approximately equal to the height of the upper end of the fourth insulator. In agreement, the fourth insulator has excess oxygen, and the oxide semiconductor has a first region overlapping with the first conductor and a second region having lower resistance than the first region. The first insulator and the fifth insulator have lower oxygen permeability than the fourth insulator.

Here, in the above structure, the third insulator may be referred to as a sidewall insulating layer, a sidewall insulating film, or a sidewall. In the above structure, the semiconductor device preferably has a transistor, the first conductor serves as a gate electrode of the transistor, and the second conductor and the third conductor serve as a source electrode or a drain of the transistor. Second electrode
The insulator of (1) preferably functions as a gate insulator of the transistor (sometimes referred to as a gate insulating film or a gate insulating layer).

Further, in the above structure, the fourth insulator has an opening reaching the first insulator, the fifth insulator is arranged in the opening, and the opening has an oxide semiconductor and a second insulator. Are preferably arranged so as to surround four sides of the insulator and the second conductor. Further, the fifth insulator preferably has lower hydrogen permeability than the fourth insulator.

In the above structure, at least one of the first insulator and the fifth insulator preferably contains oxygen and aluminum. In the above structure, the second
The region of may have a region overlapping with the third insulator. Further, in the above structure, the second region may contain at least one of tungsten, aluminum, titanium, magnesium, vanadium, antimony, arsenic, and sulfur.

In the above structure, the semiconductor device preferably includes a sixth insulator, the sixth insulator has a convex portion, and the oxide semiconductor is preferably formed in contact with the convex portion. Here, the oxide semiconductor preferably has a first film, a second film in contact with the top surface of the first film, and a third film in contact with the top surface of the second film. Here, the electron affinity of the second film is equal to that of the first film and the third film.
Is larger than the electron affinity of the first film, the first conductor has a region facing the side surface of the second film through the second insulator, and the height of the convex portion and the thickness of the first film. Is preferably larger than the sum of the thickness of the third film and the thickness of the second insulator. The second conductor and the third conductor are
It is preferable to contact either the upper surface of the second film or the upper surface of the third film.

Further, in the above structure, the fourth insulator may have a third region which is mixed with the fifth insulator. Also, the third region may have excess oxygen.

Alternatively, according to one embodiment of the present invention, a first insulator is formed over a substrate, an oxide semiconductor is formed over the first insulator, and then a second insulator is formed over the oxide semiconductor. Forming, then forming a first conductor on the second insulator, and then adding the first element to the oxide semiconductor film,
After that, a third insulator is formed over the first conductor and the oxide semiconductor, and then the third insulator is etched to form a fourth insulator on a side surface of the first electrode. And then
A second conductor is formed on the first conductor and the fourth insulator, then a fifth insulator is formed on the second conductor, and then a chemical mechanical polishing method is used. By removing a region including both the first region of the second conductor and the second region of the fifth insulator while planarizing the surface of the fifth insulator by the third conductivity, A body, a fourth conductor, and a sixth insulator are formed to form a first transistor. After that, a seventh insulator is formed over the sixth insulator, which is a method for manufacturing a semiconductor device. Here, the first region and the second region overlap with the first conductor, and the height of the upper ends of the third conductor and the fourth conductor is approximately the same as the height of the upper end of the sixth insulator. In agreement, the first conductor functions as the gate electrode of the first transistor, the third conductor and the fourth conductor function as the source electrode or drain electrode of the first transistor, and And the seventh insulator have lower hydrogen permeability than the sixth insulator, and at least one of the first insulator and the seventh insulator has aluminum oxide or silicon nitride.

Here, in the above structure, the fourth insulator may be referred to as a sidewall insulating layer or a sidewall insulating film. Further, in the above structure, the first element may contain at least one of tungsten, aluminum, titanium, magnesium, vanadium, antimony, arsenic, and sulfur.

Alternatively, according to one embodiment of the present invention, a first insulator is formed over a substrate, an oxide semiconductor is formed over the first insulator, and then a second insulator is formed over the oxide semiconductor. Forming, and then forming a film of the first conductor on the second insulator, forming a film of the third insulator on the first conductor, and then forming one film of the third insulator. A fourth insulator is formed by removing the portion, and thereafter,
A second conductor is formed by removing part of the first conductor, then the first element is added to the oxide semiconductor, and then the fifth insulator is formed over the fourth insulator. A film is formed on the body, and then a part of the fifth insulator is removed to form a sixth insulator on a sidewall of the first conductor, and then a third insulator is formed on the sixth insulator. The conductor is formed into a film, and then the seventh insulator is formed onto the third conductor, and the surface of the seventh insulator is planarized by a chemical mechanical polishing method to remove the third conductor. Forming a fourth conductor, a fifth conductor, and an eighth insulator by removing a region including both the first region and the second region of the seventh insulator, This is a method for manufacturing a semiconductor device, in which a first transistor is formed and then a ninth insulator is formed over a sixth insulator, a fourth conductor, and a fifth conductor. Here, the first region and the second region overlap with the second conductor, and the first insulator and the ninth insulator have lower hydrogen permeability than the eighth insulator, At least one of the insulator and the ninth insulator preferably contains oxygen and aluminum.

Here, in the above structure, the sixth insulator may be referred to as a sidewall insulating layer or a sidewall insulating film. Further, in the above structure, the first element may contain at least one of tungsten, aluminum, titanium, magnesium, vanadium, antimony, arsenic, and sulfur.

A fine transistor can be provided. Alternatively, a transistor with small parasitic capacitance can be provided. Alternatively, a transistor with high frequency characteristics can be provided. A transistor with favorable electric characteristics can be provided. Alternatively, a transistor with stable electric characteristics can be provided. Alternatively, a transistor with low power consumption can be provided. Alternatively, a highly reliable transistor can be provided. Alternatively, a novel transistor can be provided. Alternatively, a semiconductor device including at least one of these transistors can be provided.

Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention need not have all of these effects. It should be noted that the effects other than these are apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other effects from the description of the specification, drawings, claims, etc. Is.

17A and 17B are a top view and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. 3A and 3B are a top view and a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. 3A and 3B are cross-sectional views illustrating a semiconductor device of one embodiment of the present invention. 3A and 3B are cross-sectional views illustrating a semiconductor device of one embodiment of the present invention. FIG. 6 is a top view illustrating a semiconductor device according to one embodiment of the present invention. 3A and 3B are cross-sectional views illustrating a semiconductor device of one embodiment of the present invention. 6A to 6D are diagrams illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. 6A to 6D are diagrams illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. 6A to 6D are diagrams illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. 6A to 6D are diagrams illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. 6A to 6D are diagrams illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. 6A to 6D are diagrams illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. 6A to 6D are diagrams illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. 6A to 6D are diagrams illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. 6A to 6D are diagrams illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. 6A to 6D are diagrams illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. 6A to 6D are diagrams illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. 6A to 6D are diagrams illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. 6A to 6D are diagrams illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. 17A and 17B are a top view and a cross-sectional view illustrating a semiconductor device of one embodiment of the present invention. The figure explaining an energy band structure. 3A and 3B are cross-sectional views illustrating a semiconductor device of one embodiment of the present invention. 3A and 3B are cross-sectional views illustrating a semiconductor device of one embodiment of the present invention. 3A and 3B are cross-sectional views illustrating a semiconductor device of one embodiment of the present invention. 3A and 3B are cross-sectional views illustrating a semiconductor device of one embodiment of the present invention. 6A to 6D are diagrams illustrating an example of a method for manufacturing a semiconductor device according to one embodiment of the present invention. 9A and 9B are Cs-corrected high-resolution TEM images in a cross section of a CAAC-OS and cross-sectional schematic views of the CAAC-OS. Cs-corrected high-resolution TEM image on the plane of the CAAC-OS. 6A and 6B each illustrate a structural analysis of a CAAC-OS and a single crystal oxide semiconductor by XRD. The figure which shows the electron diffraction pattern of CAAC-OS. FIG. 10 is a diagram showing a change in a crystal part of an In—Ga—Zn oxide due to electron irradiation. 3A and 3B are cross-sectional views illustrating a semiconductor device of one embodiment of the present invention. 3A and 3B are cross-sectional views illustrating a semiconductor device of one embodiment of the present invention. 3A and 3B are cross-sectional views illustrating a semiconductor device of one embodiment of the present invention. 3A and 3B are cross-sectional views illustrating a semiconductor device of one embodiment of the present invention. FIG. 9 is a circuit diagram of a semiconductor device according to one embodiment of the present invention. FIG. 9 is a circuit diagram of a semiconductor device according to one embodiment of the present invention. FIG. 3 is a block diagram showing a configuration example of a CPU. FIG. 6 is a circuit diagram illustrating an example of a memory element. FIG. 6 illustrates an example of an imaging device. FIG. 6 illustrates an example of an imaging device. FIG. 6 illustrates an example of an imaging device. FIG. 6 illustrates a structural example of a pixel. FIG. 6 illustrates a structural example of a pixel. The circuit diagram showing an example of an imaging device. Sectional drawing which shows the structural example of an imaging device. Sectional drawing which shows the structural example of an imaging device. 3A and 3B are a block diagram and a circuit diagram illustrating an example of a display device. FIG. 13 is a block diagram illustrating an example of a display device. FIG. 6 illustrates an example of a display device. FIG. 6 illustrates an example of a display device. FIG. 6 illustrates an example of a display module. FIG. 3 is a block diagram illustrating an example of an RF tag. 6A and 6B are diagrams illustrating a usage example of an RF tag. FIG. 3 is a perspective view showing a cross-sectional structure of a package using a lead frame type interposer. 7A to 7C each illustrate an example of an electronic device. The top view which shows an example of a film-forming apparatus. Sectional drawing which shows an example of a film-forming apparatus. 3A and 3B are cross-sectional views illustrating a semiconductor device of one embodiment of the present invention. 3A and 3B are cross-sectional views illustrating a semiconductor device of one embodiment of the present invention.

Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously modified without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structure of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and repeated description thereof may be omitted.

Further, the position, size, range, and the like of each configuration illustrated in the drawings and the like may not represent the actual position, size, range, or the like in order to facilitate understanding of the present invention. Therefore, the disclosed invention is not necessarily limited to the position, size, range, or the like disclosed in the drawings and the like.
For example, in an actual manufacturing process, a layer, a resist mask, or the like may be unintentionally diminished by a process such as etching, but may be omitted for easy understanding.

In addition, in the drawings, in order to facilitate understanding of the invention, description of some components may be omitted. In addition, description of some hidden lines may be omitted.

In this specification and the like, ordinal numbers such as “first” and “second” are added to avoid confusion among constituent elements and do not indicate any order or order such as a process order or a stacking order. Further, even in the present specification and the like, even if a term does not have an ordinal number, the ordinal number may be added in the claims in order to avoid confusion of constituent elements. Further, even in this specification and the like, even if a term has an ordinal number, a different ordinal number may be attached in the claims. Further, even if a term has an ordinal number in this specification and the like, the ordinal number may be omitted in the claims and the like.

Further, in this specification and the like, the terms “electrode” and “wiring” do not functionally limit these components. For example, "electrode" may be used as part of "wiring" and vice versa. Furthermore, the terms "electrode" and "wiring" refer to multiple "electrodes" and "wiring".
It also includes the case where the "wiring" is integrally formed.

Note that the term such as “over” or “below” in this specification and the like does not necessarily mean that a component is placed immediately above or below the component and is in direct contact with the component. For example, in the expression “electrode B on insulator A”, it is not necessary that the electrode B is formed directly on the insulator A,
Those including other components between the insulator A and the electrode B are not excluded.

Also, the functions of the source and drain are when using transistors of different polarities,
It is difficult to determine which is the source or the drain, because they switch each other depending on the operating conditions such as when the direction of the current changes in the circuit operation. Therefore, in this specification, the terms “source” and “drain” can be interchanged.

Further, in this specification and the like, when it is explicitly described that X and Y are connected, a case where X and Y are electrically connected and a case where X and Y function The case where they are connected to each other and the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relation, for example, the connection relation shown in the drawing or the text, and other than the connection relation shown in the drawing or the text is also described in the drawing or the text.

In addition, in this specification and the like, the term “electrically connected” includes the case of being connected through “something having an electrical action”. Here, the “object having some kind of electrical action” is not particularly limited as long as it can transfer an electric signal between the connection targets. Therefore, even when expressed as "electrically connected", in an actual circuit,
In some cases, there is no physical connection and only the wiring extends.

Note that the channel length is, for example, in a top view of a transistor, a region where a semiconductor (or a portion of a semiconductor in which current flows) and a gate electrode overlap with each other in a top view of a transistor, or a region where a channel is formed. In (also referred to as “channel formation region”), the distance between the source (source region or source electrode) and the drain (drain region or drain electrode). Note that in one transistor, the channel length does not necessarily have the same value in all regions. That is, the channel length of one transistor may not be set to one value. Therefore, in this specification, the channel length is any one value, the maximum value, the minimum value, or the average value in the region where the channel is formed.

The channel width is, for example, a region where a semiconductor (or a portion of a semiconductor in which a current flows when the transistor is in an on state) and a gate electrode overlap with each other, or a source and a drain face each other in a region where a channel is formed. It means the length of the part. Note that in one transistor, the channel width does not necessarily have the same value in all regions. That is,
The channel width of one transistor may not be set to one value in some cases. Therefore, in this specification, the channel width is any one of the values, the maximum value, the minimum value, or the average value in the region where the channel is formed.

Note that depending on the structure of the transistor, a channel width in a region where a channel is actually formed (also referred to as an “effective channel width”) and a channel width shown in a top view of the transistor (“apparent channel width”). Also referred to as), and may be different. For example, when the gate electrode covers the side surface of the semiconductor film, the effective channel width becomes larger than the apparent channel width, and the effect thereof may not be negligible. For example, in a transistor having a fine gate electrode covering the side surface of the semiconductor, the ratio of the channel region formed on the side surface of the semiconductor may be higher than the ratio of the channel region formed on the upper surface of the semiconductor. In that case, the effective channel width becomes larger than the apparent channel width.

In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the semiconductor shape is known. Therefore, it is difficult to measure the effective channel width accurately when the shape of the semiconductor is not known accurately.

Therefore, in this specification, the apparent channel width is referred to as “enclosed channel width (SCW:S
sometimes referred to as "rounded Channel Width)". Further, in this specification, when simply described as a channel width, it may indicate an enclosed channel width or an apparent channel width. Alternatively, in this specification, when simply described as channel width,
It may refer to the effective channel width. The channel length, the channel width, the effective channel width, the apparent channel width, the enclosed channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.

Note that when the field-effect mobility of the transistor, the current value per channel width, or the like is calculated and obtained, the enclosed channel width may be used in some cases. In that case, the value may be different from the value calculated by using the effective channel width.

Note that the impurities of the semiconductor refer to, for example, components other than the main constituents of the semiconductor. For example, an element whose concentration is less than 0.1 atomic% can be said to be an impurity. Due to the inclusion of impurities, for example,
In some cases, the DOS (Density of State) of the semiconductor may be increased, the carrier mobility may be decreased, and the crystallinity may be decreased. When the semiconductor is an oxide semiconductor, the impurities that change the characteristics of the semiconductor include, for example, a Group 1 element and a second element.
There are group elements, group 13 elements, group 14 elements, group 15 elements, and transition metals other than the main components of oxide semiconductors. In particular, for example, hydrogen (also included in water), lithium, sodium, Examples include silicon, boron, phosphorus, carbon, and nitrogen. In the case of an oxide semiconductor, oxygen vacancies may be formed by the mixture of impurities such as hydrogen. When the semiconductor is silicon, examples of impurities that change the characteristics of the semiconductor include a Group 1 element other than oxygen and hydrogen, a Group 2 element, a Group 13 element, and a Group 15 element.

Further, in this specification, “parallel” means a state in which two straight lines are arranged at an angle of −10° or more and 10° or less. Therefore, a case of -5° or more and 5° or less is also included. Also,"
“Substantially parallel” means a state in which two straight lines are arranged at an angle of −30° or more and 30° or less. Further, “vertical” and “orthogonal” refer to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, the case of 85° or more and 95° or less is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60° or more and 120° or less.

In this specification and the like, the terms “same”, “same”, “equal”, “uniform” (including their synonyms), etc., regarding count values and measurement values are excluded unless explicitly stated. , Plus or minus 20% error.

In addition, in this specification, when the etching step is performed after the photolithography step, the resist mask formed in the photolithography step is
It should be removed after the etching process is completed.

Further, in this specification and the like, the high power supply potential VDD (hereinafter also referred to as “VDD” or “H potential”) refers to a power supply potential higher than the low power supply potential VSS. Further, the low power supply potential VSS (hereinafter, also simply referred to as “VSS” or “L potential”) indicates a power supply potential lower than the high power supply potential VDD. Further, the ground potential can be used as VDD or VSS. For example, when VDD is the ground potential, VSS is a potential lower than the ground potential,
When VSS is ground potential, VDD is higher than ground potential.

Note that the term “film” and the term “layer” can be interchanged with each other depending on the case or circumstances. For example, it may be possible to change the term "conductive layer" to the term "conductive film". Alternatively, for example, it may be possible to change the term “insulating film” to the term “insulating layer”.

In this specification, trigonal and rhombohedral crystal systems are included in a hexagonal crystal system.

(Embodiment 1)
In this embodiment, a structural example of the semiconductor device of one embodiment of the present invention will be described.

<Structure example>
FIG. 1A is a top view of a semiconductor device of one embodiment of the present invention. FIG. 1(B) corresponds to FIG.
) Shows a cross section taken along one-dot chain line L1-L2 and a cross section taken along one-dot chain line W1-W2. Figure 1(B)
The semiconductor device illustrated in 1 has a substrate 101, an insulator 102 over the substrate 101, a transistor 100 over the insulator 102, an insulator 110 that covers the transistor 100, and an insulator 111 over the insulator 110.

The transistor 100 includes an oxide layer 104 over the insulator 103, an insulator 105 over the oxide layer 104, a conductor 106 over the insulator 105, and an insulator 108 formed on a sidewall of the conductor 106. The conductor 109 a and the conductor 109 b are in contact with the side surface of the oxide layer 104 and the side surface of the insulator 108. The insulator 108 is preferably adjacent to the side surface of the conductor 106.

The conductor 106 functions as a first gate electrode of the transistor 100, the conductors 109a and 109b function as a source electrode or a drain electrode of the transistor 100, and the insulator 105 functions as a gate insulator of the transistor 100. Is preferred.

Here, the oxide layer 104 can be formed as a single layer or a plurality of layers. For example, in FIG.
As shown in (B), the oxide layer 104 is preferably formed of three layers of an oxide layer 104a, an oxide layer 104b, and an oxide layer 104c. The oxide layer 104b is the oxide layer 104a.
And the oxide layer 104c is formed on and in contact with the oxide layer 104b.

The oxide layer 104a and the oxide layer 104c are closer to an insulator than the oxide layer 104b.
Therefore, when the gate voltage is applied, the oxide layer 104a, the oxide layer 104b, and the oxide layer 10
4c, a channel is easily formed in the oxide layer 104b. Therefore, in this specification and the like, the oxide layer 104a and the oxide layer 104c may be referred to as insulators.

A transistor 100 illustrated in FIG. 1B includes an oxide layer 104a over the insulator 103, an oxide layer 104b in contact with the top surface of the oxide layer 104a, and an oxide layer 104c in contact with the top surface of the oxide layer 104b. And an insulator 105 over the oxide layer 104c. The insulator 108 has a region in contact with the upper surface of the insulator 105. In addition, the lower surface of the insulator 108 has the conductor 106
Approximately coincides with the bottom surface of. In addition, the conductors 109a and 109b are formed using the oxide layer 104.
It has a region in contact with the upper surface of b.

In addition, the transistor 100 has a region in the oxide layer 104 which overlaps with the insulator 108,
A region which overlaps with the conductors 109a and 109b contains a metal element 131 which is different from the main component of the oxide layer 104. The metal element 131 may be contained in part of each of the insulator 105, the oxide layer 104, and the insulator 103. The end portion of the region 135 containing the metal element 131 is shown by a dashed line in FIG. 1B as an example. In FIG. 1B, the region 135 is formed above a dashed line showing an end portion of the region 135.

Note that in the oxide layer 104, the region 135 can function as a source region or a drain region of the transistor 100. Therefore, the region sandwiched between the regions 135 of the oxide layer 104 can function as a channel formation region.

As shown in FIG. 1B, the height of the upper end of the insulator 110 and the height of the upper ends of the conductors 109a and 109b are preferably substantially equal to each other. In addition, the insulator 110 and the conductor 1
The upper surfaces of the conductor 09a, the conductor 109b, the insulator 108, and the insulator 107 preferably form a continuous flat plane, and the insulator 111 is formed over the plane.

Further, in FIG. 1 and the like, the oxide layer 104 may have a structure that does not include either the oxide layer 104a or the oxide layer 104c.

As shown in FIG. 1B, the insulator 103 may have a convex portion. In that case, the oxide layer 104 is preferably formed in contact with the upper portion of the convex portion. Here, the characteristics of the transistor 100 are improved by making the sum of the height of the convex portion and the thickness of the oxide layer 104a larger than the sum of the thickness of the oxide layer 104c and the thickness of the oxide layer 104b. You may be able to.

FIG. 59A shows a modification example of a cross section corresponding to dashed-dotted line L1-L2 in the cross section shown in FIG. The semiconductor device of one embodiment of the present invention does not need to have the insulator 107 over the conductor 106 as in the example shown in FIG. It is more preferable to have an insulator 107 over the conductor 106 as shown in FIG. When the transistor 100 includes the insulator 107, the manufacturing process of the transistor 100 can be stabilized in some cases. By stabilizing the manufacturing process, the characteristics of the transistor 100 can be improved.

In addition, the transistor 100 includes the insulator 118 and the conductor 117 over the insulator 102,
May have. In the example illustrated in FIG. 1B, the conductor 117 is formed so as to fill the insulator 118. The insulator 103 is formed so as to fill the insulator 118.
18 is formed. Here, the conductor 117 preferably functions as the second gate electrode of the transistor 100. The potential of the second gate electrode may be the same as that of the first gate of the transistor 100, the ground potential (GND potential), or any potential. Moreover, by changing the potential of the second gate electrode independently without interlocking with the first gate electrode,
The threshold voltage of the transistor can be changed.

By providing the conductor 106 and the conductor 117 with the oxide layer 104 interposed therebetween, and further by setting the conductor 106 and the conductor 117 to have the same potential, the region where carriers flow in the oxide layer 104 has a thickness direction. , The carrier movement amount increases. As a result, the on-state current of the transistor 100 is increased and the field effect mobility is increased.

Therefore, the transistor 100 is a transistor having a large on-state current with respect to the occupied area. That is, the area occupied by the transistor 100 can be reduced with respect to the required on-state current. Therefore, a highly integrated semiconductor device can be realized.

In addition, since the first gate electrode and the second gate electrode are formed of conductive layers, a function of preventing an electric field generated outside the transistor from acting on the semiconductor layer in which a channel is formed (especially an electric field for static electricity or the like). Has a shielding function). Note that the electric field shielding function can be improved by forming the second gate electrode larger than the semiconductor layer and covering the semiconductor layer with the second gate electrode.

Since each of the conductor 106 and the conductor 117 has a function of blocking an electric field from the outside, electric charge such as charged particles generated above the conductor 106 and below the conductor 117 is charged in the channel formation region of the oxide layer 104. Does not affect As a result, the deterioration of the stress test (for example, applying a negative charge to the gate-GBT (Gate Bias-Temperature) stress test) is suppressed. Further, the conductor 106 and the conductor 117 can be blocked so that an electric field generated from the drain electrode does not act on the semiconductor layer. Therefore, it is possible to suppress the fluctuation of the rising voltage of the on-current due to the fluctuation of the drain voltage. Note that this effect remarkably occurs when a potential is supplied to the conductor 106 and the conductor 117.

Note that the BT stress test is a kind of accelerated test, and it is possible to evaluate in a short time a characteristic change (aging change) of a transistor caused by long-term use. In particular, the amount of fluctuation in the threshold voltage of the transistor before and after the BT stress test is an important index for examining the reliability. It can be said that a transistor having higher reliability has a smaller threshold voltage variation before and after the BT stress test.

Further, the conductor 106 and the conductor 117 are included, and the conductor 106 and the conductor 117 are included.
By setting the same potential, the fluctuation amount of the threshold voltage is reduced. For this reason, variations in electrical characteristics among a plurality of transistors are also reduced at the same time.

Further, the transistor having the second gate electrode applies positive charge to the gate +GB
The fluctuation of the threshold voltage before and after the T stress test is also smaller than that of the transistor having no second gate electrode.

Further, when light is incident from the second gate electrode side, light is incident on the semiconductor layer from the second gate electrode side by forming the second gate electrode with a conductive film having a light-blocking property. Can be prevented. Therefore, light deterioration of the semiconductor layer can be prevented, and deterioration of electric characteristics such as a shift of the threshold voltage of the transistor can be prevented.

In addition, in the cross section corresponding to the alternate long and short dash line L1-L2 among the cross sections shown in FIG.
The end portion 315 of the insulator 108 is located outside the end portion 316 of the conductor 117.
As shown in 0 (A), the positions of the end portion 315 and the end portion 316 may be substantially the same. Or
As shown in FIG. 60B, the end portion 315 may be located inside the end portion 316.

In addition, the semiconductor device of one embodiment of the present invention includes an insulator 112 over the insulator 111, and an insulator 11.
0, the contact plug 113 formed to fill the insulator 111 and the insulator 112
a, the contact plug 113b, and the contact plug 113c, and the conductor 114a, the conductor 114b, and the conductor 114c over the insulator 112 may be included. Conductor 114
The a, the conductor 114b, and the conductor 114c can be used for, for example, wiring for routing.

The semiconductor device of one embodiment of the present invention may include a semiconductor element or the like between the substrate 101 and the insulator 102.

FIG. 2A is a top view of a semiconductor device of one embodiment of the present invention. 2(B) is shown in FIG.
) Shows a cross section taken along one-dot chain line L1-L2 and a cross section taken along one-dot chain line W1-W2. In FIG. 2, the semiconductor device has a transistor 100. The semiconductor device illustrated in FIG. 2 is different from that in FIG. 1 in the structure of the insulator 108 included in the transistor 100. In FIG. 1B, the bottom surface of the insulator 108 is substantially aligned with the bottom surface of the conductor 106, whereas in FIG. 2B, the bottom surface of the insulator 108 is substantially aligned with the bottom surface of the oxide layer 104c. To do. Further, in FIG. 1B, the insulator 108 is in contact with the top surface of the insulator 105, whereas in FIG. 2B, the insulator 108 is in contact with the top surface of the oxide layer 104b. In addition, the end portions of the oxide layer 104c and the insulator 105 are substantially aligned with the end portions of the insulator 108 in FIG. 1B, whereas they are substantially aligned with the end portions of the conductor 106 in FIG. To do.

Here, as illustrated in FIG. 2B, the transistor 100 may include an insulator 108b in contact with a side surface of the oxide layer 104b or the like.

Further, as shown in FIG. 3A, the end portion of the oxide layer 104c may be located outside the end portion of the insulator 108. In the transistor 100 illustrated in FIG. 3A, the oxide layer 1
The end of 04c is located outside the end of the insulator 108. In addition, the end portion of the oxide layer 104c is located outside the end portion of the conductor 109a or the conductor 109b.

Further, as shown in FIG. 59B, the end portion of the oxide layer 104c and the end portion of the insulator 105 may be located outside the end portions of the conductor 109a and the conductor 109b. .. In addition, the end portion of the oxide layer 104c and the end portion of the insulator 105 may be approximately aligned, or may not be aligned as illustrated in FIG.

Further, as shown in FIG. 59C, the end portion of the insulator 105 may be located outside the insulator 108 and may be located inside the end portions of the conductors 109a and 109b. .. Although the end portion of the oxide layer 104c is located outside the end portion of the conductor 109a or the conductor 109b in FIG. 59C, it may be located inside.

In addition, the end portion of the oxide layer 104c may be located outside the end portion of the conductor 109a and the end portion of the conductor 109b. In this case, the conductors 109a and 109b are
An oxide layer 104c is provided between the insulator 103 and the insulator 103.

Further, as shown in FIG. 4, the end portion of the oxide layer 104c may be substantially aligned with the oxide layer 104b.

<Explanation of components>

[Oxide layer 104]
The oxide layer 104 preferably has a structure in which the oxide layer 104a, the oxide layer 104b, and the oxide layer 104c are stacked.

As the oxide layer 104, for example, an oxide semiconductor containing indium (In) is preferably used. The oxide semiconductor has a high carrier mobility (electron mobility) when containing indium, for example. Further, the oxide semiconductor preferably contains the element M.

The element M is preferably aluminum, gallium, yttrium, tin or the like. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten and magnesium. However, as the element M, it may be acceptable to combine a plurality of the aforementioned elements. The element M is, for example, an element having a high binding energy with oxygen. The element M is, for example, an element having a function of increasing the energy gap of the oxide semiconductor. In addition, the oxide semiconductor preferably contains zinc. If the oxide semiconductor contains zinc, it may be easily crystallized.

However, the oxide layer 104 is not limited to an oxide containing indium. Oxide layer 104
May be, for example, an oxide not containing indium but containing zinc, an oxide containing gallium, an oxide containing gallium, an oxide containing tin, such as zinc tin oxide, gallium tin oxide, and gallium oxide.

For the oxide layer 104, for example, an oxide semiconductor with a wide energy gap is used. The energy gap of the oxide semiconductor used for the oxide layer 104 is, for example, 2.5 eV or more.
2 eV or less, preferably 2.8 eV or more and 3.8 eV or less, more preferably 3 eV or more 3.
． It is 5 eV or less.

The oxide semiconductor is formed by a sputtering method or a CVD (Chemical Vapor Dep) method.
position (MOCVD (Metal Organic Chemical V
apor Deposition) method, ALD (Atomic Layer Depos)
ionization) method, thermal CVD method or PECVD (Plasma Enhanced Ch
(e.g., but not limited to, electrical vapor deposition) method),
MBE (Molecular Beam Epitaxy) method or PLD (Pulse)
The film may be formed by using the d Laser Deposition method. The plasma CVD method can obtain a high quality film at a relatively low temperature. When a film formation method that does not use plasma at the time of film formation, such as MOCVD method, ALD method, or thermal CVD method, is used, the surface to be formed is less likely to be damaged, and a film with few defects can be obtained.

The CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, the film forming method is not easily affected by the shape of the object to be processed and has a good step coverage. In particular, since the ALD method has excellent step coverage and excellent thickness uniformity, it is suitable for coating the surface of the opening having a high aspect ratio. However, since the ALD method has a relatively low film forming rate, it may be preferable to use it in combination with another film forming method such as a CVD method having a high film forming rate.

In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of the source gas. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gas. In addition, for example, in the CVD method and the ALD method, a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas during film formation. When forming a film while changing the flow rate ratio of the source gas, it is possible to shorten the time required for film formation by the amount of time required for transportation and pressure adjustment, as compared with the case of forming a film using a plurality of film formation chambers. it can. Therefore, the productivity of the transistor or the semiconductor device can be increased in some cases.

For example, when an InGaZnO _X (X>0) film is formed as the oxide layer 104 by a thermal CVD method, trimethyl indium (In(CH ₃ ) ₃ ) and trimethyl gallium (Ga(
CH ₃ ) ₃ ) and dimethyl zinc (Zn(CH ₃ ) ₂ ) are used. Further, the combination is not limited to these, and triethyl gallium (Ga(C ₂ H ₅
) ₃ ) can be used, and diethyl zinc (Zn(C ₂ H ₅ ) ₂ ) can be used instead of dimethyl zinc.
Can also be used.

For example, when an InGaZnO _X (X>0) film is formed by the ALD method as the oxide layer 104, In(CH ₃ ) ₃ gas and O ₃ gas are sequentially and repeatedly introduced to form an InO ₂ layer. After that, Ga(CH ₃ ) ₃ gas and O ₃ gas are sequentially and repeatedly introduced to form a GaO layer, and then Zn(CH ₃ ) ₂ gas and O ₃ gas are successively and repeatedly introduced to form a ZnO layer. To do. The order of these layers is not limited to this example. Moreover, using these gases, InGa
A mixed compound layer such as an O ₂ layer, an InZnO ₂ layer, a GaInO layer, a ZnInO layer, or a GaZnO layer may be formed. H ₂ bubbling with an inert gas such as Ar was used instead of O ₃ gas.
O gas may be used, but it is preferable to use O ₃ gas that does not contain H. In(C
Instead of H ₃ ) ₃ gas, In(C ₂ H ₅ ) ₃ gas or tris(acetylacetonato)indium may be used. In addition, tris(acetylacetonato)indium is In(aca
c) Also called ₃ . Further, Ga(C ₃ H ₅ ) ₃ gas or tris(acetylacetonato)gallium may be used instead of Ga(CH ₃ ) ₃ gas. Note that tris(acetylacetonato)gallium is also referred to as Ga(acac) ₃ . Alternatively, Zn(CH ₃ ) ₂ gas or zinc acetate may be used. It is not limited to these gas species.

When forming an oxide semiconductor by a sputtering method, a target containing indium is preferably used in order to reduce the number of particles. Further, when an oxide target having a high atomic ratio of the element M is used, the target may have low conductivity. When a target containing indium is used, the conductivity of the target can be increased and DC discharge and AC discharge are facilitated, so that it is easy to support a large-area substrate. Therefore, the productivity of the semiconductor device can be improved.

In the case where an oxide semiconductor is formed by a sputtering method, the atomic ratio of the target is I
n:M:Zn 3:1:1, 3:1:2, 3:1:4, 1:1:0.5, 1:1:1, 1
It may be 1:2, 1:4:4, 4:2:4.1, or the like.

Note that when an oxide semiconductor is formed by a sputtering method, an oxide semiconductor with an atomic ratio which is different from the atomic ratio of a target may be formed. In particular, zinc may have a smaller atomic ratio in the formed film than the target atomic ratio. Specifically, the atomic ratio of zinc contained in the target may be 40 atomic% or more and 90 atomic% or less.

The oxide layer 104a and the oxide layer 104c are preferably formed using a material containing one or more kinds of the same metal element among elements other than oxygen included in the oxide layer 104b. When such a material is used, an interface state can be made unlikely to occur at the interface with the oxide layer 104a and the oxide layer 104b and the interface with the oxide layer 104c and the oxide layer 104b. Therefore, carrier scattering or capture at the interface is unlikely to occur, and the field-effect mobility of the transistor can be improved. In addition, variations in threshold voltage of the transistor can be reduced. Therefore, it is possible to realize a semiconductor device having good electrical characteristics.

The thickness of the oxide layers 104a and 104c is 3 nm or more and 100 nm or less, preferably 3 nm or more and 50 nm or less. The thickness of the oxide layer 104b is 3 nm or more 2
00 nm or less, preferably 3 nm to 100 nm, more preferably 3 nm to 50
nm or less.

The oxide layer 104b is an In-M-Zn oxide (oxide containing In, the elements M, and Zn).
And when the oxide layers 104a and 104c are also In-M-Zn oxides,
In:M:Zn=x ₁ :y ₁ :z ₁ [atomic ratio] for the oxide layers 104 a and 104 c, and In:M:Zn=x ₂ :y ₂ :z ₂ [for the oxide layer 104 b]. Atomic ratio], y
₁ / _{x 1} is the oxide layer 104a which is larger than _{y 2} / _x 2, selects oxide layer 104c, and an oxide layer 104b. Preferably, the oxide layer 104a, the oxide layer 104c, and the oxide layer 104b in which y ₁ /x ₁ is 1.5 times or more larger than y ₂ /x ₂ are selected. More preferably, oxide layer 104a in which y ₁ /x ₁ is twice or more larger than y ₂ /x ₂ ,
The oxide layer 104c and the oxide layer 104b are selected. More preferably, the oxide layer 104a, the oxide layer 104c, and the oxide layer 104b in which y ₁ /x ₁ is three times or more larger than y ₂ /x ₂ are selected. At this time, in the oxide layer 104b, y ₁ is preferably x ₁ or more because stable electrical characteristics can be given to the transistor. However, when y ₁ is 3 times or more as large as x ₁ , the field-effect mobility of the transistor is lowered, so y ₁ is preferably less than 3 times as large as x ₁ . With the above structure of the oxide layers 104a and 104c, the oxide layers 104a and 104c can be layers in which oxygen vacancies are less likely to occur than the oxide layers 104b.

Note that when the oxide layer 104a is an In-M-Zn oxide, the sum of In and M is 100a.
When In%, In is preferably less than 50 atomic% and M is 50 atomic %.
ic%, more preferably In is less than 25 atomic% and M is 75 atomic.
higher than c%. In the case where the oxide layer 104b is an In-M-Zn oxide, In is higher than 25 atomic %, M is less than 75 atomic %, more preferably In is 34 atomic, when the sum of In and M is 100 atomic %. % And less than 66 atomic%. Further, when the oxide layer 104c is an In-M-Zn oxide, when the sum of In and M is 100 atomic %, In is preferably 50a.
less than tomic%, M is higher than 50 atomic%, more preferably In is 25 at
less than omic% and M is higher than 75 atomic%. Note that the oxide layer 104c may use the same oxide as the oxide layer 104a.

For example, as the oxide layer 104a containing In or Ga and the oxide layer 104c containing In or Ga, In:Ga:Zn=1:3:2, 1:3:4, 1:3:6, 1: 6:
An In-Ga-Zn oxide formed using a target with an atomic ratio of 4, or 1:9:6, or a target with an atomic ratio of In:Ga = 1:9, or 7:93 is used. The In-Ga oxide formed as described above can be used. Further, as the oxide layer 104b, for example,
An In—Ga—Zn oxide formed using a target with an atomic ratio of In:Ga:Zn=1:1:1 or 3:1:2 can be used. Note that the atomic number ratios of the oxide layer 104a and the oxide layer 104b are each ±20 of the above atomic number ratio as an error.
Including% fluctuation.

For the oxide layer 104b, an oxide having an electron affinity higher than those of the oxide layers 104a and 104c is used. For example, the oxide layer 104b has an electron affinity higher than or equal to 0.07 eV and lower than or equal to 1.3 eV, preferably 0.1 eV as compared with the oxide layers 104a and 104c.
An oxide that is greater than or equal to 0.7 eV and less, and more preferably greater than or equal to 0.15 eV and less than 0.4 eV is used. The electron affinity is the difference between the vacuum level and the energy at the bottom of the conduction band.

Note that indium gallium oxide has a low electron affinity and a high oxygen blocking property. Therefore, the oxide layer 104c preferably contains indium gallium oxide. The gallium atomic ratio [Ga/(In+Ga)] is, for example, 70% or more, preferably 80% or more,
More preferably, it is 90% or more.

However, the oxide layer 104a and/or the oxide layer 104c may be gallium oxide. For example, when gallium oxide is used for the oxide layer 104c, leakage current between the electrode 105a or the electrode 105b and the conductor 106 can be reduced. That is, the off-state current of the transistor 100 can be reduced.

The oxide layers 104a and 104c have an electron affinity lower than that of the oxide layer 104b, for example, and thus are closer to insulators than the oxide layer 104b. Therefore, when the gate voltage is applied, the oxide layer 104b among the oxide layer 104a, the oxide layer 104b, and the oxide layer 104c.
A channel is easy to be formed.

In order to impart stable electric characteristics to a transistor including an oxide semiconductor in a semiconductor layer in which a channel is formed (also referred to as an “OS transistor”), impurities and oxygen vacancies in the oxide semiconductor are reduced. It is preferable that the oxide layer 104b be made highly pure and intrinsic, and the oxide layer 104b be an intrinsic or substantially intrinsic oxide semiconductor. For example, oxygen vacancies can be reduced in some cases by supplying excess oxygen to the oxide layer 104b. Also, at least the oxide layer 1
It is preferable that the channel formation region in 04b be an oxide semiconductor which can be regarded as intrinsic or substantially intrinsic.

In addition, in the oxide layer 104, at least the oxide layer 104b includes the CAAC-OS (CA
Axis Aligned Crystalline Oxide Semiconductor
tor) is preferably used. Note that the CAAC-OS will be described in detail in a later embodiment.

Here, the region which is not a CAAC or a region other than the region having c-axis alignment is preferably at least less than 20% of the whole oxide semiconductor film used for the oxide layer 104b.

The CAAC-OS has a dielectric anisotropy. Specifically, the CAAC-OS has a larger permittivity in the c-axis direction than in the a-axis direction and the b-axis direction. A transistor in which a gate electrode is arranged in the c-axis direction using a CAAC-OS for a semiconductor film in which a channel is formed has a large permittivity in the c-axis direction; therefore, an electric field generated from the gate electrode easily reaches the entire CAAC-OS. ..
Therefore, the subthreshold swing value (S value) can be reduced. In addition, in a transistor including a CAAC-OS for a semiconductor film, an increase in S value due to miniaturization is unlikely to occur.

In addition, since the CAAC-OS has a small dielectric constant in the a-axis direction and the b-axis direction, the influence of the electric field generated between the source and the drain is reduced. Therefore, a channel length modulation effect, a short channel effect, or the like is less likely to occur, and the reliability of the transistor can be improved.

Here, the channel length modulation effect means a phenomenon in which the depletion layer spreads from the drain side and the effective channel length becomes shorter when the drain voltage is higher than the threshold voltage. The short channel effect is a phenomenon in which electrical characteristics such as a decrease in threshold voltage are deteriorated due to a decrease in channel length. The finer the transistor, the more easily the electrical characteristics are deteriorated due to these phenomena.

[Energy band structure of oxide semiconductor film]
Here, a function and an effect of the oxide layer 104 formed by stacking the oxide layers 104a, 104b, and 104c are described with reference to an energy band structure diagram in FIG. To do. FIG. 21A shows an energy band structure of a portion indicated by dashed-dotted line A1-A2 in FIG. That is, FIG. 21A shows an energy band structure of a channel formation region of the transistor 100.

21A, Ec382, Ec383a, Ec383b, Ec383c, Ec38.
6 is an insulator 103, an oxide layer 104a, an oxide layer 104b, and an oxide layer 104, respectively.
c, the energy at the bottom of the conduction band of the insulator 105 is shown. In addition, FIG. 21B illustrates an example of the case where the oxide layer 104a is not used.

Here, the electron affinity has a value obtained by subtracting the energy gap from the difference between the vacuum level and the energy at the upper end of the valence band (also referred to as “ionization potential”). In addition, the energy gap is a spectroscopic ellipsometer (UT-300 manufactured by HORIBA JOBIN YVON).
) Can be used for measurement. Further, the energy difference between the vacuum level and the upper end of the valence band is determined by the ultraviolet photoelectron spectroscopy (UPS).
Roscopy) device (VersaProbe, PHI).

Note that In- formed by using a target with an atomic ratio of In:Ga:Zn=1:3:2.
The Ga-Zn oxide has an energy gap of about 3.5 eV and an electron affinity of about 4.5 eV. In addition, In formed using a target with an atomic ratio of In:Ga:Zn=1:3:4
The energy gap of -Ga-Zn oxide is about 3.4 eV, and the electron affinity is about 4.5 eV. I formed by using a target with an atomic ratio of In:Ga:Zn=1:3:6
The n-Ga-Zn oxide has an energy gap of about 3.3 eV and an electron affinity of about 4.5 eV.
Is. An In—Ga—Zn oxide formed using a target with an atomic ratio of In:Ga:Zn=1:6:2 has an energy gap of about 3.9 eV and an electron affinity of about 4.3 e.
V. An In—Ga—Zn oxide formed using a target with an atomic ratio of In:Ga:Zn=1:6:8 has an energy gap of about 3.5 eV and an electron affinity of about 4.4.
eV. An In—Ga—Zn oxide formed using a target with an atomic ratio of In:Ga:Zn=1:6:10 has an energy gap of approximately 3.5 eV and an electron affinity of approximately 4.
． It is 5 eV. An In—Ga—Zn oxide formed using a target with an atomic ratio of In:Ga:Zn=1:1:1 has an energy gap of about 3.2 eV and an electron affinity of about 4.7 eV. An In—Ga—Zn oxide formed using a target with an atomic ratio of In:Ga:Zn=3:1:2 has an energy gap of about 2.8 eV and an electron affinity of about 5.0 eV.

Since the insulator 103 and the insulator 105 are insulators, Ec382 and Ec386 are equal to Ec3.
83a, Ec383b, and Ec383c are closer to the vacuum level (electron affinity is smaller).

Further, Ec383a is closer to the vacuum level than Ec383b. Specifically, Ec383
It is preferable that a is closer to a vacuum level than Ec383b by 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, and more preferably 0.15 eV or more and 0.4 eV or less.

Further, Ec383c is closer to the vacuum level than Ec383b. Specifically, Ec383
c is preferably 0.07 eV or more and 1.3 eV or less, preferably 0.1 eV or more and 0.7 eV or less, more preferably 0.15 eV or more and 0.4 eV or less, closer to the vacuum level than Ec383b.

Here, a mixed region of the oxide layer 104a and the oxide layer 104b may be provided between the oxide layer 104a and the oxide layer 104b. In addition, the oxide layer 104b and the oxide layer 104
There may be a mixed region between the oxide layer 104b and the oxide layer 104c between the region c and the region c.
In the mixed region, the interface state density becomes low. Therefore, the oxide layer 104a and the oxide layer 104b
The stacked body of the oxide layer 104c and the oxide layer 104c has a band structure in which energy continuously changes (also referred to as a continuous bond) in the vicinity of each interface.

At this time, the electrons mainly move in the oxide layer 104b, not in the oxide layer 104a and the oxide layer 104c. Therefore, the oxide layer 104a and the oxide layer 104b are
By reducing the interface state density at the interface between the oxide layer 104b and the oxide layer 104c and the interface state density at the interface between the oxide layer 104b and the oxide layer 104c, electron transfer in the oxide layer 104b is less likely to occur and the transistor 100 The ON current of can be increased.

In addition, the interface between the oxide layer 104a and the insulator 103, and the oxide layer 104c and the insulator 10
Although a trap level 390 may be formed near the interface of No. 5 due to impurities or defects,
With the oxide layer 104a and the oxide layer 104c, the oxide layer 104b and the trap level can be separated from each other.

Note that when the transistor 100 has an s-channel structure, the oxide layer 104b
A channel is formed over the entire area. Therefore, the thicker the oxide layer 104b, the larger the channel region. That is, the thicker the oxide layer 104b is, the higher the on-state current of the transistor 100 can be. For example, the oxide layer 104b having a region with a thickness of 20 nm or more, preferably 40 nm or more, further preferably 60 nm or more, more preferably 100 nm or more.
And it is sufficient. However, since the productivity of the semiconductor device including the transistor 100 may be reduced, for example, 300 nm or less, preferably 200 nm or less, more preferably 1 nm or less.
The oxide layer 104b may have a region with a thickness of 50 nm or less.

In addition, in order to increase the on-state current of the transistor 100, it is preferable that the thickness of the oxide layer 104c be smaller. For example, the oxide layer 104c may have a region of less than 10 nm, preferably 5 nm or less, further preferably 3 nm or less. On the other hand, the oxide layer 104c is
To the oxide layer 104b in which a channel is formed, an element other than oxygen which forms an adjacent insulator (
Hydrogen, silicon, etc.) has the function of blocking so that it does not enter. Therefore, the oxide layer 104c preferably has a certain thickness. For example, the oxide layer 104c having a region with a thickness of 0.3 nm or more, preferably 1 nm or more, more preferably 2 nm or more.
And it is sufficient.

Further, in order to improve reliability, it is preferable that the oxide layer 104a be thick and the oxide layer 104c be thin. For example, 10 nm or more, preferably 20 nm or more, more preferably 4
The oxide layer 104a may have a region with a thickness of 0 nm or more, more preferably 60 nm or more. By increasing the thickness of the oxide layer 104a, the adjacent insulator and oxide layer 104a
The distance from the interface with a to the oxide layer 104b where the channel is formed can be increased.
However, since the productivity of the semiconductor device including the transistor 100 may be reduced, the oxide layer 104a having a region with a thickness of 200 nm or less, preferably 120 nm or less, further preferably 80 nm or less may be used, for example.

Note that silicon in the oxide semiconductor might serve as a carrier trap or a carrier generation source. Therefore, the lower the silicon concentration of the oxide layer 104b, the better. For example, between the oxide layer 104b and the oxide layer 104a, for example, secondary ion mass spectrometry (SIMS:
1×1 in Secondary Ion Mass Spectrometry)
It has a region having a silicon concentration of less than 0 ¹⁹ atoms/cm ³ , preferably less than 5×10 ¹⁸ atoms/cm ³ , and more preferably less than 2×10 ¹⁸ atoms/cm ³ .
In addition, 1×10 ¹⁹ is formed between the oxide layer 104b and the oxide layer 104c in SIMS.
There is a region having a silicon concentration of less than atoms/cm ³ , preferably less than 5×10 ¹⁸ atoms/cm ³ , and more preferably less than 2×10 ¹⁸ atoms/cm ³ .

Further, in order to reduce the hydrogen concentration of the oxide layer 104b, it is preferable to reduce the hydrogen concentration of the oxide layers 104a and 104c. Oxide layer 104a and oxide layer 104c
Is 2×10 ²⁰ atoms/cm ³ or less, preferably 5×10 ¹⁹ in SIMS.
It has a region having a hydrogen concentration of atoms/cm ³ or less, more preferably 1×10 ¹⁹ atoms/cm ³ or less, and further preferably 5×10 ¹⁸ atoms/cm ³ or less. Also,
In order to reduce the nitrogen concentration of the oxide layer 104b, the oxide layer 104a and the oxide layer 104 may be reduced.
It is preferable to reduce the nitrogen concentration of c. The oxide layer 104a and the oxide layer 104c are SI
In MS, less than 5×10 ¹⁹ atoms/cm ³ , preferably 5×10 ¹⁸ atoms
It has a region having a nitrogen concentration of s/cm ³ or less, more preferably 1×10 ¹⁸ atoms/cm ³ or less, and further preferably 5×10 ¹⁷ atoms/cm ³ or less.

Note that when copper is mixed into the oxide semiconductor, an electron trap may be generated. The electron trap may change the threshold voltage of the transistor in the positive direction. Therefore, the lower the copper concentration on the surface or inside the oxide layer 104b, the more preferable. For example, the oxide layer 104b has a copper concentration of 1×10 ¹⁹ atoms/cm ³ or less and 5×10 ¹⁸ atoms.
/Cm ³ or less, or 1×10 ¹⁸ atoms/cm ³ or less is preferable.

The above three-layer structure is an example. For example, a two-layer structure without the oxide layer 104a or the oxide layer 104c may be used. Alternatively, the oxide layer 104a, the oxide layer 104b, and the oxide layer 104 are provided above or below the oxide layer 104a or above or below the oxide layer 104c.
A four-layer structure having any one of the semiconductors exemplified as c may be used. Alternatively, the oxide layer 104a, the oxide layer 104b, and the oxide layer 104b are provided at any two or more positions on the oxide layer 104a, the oxide layer 104a, the oxide layer 104c, and the oxide layer 104c. 104
An n-layer structure (n is an integer of 5 or more) having any one of the semiconductors exemplified as c may be used.

In particular, in the transistor 100 illustrated in this embodiment, the upper surface and the side surface of the oxide layer 104b are in contact with the oxide layer 104c and the lower surface of the oxide layer 104b is in contact with the oxide layer 104a in the channel width direction. (See FIG. 1C). Thus, the oxide layer 104
With the structure in which b is covered with the oxide layer 104a and the oxide layer 104c, the influence of the trap level can be further reduced.

In addition, the band gaps of the oxide layer 104a and the oxide layer 104c are as follows.
It is preferable that the band gap is wider than that of 4b.

According to one embodiment of the present invention, a transistor with less variation in electrical characteristics can be realized. Therefore, a semiconductor device with less variation in electrical characteristics can be realized. According to one embodiment of the present invention, a highly reliable transistor can be realized. Therefore, a highly reliable semiconductor device can be realized.

Since the band gap of an oxide semiconductor is 2 eV or more, the off-state current of a transistor including an oxide semiconductor for a semiconductor film in which a channel is formed can be extremely low. Specifically, when the voltage between the source and the drain is 3.5 V and the room temperature (25° C.), the off current per 1 μm of the channel width is less than 1×10 ⁻²⁰ A, less than 1×10 ⁻²² A, or 1 It can be less than ×10 ⁻²⁴ A. That is, the on/off ratio is 20 digits or more and 15
It can be 0 or less digits.

According to one embodiment of the present invention, a transistor with low power consumption can be realized. Therefore, a semiconductor device with low power consumption can be realized.

[Insulator 102]
The insulator 102 is aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, or lanthanum oxide. , A material selected from neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, or the like is used in a single layer or stacked layers. Alternatively, a material obtained by mixing a plurality of materials among an oxide material, a nitride material, an oxynitride material, and a nitride oxide material may be used.

Note that in this specification, a nitride oxide refers to a compound in which the content of nitrogen is higher than that of oxygen. The oxynitride refers to a compound having a higher oxygen content than nitrogen. The content of each element is, for example, Rutherford backscattering method (RBS: Rutherford Ba).
ckscattering Spectrometry) or the like.

In particular, the insulator 102 is preferably formed using an insulating material having low impurity permeability. For example, it is preferable that oxygen permeability is low. Further, for example, it is preferable that hydrogen permeability is low. For example, an insulating material including boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum in a single layer, or It may be used by stacking. For example, as an insulating material having low impurity permeability, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide is used. , Silicon nitride, and the like. Alternatively, as the insulator 102, indium tin zinc oxide (In—Sn—Zn oxide) having high insulating property or the like may be used.

Note that the insulator 102 may include an oxide containing indium. Also, the insulator 10
2 may have an oxide with indium and zinc. The insulator 102 may also include an oxide containing indium, zinc, and the element M. When the insulator 102 includes an oxide containing indium, an oxide containing indium and zinc, or an oxide containing indium, zinc, and the element M, oxygen permeability can be reduced in some cases.

The method for forming the insulator 102 is not particularly limited, and various forming methods such as a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, or a spin coating method can be used. The thickness of the insulator 102 and the insulator 110 is 10 nm or more and 500 nm or less, preferably 50 nm.
The thickness may be not less than nm and not more than 300 nm.

For example, in the case of forming an aluminum oxide film as the insulator 102 by using a thermal CVD method, a raw material gas obtained by vaporizing a liquid (such as TMA) containing a solvent and an aluminum precursor compound, and H ₂ O as an oxidizer. Two types of gas are used. The chemical formula of trimethylaluminum is Al(CH ₃ ) ₃ . Other material liquids include tris(dimethylamide)aluminum, triisobutylaluminum, aluminum tris(2,2,6,6-tetramethyl-3,5-heptanedionate), and the like.

By using an insulating material with low impurity permeability for the insulator 102, diffusion of impurities from the substrate 101 side can be suppressed and reliability of the transistor can be improved. By using an insulating material with low impurity permeability for the insulator 111, diffusion of impurities from the insulator 112 side can be suppressed and reliability of the transistor can be improved.

As the insulator 102, a plurality of insulators formed of these materials may be stacked and used.

[Insulator 111 and Insulator 110b]
Further, the insulator 111 and the insulator 110b are preferably formed using an insulating material having low impurity permeability. For example, the insulator 111 and the insulator 110b preferably have low oxygen permeability. Further, for example, the insulator 111 and the insulator 110b preferably have low hydrogen permeability. Further, for example, the insulator 111 and the insulator 110b preferably have low water permeability. A material that can be used for the insulator 111 and the insulator 110b,
For the method for manufacturing the insulator 111 and the insulator 110b, the description of the insulator 102 can be referred to.

Due to the low oxygen permeability of the insulator 111 and the insulator 110b, the oxide layer 104b
It may be possible to prevent the excess oxygen supplied to the outside from diffusing outward.

[Insulator 103]
As the insulator 103, for example, silicon oxide, silicon oxynitride, silicon nitride oxide,
Silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like may be used, and a stacked layer or a single layer is formed. The insulator 402 and the insulator 412 are formed by a sputtering method, a CVD method (a thermal CVD method, a MOCVD method, a PEC method).
VD method and the like), MBE method, ALD method, PLD method and the like can be used. In particular, it is preferable to form the insulating film by a CVD method, preferably a plasma CVD method because coverage can be improved. In order to reduce plasma damage, heat CV
The D method, MOCVD method or ALD method is preferable.

Further, the insulator 103 may have a charge trap layer. For example, as shown in FIG. 4B, the insulator 103 has a stacked structure of an insulator 103a, an insulator 103b, and an insulator 103c,
The insulator 103b may be a charge trap layer by using hafnium oxide, aluminum oxide, tantalum oxide, aluminum silicate, or the like as the insulator 103b. As the insulator 103a and the insulator 103c, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like can be used. By injecting electrons into the insulator 103b, the threshold voltage of the transistor can be changed. The tunnel effect may be used to inject the electrons into the insulator 103b. By applying a positive voltage to the conductor 117, tunnel electrons can be injected into the insulator 103b.

The insulator 103 can be formed using a material and a method similar to those of the insulator 102. Further, in order to prevent an increase in hydrogen concentration in the oxide layer 104, the hydrogen concentration in the insulator 103 is preferably reduced. Specifically, the hydrogen concentration in the insulator 103 is 2×10 ²⁰ atoms/cm ³ or less, preferably 5×10 ¹⁹ atoms/cm ^{3 in} SIMS.
Or less, more preferably 1×10 ¹⁹ atoms/cm ³ or less, and further preferably 5×10.
¹⁸ atoms/cm ³ or less. Further, it is preferable to reduce the nitrogen concentration in the insulator 103 in order to prevent an increase in the nitrogen concentration in the oxide semiconductor. Specifically, the insulator 103
, Nitrogen concentration in SIMS is less than 5×10 ¹⁹ atoms/cm ³ , preferably 5×10 ¹⁸ atoms/cm ³ or less, more preferably 1×10 ¹⁸ atoms/cm 3.
³ or less, more preferably 5×10 ¹⁷ atoms/cm ³ or less.

The insulator 103 is preferably formed using an insulator from which oxygen is released by heating (also referred to as an “insulator containing excess oxygen”). Specifically, in TDS analysis, the desorption amount of oxygen converted into oxygen atoms is 1.0×10 ¹⁸ atoms/cm ³ or more, preferably 3
． It is preferable to use an insulator having a density of 0×10 ²⁰ atoms/cm ³ or more.

Alternatively, the insulator containing excess oxygen can be formed by performing treatment for adding oxygen to the insulator. The treatment for adding oxygen can be performed by heat treatment in an oxygen atmosphere, an ion implantation apparatus, an ion doping apparatus, or a plasma treatment apparatus. As a gas for adding oxygen, an oxygen gas such as ¹⁶ O ₂ or ¹⁸ O ₂ , a nitrous oxide gas, or an ozone gas can be used. In this specification, the treatment of adding oxygen is also referred to as "oxygen doping treatment". The treatment of adding oxygen is performed by, for example, forming the insulator 118 and then forming the insulator 103.
May be performed after the formation of the film, and before the formation of the oxide layer 104e. Further, high-density plasma treatment or the like may be performed. High-density plasma may be generated using microwaves. In the high density plasma treatment, for example, an oxidizing gas such as oxygen or nitrous oxide may be used. Alternatively, a mixed gas of an oxidizing gas and a rare gas such as He, Ar, Kr, or Xe may be used. A bias may be applied to the substrate in the high density plasma treatment. As a result, oxygen ions in the plasma can be drawn to the substrate side. The high-density plasma treatment may be performed while heating the substrate. For example, when high-density plasma treatment is performed instead of the heat treatment, the same effect can be obtained at a temperature lower than the temperature of the heat treatment. The high-density plasma treatment may be performed, for example, after the insulator 118 is formed, after the insulator 103 is formed, and before the oxide layer 104e is formed.

Here, for example, a so-called multi-chamber apparatus having a processing chamber for forming the insulator 103, a processing chamber for performing high-density plasma processing, and a substrate processing chamber for transferring between the chambers. By using, the film formation of the insulator 103 and the high-density plasma treatment are continuously performed without being exposed to the air, and thus entry of impurities into the film and the interface can be reduced, which is preferable. Further, the process time can be shortened, which may lead to cost reduction. In addition, since the process can be simplified, the yield may be improved. Here, for example, the substrate processing chamber may be in a reduced pressure atmosphere.

Similarly, for example, a processing chamber for forming the insulator 103, a processing chamber for forming the oxide layer 104d, a processing chamber for forming the oxide layer 104e, and a high-density plasma treatment are performed. By using a multi-chamber apparatus having a processing chamber for performing the treatment and a substrate transfer chamber for transporting between the processing chambers, film formation of the insulator 103, high-density plasma treatment, and oxide layer 104d are performed. And the oxide layer 104e can be continuously performed without exposure to the atmosphere, which is preferable.

The thickness of the insulator 103 is preferably 1 nm or more and 50 nm or less, more preferably 3 nm or more and 30 nm or less, and further preferably 5 nm or more and 10 nm or less. Oxygen doping treatment may be performed after the oxide layer 104f is formed. Further, oxygen doping treatment may be performed after the insulator 103 is formed. Further, heat treatment may be performed after the insulator 103 is formed. In this embodiment,
Silicon oxide, for example, is formed as the insulator 103.

<Structure example 2>
FIG. 5A is a top view of the semiconductor device. Further, FIG. 6(A) shows a dashed-dotted line L shown in FIG.
1-L2 shows a cross section, and FIG. 6B shows a cross section taken along one-dot chain line W1-W2 shown in FIG. The semiconductor device illustrated in FIGS. 5A, 6</b>A, and 6</b>B includes a transistor 10
Insulator 111 located above 0 and insulator 102 located below transistor 100
And insulators 110b surrounding the four sides of the transistor 100. The insulator 102, the insulator 111, and the insulator 110b surround the transistor 100 on six sides. Further, in FIG. 6A, the insulator 110b is the contact plug 113a or the contact plug 1
It is located outside 13b. Further, in FIG. 6B, the insulator 110b is located outside the contact plugs 113c and 113d. Here, the outer side means that the distance from the transistor 100 is longer with the transistor 100 as the center, for example.

In addition, as illustrated in FIG. 5B, the insulator 102, the insulator 111, and the insulator 110b.
May have a structure surrounding a plurality of transistors 100. On the top surface of the semiconductor device illustrated in FIG. 5B, the two transistors 100 are surrounded by the insulator 110b. Although not shown, an insulator 111 is provided above the two transistors 100 in the cross section of the semiconductor device.
And has an insulator 102 below. Therefore, the two transistors 100 have the insulator 1
02, the insulator 111, and the insulator 110b surround the hexagon. In addition, the insulator 110b preferably has a closed shape on the top surface of the semiconductor device. Examples of the closed shape include a polygon, a circle, an ellipse, and a closed curve formed by connecting a curve and a straight line. For example, it may be a quadrangle as shown in FIG. 5(A), or as shown in FIG. 5(B),
The quadrangle may have rounded corners.

The characteristics of the transistor 100 may change with the movement of water, hydrogen, or oxygen. Since the insulator 100, the insulator 111, and the insulator 110b surround the transistor 100 in six directions, hydrogen and hydrogen are mixed into the transistor 100 from the outside of the enclosed region and the transistor 100 is provided outside the enclosed region. The release of oxygen can be suppressed. Therefore, variation in characteristics of the transistor 100 can be suppressed.

Note that one embodiment of the present invention is described in this embodiment. Alternatively, one embodiment of the present invention will be described in another embodiment. However, one embodiment of the present invention is not limited to these. That is, in this embodiment and the other embodiments, various aspects of the invention are described; therefore, one aspect of the present invention is not limited to a particular aspect. For example, although an example in which the channel formation region, the source/drain region, or the like of a transistor such as the transistor 100 includes an oxide semiconductor is described as one embodiment of the present invention, one embodiment of the present invention is not limited to this. Depending on the case or conditions, the various transistors, the channel formation region of the transistor, the source/drain region of the transistor, or the like in one embodiment of the present invention may include various semiconductors. Depending on circumstances or conditions, various transistors in one embodiment of the present invention, channel formation regions of the transistors, or
The source/drain region or the like of the transistor may include at least one of silicon, germanium, silicon germanium, silicon carbide, gallium arsenide, aluminum gallium arsenide, indium phosphide, gallium nitride, or an organic semiconductor. Alternatively, for example, in some cases or in some circumstances, various transistors in one embodiment of the present invention, a channel formation region of the transistor, a source/drain region of the transistor, or the like do not include an oxide semiconductor. Good.

(Embodiment 2)
In this embodiment, a method for manufacturing the semiconductor device described in Embodiment 1 will be described.

<Production method>
A method for manufacturing the semiconductor device illustrated in FIG. 1 is described with reference to FIGS.

The insulator 102 is formed over the substrate 101. Next, the insulator 118 is formed over the insulator 102. Next, a mask 301 is formed over the insulator 118 (see FIG. 7A).

There is no particular limitation on the material used for the substrate 101, but it is necessary that the material have heat resistance high enough to withstand at least heat treatment performed later. For example, a glass substrate such as barium borosilicate glass or aluminoborosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used.

Further, as the substrate 101, a single crystal semiconductor substrate made of a material such as silicon or silicon carbide,
A polycrystalline semiconductor substrate, a compound semiconductor substrate made of silicon germanium, or the like may be used. Alternatively, an SOI substrate, a semiconductor substrate on which semiconductor elements such as strain transistors or FIN transistors are formed, or the like can be used. Alternatively, a high electron mobility transistor (HEMT: High Electron Mobility Transistor)
For example, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide, silicon germanium, or the like which is applicable to (tor) may be used. That is, the substrate 101 is not limited to a simple supporting substrate, and may be a substrate on which other devices such as transistors are formed. In this case, at least one of the gate, the source, and the drain of the transistor 100 may be electrically connected to the above other device.

Note that a flexible substrate (flexible substrate) may be used as the substrate 101. In the case of using a flexible substrate, a transistor, a capacitor, or the like may be directly manufactured over the flexible substrate, or a transistor, a capacitor, or the like may be manufactured over another manufacturing substrate and then the flexible substrate is formed. You may peel and transpose. Note that a separation layer may be formed between the manufacturing substrate and the transistor, the capacitor, or the like in order to separate and transfer the manufacturing substrate to the flexible substrate.

As the flexible substrate, for example, metal, alloy, resin or glass, or fiber thereof can be used. It is preferable that the flexible substrate used for the substrate 101 have a lower linear expansion coefficient because deformation due to the environment is suppressed. For the flexible substrate used for the substrate 101, for example, a material having a linear expansion coefficient of 1×10 ⁻³ /K or less, 5×10 ⁻⁵ /K or less, or 1×10 ⁻⁵ /K or less may be used. .. Examples of the resin include polyester, polyolefin, polyamide (nylon, aramid, etc.), polyimide, polycarbonate, acrylic resin and the like. In particular, aramid is suitable as a flexible substrate because of its low linear expansion coefficient.

The mask 301 may be formed by a lithography method using a resist, for example. Alternatively, a hard mask made of an inorganic film or a metal film may be formed. The resist mask can be formed by a photolithography method, a printing method, an inkjet method, or the like as appropriate.
When the resist mask is formed by a printing method, an inkjet method, or the like, a photomask is not used, so that manufacturing cost can be reduced.

The formation of the resist mask by the photolithography method is performed by irradiating the photosensitive resist with light through the photomask and removing the resist in the exposed portion (or the unexposed portion) with a developing solution. The light irradiating the photosensitive resist is KrF excimer laser light, Ar.
Examples include F excimer laser light and EUV (Extreme Ultraviolet) light. Also, an immersion technique may be used in which a liquid (for example, water) is filled between the substrate and the projection lens to perform exposure. Further, an electron beam or an ion beam may be used instead of the above-mentioned light. If an electron beam or an ion beam is used, a photomask is unnecessary. Note that the resist mask can be removed by a dry etching method such as ashing or a wet etching method using a dedicated peeling solution or the like. Both a dry etching method and a wet etching method may be used.

Next, part of the insulator 118 is removed using the mask 301, so that the opening 306 is formed (see FIG. 7B). To remove the insulator 118, for example, dry etching or the like may be used.

Next, a conductor 117d is formed over the upper surface of the insulator 118 and in the opening 306 (see FIG.
See C). ).

Next, by removing a part of the conductor 117d, the conductor 117 is formed (see FIG.
See D). ). To remove the conductor 117d, for example, chemical mechanical polishing (Chemical polishing) is used.
It is preferable to use a polishing method such as a mechanical polishing (CMP) method. Alternatively, dry etching may be used. For example, a method such as etch back may be used.

Here, the CMP method is a method of flattening the surface of a workpiece by a combined chemical and mechanical action. Generally, a polishing cloth is pasted on the polishing stage, and while the slurry (polishing agent) is supplied between the work piece and the polishing cloth, the polishing stage and the work piece are rotated or rocked to form a slurry. Is a method of polishing the surface of a workpiece by a chemical reaction between the surface of the workpiece and the surface of the workpiece and mechanical polishing between the polishing cloth and the workpiece.

Next, the insulator 103, the oxide layer 104d, and the oxide layer 104e are sequentially formed over the insulator 118 and the conductor 117.

Next, in order to further reduce impurities such as moisture or hydrogen contained in the oxide layer 104d and the oxide layer 104e so that the oxide layer 104d and the oxide layer 104e are highly purified,
It is preferable to perform heat treatment.

For example, in a reduced pressure atmosphere, an inert atmosphere such as nitrogen or a rare gas, an oxidizing atmosphere, or an ultra-dry air (CRDS (Cavity Ring Down Laser Spectroscopy)) Oxide layer 104d and oxide layer 10 under an atmosphere of 20 ppm (-55° C. in dew point conversion) or less, preferably 1 ppm or less, preferably 10 ppb or less.
Heat treatment is applied to 4e. Note that the oxidizing atmosphere means an atmosphere containing an oxidizing gas such as oxygen, ozone, or oxygen nitride at 10 ppm or more. Further, the inert atmosphere refers to an atmosphere in which the oxidizing gas is less than 10 ppm and is filled with nitrogen or a rare gas.

By heat treatment, oxygen contained in the insulator 103 is diffused into the oxide layers 104d and 104e at the same time as the release of impurities, so that oxygen vacancies contained in the oxide semiconductor layer are reduced. You can Note that after the heat treatment in an inert gas atmosphere, the heat treatment may be performed in an atmosphere containing an oxidizing gas in an amount of 10 ppm or higher, 1% or higher, or 10% or higher in order to supplement desorbed oxygen. Note that the heat treatment is performed on the oxide layer 104d and the oxide layer 10.
It may be performed any time after the formation of 4e. For example, the oxide layer 104a and the oxide layer 10
Heat treatment may be performed after the formation of 4b. Alternatively, it may be performed after the oxide layer 104c is formed later.

The heating device used for the heat treatment is not particularly limited, and may be a device that heats the object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element. For example, electric furnace, L
RTA (Lamp Rapid Thermal Anneal) device, GRTA (Ga
s Rapid Thermal Anneal (RTA) such as a device.
rmal Anneal) apparatus can be used. The LRTA device is a device for heating an object to be processed by radiating light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, and a high pressure mercury lamp. The GRTA device is a device that performs heat treatment using a high-temperature gas.

The heat treatment may be performed at 250 °C to 650 °C inclusive, preferably 300 °C to 500 °C inclusive. The processing time is within 24 hours. A heat treatment for more than 24 hours is not preferable because it causes a decrease in productivity.

Note that oxygen doping treatment may be performed after the oxide layer 104d is formed or after the oxide layer 104e is formed.

Next, the mask 302 is formed over the oxide layer 104e (see FIG. 8A). Mask 3
For 02, refer to the mask 301. Then, the oxide layer 104 is formed using the mask 302.
e, the oxide layer 104d, and the insulator 103 are partly removed to form the oxide layer 104a and the oxide layer 104b (see FIG. 8B). Oxide layer 104e, oxide layer 104
For removing d and the insulator 103, for example, dry etching or wet etching can be used.

When the conductor, the semiconductor, and the insulator are etched by a dry etching method, a gas containing a halogen element can be used as an etching gas. Examples of the gas containing a halogen element include chlorine (Cl ₂ ), boron trichloride (BCl ₃ ), and silicon tetrachloride (SiCl _{4 ).}
) Or carbon tetrachloride (CCl ₄ ), a chlorine-based gas typified by carbon tetrafluoride (CF ₄
), sulfur hexafluoride (SF ₆ ), nitrogen trifluoride (NF ₃ ), or trifluoromethane (C
Fluorine-based gas typified by HF ₃ ), hydrogen bromide (HBr), or oxygen can be used as appropriate. An inert gas may be added to the etching gas used. Further, as etching gas for etching the oxide semiconductor, methane (CH ₄ ), ethane (C ₂
H _6), may be used propane _{(C 3 H} 8), or butane _{(C 4 H 10)} hydrocarbon gas and a mixed gas of an inert gas such as.

As a dry etching method, parallel plate type RIE (Reactive Ion) is used.
Etching) method and ICP (Inductively Coupled Plasma)
a: Inductively coupled plasma method, DF-CCP (Dual Frequency Capa)
The method may be used, such as a “Citially Coupled Plasma” method. The etching conditions (for example, the amount of power applied to the coil-type electrode, the amount of power applied to the electrode on the substrate side, the electrode temperature on the substrate side, etc.) may be appropriately adjusted so that the desired processed shape can be etched. ..

Next, the oxide layer 104f, the insulator 105d, the conductor 106d, and the insulator 107d are formed over the top surface and the side surface of the oxide layer 104b, the side surface of the oxide layer 104a, and the insulator 103.
Are sequentially formed. After that, a mask 303 is formed on the upper surface of the insulator 107d (FIG. 8C).
reference. ). For the mask 303, the mask 301 may be referred to.

Next, the insulator 107d and the conductor 106d are partially removed by dry etching or the like using the mask 303 to form the insulator 107 and the conductor 106 (FIG.
See A). ).

As the conductive material for forming the conductor 106, aluminum, chromium, copper, silver,
A material containing at least one metal element selected from gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium and the like can be used. Alternatively, a semiconductor having high electric conductivity, which is typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used. As the conductor 106, a plurality of conductive layers formed of these materials may be stacked and used.

In addition, the conductor 106 is formed of indium tin oxide (ITO).
de), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, indium tin oxide containing silicon. It is also possible to apply a conductive material containing oxygen such as, and a conductive material containing nitrogen such as titanium nitride and tantalum nitride. Alternatively, a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are combined can be used. Alternatively, a stacked-layer structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined can be used. Alternatively, a stacked structure in which the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen are combined can be used. The thickness of the conductor 106 is preferably 10 nm or more and 500 nm or less, and 20 nm or more and 300 nm.
nm or less is more preferable, and 30 nm or more and 200 nm or less is further preferable. In this embodiment, as the conductive layer 126, a stack of titanium nitride and tungsten is used. Specifically, 150-nm-thick tungsten is formed over 10-nm-thick titanium nitride.

The method for forming the conductor 106 is not particularly limited, and various forming methods such as an evaporation method, a CVD method, and a sputtering method can be used.

[Metallic element 131]
Next, the metal element 131 is introduced using the conductor 106 and the insulator 107 as a mask (see FIG. 9C). Note that in FIG. 9C, the metal element 131 is indicated by an arrow. The metal element 131 can be introduced by an ion implantation method, a plasma doping method, or the like. In FIG. 9C, the end portion of the region 135 into which the metal element 131 is introduced is shown by a broken line. The depth of the region 135 into which the metal element is introduced and the concentration of the metal element contained in the region 135 can be determined by processing conditions such as an ion implantation method and a plasma doping method.

As the metal element 131, it is preferable to use one or more metal elements. For example, as the metal element 131, tungsten, aluminum, titanium, magnesium, vanadium,
One or more of the elements such as antimony, arsenic, and sulfur can be used.
The dose amount of the metal element 131 is 1×10 ¹² ions/cm ² or more and 1×10 ¹⁶ ions
/Cm ² or less, preferably 1×10 ¹³ ions/cm ² or more and 1×10 ¹⁵ ions/c
It may be m ² or less. The acceleration voltage at the time of introducing the metal element 131 may be 5 kV or more and 50 kV or less, preferably 10 kV or more and 30 kV or less. In this embodiment mode, tungsten is used as the metal element 131. When the metal element 131 is introduced using the conductor 106 and the insulator 107 as a mask, the region 135 can be formed adjacent to the channel formation region by self-alignment.

Here, when the metal element 131 is formed of a material such as tungsten or titanium that is easily bonded to oxygen, an oxide of the metal element 131 is formed, so that the metal element 131 is introduced into the oxide layer 104 in the region where the metal element 131 is introduced. Oxygen deficiency (also referred to as “Vo”) may increase. Note that when hydrogen is bonded to Vo to form VoH, the carrier density of the region is increased and the resistivity is decreased.

After the introduction of the metal element 131, heat treatment may be performed. The heat treatment is preferably 200°C
Or more and 500°C or less, more preferably 300°C or more and 450°C or less, further preferably 350
It suffices to carry out at a temperature of not lower than 400°C and not higher than 400°C. When hydrogen is bonded to Vo to form VoH by the heat treatment, carrier density in the region is further increased and resistivity is further reduced.

Therefore, the region 135 in the oxide layer 104 has higher carrier density and lower resistivity than a region (channel formation region) of the oxide layer 104 which overlaps with the conductor 106. Therefore, the region 135 in the oxide layer 104 may have lower resistance than a region (a channel formation region) of the oxide layer 104 which overlaps with the conductor 106.

In this embodiment mode, tungsten is used as the metal element 131. Further, it is introduced into part of the oxide layer 104 by an ion implantation method. The introduction of tungsten forms a region containing tungsten oxide in the oxide layer 104.

Next, the insulator 108d is formed over the insulator 105d and the insulator 107 (see FIG.
See C). ).

Next, the insulator 108d is etched by an anisotropic dry etching method to form the conductor 10
An insulator 108 is formed on the side wall of 6. At this time, a region of the insulator 105d which does not overlap with either the insulator 108 or the conductor 106 is also etched, so that the insulator 105 is formed.
Further, a region of the oxide layer 104f which does not overlap with either the insulator 108 or the conductor 106 is also etched, so that the oxide layer 104c is formed. Therefore, part of the oxide layer 104b is exposed when the insulator 108 is formed.

At this time, part of the exposed oxide layer 104b is etched, and the oxide layer 1 having a convex portion is formed.
04b may be formed. Here, FIGS. 20A and 20B show the transistor 100 in which a projection is formed in the oxide layer 104b. FIG. 20A is a plan view of the transistor 100. 20B is a dashed-dotted line L1 shown in FIG.
FIG. 6 is a cross-sectional view taken along -L2 line and one-dot chain line W1-W2.

[Insulator 107 and Insulator 108]
Here, when the insulator 108d is partly etched by the anisotropic dry etching method to form the insulator 108, the insulator 107 is preferably not etched. Alternatively, the etching rate of the insulator 107 is preferably lower than that of the insulator 108d. Therefore, the insulator 107 preferably contains a main element which is different from the main element of the insulator 108, for example. Alternatively, for example, the insulator 107 is, for example, the insulator 10
It is preferable that the composition is different from that of No. 8. The thickness of the insulator 107 is preferably 5 nm or more and 100 nm or less, and more preferably 10 nm or more and 50 nm or less.

Here, as an example, silicon oxide or silicon oxynitride is used as the insulator 108, and silicon nitride or silicon nitride oxide is used as the insulator 107. When the atomic ratio of nitrogen in the insulator 107 is higher than that in the insulator 108, the etching rate of the insulator 107 can be reduced in some cases when the insulator 108 is etched.

As a further example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride can be used for the insulator 108, and aluminum nitride, aluminum oxide, aluminum nitride oxide, or aluminum oxynitride can be used for the insulator 107. is there.

As a further example, when silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride is used as the insulator 108, the oxide layer 104 is used as the insulator 107.
In some cases, a material that can be used as

Here, the insulator 108d may be etched by an anisotropic dry etching method to form an insulator other than the sidewall of the conductor 106. For example, the oxide layer 104
In some cases, an insulator may be formed on the side wall of b.

Next, a conductor 109d is formed over the insulator 103, the oxide layer 104b, and the insulator 107.
Is formed (see FIG. 10B). Here, the conductor 109d preferably covers the side surface of the insulator 108. The thickness of the conductor 109d is preferably 5 nm or more and 500 nm or less, and 1
The thickness is more preferably 0 nm or more and 200 nm or less, further preferably 15 nm or more and 100 nm or less. In this embodiment, 20-nm-thick tungsten is used as the conductor 109d.

Alternatively, as the conductor 109d, titanium oxide having a thickness of 5 nm and a thickness of 20 nm on the titanium oxide are used.
nm, and a 5 nm thick titanium oxide film over tungsten may be used.

Next, part of the conductor 109d is removed using a mask to form a conductor 109e (see FIG. 10C). After that, the insulator 110d is formed (see FIG. 11A).

[Conductor 109a and Conductor 109b]
Next, the insulator 110d and the conductor 109 are flattened with respect to the substrate 101.
By removing part of e, the conductors 109a and 109b are formed (see FIG. 1).
See 1(B). ). By removing a part of the conductor 109e, the conductor 109d is removed.
By removing a region overlapping with the conductor 106, the conductor 109e can be separated and the conductor 109a and the conductor 109b can be formed.

Here, a polishing method such as a CMP method can be used to remove the insulator 110d and the conductor 109e. Alternatively, dry etching may be used. For example, a method such as etch back may be used.

When a polishing method such as a CMP method is used for removing the insulator 110d and the conductor 109e, the polishing rate of the conductor 109d and the insulator 110d may have a distribution in the surface of the sample. In this case, the exposure time of the insulator 107 may be long in a portion where the polishing rate is high. The polishing rate of the insulator 107 is preferably lower than that of the conductor 109e and the insulator 110d. Since the insulator 107 has a low polishing rate, the insulator 585 can serve as a polishing stopper film in the step of polishing the conductor 109d and the insulator 110d.

Here, in one embodiment of the present invention, for example, when a mask is formed by lithography, a position where the mask is formed may be displaced depending on accuracy of an apparatus for lithography. In such a case, a distance is generated between the ends of the conductors 109a and 109b and the ends of the insulator 108. On the other hand, in one embodiment of the present invention, the conductor 1
It is not necessary to use a mask or the like when forming 09a and the conductor 109b. Therefore, the area of the transistor 100 viewed from the top can be further reduced. By reducing the area of the transistor 100, integration of a circuit included in the semiconductor device can be realized.

The top surfaces of the insulator 110, the conductor 109a, the conductor 109b, the insulator 108, and the insulator 107 form a continuous flat surface. By forming the insulator 111 on the flat surface, for example, the coverage of the insulator 111 can be improved and hydrogen permeability can be further lowered, which is preferable. Further, since the blocking ability of the insulator 111 is improved, the insulator 111 may be thinned in some cases. By thinning the insulator 111, for example, when the opening is formed in the insulator 111 by dry etching or the like, the etching time can be shortened. If the etching time is too long, for example, the mask width may be reduced and the opening may become large, which makes it difficult to miniaturize. By shortening the etching time, for example, a finer opening can be provided, which is preferable.

As the conductors 109a and 109b, for example, a conductive material having a high embeddability such as tungsten or polysilicon can be used. In addition, the side surface and the bottom surface of the material may be covered with a barrier layer (diffusion prevention layer) formed of a titanium layer, a titanium nitride layer, or a stacked layer thereof. Further, for example, as shown in FIG. 3B, the conductor 109a has three layers of a conductor 109j, a conductor 109k, and a conductor 109l, the conductor 109b has a conductor 109m, and a conductor 1
09n and the conductor 109o may have a three-layer structure. Here, the conductor 109j
It is preferable that the conductor 109m is used as a barrier layer. Alternatively, the conductors 109l and 109o may be barrier layers. Here, when the conductors 109a and 109b function as electrodes, the barrier layer and the barrier layer may be referred to as electrodes.

Note that the conductor 109a and the conductor 109b are made of, for example, tungsten or titanium.
When a material having a property of extracting oxygen from the oxide layer 104 is used, Vo in the oxide layer 104 which is in contact with the conductors 109a and 109b is increased. Therefore, the oxide layer 104
In the region 135 formed in the above region, the carrier density of a region where the conductors 109a and 109b are in contact with each other is increased and the resistivity is decreased. Note that when hydrogen is bonded to Vo to form VoH, the carrier density in the region is further increased and the resistivity is further reduced.

Therefore, in the oxide layer 104, rather than the carrier density of a region overlapping with the insulator 108,
The carrier density in a region where the conductors 109a and 109b are in contact with each other may be high. In addition, in the oxide layer 104, the electric conductivity of the conductor 10 is higher than that of a region of the oxide layer 104 which overlaps with the insulator 108.
In some cases, the resistivity of the region where 9a and the conductor 109b are in contact is small. In addition, in the oxide layer 104, the resistance of a region where the conductors 109a and 109b are in contact with each other may be lower than the resistance of a region overlapping with the insulator 108.

Next, the insulator 111 is formed over the insulator 110, the conductor 109a, the conductor 109b, and the like (see FIG. 12A).

In this embodiment, as the insulator 111, aluminum oxide is formed by a sputtering method. Further, a gas containing oxygen is used as the sputtering gas. When the insulator 111 is formed by a sputtering method, a mixed layer which mixes the insulator 111 and the surface where the insulator 111 is formed and the vicinity thereof is formed. Specifically, the mixed layer 145 is formed at the interface between the insulator 110 and the insulator 111 and in the vicinity thereof.

In addition, the mixed layer 145 contains part of the sputtering gas. In this embodiment mode, since a gas containing oxygen is used as the sputtering gas, the mixed layer 145 contains oxygen.
Therefore, the mixed layer 145 has excess oxygen.

Next, heat treatment is performed. The heat treatment may be performed at 200 °C to 500 °C inclusive, more preferably 300 °C to 450 °C inclusive, and further preferably 350 °C to 400 °C inclusive. Note that the temperature of heat treatment performed at this time is lower than or equal to the temperature of heat treatment performed after the metal element 131 is introduced.

By the heat treatment, oxygen contained in the mixed layer 145 diffuses. Here, excess oxygen contained in the mixed layer 145 diffuses into the oxide layer 104a, the oxide layer 104b, and the oxide layer 104c through the insulator 110, the insulator 103, the insulator 108, the insulator 105, and the like. Insulator 1
11 and the insulator 102 are made of a material that does not easily transmit oxygen, so that excess oxygen contained in the mixed layer 145 is effectively diffused into the oxide layer 104b through the insulator 110, the insulator 103, and the like. You can FIG. 1 shows how excess oxygen contained in the mixed layer 145 diffuses.
2(B) is indicated by an arrow.

Next, the insulator 112 is formed over the insulator 111. Then, the insulator 112 and the insulator 11
1 and the insulator 110, an opening 307 reaching the conductor 109a and the like is formed (see FIG.
See A). ).

Next, a conductor is formed over the insulator 112 and in the opening 307, and part of the conductor is removed so that the top surface of the contact plug 113 is flattened with respect to the substrate 101, whereby the contact plug 113 is formed.
a, the contact plug 113b, and the contact plug 113c are formed (see FIG.
See B). ). A CMP method, for example, can be used to remove the conductor.

Contact plug 113a, contact plug 113b, and contact plug 11
As 3c, for example, a conductive material having a high embedding property such as tungsten or polysilicon can be used. Although not shown, the side surface and the bottom surface of the material may be covered with a barrier layer (diffusion prevention layer) formed of a titanium layer, a titanium nitride layer, or a stacked layer thereof. In this case, the barrier layer may also be referred to as an electrode.

The insulator 112 can be formed using a material and a method similar to those of the insulator 103. Also,
As the insulator 112, a heat-resistant organic material such as polyimide, acrylic resin, benzocyclobutene resin, polyamide, or epoxy resin can be used. In addition to the above organic material, a low dielectric constant material (low-k material), a siloxane resin, PSG (phosphorus glass), BPSG (phosphorus glass), or the like can be used. Note that the insulator 112 may be formed by stacking a plurality of insulators formed of these materials.

Note that a siloxane-based resin is a Si-O- formed using a siloxane-based material as a starting material.
It corresponds to a resin containing Si bonds. The siloxane-based resin may use an organic group (for example, an alkyl group or an aryl group) or a fluoro group as a substituent. Further, the organic group may have a fluoro group.

The method for forming the insulator 112 is not particularly limited, and may be a sputtering method or an SOG method depending on the material.
A method such as spin coating, dip coating, spray coating, droplet discharge method (ink jet method, etc.), printing method (screen printing, offset printing, etc.) may be used. By combining the baking step of the insulator 112 and another heat treatment step, a transistor can be efficiently manufactured.

Next, chemical mechanical polishing (CMP: Chemical Mechanical) is performed on the sample surface.
Polishing) processing (also referred to as "CMP processing") is performed (see FIG. 11A). By performing the CMP treatment, unevenness on the surface of the sample can be reduced and the coverage with an insulator or a conductive layer formed thereafter can be improved.

After that, the conductor 114a, the conductor 114b, and the conductor 114c are formed over the insulator 112, whereby the semiconductor device illustrated in FIG. 1 can be manufactured (see FIG. 14).

Note that the insulator 118, the insulator 105d, the insulator 110d, and the insulator 112 are deposited as follows.
The method for forming the insulator 103 can be referred to. In addition, the insulator 118, the insulator 105,
For the insulator 110 and the insulator 112, the material and structure shown as the insulator 103 can be used.

For the formation of the conductor 117d, the conductor 109d, the contact plugs 113a to 113c, and the conductors 114a to 114c, the conductor 106d can be referred to. Also, the conductor 1
The material and the structure shown as the conductor 106 can be used for 17, the conductor 109a, the conductor 109b, the contact plugs 113a to 113c, and the conductors 114a to 114c.

Here, in FIG. 9B, the metal element 131 is added before the insulator 108 is formed, but as shown in FIG. 15A, after the metal element 131 is added, the metal element 131 is added. Figure 1 before
An insulator 108d is formed as shown in FIG. 5A, then the insulator 108 is formed as shown in FIG. 15B, and then a metal element 131 is added as shown in FIG. 15C. You may. After that, the insulator 110, the conductor 109a, the conductor 109b, the insulator 111, and the insulator 11
2, the contact plug 113a, the conductor 114a, and the like are formed, and the semiconductor device shown in FIG. 16 can be manufactured. Here, in FIG. 16, as compared with the region under the insulator 108,
The concentration of the metal element 131 may increase in the region outside thereof.

<Production method 2>
Next, a method for manufacturing the semiconductor device illustrated in FIG. 2 is described with reference to FIGS.

Using the method shown in FIGS. 7A to 9A, the insulator 102, the insulator 118, the conductor 117, the insulator 103, the oxide layer 104a, the oxide layer 104b, and the oxide over the substrate 101 are formed. The material layer 104f, the insulator 105d, the conductor 106, and the insulator 107 are formed. After that, the insulator 105d and part of the oxide layer 104f are removed using the conductor 106 as a mask.
05 and the oxide layer 104c are formed (see FIG. 17A). In FIG. 17A, side surfaces of the oxide layer 104c, the insulator 105, the conductor 106, and the insulator 107 are preferably substantially aligned with each other.

Next, the metal element 131 is introduced using the conductor 106 and the insulator 107 as a mask (see FIG. 17B). In FIG. 17B, the metal element 131 is indicated by an arrow, and the metal element 1
The end of the region 135 into which 31 is introduced is shown by a broken line.

Next, the insulator 108d is formed over the oxide layer 104b, the insulator 103, and the insulator 107 (see FIG. 17C). Then, the conductor 10 is formed by anisotropic dry etching.
An insulator 108 is formed on the sidewall of 6 (see FIG. 18A). Here, the insulator 108d may be etched by an anisotropic dry etching method to form an insulator other than the sidewall of the conductor 106. FIG. 18A illustrates an example in which the insulator 108b is formed on the sidewall of the oxide layer 104b.

Next, the conductor 109a, the conductor 109b, the insulator 110, and the insulator 111 are formed using the method illustrated in FIGS. 10B to 12A (see FIG. 18B). ..

In this embodiment, as the insulator 111, aluminum oxide is formed by a sputtering method. Further, a gas containing oxygen is used as the sputtering gas. When the insulator 111 is formed by a sputtering method, a mixed layer which mixes the insulator 111 and the surface where the insulator 111 is formed and the vicinity thereof is formed. Specifically, the mixed layer 145 is formed at the interface between the insulator 110 and the insulator 111 and in the vicinity thereof.

In addition, the mixed layer 145 contains part of the sputtering gas. In this embodiment mode, since a gas containing oxygen is used as the sputtering gas, the mixed layer 145 contains oxygen.
Therefore, the mixed layer 145 becomes a layer containing excess oxygen.

Next, heat treatment is performed. The heat treatment may be performed at 200 °C to 500 °C inclusive, more preferably 300 °C to 450 °C inclusive, and further preferably 350 °C to 400 °C inclusive. Note that the temperature of heat treatment performed at this time is lower than or equal to the temperature of heat treatment performed after the metal element 131 is introduced.

By the heat treatment, oxygen contained in the mixed layer 145 diffuses. Here, excess oxygen contained in the mixed layer 145 passes through the insulator 110, the insulator 103, the insulator 108, and the like, and the oxide layer 10
4a, oxide layer 104b, and oxide layer 104c. By using a material that does not easily transmit oxygen as the insulator 111 and the insulator 102, excess oxygen contained in the mixed layer 145 is efficiently diffused into the oxide layer 104b through the insulator 110, the insulator 103, and the like. be able to. A state in which excess oxygen contained in the mixed layer 145 diffuses is shown by an arrow in FIG.

After that, the insulator 112, the contact plug 113a, the conductor 114a, and the like are formed, and
The semiconductor device shown in can be manufactured (see FIG. 19B).

<Structure 300>
In the formation of the conductors 109a and 109b illustrated in FIG.
On the other hand, part of the insulator 110d and the conductor 109e is removed so that the upper surface is flat. When a polishing method such as a CMP method is used to remove the insulator 110d and the conductor 109e, the polishing rate may have a distribution in the surface of the sample. In such a case, excessive polishing may occur at a portion having a high polishing rate, and the insulator 108, the insulator 107, and a part of the conductor 106 may be removed. Here, by arranging the structures such as the conductors 106 densely, it may be possible to suppress excessive polishing, which is preferable.

FIG. 22A illustrates an example of a cross section in the channel length direction of a semiconductor device including a structure 100d to be the transistor 100. Here, in FIG. 22A, in the insulator 110d, a difference in height between upper surfaces of a region where the structure 100d is provided and a region where the structure 100d is not provided is 311. Here, it is more preferable that the length 311 is small. Length 311
In some cases, the surface flatness of the insulator 110 obtained after the formation of the conductor 109a and the conductor 109b can be improved by making the value smaller.

The semiconductor device illustrated in FIG. 22B includes a structure body 100d serving as the transistor 100 and a structure body 300d serving as the structure body 300. The structure 300d is adjacent to the structure 100d. It is preferable that the semiconductor device include the structure body 300 because excessive polishing can be suppressed in the step of removing the insulator 110d and the conductor 109d.

The structure 100d preferably includes the conductor 106. Structure 300 (Structure 30
0d) may have the same structure as the transistor 100 (structure 100d). Or
The structure body 300 (structure body 300d) may include only some components of the transistor 100 (structure body 100d). In the example illustrated in FIG. 23, the structure 300d includes the conductor 109e, the conductor 106, the insulator 108, the insulator 107, and the insulator 1 among the components of the structure 100d.
05, the oxide layer 104c is included, and the oxide layer 104b and the oxide layer 104a are not included.

In addition, in FIG. 23, the structure 300d shows an example in which the insulator 103 does not have a convex portion. Alternatively, the protrusion of the insulator 103 of the structure 300d has the insulator 103 of the structure 100d.
The height may be smaller than that of the convex portion of the. Here, in FIG. 23, the insulator 110
In d, the difference in height between the upper surface of the region where the structure 100d is provided and the upper surface of the region where the structure 300d is provided is 314. When the semiconductor device has the structure 300d, the length 314 can be shorter than the length 311 illustrated in FIG. 22A, which is preferable.

The length between the conductor 106 included in the structure body 100d and the conductor 106 included in the structure body 300d is 312. Here, for example, the length 312 is 0.5 times or more and 10 times or less, or 1 time or more and 5 times or less, of the length 313 of the oxide layer 104b in the cross section in the channel direction of the transistor 100.

In addition, the structure 300 may not function as a semiconductor element in the semiconductor device.
For example, the structure 300 may not be connected to a wiring. Further, in a circuit included in the semiconductor device, a signal input to the circuit need not be electrically connected to the structure body 300. Note that the structure 300 may be referred to as a dummy pattern or a dummy element.

FIG. 24A illustrates an example of a semiconductor device including two structures 100d. Figure 24 (A)
24B by removing a part of the insulator 110d and the conductor 109d in FIG.
), two transistors 100 are obtained.

Here, in FIG. 24A, when the two structure bodies 100d are sparsely present, by removing a part of the insulator 110d and the conductor 109d, as shown in FIG. A recess may be formed in the insulator 110 between the two transistors 100. At this time, excessive polishing may occur and the insulator 108, the insulator 107, and part of the conductor 106 may be removed.

By forming one or a plurality of structure bodies 300d adjacent to the structure body 100d as illustrated in FIG. 25A, excessive polishing can be suppressed when the conductors 109a, 109b, and 110 are formed. Therefore, it is preferable (see FIG. 25B). Further, the surface of the insulator 110 can be made flatter, which is preferable. In addition, the upper surface of the insulator 110 and the conductor 1
09a and the upper ends of the conductors 109b may be able to substantially coincide with each other, which is preferable.

In addition, in FIG. 25C, the structure 300 includes a conductor 109 a, a conductor 109 b, and a conductor 1.
06, the insulator 108, the insulator 107, the insulator 105, and the oxide layer 104c are shown, but the oxide layer 104b and the oxide layer 104a are not provided. It is preferable to form one or a plurality of the structure bodies 300d because excessive polishing can be suppressed when the conductors 109a, 109b, and the insulator 110 are formed.

<Production method 3>
Next, a method for manufacturing the semiconductor device illustrated in FIGS. 6A to 6C will be described with reference to FIGS.

As shown in FIGS. 7A to 11B, the insulator 102 and the conductor 11 are formed on the substrate 101.
7, insulator 118, insulator 103, oxide layer 104a, oxide layer 104b, oxide layer 10
4c, the insulator 105, the conductor 106, the insulator 107, the insulator 108, the conductor 109e, the insulator 110, and the like are formed (see FIG. 26A).

Next, the opening 308 reaching the insulator 102 is formed in the insulator 110, the insulator 103, and the insulator 118 (see FIG. 26B).

Next, an insulator to be the insulator 110b is formed over the insulator 110 and inside the opening 308. After that, the upper surface of the insulator 110 is removed so that the upper surface of the insulator 110 is exposed in parallel to the substrate 101 and the insulator 110b is formed. After that, as illustrated in FIG. 26C, the insulator 111 is formed over the insulator 110 and the insulator 110b, whereby the semiconductor device illustrated in FIG. 6 can be manufactured.

At least part of this embodiment can be implemented in appropriate combination with any of the other embodiments described in this specification.

(Embodiment 3)
The oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single crystal oxide semiconductor other than the single crystal oxide semiconductor. As the non-single-crystal oxide semiconductor, CAAC-OS, polycrystalline oxide semiconductor, nc-O
S (nanocrystal Oxide Semiconductor), pseudo-amorphous oxide semiconductor (a-like OS: amorphous like Oxid)
e Semiconductor), an amorphous oxide semiconductor, and the like.

From another viewpoint, an oxide semiconductor is classified into an amorphous oxide semiconductor and a crystalline oxide semiconductor other than the amorphous oxide semiconductor. As the crystalline oxide semiconductor, a single crystal oxide semiconductor, CAAC-
There are an OS, a polycrystalline oxide semiconductor, an nc-OS, and the like.

As the definition of the amorphous structure, it is generally known that it is not fixed in a metastable state, isotropic, and does not have a heterogeneous structure. It can also be said that the structure has a flexible bond angle and short-range order, but no long-range order.

On the contrary, in the case of an oxide semiconductor which is essentially stable, it is completely amorphous.
It cannot be called a terry amorphous oxide semiconductor. In addition, an oxide semiconductor that is not isotropic (eg, has a periodic structure in a minute region) cannot be called a completely amorphous oxide semiconductor. However, although the a-like OS has a periodic structure in a minute region, it has a void (also referred to as a “void”) and has an unstable structure. Therefore, it can be said that the physical properties are close to those of an amorphous oxide semiconductor.

<CAAC-OS>
The CAAC-OS is one of oxide semiconductors having a plurality of c-axis aligned crystal parts (also referred to as “pellets”).

Transmission Electron Microscope (TEM)
composite image of the bright field image and the diffraction pattern of the CAAC-OS ("
Also referred to as "high-resolution TEM image". ), a plurality of pellets can be confirmed. On the other hand, in a high-resolution TEM image, a boundary between pellets, that is, a crystal grain boundary (also referred to as a “grain boundary”) cannot be clearly confirmed. Therefore, it can be said that in the CAAC-OS, electron mobility is less likely to be reduced due to the crystal grain boundaries.

The CAAC-OS observed by TEM will be described below. FIG. 27A shows a high-resolution TEM image of a cross section of the CAAC-OS observed from a direction substantially parallel to the sample surface.
Spherical aberration correction (Spherical Aberratio) was used to observe high-resolution TEM images.
nCorrector) function was used. A high-resolution TEM image using the spherical aberration correction function is particularly called a Cs-corrected high-resolution TEM image. Acquisition of a Cs-corrected high-resolution TEM image is performed, for example, by
This can be performed with an atomic resolution analysis electron microscope JEM-ARM200F manufactured by JEOL Ltd.

FIG. 27B shows a Cs-corrected high-resolution TEM image in which the region (1) of FIG. 27A is enlarged. From FIG. 27B, it can be confirmed that the metal atoms are arranged in layers in the pellet. The arrangement of each layer of metal atoms reflects unevenness on a surface (also referred to as a “formation surface”) on which a film of the CAAC-OS is formed or an upper surface, and is parallel to the formation surface or the top surface of the CAAC-OS. ..

As shown in FIG. 27B, the CAAC-OS has a characteristic atomic arrangement. Fig. 27 (C
) Indicates the characteristic atomic arrangement by an auxiliary line. 27(B) and 27(C
From (), it can be seen that the size of one pellet is 1 nm or more and that of 3 nm or more, and the size of the gap caused by the inclination between the pellets is about 0.8 nm.
Therefore, the pellet can also be called a nanocrystal (nc). In addition, CAAC-OS is replaced by CANC (C-Axis Aligned nanocr).
It can also be referred to as an oxide semiconductor having y stals).

Here, when the layout of the CAAC-OS pellets 5100 on the substrate 5120 is schematically shown based on the Cs-corrected high-resolution TEM image, a structure in which bricks or blocks are stacked is formed (FIG. 27D). reference.). The portion in which the pellets are tilted as observed in FIG. 27C corresponds to a region 5161 shown in FIG. 27D.

Further, in FIG. 28A, C of a plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface.
The s-corrected high-resolution TEM image is shown. Area (1), area (2), and area (3 in FIG. 28A)
28(B), FIG. 28(C) and FIG. 28(D) show Cs-corrected high resolution TEM images of FIG. From FIG. 28B, FIG. 28C, and FIG. 28D, it can be confirmed that the metal atoms in the pellet are arranged in a triangular shape, a quadrangular shape, or a hexagonal shape. However, there is no regularity in the arrangement of metal atoms between different pellets.

Next, C analyzed by X-ray diffraction (XRD:X-Ray Diffraction)
The AAC-OS will be described. For example, CAAC-O having a crystal of InGaZnO ₄
When S is subjected to a structural analysis by the out-of-plane method, a peak may appear near the diffraction angle (2θ) of 31° as shown in FIG. This peak is due to InGa
Since it belongs to the (009) plane of the ZnO ₄ crystal, it was confirmed that the CAAC-OS crystal has c-axis orientation and the c-axis is oriented substantially perpendicular to the formation surface or the top surface. it can.

Note that 2θ is 31 in structural analysis by the out-of-plane method of CAAC-OS.
In addition to the peak near 2°, a peak may appear near 2θ of around 36°. 2θ is 36°
The peak in the vicinity indicates that a part of the CAAC-OS contains a crystal having no c-axis alignment. More preferable CAAC-OS has a peak at 2θ of around 31° and a peak of 2θ at around 36° in a structural analysis by an out-of-plane method.

On the other hand, with respect to the CAAC-OS, in-pla which makes X-rays incident from a direction substantially perpendicular to the c-axis.
When structural analysis is performed by the ne method, a peak appears at 2θ of around 56°. This peak is I
It is assigned to the (110) plane of the crystal of nGaZnO ₄ . In the case of CAAC-OS, 2θ is 5
Even if the sample is fixed at around 6° and the analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), no clear peak appears as shown in FIG. 29(B). .. On the other hand, in the case of a single crystal oxide semiconductor of InGaZnO ₄ , 2θ is fixed at around 56° and φ
When scanned, as shown in FIG. 29C, six peaks belonging to a crystal plane equivalent to the (110) plane are observed. Therefore, from the structural analysis using XRD, it can be confirmed that the CAAC-OS has irregular a-axis and b-axis orientations.

Next, the CAAC-OS analyzed by electron diffraction will be described. For example, InGa
For the CAAC-OS having ZnO ₄ crystals, the probe diameter was 300 nm parallel to the sample surface.
When an electron beam of (1) is incident, a diffraction pattern (also referred to as a “selective field transmission electron diffraction pattern”) as shown in FIG. 30A may appear. In this diffraction pattern, InGaZn
A spot due to the (009) plane of the O ₄ crystal is included. Therefore, electron diffraction also shows that the pellets included in the CAAC-OS have c-axis orientation and the c-axis is oriented in a direction substantially perpendicular to the formation surface or the top surface. On the other hand, FIG. 30B shows a diffraction pattern when an electron beam having a probe diameter of 300 nm is incident on the same sample perpendicularly to the sample surface.
From FIG. 30B, a ring-shaped diffraction pattern is confirmed. Therefore, the electron diffraction also shows that the a-axis and the b-axis of the pellet included in the CAAC-OS do not have orientation. Note that the first ring in FIG. 30B is a (010) crystal of InGaZnO _4.
It is considered that this is due to the plane and the (100) plane. The second ring in FIG. 30B is considered to be derived from the (110) plane and the like.

As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Since the crystallinity of an oxide semiconductor may be lowered due to entry of impurities or generation of defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities or defects (such as oxygen vacancies) from the opposite viewpoint.

Note that the impurities are elements other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, and transition metal elements. For example, an element such as silicon which has a stronger bonding force with oxygen than a metal element forming the oxide semiconductor deprives the oxide semiconductor of oxygen, which disturbs the atomic arrangement of the oxide semiconductor and reduces crystallinity. It becomes a factor. Also, heavy metals such as iron and nickel, argon,
Carbon dioxide or the like has a large atomic radius (or a molecular radius), which disturbs the atomic arrangement of the oxide semiconductor and causes a decrease in crystallinity.

When the oxide semiconductor has impurities or defects, characteristics thereof may be changed by light, heat, or the like. For example, an impurity contained in the oxide semiconductor may serve as a carrier trap or a carrier generation source. Further, oxygen vacancies in the oxide semiconductor might serve as carrier traps or serve as carrier generation sources by capturing hydrogen.

The CAAC-OS with few impurities and oxygen vacancies is an oxide semiconductor with low carrier density. Specifically, it is less than 8×10 ¹¹ pieces/cm ³ , preferably less than 1×10 ¹¹ /cm ³ , more preferably less than 1×10 ¹⁰ pieces/cm ³ and 1×10 ⁻⁹ pieces/cm ^3. An oxide semiconductor having the above carrier density can be obtained. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. The CAAC-OS has a low impurity concentration and a low density of defect states. That is, it can be said that the oxide semiconductor has stable characteristics.

<nc-OS>
The nc-OS has a region where a crystal part can be confirmed and a region where a clear crystal part cannot be confirmed in a high-resolution TEM image. The crystal part included in the nc-OS often has a size of 1 nm to 10 nm inclusive, or 1 nm to 3 nm inclusive. Note that an oxide semiconductor in which the size of a crystal portion is greater than 10 nm and 100 nm or less is referred to as a microcrystalline oxide semiconductor in some cases. In the nc-OS, for example, in a high-resolution TEM image, crystal grain boundaries may not be clearly confirmed in some cases. Note that nanocrystals may have the same origin as pellets in CAAC-OS. Therefore, the crystal part of nc-OS may be called a pellet below.

The nc-OS has a periodic atomic arrangement in a minute region (for example, a region of 1 nm or more and 10 nm or less, particularly a region of 1 nm or more and 3 nm or less). Further, in the nc-OS, no regularity is found in the crystal orientation between different pellets. Therefore, no orientation is seen in the entire film. Therefore, the nc-OS may be indistinguishable from the a-like OS or the amorphous oxide semiconductor depending on the analysis method. For example, when an X-ray having a diameter larger than that of the pellet is used for nc-OS, a peak indicating a crystal plane is not detected by analysis by the out-of-plane method. Also, for nc-OS, a probe diameter larger than the pellet (for example, 50
When electron diffraction is performed using an electron beam of (nm or more), a diffraction pattern such as a halo pattern is observed. On the other hand, spots are observed when the nc-OS is subjected to nanobeam electron diffraction using an electron beam having a probe diameter close to or smaller than the pellet size. Also,
When nanobeam electron diffraction is performed on the nc-OS, a region with high luminance may be observed like a circle (in a ring shape). Further, a plurality of spots may be observed in the ring-shaped area.

Thus, since the crystal orientation does not have regularity between the pellets (nanocrystals), nc
-OS is an oxide semiconductor having RANC (Random Aligned nanocrystals), or NANC (Non-Aligned nanocrystals).
It can also be called an oxide semiconductor having s).

The nc-OS is an oxide semiconductor that has higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than the a-like OS or an amorphous oxide semiconductor. However, in the nc-OS, no regularity is found in the crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

<a-like OS>
The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. In the a-like OS, a void may be observed in a high resolution TEM image. Further, in a high-resolution TEM image, a region where a crystal part can be clearly confirmed,
And a region where the crystal part cannot be confirmed.

The a-like OS has an unstable structure because it has a void. In the following, a-lik
Since eOS has a more unstable structure than CAAC-OS and nc-OS, a structure change due to electron irradiation is shown.

As a sample for electron irradiation, a-like OS (referred to as sample A), nc-OS.
(Specified as sample B) and CAAC-OS (denoted as sample C) are prepared. All the samples are In-Ga-Zn oxides.

First, a high-resolution cross-sectional TEM image of each sample is acquired. It is understood from the high-resolution cross-sectional TEM images that each sample has a crystal part.

The determination as to which part is regarded as one crystal part may be performed as follows. For example, a unit cell of a crystal of InGaZnO ₄ has a structure in which three layers of In—O layers and six layers of Ga—Zn—O layers, nine layers in total, are layered in the c-axis direction. Are known. The spacing between these adjacent layers is about the same as the lattice spacing (also referred to as “d value”) of the (009) plane, and the value is determined to be 0.29 nm by crystal structure analysis. Therefore, a location where the lattice fringe spacing is 0.28 nm or more and 0.30 nm or less can be regarded as a crystal portion of InGaZnO ₄ . Note that the lattice fringes correspond to the ab plane of the InGaZnO ₄ crystal.

FIG. 31 is an example in which the average size of the crystal parts (22 to 45 points) of each sample was investigated. However, the length of the above-mentioned lattice stripes is the size of the crystal part. From FIG. 31, a-li
It can be seen that in the ke OS, the crystal part becomes larger according to the cumulative electron irradiation dose. Specifically, as shown by (1) in FIG. 31, a crystal part (also called “initial nucleus”) having a size of about 1.2 nm in the initial observation with TEM has a cumulative electron irradiation dose. Is 4.2×10
^It can be seen that at ⁸ e ⁻ /nm ² , it has grown to a size of about 2.6 nm. On the other hand, in the nc-OS and the CAAC-OS, the cumulative electron irradiation amount is 4.2× from the start of electron irradiation.
It can be seen that in the range up to 10 ⁸ e ⁻ /nm ² , there is no change in the size of the crystal part. Specifically, as shown by (2) and (3) in FIG. 31, regardless of the cumulative dose of electrons, n
The crystal part sizes of c-OS and CAAC-OS are about 1.4 nm and 2.
It can be seen that the thickness is about 1 nm.

As described above, in the a-like OS, crystal growth may be observed by electron irradiation. On the other hand, in the nc-OS and the CAAC-OS, it can be seen that almost no growth of crystal parts due to electron irradiation is observed. That is, a-like OS is nc-OS and CAAC-
It can be seen that the structure is unstable as compared with the OS.

Further, since it has a void, the a-like OS has a lower density than the nc-OS and the CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition. Also, the density of nc-OS and CAA
The density of C-OS is 92.3% or more and less than 100% of the density of a single crystal having the same composition. It is difficult to form an oxide semiconductor having a single crystal density of less than 78%.

For example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio],
The density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g/cm ³ . Therefore, for example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], the density of a-like OS is 5.0 g/cm ³ or more and less than 5.9 g/cm ^3. .. In addition, for example, in an oxide semiconductor satisfying In:Ga:Zn=1:1:1 [atomic ratio], the density of nc-OS and the density of CAAC-OS are 5.9 g/cm ³ or more and 6.3 g/cm ³ or more. cm
It becomes less than ³ .

Note that a single crystal with the same composition may not exist. In that case, by combining single crystals having different compositions at an arbitrary ratio, the density corresponding to a single crystal having a desired composition can be estimated. The density corresponding to a single crystal having a desired composition may be estimated by using a weighted average with respect to a ratio of combining single crystals having different compositions. However, it is preferable to estimate the density by combining as few kinds of single crystals as possible.

As described above, oxide semiconductors have various structures and have various characteristics.
Note that the oxide semiconductor is, for example, an amorphous oxide semiconductor, a-like OS, or nc-OS.
, CAAC-OS, a stacked film including two or more kinds may be used.

This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.

(Embodiment 4)
In this embodiment, an example of a semiconductor device including the transistor disclosed in this specification and the like will be described.

<<Structural example of semiconductor device>>
32A to 32C are cross-sectional views of the semiconductor device 400. Semiconductor device 40
0 has a transistor 100 and a transistor 281. Note that the transistor 100 can be replaced with any of the other transistors described in the above embodiments. 32A is a cross-sectional view in the channel length direction of the transistor 100 and the transistor 281, and FIG. 32B is a cross-sectional view in the channel width direction. 32C shows the transistor 28 in FIG.
It is an enlarged view of 1.

The semiconductor device 400 uses an n-type semiconductor as the substrate 401. The transistor 281 is
A channel forming region 283, a high concentration p-type impurity region 285, an insulator 286, a conductor 287,
It has a structure 288. Further, a low-concentration p-type impurity region 284 is provided in a region overlapping with the structure body 288 with the insulator 286 interposed therebetween. The insulator 286 can function as a gate insulating layer. The conductor 287 can function as a gate electrode. The transistor 281 has a channel formation region 283.
Are formed on a part of the substrate 401.

The low-concentration p-type impurity region 284 can be formed by forming an impurity element after the conductor 287 is formed and before the structure 288 is formed using the conductor 287 as a mask. That is, the low concentration p-type impurity region 284 can be formed by self-alignment. After the structure body 288 is formed, the high concentration p-type impurity region 285 is formed. The low-concentration p-type impurity region 284 has the same conductivity type as the high-concentration p-type impurity region 285, and the concentration of the impurity imparting the conductivity type is lower than that of the high-concentration p-type impurity region 285. Further, the low concentration p-type impurity region 284 is
It may not be provided depending on the situation.

The transistor 281 is electrically isolated from other transistors by the element isolation layer 414. The element isolation region is formed by LOCOS (Local Oxidation of S).
ilicon) method and STI method (Shallow Trench Isolation)
Etc. can be used.

The transistor 281 can function as a p-channel transistor. The insulator 403 is formed over the transistor 282, and the insulator 404 is formed over the insulator 403. The insulator 403 and the insulator 404 can be formed using a material and a method similar to those of the insulator 111. Note that the insulator 403 and the insulator 404 are preferably formed using an insulating material having a function of preventing diffusion of impurities such as oxygen, hydrogen, water, alkali metal, and alkaline earth metal. Note that either one of the insulator 403 and the insulator 404 may be omitted, or an insulating layer may be further stacked.

Further, the semiconductor device 400 includes the insulator 405 having a flat surface on the insulator 404. The insulator 405 can be formed using a material and a method similar to those of the insulator 112. Further, the surface of the insulator 405 may be subjected to CMP treatment.

In addition, a conductor 413a, a conductor 413b, and a conductor 413c are provided over the insulator 405.
Are formed. The conductor 413a, the conductor 413b, and the conductor 413c can be manufactured using a material and a method similar to those of the conductor 109a.

In addition, the conductor 413a has a high-concentration p-type impurity region 28 via the contact plug 406a.
5 is electrically connected to one side. The conductor 413b is electrically connected to the other of the high concentration p-type impurity regions 285 via the contact plug 406b. The conductor 413c is electrically connected to the conductor 287 through the contact plug 406c.

In addition, the insulator 407 is formed so as to cover the conductors 413a, 413b, and 413c.
Has been formed. The insulator 407 can be formed using a material and a method similar to those of the insulator 405. Further, the surface of the insulator 407 may be subjected to CMP treatment.

Further, the insulator 102 is formed over the insulator 407. The transistor 100 is formed over the insulator 102. The insulator 111 is formed over the transistor 100. The structure of a layer above the insulator 407 can be understood by considering the above embodiment. Therefore, detailed description in this embodiment will be omitted. The conductor 109b is electrically connected to the conductor 413b via the contact plug 112d.

<Modification 1>
An n-channel transistor may be provided over the substrate 401. 33A and 33B are cross-sectional views of the semiconductor device 410. The semiconductor device 410 is the semiconductor device 40.
0 has an n-channel transistor 282 added. 33A is a cross-sectional view of the transistor 100, the transistor 281, and the transistor 282 in the channel length direction, and FIG. 33B is an enlarged view of the transistor 281.

In the transistor 282, the channel formation region 1283 is formed in the well 220. The transistor 282 includes a channel formation region 1283, a high concentration n-type impurity region 1285,
It has an insulator 286, a conductor 287, and a structure 288. Further, a low concentration n-type impurity region 1284 is provided in a region overlapping with the structure body 288 with the insulator 286 interposed therebetween.

The low-concentration n-type impurity region 1284 can be formed by forming an impurity element after the conductor 287 is formed and before the structure 288 is formed using the conductor 287 as a mask.
That is, the low concentration n-type impurity region 1284 can be formed by self-alignment. After the structure body 288 is formed, the high concentration n-type impurity region 1285 is formed. The low-concentration n-type impurity region 1284 has the same conductivity type as the high-concentration n-type impurity region 1285, and the concentration of the impurity imparting the conductivity type is lower than that of the high-concentration n-type impurity region 1285. Further, the low concentration n-type impurity region 1284 may not be provided depending on the situation.

<Modification 2>
The transistor 100 may be further provided above the transistor 100. FIG. 34 shows
FIG. 6 is a cross-sectional view of the semiconductor device 420. The semiconductor device 420 includes a transistor 100a having the same structure as the transistor 100 over the semiconductor device 410. Also, the transistor 1
An insulator 111 a is provided on the surface 00.

The transistor 100a is provided over the insulator 112 with the insulator 407a interposed therebetween. Also,
Although not shown in FIG. 34, the insulator 112 and the insulator 103 included in the transistor 100a are included.
You may provide the insulator 102a between a and a. Insulator 407a, insulator 103a, insulator 1
02a and the insulator 111a can be provided using a material and a method similar to those of the insulator 407, the insulator 103, the insulator 102, and the insulator 111, respectively. Also, the transistor 1
00a can be manufactured similarly to the transistor 100.

In addition, the semiconductor device 420 includes a capacitor 141 and a capacitor 142. The one conductor 413c included in the capacitor 141 can be provided in the same layer as the conductors 413a and 413b by using part of a conductive layer for forming the conductors 413a and 413b. The other conductor 109c forming the capacitor 141 is the conductor 10c.
Part of the conductive layer for forming the conductor 9a and the conductor 109b can be used and provided in the same layer as the conductor 109a and the conductor 109b. The insulating layer sandwiched between the conductor 109c and the conductor 413c can function as a dielectric layer of the capacitor 141.

<Modification 3>
35A to 35C are cross-sectional views of the semiconductor device 430. Semiconductor device 430
Has a configuration in which the transistor 281 included in the semiconductor device 400 is replaced with a Fin-type transistor 291. By making the transistor a Fin type, the effective channel width is increased, and the on-characteristics of the transistor can be improved. Further, the contribution of the electric field of the gate electrode to the channel formation region can be increased, so that the off characteristics of the transistor can be improved.

In addition, the semiconductor device 430 is different from the semiconductor device 400 in that the capacitor 413 is provided above the transistor. The capacitor 413 includes a conductor 114b, a second conductor, and
And a conductor 114 and an insulator sandwiched between the second conductor and the conductor 114. Conductor 114b is insulator 1
12 are provided. The conductor 114b is connected to the conductor 109b functioning as a drain electrode or a source electrode of the transistor 100 through the contact plug 113b,
The conductor 109b is connected to the conductor 287 serving as a gate electrode of the transistor 291 through the contact plugs provided in the openings of the insulator 407, the insulator 102, and the insulator 118, the conductor 413b, and the like.

[Semiconductor circuit]
The transistors disclosed in this specification and the like include logic circuits such as an OR circuit, an AND circuit, a NAND circuit, and a NOR circuit, an inverter circuit, a buffer circuit, a shift register circuit, a flip-flop circuit, an encoder circuit, a decoder circuit, and an amplifier circuit. It can be used for various semiconductor circuits such as an analog switch circuit, an integrating circuit, a differentiating circuit, and a memory element.

In this embodiment, an example of a CMOS circuit or the like which can be used for a peripheral circuit and a pixel circuit is described with reference to FIGS. Note that in circuit diagrams and the like referred to in this specification and the like, “OS” is added to a circuit symbol of a transistor to which an OS transistor is preferably applied.

The CMOS circuit illustrated in FIG. 36A illustrates a configuration example of an inverter circuit in which a p-channel transistor 281 and an n-channel transistor 282 are connected in series and their gates are connected.

The CMOS circuit illustrated in FIG. 36B illustrates a structural example of an analog switch circuit in which a p-channel transistor 281 and an n-channel transistor 282 are connected in parallel.

The CMOS circuit illustrated in FIG. 36C includes a transistor 281a, a transistor 281b,
A configuration example of a NAND circuit including the transistor 282a and the transistor 282b is shown. The output potential of the NAND circuit changes depending on the combination of the potentials input to the input terminals IN_A and IN_B.

〔Storage device〕
The circuit illustrated in FIG. 37A illustrates a structural example of a memory device in which one of a source and a drain of the transistor 289 is connected to the gate of the transistor 1281 and one electrode of the capacitor 257. The circuit illustrated in FIG. 37B illustrates a structural example of a memory device in which one of a source and a drain of the transistor 289 is connected to one electrode of the capacitor 257.

In the circuits illustrated in FIGS. 37A and 37B, charge input from the other of the source and the drain of the transistor 289 can be held in the node 256. By using the OS transistor as the transistor 289, the charge of the node 256 can be held for a long time.

Although a p-channel transistor is shown as the transistor 1281 in FIG. 37A, an n-channel transistor may be used. For example, the transistor 281 or the transistor 282 may be used as the transistor 1281. Further, an OS transistor may be used as the transistor 1281.

Here, regarding the semiconductor device (memory device) illustrated in FIGS. 37A and 37B,
I will explain in detail.

A semiconductor device illustrated in FIG. 37A includes a transistor 1281 including a first semiconductor and a second semiconductor
The transistor 289 and the capacitor 257 each including the semiconductor of FIG.

The transistor 289 is the OS transistor disclosed in the above embodiment. Since the off-state current of the transistor 289 is small, stored data can be held in a specific node of the semiconductor device for a long time. That is, the refresh operation is not necessary or the frequency of the refresh operation can be extremely reduced, so that the semiconductor device has low power consumption.

In FIG. 37A, the wiring 251 is electrically connected to one of a source and a drain of the transistor 1281 and the wiring 252 is electrically connected to the other of the source and the drain of the transistor 1281. The wiring 253 is electrically connected to one of a source and a drain of the transistor 289 and the wiring 254 is electrically connected to a gate of the transistor 289. The gate of the transistor 1281, the other of the source and the drain of the transistor 289, and one of the electrodes of the capacitor 257 are electrically connected to the node 256. The wiring 255 is electrically connected to the other electrode of the capacitor 257.

The semiconductor device in FIG. 37A has a characteristic of being able to retain the charge applied to the node 256, and thus can write, retain, and read data as described below.

[Write operation, hold operation]
Writing and holding of information will be described. First, the potential of the wiring 254 is set to a potential at which the transistor 289 is turned on. Accordingly, the potential of the wiring 253 is changed to the node 256.
Given to. That is, a predetermined charge is applied to the node 256 (writing). here,
It is assumed that either one of the charges that gives two different potential levels (hereinafter, referred to as “Low level charge” and “High level charge”) is given. After that, the potential of the wiring 254 is set to a potential at which the transistor 289 is turned off, so that electric charge is held in the node 256.

Note that the high-level charge is a charge that gives a higher potential to the node 256 than the low-level charge. In the case where a p-channel transistor is used as the transistor 1281, both the high-level charge and the low-level charge are charges that give a potential higher than the threshold voltage of the transistor. In the case where an n-channel transistor is used as the transistor 1281, the high-level charge and the low-level charge are both potentials lower than the threshold voltage of the transistor. That is, high level charge and L
The ow level charge is charge that gives a potential for turning off the transistor.

Since the off-state current of the transistor 289 is extremely small, the charge of the node 256 is held for a long time.

[Read operation]
Next, reading of information will be described. In a state given the potential different from the predetermined potential of the wiring 252 (constant potential) to the wiring 251, given a read potential _{V R} to the wiring 255, the node 25
The information held in 6 can be read.

When the potential given by the High level charge is V _H and the potential given by the Low level charge is V _L , the read potential V _R is {(Vth−V _H )+(Vth+V _L )}/
You can set it to 2. Note that the potential of the wiring 255 when data is not read is higher than V _H when a p-channel transistor is used as the transistor 1281 and lower than V _L when an n-channel transistor is used as the transistor 1281. It may be a potential.

For example, when using a p-channel transistor in the transistor 1281, Vth of the transistor 1281 is -2 V, 1V and _{V H,} the the _{V L} and -1 V, the _{V R} -2
It should be V. When potential written to the node 256 is _{V H,} the _{V R} is applied to the wiring 255, the gate to _V R + _{V H} of the transistor 1281, i.e. -1V is applied. Since -1V is higher than Vth, the transistor 1281 is not turned on. Therefore, the potential of the wiring 252 does not change. Also, potential written to the node 256 when the _{V L,} when _{V R} is applied to the wiring 255, the gate of the transistor 1281 _V R + _{V L,} i.e. -3V is applied. Since -3V is lower than Vth, the transistor 1281 is turned on. Therefore, the potential of the wiring 252 changes.

In the case where an n-channel transistor is used as the transistor 1281, Vth of the transistor 1281 is 2V, V _R is 2V, and V _H is 1V and _VL is -1V. When potential written to the node 256 is _{V H,} the _{V R} is applied to the wiring 255, _V R + _{V H} to the gate of the transistor 1281, i.e. 3V is applied. Since 3V is higher than Vth, the transistor 1281 is turned on. Therefore, the potential of the wiring 252 changes. In addition, when the potential written in the node 256 is V _L , V is applied to the wiring 255.
_{When R} is given, V _R +V _L , that is, 1 V is applied to the gate of the transistor 1281. Since 1V is lower than Vth, the transistor 1281 is not turned on. Therefore, the potential of the wiring 252 does not change.

The information held in the node 256 can be read by determining the potential of the wiring 252.

The semiconductor device in FIG. 37B does not include the transistor 1281 in FIG.
Different from the semiconductor device shown in. In this case also, data can be written and held by the same operation as the semiconductor device illustrated in FIG.

Reading of information in the semiconductor device in FIG. 37B is described. Wiring 25
4 is supplied with a potential for turning on the transistor 289, the wiring 25 which is in a floating state
3 is electrically connected to the capacitor 257, and charges are redistributed between the wiring 253 and the capacitor 257. As a result, the potential of the wiring 253 changes. The amount of change in the potential of the wiring 253 is determined by the node 256.
Takes different values depending on the potential of (or the charge accumulated in the node 256).

For example, if the potential of the node 256 is V, the capacitance of the capacitor 257 is C, the capacitance component of the wiring 253 is CB, and the potential of the wiring 253 before the charge is redistributed is VB0, the charge is redistributed. The potential of the wiring 253 is (CB×VB0+C×V)/(CB+C). Therefore, assuming that the potential of the node 256 has two states of V1 and V0 (V1>V0) as the state of the memory cell, the potential of the wiring 253 (=(CB
It can be seen that ×VB0+C×V1)/(CB+C)) is higher than the potential of the wiring 253 (=(CB×VB0+C×V0)/(CB+C)) when the potential V0 is held.

Then, by comparing the potential of the wiring 253 with a predetermined potential, data can be read.

The semiconductor device described above can hold stored data for a long time by applying a transistor including an oxide semiconductor and having extremely low off-state current. That is, the refresh operation becomes unnecessary or the frequency of the refresh operation can be extremely reduced, so that a semiconductor device with low power consumption can be realized. Further, even when power is not supplied (however, the potential is preferably fixed), the stored content can be held for a long time.

In addition, the semiconductor device does not require high voltage for writing data, and thus deterioration of the element is less likely to occur. For example, unlike the conventional nonvolatile memory, since neither injection of electrons into the floating gate nor extraction of electrons from the floating gate is performed, the problem of deterioration of the insulator does not occur at all. That is, the semiconductor device according to one embodiment of the present invention is a semiconductor device in which there is no limitation on the number of rewritable times, which is a problem in the conventional nonvolatile memory, and the reliability is dramatically improved. Further, data is written depending on whether the transistor is on or off, which enables high-speed operation.

[CPU]
In this embodiment, a CPU will be described as an example of a semiconductor device including any of the above transistors. FIG. 38 is a block diagram showing a configuration example of a CPU partially using the above transistor.

The CPU shown in FIG. 38 has an ALU 1191 (ALU: Arithme) on the substrate 1190.
TIC logic unit (arithmetic circuit), ALU controller 1192, instruction decoder 1193, interrupt controller 1194, timing controller 1195, register 1196, register controller 1197, bus interface 1198 (Bus I/F), rewritable ROM 1199, and ROM interface 1189. (ROM I/F). The substrate 1190 is a semiconductor substrate, SOI
A substrate, a glass substrate, or the like is used. ROM 1199 and ROM interface 1189
May be provided on another chip. Of course, the CPU shown in FIG. 38 is merely an example in which the configuration is simplified and shown, and an actual CPU has various configurations depending on its application. For example, the configuration including the CPU or the arithmetic circuit illustrated in FIG. 38 may be one core, a plurality of the cores may be included, and each core may operate in parallel. The number of bits that the CPU can handle in the internal arithmetic circuit or the data bus is, for example, 8 bits, 16 bits, 32 bits, or 6 bits.
It can be 4 bits or the like.

The instruction input to the CPU via the bus interface 1198 is input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195.

The ALU controller 1192, the interrupt controller 1194, the register controller 1197, and the timing controller 1195 perform various controls based on the decoded instruction. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. Further, the interrupt controller 1194 determines and processes an interrupt request from an external input/output device or a peripheral circuit during execution of the program of the CPU based on its priority or mask state. The register controller 1197 generates the address of the register 1196, and reads or writes the register 1196 according to the state of the CPU.

Further, the timing controller 1195 includes the ALU 1191 and the ALU controller 11
92, a signal for controlling the timing of the operation of the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal based on the reference clock signal, and supplies the internal clock signal to the various circuits.

In the CPU shown in FIG. 38, a memory cell is provided in the register 1196. As the memory cell of the register 1196, the above transistor, the memory device, or the like can be used.

In the CPU shown in FIG. 38, the register controller 1197 selects a holding operation in the register 1196 according to an instruction from the ALU 1191. That is, register 1
In the memory cell of 196, selection is made between holding data by a flip-flop and holding data by a capacitor. When data holding by the flip-flop is selected, power supply voltage is supplied to the memory element in the register 1196. When data retention is selected in the capacitor, data is rewritten in the capacitor and supply of power supply voltage to the memory cell in the register 1196 can be stopped.

FIG. 39 is an example of a circuit diagram of a memory element that can be used as the register 1196. The storage element 730 includes a circuit 701 in which stored data is volatilized by powering off, a circuit 702 in which stored data is not volatized by powering off, a switch 703, a switch 704, and a logic element 706.
And a capacitor 707 and a circuit 720 having a selection function. The circuit 702 includes a capacitor 708, a transistor 709, and a transistor 710. Note that the memory element 730 may further include another element such as a diode, a resistor, or an inductor as needed.

Here, the memory device described above can be used for the circuit 702. When the supply of the power supply voltage to the memory element 730 is stopped, the ground potential (0 V) or the potential at which the transistor 709 is turned off is continuously input to the gate of the transistor 709 in the circuit 702. For example, the gate of the transistor 709 is grounded via a load such as a resistor.

The switch 703 is formed using a transistor 713 of one conductivity type (eg, n-channel type), and the switch 704 is formed using a transistor 714 of a conductivity type (eg, p-channel type) opposite to that of the transistor 713. Here is an example: Here, the first terminal of the switch 703 corresponds to one of the source and the drain of the transistor 713, the second terminal of the switch 703 corresponds to the other of the source and the drain of the transistor 713, and the switch 703 is the gate of the transistor 713. Depending on the control signal RD input to, the conduction or non-conduction between the first terminal and the second terminal (that is, the on state or the off state of the transistor 713) is selected. The first terminal of the switch 704 corresponds to one of the source and the drain of the transistor 714, the second terminal of the switch 704 corresponds to the other of the source and the drain of the transistor 714, and the switch 704 is input to the gate of the transistor 714. Depending on the control signal RD, the conduction or non-conduction between the first terminal and the second terminal (that is, the on state or the off state of the transistor 714) is selected.

One of a source and a drain of the transistor 709 is electrically connected to one of a pair of electrodes of the capacitor 708 and a gate of the transistor 710. Here, the connection portion is the node M2. One of a source and a drain of the transistor 710 is electrically connected to a wiring which can supply a low power supply potential (eg, a GND line), and the other is a switch 703.
Is electrically connected to the first terminal (one of a source and a drain of the transistor 713) of the.
A second terminal of the switch 703 (the other of the source and the drain of the transistor 713) is electrically connected to a first terminal of the switch 704 (one of the source and the drain of the transistor 714). The second terminal of the switch 704 (the other of the source and the drain of the transistor 714)
Is electrically connected to a wiring capable of supplying the power supply potential VDD. The second terminal of the switch 703 (the other of the source and the drain of the transistor 713) and the first terminal of the switch 704.
(A source and a drain of the transistor 714), an input terminal of the logic element 706, and one of a pair of electrodes of the capacitor 707 are electrically connected to each other. Here, the connection portion is assumed to be the node M1. The other of the pair of electrodes of the capacitor 707 can have a structure in which a constant potential is input. For example, low power supply potential (GND, etc.) or high power supply potential (
VDD or the like) may be input. The other of the pair of electrodes of the capacitor 707 is electrically connected to a wiring capable of supplying a low power supply potential (eg, a GND line). The other of the pair of electrodes of the capacitor 708 can have a structure in which a constant potential is input. For example, a low power supply potential (GND or the like) or a high power supply potential (VDD or the like) can be input. The other of the pair of electrodes of the capacitor 708 is electrically connected to a wiring that can supply a low power supply potential (eg, a GND line).

Note that the capacitor 707 and the capacitor 708 can be omitted by positively utilizing the parasitic capacitance or the like of a transistor or a wiring.

The control signal WE is input to the gate electrode of the transistor 709. The switch 703 and the switch 704 are connected to the first terminal and the second terminal by a control signal RD different from the control signal WE.
The conduction state or non-conduction state between the terminals of the switch is selected, and the first terminal and the second terminal of one switch are selected.
When the terminals of the other switch are in the conductive state, the first switch and the second terminal of the other switch are in the non-conductive state.

A signal corresponding to the data held in the circuit 701 is input to the other of the source and the drain of the transistor 709. In the example shown in FIG. 39, the signal output from the circuit 701 is input to the other of the source and the drain of the transistor 709. The signal output from the second terminal of the switch 703 (the other of the source and the drain of the transistor 713) is the logic element 7
The logical value is inverted by 06 to become an inverted signal, which is input to the circuit 701 through the circuit 720.

Note that in FIG. 39, a signal output from the second terminal of the switch 703 (the other of the source and the drain of the transistor 713) is supplied to the circuit 70 through the logic element 706 and the circuit 720.
Although an example of inputting 1 is shown, the present invention is not limited to this. The signal output from the second terminal of the switch 703 (the other of the source and the drain of the transistor 713) may be input to the circuit 701 without being inverted in logical value. For example, when there is a node in the circuit 701 in which a signal in which the logical value of the signal input from the input terminal is inverted is held, the switch 70
The signal output from the second terminal of the third terminal (the other of the source and the drain of the transistor 713) can be input to the node.

The transistor 709 in FIG. 39 corresponds to the transistor 15 illustrated in Embodiment Mode 1 above.
0 can be used. Further, the control signal WE can be input to the gate electrode and the control signal WE2 can be input to the back gate electrode. The control signal WE2 may be a signal having a constant potential. As the constant potential, for example, a ground potential GND, a potential smaller than the source potential of the transistor 709, or the like is selected. The control signal WE2 is a potential signal for controlling the threshold voltage of the transistor 709 and can further reduce the drain current of the transistor 709 when the gate voltage is 0V. Note that as the transistor 709, a transistor without the second gate can be used.

In addition, in FIG. 39, among the transistors used for the memory element 730, the transistors other than the transistor 709 are layers or a substrate 1190 formed using a semiconductor other than an oxide semiconductor.
The channel can be formed in the transistor. For example, it can be a transistor in which a channel is formed in a silicon layer or a silicon substrate. In addition, the storage element 7
All the transistors used for 30 can be transistors whose channels are formed using an oxide semiconductor layer. Alternatively, in the memory element 730, a transistor other than the transistor 709 is combined with a transistor whose channel is formed using an oxide semiconductor layer and a transistor whose channel is formed in a layer formed using a semiconductor other than an oxide semiconductor or the substrate 1190. You may use.

A flip-flop circuit can be used for the circuit 701 in FIG. 39, for example.
As the logic element 706, for example, an inverter, a clocked inverter, or the like can be used.

In the semiconductor device of one embodiment of the present invention, the data stored in the circuit 701 can be held in the node M2 by the capacitor 708 provided in the circuit 702 while the power supply voltage is not supplied to the memory element 730. ..

In addition, as described above, the transistor in which a channel is formed in the oxide semiconductor layer has extremely low off-state current. For example, the off-state current of a transistor whose channel is formed in an oxide semiconductor layer is significantly lower than the off-state current of a transistor whose channel is formed in crystalline silicon. Therefore, by using the transistor as the transistor 709, the signal held in the capacitor 708 can be kept for a long time even when the power supply voltage is not supplied to the memory element 730. In this way, the memory element 730 can retain the memory content (data) even while the supply of the power supply voltage is stopped.

Further, by providing the switch 703 and the switch 704, the time until the circuit 701 holds the original data again after the supply of power supply voltage is restarted can be shortened.

In addition, in the circuit 702, the signal held at the node M2 is input to the gate of the transistor 710. Therefore, after the supply of the power supply voltage to the memory element 730 is restarted, the signal held in the node M2 can be converted into the state of the transistor 710 (on state or off state) and read from the circuit 702. .. Therefore, the original signal can be accurately read even if the potential corresponding to the signal held in the node M2 is slightly changed.

By using such a memory element 730 in a memory device such as a register or a cache memory included in a CPU, data in the memory device can be prevented from being lost due to supply of power supply voltage being stopped. Moreover, after the supply of the power supply voltage is restarted, the state before the power supply is stopped can be restored in a short time. Therefore, power supply can be stopped for a short period of time in the entire CPU or one or a plurality of logic circuits included in the CPU, and the frequency of power supply stop can be increased, so that power consumption can be suppressed.

In this embodiment mode, the storage element 730 is described as an example of being used for the CPU, but the storage element 7
30 is a DSP (Digital Signal Processor), a custom LS
LSI such as I, PLD (Programmable Logic Device), RF
It can also be applied to a (Radio Frequency) tag.

[Imaging device]
An imaging device will be described as an example of a semiconductor device including the above transistor.

<Configuration Example of Imaging Device 600>
FIG. 40A is a plan view showing a configuration example of the imaging device 600. The imaging device 600 includes a pixel portion 621, a first circuit 260, a second circuit 270, a third circuit 280, and a fourth circuit 290. Note that in this specification and the like, the first circuit 260 to the fourth circuit 29 are included.
0 and the like may be referred to as “peripheral circuits” or “driving circuits”. For example, the first circuit 26
It can be said that 0 is a part of the peripheral circuit.

FIG. 40B is a diagram showing a configuration example of the pixel portion 621. The pixel portion 621 has p columns and q rows (
p and q have a plurality of pixels 622 (image pickup elements) arranged in a matrix of 2 or more natural numbers. Note that n in FIG. 40B is a natural number of 1 or more and p or less, and m is a natural number of 1 or more and q or less.

For example, when the pixels 622 are arranged in a 1920×1080 matrix, an imaging device 600 capable of imaging at a so-called full high-definition (also referred to as “2K resolution”, “2K1K”, “2K”, etc.) resolution is realized. You can Further, for example, the pixel 622 is set to 40
When arranged in a matrix of 96×2160, an image pickup device 6 capable of picking up images in a so-called ultra high-definition (also called “4K resolution”, “4K2K”, “4K”, etc.) resolution.
00 can be realized. Further, for example, when the pixels 622 are arranged in a matrix of 8192×4320, so-called super high-definition (“8K resolution”, “8K4K”,
Also known as "8K". It is possible to realize the image pickup apparatus 600 capable of picking up images with the resolution of (1). By increasing the number of display elements, it is possible to realize the image pickup apparatus 600 capable of picking up images at a resolution of 16K or 32K.

The first circuit 260 and the second circuit 270 have a function of connecting to the plurality of pixels 622 and supplying a signal for driving the plurality of pixels 622. In addition, the first circuit 260 may have a function of processing an analog signal output from the pixel 622. Further, the third circuit 280 may have a function of controlling operation timing of peripheral circuits. For example, it may have a function of generating a clock signal. Further, it may have a function of converting the frequency of a clock signal supplied from the outside. Further, the third circuit 280 may have a function of supplying a reference potential signal (for example, a ramp wave signal or the like).

The peripheral circuit includes at least one of a logic circuit, a switch, a buffer, an amplifier circuit, and a conversion circuit. In addition, transistors and the like used in the peripheral circuits are provided in the pixel drive circuit 6 described later.
It may be formed by using a part of a semiconductor formed for manufacturing 10. Further, part or all of the peripheral circuit may be mounted by a semiconductor device such as an IC.

Note that as the peripheral circuit, at least one of the first circuit 260 to the fourth circuit 290 may be omitted. For example, the function of one of the first circuit 260 and the fourth circuit 290 is added to the other of the first circuit 260 and the fourth circuit 290, and the first circuit 260 and the fourth circuit 290 are added.
One of the circuits 290 may be omitted. Further, for example, by adding the function of one of the second circuit 270 or the third circuit 280 to the other of the second circuit 270 or the third circuit 280,
One of the second circuit 270 and the third circuit 280 may be omitted. Also, for example, the first
Other peripheral circuits may be omitted by adding the function of the other peripheral circuit to any one of the circuits 260 to 290.

Further, as shown in FIG. 41, the first circuit 260 to the fourth circuit 290 may be provided along the outer periphery of the pixel portion 621. In addition, in the pixel portion 621 included in the imaging device 600, the pixel 6
22 may be arranged at an angle. By arranging the pixels 622 so as to be inclined, the pixel interval (pitch) in the row direction and the column direction can be shortened. Accordingly, the quality of the image captured by the image capturing device 600 can be further improved.

Further, as shown in FIG. 42, the pixel portion 621 may be provided so as to be stacked over the first circuit 260 to the fourth circuit 290. FIG. 42A is a top view of the imaging device 600 in which the pixel portion 621 is formed over the first circuit 260 to the fourth circuit 290. In addition, FIG. 42(B)
FIG. 43 is a perspective view for explaining the configuration of the image pickup apparatus 600 shown in FIG. 42(A).

By providing the pixel portion 621 over the first circuit 260 to the fourth circuit 290,
The area occupied by the pixel portion 621 with respect to the size of the imaging device 600 can be increased. Therefore, the light receiving sensitivity of the imaging device 600 can be improved. Moreover, the dynamic range of the imaging device 600 can be improved. In addition, the resolution of the imaging device 600 can be improved. In addition, the reproducibility of the image captured by the imaging device 600 can be improved. In addition, the degree of integration of the imaging device 600 can be improved.

[Color filters, etc.]
The pixel 622 included in the imaging device 600 is used as a sub-pixel, and a filter (color filter) that transmits light in different wavelength bands is provided in each of the plurality of pixels 622 to obtain information for realizing color image display. be able to.

FIG. 43A is a plan view illustrating an example of the pixel 623 for acquiring a color image.
FIG. 43A shows a pixel 62 provided with a color filter that transmits light in the red (R) wavelength range.
2 (hereinafter also referred to as “pixel 622R”), a pixel 622 (hereinafter also referred to as “pixel 622G”) provided with a color filter that transmits light in the green (G) wavelength range, and a blue (B) wavelength range The pixel 622 (hereinafter, also referred to as a “pixel 622B”) provided with a color filter which transmits the light of FIG. The pixel 622R, the pixel 622G, and the pixel 622B are combined into one pixel 623.
To function as.

Note that the color filter used for the pixel 623 is not limited to red (R), green (G), and blue (B), and a color filter that transmits cyan (C), yellow (Y), and magenta (M) light. May be used. Pixel 6 for detecting light of at least three different wavelength bands in one pixel 623
By providing 22, a full-color image can be acquired.

FIG. 43B shows a color filter which transmits yellow (Y) light in addition to the pixel 622 provided with color filters which transmit red (R), green (G) and blue (B) light, respectively. The pixel 623 including the pixel 622 provided with is illustrated. FIG. 43C shows a pixel 622 provided with a color filter which transmits cyan (C), yellow (Y), and magenta (M) light, and a color filter which transmits blue (B) light. The pixel 623 including the pixel 622 provided with is illustrated. By providing one pixel 623 with the pixels 622 that detect light of four or more different wavelength bands, the color reproducibility of the acquired image can be further improved.

Further, the pixel number ratio (or light receiving area ratio) of the pixels 622R, the pixels 622G, and the pixels 622B does not necessarily have to be 1:1:1. As shown in FIG. 43D, the pixel number ratio (
A Bayer arrangement in which the ratio of the light receiving area) is set to red:green:blue=1:2:1 may be adopted. Further, the pixel number ratio (light receiving area ratio) may be set to red:green:blue=1:6:1.

Although the number of pixels 622 used for the pixel 623 may be one, two or more are preferable. For example, by providing two or more pixels 622 that detect light in the same wavelength range, redundancy can be increased and the reliability of the imaging device 600 can be increased.

Further, by using an IR (IR: Infrared) filter that absorbs or reflects light having a wavelength equal to or shorter than the wavelength of visible light and transmits infrared light as a filter, an imaging device 600 that detects infrared light is realized. can do. Further, as a filter, UV (UV: Ultra Vio) which absorbs or reflects light having a wavelength of visible light or more and transmits ultraviolet light is transmitted.
By using the let) filter, it is possible to realize the imaging device 600 that detects ultraviolet light. Further, by using a scintillator that converts radiation into ultraviolet light or visible light as a filter, the imaging device 600 can also function as a radiation detector that detects X-rays, γ-rays, and the like.

In addition, when an ND (ND: Neutral Density) filter (darkening filter) is used as a filter, a phenomenon in which an output is saturated when a large amount of light enters a photoelectric conversion element (light receiving element) (hereinafter, referred to as “output Also referred to as “saturation”). By using a combination of ND filters with different light extinction amounts, the dynamic range of the image pickup device can be increased.

In addition to the filter described above, a lens may be provided in the pixel 622. Here, FIG.
An arrangement example of the pixel 622, the filter 624, and the lens 625 will be described with reference to the cross-sectional view of FIG. By providing the lens 625, incident light can be efficiently received by the photoelectric conversion element.
Specifically, as shown in FIG. 44A, light 660 is converted into photoelectric conversion element 601 through a lens 625 formed in a pixel 622, a filter 624 (filters 624R, 624G, 624B), a pixel driver circuit 610, and the like. The structure can be made to be incident on.

However, as shown in a region surrounded by a chain double-dashed line, a part of the light 660 indicated by an arrow is included in the wiring group 62.
The light may be shielded by a part of 6, the transistor, the capacitor, and/or the like. Therefore, as shown in FIG. 44B, a lens 625 and a filter 624 may be formed on the photoelectric conversion element 601 side so that the photoelectric conversion element 601 can efficiently receive incident light. By inputting the light 660 from the photoelectric conversion element 601 side, it is possible to provide the imaging device 600 having high light receiving sensitivity.

45A to 45C, a pixel driver circuit 6 that can be used for the pixel portion 621 is shown.
10 shows an example. A pixel driver circuit 610 illustrated in FIG. 45A includes a transistor 602, a transistor 604, and a capacitor 606, and is connected to the photoelectric conversion element 601. One of a source and a drain of the transistor 602 is electrically connected to the photoelectric conversion element 601, and the other of the source and the drain of the transistor 602 is electrically connected to a gate of the transistor 604 through a node 607 (charge storage portion). There is.

An OS transistor is preferably used as the transistor 602. The off-state current of the OS transistor can be extremely small, so that the capacitor 606 can be small. Alternatively, as illustrated in FIG. 45B, the capacitor 606 can be omitted.
When an OS transistor is used as the transistor 602, the potential of the node 607 does not easily change. Therefore, it is possible to realize an imaging device that is less likely to be affected by noise. Note that an OS transistor may be used as the transistor 604.

As the photoelectric conversion element 601, a diode element in which a pn-type or pin-type junction is formed in a silicon substrate can be used. Alternatively, a pin diode element or the like using an amorphous silicon film, a microcrystalline silicon film, or the like may be used. Alternatively, a diode-connected transistor may be used. Further, a variable resistor or the like utilizing the photoelectric effect may be formed using silicon, germanium, selenium, or the like.

Alternatively, the photoelectric conversion element may be formed using a material capable of absorbing radiation and generating electric charge. Materials capable of absorbing radiation and generating charges include lead iodide, mercury iodide, gallium arsenide, CdTe, CdZn, and the like.

A pixel driver circuit 610 illustrated in FIG. 45C includes a transistor 602 and a transistor 603.
, A transistor 604, a transistor 605, and a capacitor 606, which are connected to the photoelectric conversion element 601. Note that the pixel driver circuit 610 illustrated in FIG. 45C illustrates the case where a photodiode is used as the photoelectric conversion element 601. One of a source and a drain of the transistor 602 is electrically connected to a cathode of the photoelectric conversion element 601, and the other is electrically connected to a node 607. The anode of the photoelectric conversion element 601 is the wiring 611.
Is electrically connected to. One of a source and a drain of the transistor 603 is electrically connected to the node 607, and the other is electrically connected to the wiring 608. A gate of the transistor 604 is electrically connected to the node 607, one of a source and a drain is electrically connected to the wiring 609, and the other is electrically connected to one of a source and a drain of the transistor 605. The other of the source and the drain of the transistor 605 is the wiring 60
8 is electrically connected. One electrode of the capacitor 606 is electrically connected to the node 607 and the other electrode is electrically connected to the wiring 611.

The transistor 602 can function as a transfer transistor. The transfer signal TX is supplied to the gate of the transistor 602. The transistor 603 can function as a reset transistor. The reset signal RST is supplied to the gate of the transistor 603. The transistor 604 can function as an amplification transistor. The transistor 605 can function as a selection transistor. A selection signal SEL is supplied to the gate of the transistor 605. In addition, VDD is supplied to the wiring 608 and VSS is supplied to the wiring 611.

Next, operation of the pixel driver circuit 610 illustrated in FIG. 45C is described. First, the transistor 603 is turned on and VDD is supplied to the node 607 (reset operation). After that, when the transistor 603 is turned off, VDD is held in the node 607. Next, when the transistor 602 is turned on, the potential of the node 607 changes according to the amount of light received by the photoelectric conversion element 601 (accumulation operation). After that, when the transistor 602 is turned off, the potential of the node 607 is held. Next, when the transistor 605 is turned on, a potential corresponding to the potential of the node 607 is output from the wiring 609 (selection operation). Wiring 60
By detecting the potential of 9, the amount of light received by the photoelectric conversion element 601 can be known.

An OS transistor is preferably used for the transistors 602 and 603. As described above, the off-state current of the OS transistor can be extremely small, so that the capacitor 606 can be small. Alternatively, the capacitor 606 can be omitted. When OS transistors are used as the transistors 602 and 603, the potential of the node 607 is less likely to change. Therefore, it is possible to realize an imaging device that is less likely to be affected by noise.

Pixel 6 using any of the pixel driving circuits 610 shown in FIGS. 45A to 45C
By arranging 22 in a matrix, an imaging device with high resolution can be realized.

For example, when the pixel driving circuits 610 are arranged in a 1920×1080 matrix, so-called full high-definition (also called “2K resolution”, “2K1K”, “2K”, etc.).
It is possible to realize an image pickup apparatus capable of picking up images with the resolution of. Also, for example, the pixel drive circuit 6
By arranging 10 in a matrix of 4096×2160, it is possible to realize an image pickup apparatus capable of picking up an image with a so-called ultra high-definition (also called “4K resolution”, “4K2K”, “4K”, etc.) resolution. In addition, for example, the pixel drive circuit 610 is set to 8192×43.
When arranged in a matrix of 20, so-called Super Hi-Vision (“8K resolution”, “
It is also called "8K4K", "8K", etc. It is possible to realize an image pickup apparatus capable of picking up an image with the resolution (1). By increasing the number of display elements, it is possible to realize an image pickup device capable of picking up an image with a resolution of 16K or 32K.

FIG. 46 shows a structural example of the pixel 622 using the above transistor. FIG. 46 shows a pixel 62
2 is a partial cross-sectional view of FIG.

A pixel 622 shown in FIG. 46 uses an n-type semiconductor as the substrate 401. Also, the substrate 4
01, the p-type semiconductor 221 of the photoelectric conversion element 601 is provided. Further, a part of the substrate 401 functions as the n-type semiconductor 223 of the photoelectric conversion element 601.

The transistor 604 is provided over the substrate 401. Transistor 604 is n
It can function as a channel transistor. Further, a p-type semiconductor well 220 is provided in a part of the substrate 401. The well 220 can be provided by a method similar to that for forming the p-type semiconductor 221. Further, the well 220 and the p-type semiconductor 221 can be formed simultaneously. Note that the transistor 282 described above can be used as the transistor 604, for example.

In addition, the insulator 403 and the insulator 40 are provided over the photoelectric conversion element 601 and the transistor 604.
4 and the insulator 405 are formed. Substrate 401 of insulators 403 to 405
The opening 224 is formed in a region overlapping with the (n-type semiconductor 223), and the insulators 403 to 4 are formed.
An opening 225 is formed in a region overlapping with the p-type semiconductor 221 of 05. Also, the opening 224
A contact plug 406 is formed in the opening 225. Contact plug 40
6 can be provided similarly to the contact plug 113a described above. Absolutely, opening 22
4 and the openings 225 are not particularly limited in the number and arrangement thereof. Therefore, it is possible to realize an imaging device having a high degree of freedom in layout.

Further, a conductor 421, a conductor 422, and a conductor 429 are formed over the insulator 405. The conductor 421 is electrically connected to the n-type semiconductor 223 (substrate 401) via the contact plug 406 provided in the opening 224. Further, the conductor 429 is electrically connected to the p-type semiconductor 221 through the contact plug 406 provided in the opening 225. The conductor 422 can function as one electrode of the capacitor 606.

An insulator 407 is formed so as to cover the conductor 421, the conductor 429, and the conductor 422. The insulator 407 can be formed using a material and a method similar to those of the insulator 405. Further, the surface of the insulator 407 may be subjected to CMP treatment. By performing the CMP treatment, unevenness on the surface of the sample can be reduced and coverage with an insulating layer or a conductive layer formed thereafter can be improved. The conductor 421, the conductor 422, and the conductor 429 are the conductor 114a described above.
It can be formed by the same material and method.

In addition, the insulator 102 is formed over the insulator 407, and the conductor 427 is formed over the insulator 102.
, A conductor 119, and an electrode 273 are formed. The conductor 427 is electrically connected to the conductor 429 through a contact plug. The conductor 119 is a transistor 602.
Can function as a back gate for. The electrode 273 can function as the other electrode of the capacitor 606. As the transistor 602, for example, the above-described transistor 100 can be used.

In addition, the conductor 109a is electrically connected to the conductor 427 through a contact plug.

<Modification 1>
FIG. 47 shows a configuration example of the pixel 622 different from that in FIG. FIG. 47 is a cross-sectional view of part of the pixel 622.

A pixel 622 shown in FIG. 47 includes a transistor 604 and a transistor 605 over a substrate 401.
Is provided. The transistor 604 can function as an n-channel transistor. The transistor 605 can function as a p-channel transistor. Note that the transistor 282 described above can be used as the transistor 604, for example. As the transistor 605, the above-described transistor 281 can be used, for example.

Conductors 413a to 413d are formed over the insulator 405. Conductor 41
3a is electrically connected to one of a source and a drain of the transistor 604,
13b is electrically connected to the other of the source and the drain of the transistor 604.
The conductor 413c is electrically connected to the gate of the transistor 604. Conductor 41
3b is electrically connected to one of a source and a drain of the transistor 605,
13d is electrically connected to the other of the source and the drain of the transistor 605.

The conductor 109b and the conductor 413c are electrically connected via the contact plug 112d. In addition, the insulator 4 is formed on the conductor 114a, the conductor 114b, and the insulator 112.
15 is formed. The insulator 415 can be formed using a material and a method similar to those of the insulator 111.

Further, in the pixel 622 illustrated in FIG. 47, the photoelectric conversion element 601 is provided over the insulator 415. In addition, an insulator 442 is provided over the photoelectric conversion element 601, and a conductor 488 is provided over the insulator 442. The insulator 442 can be formed using a material and a method similar to those of the insulator 415.

The photoelectric conversion element 601 illustrated in FIG. 47 includes a photoelectric conversion layer 681 between a conductor 686 formed of a metal material or the like and a light-transmitting conductive layer 682. In FIG. 47, a mode in which a selenium-based material is used for the photoelectric conversion layer 681 is shown. The photoelectric conversion element 601 using a selenium-based material has characteristics of high external quantum efficiency with respect to visible light. The photoelectric conversion element can be a highly sensitive sensor in which the amplification of electrons with respect to the amount of light incident due to the avalanche phenomenon is large.
Further, since the selenium-based material has a high light absorption coefficient, it has an advantage that the photoelectric conversion layer 681 can be easily thinned.

Amorphous selenium or crystalline selenium can be used as the selenium-based material. Crystalline selenium can be obtained, for example, by heat treatment after forming amorphous selenium into a film. By making the crystal grain size of the crystalline selenium smaller than the pixel pitch, it is possible to reduce the characteristic variation among the pixels. Further, crystalline selenium has characteristics such as higher spectral sensitivity to visible light and a higher light absorption coefficient than amorphous selenium.

Although the photoelectric conversion layer 681 is illustrated as a single layer, gallium oxide, cerium oxide, or the like is provided as a hole injection blocking layer on the light-receiving surface side of the selenium-based material and oxidation is performed as an electron injection blocking layer on the conductor 686 side. Alternatively, nickel, antimony sulfide, or the like may be provided.

The photoelectric conversion layer 681 may be a layer containing a compound of copper, indium, and selenium (CIS). Alternatively, it may be a layer containing a compound of copper, indium, gallium, and selenium (CIGS). With CIS and CIGS, it is possible to form a photoelectric conversion element that can utilize the avalanche phenomenon as in the case of a single layer of selenium.

Further, CIS and CIGS are p-type semiconductors, and n-type semiconductors such as cadmium sulfide and zinc sulfide may be provided in contact with each other in order to form a junction.

In order to generate the avalanche phenomenon, a relatively high voltage (for example, 1
It is preferable to apply 0 V or more). Since the OS transistor has a higher drain breakdown voltage than the Si transistor, it is easy to apply a relatively high voltage to the photoelectric conversion element. Therefore, by combining an OS transistor having a high drain breakdown voltage and a photoelectric conversion element including a selenium-based material as a photoelectric conversion layer, an imaging device with high sensitivity and high reliability can be obtained.

The light-transmitting conductive layer 682 includes, for example, indium tin oxide, indium tin oxide containing silicon, indium oxide containing zinc, zinc oxide, zinc oxide containing gallium, zinc oxide containing aluminum, tin oxide, or fluorine. Tin oxide containing, tin oxide containing antimony, graphene, or the like can be used. The light-transmitting conductive layer 682 is not limited to a single layer and may be a stack of different films. Further, in FIG. 47, the light-transmitting conductive layer 682 and the wiring 487 are connected to the conductor 48.
8 and the structure in which they are electrically connected via the contact plugs 489 are illustrated, the translucent conductive layer 682 and the wiring 487 may be in direct contact with each other.

Further, the conductor 686, the wiring 487, and the like may have a structure in which a plurality of conductive layers is stacked. For example, the conductor 686 has two layers of a conductor 686a and a conductor 686b, and a wiring 487 is provided.
Can have two layers of a conductor 487a and a conductor 487b. Also, for example, the conductor 6
86a and the conductor 487a are preferably formed by selecting a metal or the like having low resistance, and the conductors 686b and 487b are preferably formed by selecting a metal or the like having good contact characteristics with the photoelectric conversion layer 681. With such a structure, the electrical characteristics of the photoelectric conversion element can be improved. Further, some metal may cause electrolytic corrosion by coming into contact with the light-transmitting conductive layer 682. Even when such a metal is used for the conductor 487a, electrolytic corrosion can be prevented by interposing the conductor 487b.

For the conductor 686b and the conductor 487b, molybdenum, tungsten, or the like can be used, for example. For the conductor 686a and the conductor 487a, for example, aluminum, titanium, or a stack in which aluminum is sandwiched by titanium can be used.

Alternatively, the insulator 442 may have a multi-layer structure. The partition 477 can be formed using an inorganic insulator, an insulating organic resin, or the like. Further, the partition wall 477 may be colored in black or the like in order to shield the transistor or the like from light and/or to determine the area of the light receiving portion per pixel.

Further, for the photoelectric conversion element 601, a p-type using an amorphous silicon film, a microcrystalline silicon film, or the like is used.
You may use an in-type diode element etc. The photodiode has a structure in which an n-type semiconductor layer, an i-type semiconductor layer, and a p-type semiconductor layer are sequentially stacked. Amorphous silicon is preferably used for the i-type semiconductor layer. For the p-type semiconductor layer and the n-type semiconductor layer, amorphous silicon or microcrystalline silicon containing a dopant imparting each conductivity type can be used. A photodiode including amorphous silicon as a photoelectric conversion layer has high sensitivity in a visible light wavelength region and easily detects weak visible light.

The pn-type or pin-type diode element is preferably provided so that the p-type semiconductor layer serves as the light receiving surface. By using the p-type semiconductor layer as the light-receiving surface, the output current of the photoelectric conversion element 601 can be increased.

The photoelectric conversion element 601 formed using the above-described selenium-based material or amorphous silicon is
It can be manufactured by using a general semiconductor manufacturing process such as a film forming process, a lithographic process, and an etching process.

[Display device]
A display device will be described as an example of a semiconductor device including the above transistor.
A display device (a liquid crystal display device, a light-emitting display device, or the like) which is a device including a display element can have various modes or can have various elements.

The display device includes, for example, EL (electroluminescence) elements (EL elements including organic and inorganic materials, organic EL elements, inorganic EL elements), LED chips (white LED chips, red LED chips, green LED chips, blue LED chips, etc.). , Transistors (transistors that emit light in response to current), electron-emitting devices, display devices using carbon nanotubes, liquid crystal devices, electronic inks, electrowetting devices, electrophoretic devices, MEMS (micro electro mechanical systems). Display elements used (eg, grating light valve (GLV), digital micromirror device (DMD), DMS (digital microshutter), MIRASOL (registered trademark), IMOD (interference modulation) element, shutter type) MEMS display device, optical interference type ME
MS display element, piezoelectric ceramic display, etc.), or quantum dots.

In addition to these, the display device also has contrast, brightness, and
It may have a display medium whose reflectance and transmittance change. For example, the display device may be a plasma display (PDP).

An EL display or the like is an example of a display device using an EL element. As an example of a display device using an electron-emitting device, a field emission display (FED) or a SED type flat display (SED: Surface-conduction) is used.
Electron-emitter Display).

An example of a display device using quantum dots for each pixel is a quantum dot display. Note that the quantum dots may be provided not in a display element but in a part of a backlight used for a liquid crystal display device or the like. By using quantum dots, display with high color purity can be performed.

As an example of a display device using a liquid crystal element, a liquid crystal display device (transmissive liquid crystal display,
There is a transflective liquid crystal display, a reflective liquid crystal display, a direct-view liquid crystal display, a projection liquid crystal display) and the like.

In the case of realizing a semi-transmissive liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrodes may have a function as a reflective electrode. For example, part or all of the pixel electrode may include aluminum, silver, or the like. Further, in that case, a memory circuit such as SRAM can be provided below the reflective electrode. Thereby, the power consumption can be further reduced.

An example of a display device using electronic ink, electronic powder fluid (registered trademark), or an electrophoretic element is electronic paper.

Note that when an LED chip is used for a display element or the like, graphene or graphite may be arranged below the electrode of the LED chip or the nitride semiconductor. Graphene or graphite may be formed into a multilayer film by stacking a plurality of layers. By providing graphene or graphite in this manner, a nitride semiconductor, for example, an n-type GaN semiconductor layer having a crystal or the like can be easily formed thereover. Further, a p-type GaN semiconductor layer having crystals or the like may be provided thereon to form an LED chip. In addition, with graphene and graphite,
An AlN layer may be provided between the crystal and the n-type GaN semiconductor layer. The GaN semiconductor layer of the LED chip may be formed by MOCVD. However, the GaN semiconductor layer included in the LED chip can be formed by a sputtering method by providing graphene.

In addition, in a display element using MEMS, a space in which the display element is sealed (for example, between an element substrate on which the display element is arranged and a counter substrate which faces the element substrate). Alternatively, a desiccant may be placed. By disposing the desiccant, it is possible to prevent the MEMS and the like from becoming difficult to move due to moisture and from easily becoming deteriorated.

<Pixel circuit configuration example>
Next, a more specific configuration example of the display device will be described with reference to FIG. Figure 48 (A
10] is a block diagram for explaining the configuration of the display device 3100. The display device 3100 includes a display area 3131, a circuit 3132, and a circuit 3133. The circuit 3132 functions as a scan line driver circuit, for example. The circuit 3133 functions as a signal line driver circuit, for example.

In addition, the display device 3100 is provided substantially in parallel with each other, and each of the m scanning lines 3135 whose potential is controlled by the circuit 3132 is provided in parallel with each other, and the circuit 3133 is provided.
And n signal lines 3136 whose potential is controlled by. Furthermore, the display area 313
1 has a plurality of pixels 3130 arranged in a matrix of m rows and n columns. Note that both m and n are natural numbers of 2 or more.

In the display region 3131, each scan line 3135 is electrically connected to the n pixels 3130 arranged in any row of the pixels 3130. In addition, each signal line 3136 is electrically connected to the m pixels 3130 arranged in any column of the pixels 3130.

Further, as illustrated in FIG. 49A, the circuit 3152 may be provided at a position facing the circuit 3132 with the display region 3131 provided therebetween. In addition, as shown in FIG.
The circuit 3153 may be provided at a position facing the circuit 3133 with 31 interposed therebetween. Fig. 49 (A
) And FIG. 49B show an example in which the circuit 3152 is connected to the scan line 3135 similarly to the circuit 3132. However, not limited to this, for example, the circuit 3 connected to the scanning line 3135
132 and the circuit 3152 may be changed every few rows. In FIG. 49B, an example in which the circuit 3153 is connected to the signal line 3136 similarly to the circuit 3133 is shown. However, not limited to this, for example, the circuit 3133 and the circuit 3153 connected to the signal line 3136 may be changed every few rows.
In addition, the circuit 3132, the circuit 3133, the circuit 3152, and the circuit 3153 are connected to the pixel 3130.
It may have a function other than driving.

Further, the circuit 3132, the circuit 3133, the circuit 3152, and the circuit 3153 may be referred to as a driver circuit portion. The pixel 3130 has a pixel circuit 3137 and a display element. The pixel circuit 3137 is a circuit which drives a display element. The transistor included in the driver circuit portion can be formed at the same time as the transistor included in the pixel circuit 3137. Alternatively, part or all of the driver circuit portion may be formed over another substrate and electrically connected to the display device 3100. For example, part or all of the driver circuit portion is formed using a single crystal substrate, and the display device 3100
May be electrically connected to.

48B and 48C each show a circuit structure which can be used for the pixel 3130 of the display device 3100.

<<Example of pixel circuit for light emitting display device>>
FIG. 48B shows an example of a pixel circuit which can be used for the light emitting display device. Fig. 48 (B
The pixel circuit 3137 shown in FIG. 4B includes a transistor 3431, a capacitor 3233, a transistor 3232, and a transistor 3434. The pixel circuit 3137 is electrically connected to the light emitting element 3125 which can function as a display element.

One of a source electrode and a drain electrode of the transistor 3431 is electrically connected to the n-th column signal line 3136 (hereinafter referred to as a signal line DL_n) to which a data signal is applied. Further, the gate electrode of the transistor 3431 is connected to the m-th scanning line 3 to which a gate signal is applied.
135 (hereinafter referred to as the scanning line GL_m).

The transistor 3431 has a function of controlling writing of a data signal to the node 3435.

One of a pair of electrodes of the capacitor 3233 is electrically connected to the node 3435, and the other is electrically connected to the node 3437. The other of the source electrode and the drain electrode of the transistor 3431 is electrically connected to the node 3435.

The capacitor 3233 has a function as a storage capacitor which holds data written in the node 3435.

One of a source electrode and a drain electrode of the transistor 3232 has a potential supply line VL_a.
, And the other is electrically connected to node 3437. Further, the gate electrode of the transistor 3232 is electrically connected to the node 3435.

One of a source electrode and a drain electrode of the transistor 3434 has a potential supply line VL_c.
, And the other is electrically connected to node 3437. Further, the gate electrode of the transistor 3434 is electrically connected to the scan line GL_m.

One of an anode and a cathode of the light emitting element 3125 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the node 3437.

As the light emitting element 3125, for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used. However, the invention is not limited to this, and for example, an inorganic EL element made of an inorganic material may be used.

For example, the potential supply line VL_a has a function of supplying VDD. In addition, the potential supply line VL
_B has a function of supplying VSS. Further, the potential supply line VL_c has a function of supplying VSS.

Here, an operation example of a display device including the pixel circuit 3137 in FIG. 48B is described. First, the pixel circuit 3137 in each row is sequentially selected by the circuit 3132, and the transistor 3
The data signal (potential) is written to the node 3435 by turning on 431. Next, the transistor 3434 is turned on and the potential of the node 3437 is set to VSS.

After that, the transistor 3431 is turned off and the data signal written to the node 3435 is held. Next, the transistor 3434 is turned off. Transistor 3232
The amount of current flowing between the source and the drain of the node is determined according to the data signal written in the node 3435. Therefore, the light emitting element 3125 emits light with a luminance according to the amount of flowing current. An image can be displayed by sequentially performing this for each row.

Further, a plurality of pixels 3130 are used as sub-pixels, and light of different wavelength bands is emitted from each sub-pixel, whereby a color image can be displayed. For example, the pixel 3130 that emits light in the red wavelength range, the pixel 3130 that emits light in the green wavelength range, and the pixel 3130 that emits light in the blue wavelength range are used as one pixel.

The wavelength range of the combined light is not limited to red, green, and blue, and may be cyan, yellow, and magenta. A color image can be displayed by providing one pixel with subpixels which emit light of at least three different wavelength bands.

Further, one or more of yellow, cyan, magenta, white, etc. may be added to red, green, and blue. For example, in addition to red, green, and blue, subpixels that emit light in the yellow wavelength range may be added. Further, one or more of red, green, blue, white, etc. may be added to cyan, yellow, and magenta. For example, in addition to cyan, yellow, and magenta, subpixels that emit light in the blue wavelength range may be added. By providing one pixel with sub-pixels that emit light in four or more different wavelength ranges,
The color reproducibility of the displayed image can be further enhanced.

Further, the ratio of the numbers of red, green, and blue pixels (or the light emitting area ratio) used for one pixel does not necessarily have to be 1:1:1. For example, the pixel number ratio (light emitting area ratio) is red:green:blue=1:1:
It may be 2. Further, the pixel number ratio (light receiving area ratio) may be set to red:green:blue=1:2:3.

Further, color display can be realized by combining a sub-pixel which emits white light with a color filter of red, green, blue, or the like. A color filter that transmits light in the red, green, or blue wavelength range may be combined with each of the sub-pixels that emit light in the red, green, or blue wavelength range.

However, the present invention is not limited to a display device for color display, and can be applied to a display device for monochrome display.

<<Example of pixel circuit for liquid crystal display device>>
FIG. 48C illustrates an example of a pixel circuit which can be used for the liquid crystal display device. Fig. 48 (C
The pixel circuit 3137 shown in FIG. 4B includes a transistor 3431 and a capacitor 3233. The pixel circuit 3137 is electrically connected to the liquid crystal element 3432 which can function as a display element.

The potential of one of the pair of electrodes of the liquid crystal element 3432 is set as appropriate in accordance with the specifications of the pixel circuit 3137. The alignment state of the liquid crystal included in the liquid crystal element 3432 is set by the data written in the node 3436. Note that a common potential (common potential) may be applied to one of a pair of electrodes of the liquid crystal element 3432 included in each of the plurality of pixel circuits 3137.

Examples of the mode of the liquid crystal element 3432 include a TN mode, an STN mode, a VA mode, and an ASM (Axially Symmetric Aligned Micro-cel).
l) mode, OCB (Optically Compensated Birefrin)
Gene) mode, FLC (Ferroelectric Liquid Crystal)
al) mode, AFLC (Anti Ferroelectric Liquid Cry)
stal) mode, MVA mode, PVA (Patterned Vertical A)
ligment) mode, IPS mode, FFS mode, or TBA (Transv)
Alternatively, an erse bend alignment mode or the like may be used. Further, as another example, an ECB (Electrically Controlled Birefring) is used.
ence) mode, PDLC (Polymer Dispersed Liquid C)
Rystal mode, PNLC (Polymer Network Liquid C)
There are various modes, such as a physical mode and a guest host mode. However, the present invention is not limited to this, and various modes can be used.

Alternatively, the liquid crystal element 3432 may be formed using a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent. A liquid crystal exhibiting a blue phase has a response speed of 1 mse
Since it is as short as c or less and it is optically isotropic, it does not require an alignment treatment and has a small viewing angle dependency.

In the pixel circuit 3137 in the m-th row and the n-th column, one of a source electrode and a drain electrode of the transistor 3431 is electrically connected to the signal line DL_n and the other is electrically connected to the node 3436. A gate electrode of the transistor 3431 is electrically connected to the scan line GL_m. The transistor 3431 has a function of controlling writing of a data signal to the node 3436.

One of a pair of electrodes of the capacitor 3233 is electrically connected to a wiring to which a specific potential is supplied (hereinafter also referred to as a “capacitance line CL”), and the other is electrically connected to a node 3436. .. The other of the pair of electrodes of the liquid crystal element 3432 is electrically connected to the node 3436. Note that the potential value of the capacitor line CL is set as appropriate in accordance with the specifications of the pixel circuit 3137. The capacitor 3233 has a function as a storage capacitor which holds data written in the node 3436.

Here, an operation example of a display device including the pixel circuit 3137 in FIG. 48C is described. First, the pixel circuit 3137 in each row is sequentially selected by the circuit 3132, the transistor 3431 is turned on, and a data signal is written to the node 3436.

Next, the transistor 3431 is turned off and the data signal written to the node 3436 is held. The amount of transmitted light of the liquid crystal element 3432 is determined according to the data signal written in the node 3436. By sequentially performing this for each row, an image can be displayed in the display area 3131.

<Example of display device configuration>
By using the transistor described in any of the above embodiments, part or the whole of a driver circuit including the transistor can be formed over the same substrate as the pixel portion, whereby a system-on-panel can be formed. A structural example of a display device in which the transistor described in any of the above embodiments can be used will be described with reference to FIGS.

[Liquid crystal display device and EL display device]
As an example of the display device, a display device using a liquid crystal element and a display device using an EL element will be described. In FIG. 50A, the pixel portion 40 provided over the first substrate 4001.
A sealing material 4005 is provided so as to surround 02 and is sealed with a second substrate 4006. In FIG. 50A, a signal line formed using a single crystal semiconductor or a polycrystalline semiconductor over a separately prepared substrate in a region different from a region surrounded by the sealant 4005 over the first substrate 4001. A driver circuit 4003 and a scan line driver circuit 4004 are mounted. In addition, the signal line driver circuit 4003, the scan line driver circuit 4004, or the pixel portion 4002.
Various signals and potentials applied to the FPC (Flexible printed circuit) are
CUTE) 4018a and FPC 4018b.

50B and 50C, the pixel portion 4 provided over the first substrate 4001.
A sealing material 4005 is provided so as to surround 002 and the scan line driver circuit 4004. A second substrate 4006 is provided over the pixel portion 4002 and the scan line driver circuit 4004. Therefore, the pixel portion 4002 and the scan line driver circuit 4004 are included in the first substrate 400.
The display element and the display element 400 are sealed by the sealing material 400, the sealing material 4005, and the second substrate 4006. In FIGS. 50B and 50C, the sealant 4005 over the first substrate 4001 is used.
A signal line driver circuit 4003 formed of a single crystal semiconductor or a polycrystalline semiconductor is mounted over a separately prepared substrate in a region different from a region surrounded by. 50B and 50C, various signals and potentials are supplied to the signal line driver circuit 4003, the scan line driver circuit 4004, or the pixel portion 4002 from the FPC 4018.

50B and 50C show an example in which the signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001; however, the invention is not limited to this structure. The scan line driver circuit may be separately formed and then mounted, or only part of the signal line driver circuit or part of the scan line driver circuit may be separately formed and then mounted.

The connection method of the drive circuit formed separately is not particularly limited, and wire bonding, COG (Chip On Glass), TCP (Tape Carrier) may be used.
Package), COF (Chip On Film), or the like can be used.
50A shows an example of mounting the signal line driver circuit 4003 and the scan line driver circuit 4004 by COG, and FIG. 50B shows an example of mounting the signal line driver circuit 4003 by COG. (C) is an example of mounting the signal line driver circuit 4003 by TCP.

In addition, the display device may include a panel in which a display element is sealed and a module in which an IC or the like including a controller is mounted on the panel.

In addition, the pixel portion and the scan line driver circuit provided over the first substrate include a plurality of transistors, and the transistor described in any of the above embodiments can be applied.

51A and 51B are cross-sectional views each illustrating a cross-sectional structure of a portion indicated by dashed line N1-N2 in FIG. 50B. The display device shown in FIGS. 51A and 51B has an electrode 40.
15, the electrode 4015 includes an anisotropic conductive layer 4019 and a terminal included in the FPC 4018.
Is electrically connected via. In addition, the electrode 4015 includes an insulating layer 4112 and an insulating layer 4
111 and the wiring 4014 in the openings formed in the insulating layer 4110.

The electrode 4015 is formed of the same conductive layer as the first electrode layer 4030, and the wiring 4014 is
The source electrode and the drain electrode of the transistor 4010 and the transistor 4011 are formed using the same conductive layer.

In addition, the pixel portion 4002 and the scan line driver circuit 4004 which are provided over the first substrate 4001 are
51A and 51B, the transistor 4010 included in the pixel portion 4002 and the transistor 40 included in the scan line driver circuit 4004 are included.
11 and 11 are illustrated. In FIG. 51A, the transistor 4010 and the transistor 4
An insulating layer 4112, an insulating layer 4111, and an insulating layer 4110 are provided over 011.
In 1B, the partition 4510 is formed over the insulating layer 4112.

The transistors 4010 and 4011 are provided over the insulating layer 4102. In addition, the transistor 4010 and the transistor 4011 are included in the insulating layer 410.
2 has an electrode 4017 formed over it, and an insulating layer 4103 is formed over the electrode 4017.
The electrode 4017 can function as a back gate electrode.

As the transistor 4010 and the transistor 4011, the transistor described in any of the above embodiments can be used. The transistors illustrated in the above embodiments have electrical characteristics that are suppressed from variation and are electrically stable. Therefore, the display device of this embodiment shown in FIGS. 51A and 51B can be a highly reliable display device.

Note that in FIGS. 51A and 51B, the case where a transistor having a structure similar to that of the transistor 160 described in the above embodiment is used as the transistor 4010 and the transistor 4011 is illustrated.

The display device illustrated in FIGS. 51A and 51B includes a capacitor 4020. The capacitor 4020 has a region where the electrode 4021 overlaps with part of one of a source electrode and a drain electrode of the transistor 4010 with the insulating layer 4103 provided therebetween. The electrode 4021 is
It is formed of the same conductive layer as the electrode 4017.

Generally, the capacitance of a capacitor provided in a display device is set in consideration of leakage current of a transistor provided in a pixel portion or the like so that charge can be held for a predetermined period. The capacitance of the capacitor may be set in consideration of off-state current of the transistor and the like.

For example, by using an OS transistor in the pixel portion of the liquid crystal display device, the capacitance of the capacitor can be set to 1/3 or less, or 1/5 or less of the liquid crystal capacitance. By using the OS transistor, the formation of the capacitor can be omitted.

The transistor 4010 provided in the pixel portion 4002 is electrically connected to a display element. FIG. 51A illustrates an example of a liquid crystal display device using a liquid crystal element as a display element. Figure 51 (A
), a liquid crystal element 4013 which is a display element includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. Note that an insulating layer 4032 and an insulating layer 4033 which function as alignment films are provided so as to sandwich the liquid crystal layer 4008. Second electrode layer 4031
Is provided on the second substrate 4006 side, and the first electrode layer 4030 and the second electrode layer 4031 overlap with each other with the liquid crystal layer 4008 interposed therebetween.

The spacer 4035 is a columnar spacer obtained by selectively etching the insulating layer, and is provided to control the distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. There is. A spherical spacer may be used.

When a liquid crystal element is used as the display element, thermotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal, ferroelectric liquid crystal, antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials show a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, etc. depending on the conditions.

Alternatively, liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. The blue phase is one of the liquid crystal phases, and is a phase that appears immediately before the transition from the cholesteric phase to the isotropic phase when the temperature of the cholesteric liquid crystal is raised. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition containing 5% by weight or more of a chiral agent is used for the liquid crystal layer in order to improve the temperature range. A liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a short response time of 1 msec or less, is optically isotropic, does not require alignment treatment, and has small viewing angle dependence. Further, since it is not necessary to provide an alignment film, rubbing treatment is not necessary, so that electrostatic breakdown caused by the rubbing treatment can be prevented and defects or damage of the liquid crystal display device during a manufacturing process can be reduced. .. Therefore, it is possible to improve the productivity of the liquid crystal display device.

Further, a method called multi-domain formation or multi-domain design in which a pixel (pixel) is divided into several regions (sub-pixels) and molecules are tilted in different directions can be used.

Further, the specific resistance of the liquid crystal material is 1×10 ⁹ Ω·cm or more, and preferably 1×10 ^{1
It is 1} Ω·cm or more, more preferably 1×10 ¹² Ω·cm or more. In addition, the value of specific resistance in this specification shall be the value measured at 20 degreeC.

The OS transistor used in this embodiment can have a low current value in the off state (off current value). Therefore, the holding time of an electric signal such as an image signal can be extended and the writing interval can be set long in the power-on state. Therefore, the frequency of refresh operations can be reduced, which leads to an effect of suppressing power consumption.

Further, since the OS transistor can obtain a relatively high field effect mobility, it can be driven at high speed. Therefore, by using the above transistor in the pixel portion of the display device, a high-quality image can be provided. In addition, since the driver circuit portion or the pixel portion can be separately formed over the same substrate, the number of components of the display device can be reduced.

Further, in the display device, an optical member (optical substrate) such as a black matrix (light-shielding layer), a polarizing member, a retardation member, and an antireflection member may be appropriately provided. For example, circularly polarized light using a polarizing substrate and a retardation substrate may be used. Further, a backlight, a sidelight, or the like may be used as the light source.

Further, a light emitting element utilizing electroluminescence can be applied as a display element included in the display device. A light-emitting element utilizing electroluminescence is distinguished depending on whether a light-emitting material is an organic compound or an inorganic compound. Generally, the former is called an organic EL element and the latter is called an inorganic EL element.

In the organic EL element, when a voltage is applied to the light emitting element, electrons and holes are injected from a pair of electrodes into a layer containing a light emitting organic compound, and a current flows. When the carriers (electrons and holes) are recombined, the light-emitting organic compound forms an excited state and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light emitting element is called a current excitation type light emitting element.

The inorganic EL element is classified into a dispersion type inorganic EL element and a thin film type inorganic EL element depending on the element structure. The dispersion-type inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light-emission mechanism is a donor-type utilizing a donor level and an acceptor level.
It is an acceptor recombination type light emission. The thin film type inorganic EL device has a structure in which a light emitting layer is sandwiched by dielectric layers and further sandwiched by electrodes, and the light emission mechanism is localized type light emission utilizing the core electron transition of metal ions. Note that, here, an organic EL element is used as a light emitting element for description.

In the light emitting element, at least one of the pair of electrodes is transparent in order to extract light emission. Then, a transistor and a light emitting element are formed over a substrate, and a top emission (top emission) structure in which light is emitted from a surface opposite to the substrate, or a bottom emission (bottom emission) structure in which light is emitted from a surface on the substrate side, There is a light emitting element with a dual emission (dual emission) structure in which light is emitted from both sides, and any light emitting element with an emission structure can be applied.

FIG. 51B illustrates an example of a light-emitting display device (also referred to as an “EL display device”) using a light-emitting element as a display element. The light emitting element 4513 which is a display element is electrically connected to the transistor 4010 provided in the pixel portion 4002. Note that the light-emitting element 4513 has a stacked-layer structure of the first electrode layer 4030, the light-emitting layer 4511, and the second electrode layer 4031, but is not limited to this structure. The structure of the light emitting element 4513 can be changed as appropriate in accordance with the direction of light extracted from the light emitting element 4513, or the like.

The partition 4510 is formed using an organic insulating material or an inorganic insulating material. It is particularly preferable to use a photosensitive resin material and form an opening over the first electrode layer 4030 so that the side surface of the opening is an inclined surface with a continuous curvature.

The light emitting layer 4511 may be formed of a single layer or a plurality of layers stacked.

A protective layer may be formed over the second electrode layer 4031 and the partition 4510 so that oxygen, hydrogen, moisture, carbon dioxide, and the like do not enter the light-emitting element 4513. As the protective layer, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, DLC (Diamond Like Carbon), or the like can be formed. In addition, the first substrate 4001, the second substrate 4006, and the sealant 4
A filling material 4514 is provided and sealed in the space sealed by 005. In this way, it is preferable to package (enclose) a protective film (a laminated film, an ultraviolet curable resin film or the like) or a cover material that has high airtightness and little degassing so as not to be exposed to the outside air.

As the filler 4514, an ultraviolet curable resin or a thermosetting resin can be used in addition to an inert gas such as nitrogen or argon. PVC (polyvinyl chloride), acrylic resin,
Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV
A (ethylene vinyl acetate) can be used. For example, nitrogen may be used as the filler.

If necessary, a polarizing plate or a circular polarizing plate (including an elliptically polarizing plate) on the emission surface of the light emitting element.
An optical film such as a retardation plate (λ/4 plate or λ/2 plate) or a color filter may be appropriately provided. Further, an antireflection film may be provided on the polarizing plate or the circularly polarizing plate. For example, it is possible to perform anti-glare processing that can reduce reflected glare by diffusing reflected light due to surface irregularities.

A first electrode layer and a second electrode layer (pixel electrode layer, common electrode layer,
(Also referred to as a counter electrode layer), the translucency and the reflectivity may be selected depending on the direction of light to be extracted, the place where the electrode layer is provided, and the pattern structure of the electrode layer.

The first electrode layer 4030 and the second electrode layer 4031 are formed of indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, and indium containing titanium oxide. A light-transmitting conductive material such as tin oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can be used.

The first electrode layer 4030 and the second electrode layer 4031 are formed of tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (
Nb), tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag), and other metals. , Or an alloy thereof, or a metal nitride thereof, and can be formed using one or more kinds.

Alternatively, the first electrode layer 4030 and the second electrode layer 4031 can be formed using a conductive composition containing a conductive high molecule (also referred to as a conductive polymer). As the conductive high molecule, a so-called π-electron conjugated conductive high molecule can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof,
Alternatively, a derivative thereof or the like can be given.

Further, since the transistor is easily damaged by static electricity or the like, it is preferable to provide a protection circuit for protecting the driving circuit. It is preferable that the protection circuit includes a non-linear element.

By using the transistor described in any of the above embodiments, a highly reliable display device can be provided. Further, by using the transistor described in any of the above embodiments, a display device with high display quality and high resolution can be provided with high definition. In addition, a display device with reduced power consumption can be provided.

[Display module]
A display module will be described as an example of a semiconductor device using the above transistor. The display module 6000 shown in FIG. 52 includes an upper cover 6001 and a lower cover 60.
02, a touch sensor 6004 connected to the FPC 6003, a display panel 6006 connected to the FPC 6005, a backlight unit 6007, a frame 6009, a printed board 6010, and a battery 6011. The backlight unit 6007,
The battery 6011, the touch sensor 6004, and the like may not be provided.

For example, the semiconductor device of one embodiment of the present invention includes a touch sensor 6004 and a display panel 6006.
It can be used for an integrated circuit mounted on the printed circuit board 6010. For example, the display device described above can be used for the display panel 6006.

The shape and size of the upper cover 6001 and the lower cover 6002 can be changed as appropriate in accordance with the size of the touch sensor 6004, the display panel 6006, or the like.

As the touch sensor 6004, a resistance film type or a capacitance type touch sensor can be used by being superimposed on the display panel 6006. It is also possible to add a touch sensor function to the display panel 6006. For example, a touch sensor electrode may be provided in each pixel of the display panel 6006 to add a touch panel function of a capacitance method. Alternatively, an optical sensor may be provided in each pixel of the display panel 6006 to add the function of an optical touch sensor.

The backlight unit 6007 has a light source 6008. The light source 6008 may be provided at the end of the backlight unit 6007 and a light diffusion plate may be used. When a light emitting display device or the like is used for the display panel 6006, the backlight unit 6007 can be omitted.

The frame 6009 has a function of protecting the display panel 6006 and a function of an electromagnetic shield for blocking an electromagnetic wave generated from the printed circuit board 6010 side. Further, the frame 6009 may have a function as a heat dissipation plate.

The printed circuit board 6010 has a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal, and the like. A battery 6011 is used as a power source for supplying power to the power circuit.
Or a commercial power source. When a commercial power source is used as the power source, the battery 6011 can be omitted.

Further, members such as a polarizing plate, a retardation plate and a prism sheet may be added to the display module 6000.

Note that this embodiment can be combined with any of the other embodiments and examples in this specification as appropriate.

[RF tag]
An RF tag will be described as an example of a semiconductor device including the above transistor.

An RF tag according to one embodiment of the present invention has a memory circuit (memory device) inside, stores information in the memory circuit, and exchanges information with the outside using a non-contact means such as wireless communication. is there.
Due to such characteristics, the RF tag can be used in an individual authentication system or the like for identifying an item by reading individual information of the item or the like. Note that high reliability is required for use in these applications.

The structure of the RF tag will be described with reference to FIG. FIG. 53 is a block diagram showing a configuration example of an RF tag.

As shown in FIG. 53, the RF tag 800 includes an antenna 804 that receives a wireless signal 803 transmitted from an antenna 802 connected to a communication device 801 (also referred to as an interrogator, a reader/writer, or the like). The above-described transistor may be used for the communication device 801. Also RF tag 8
00 includes a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a memory circuit 810, and a ROM 811. Note that as a semiconductor of a transistor which has a rectifying function and is included in the demodulation circuit 807, an oxide semiconductor which can sufficiently suppress reverse current may be used, for example. As a result, it is possible to suppress a decrease in the rectification action due to the reverse current and prevent the output of the demodulation circuit from being saturated. That is, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made close to linear. There are three main data transmission formats: an electromagnetic coupling method in which a pair of coils are arranged opposite to each other to perform communication by mutual induction, an electromagnetic induction method in which communication is performed by an induction electromagnetic field, and a radio wave method in which radio waves are used for communication. Be separated. The RF tag 800 can be used in any of the methods.

Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving a radio signal 803 to and from the antenna 802 connected to the communication device 801. In addition, the rectifier circuit 805 rectifies an input AC signal generated by receiving a wireless signal at the antenna 804, for example, rectifies half-wave double voltage, and smoothes the rectified signal by a capacitive element in the subsequent stage. This is a circuit for generating an input potential. Note that a limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. With a limiter circuit, the amplitude of the input AC signal is large,
It is a circuit for controlling so that electric power equal to or higher than a certain electric power is not input to the circuit in the subsequent stage when the internally generated voltage is large.

The constant voltage circuit 806 is a circuit for generating a stable power supply voltage from an input potential and supplying it to each circuit. Note that the constant voltage circuit 806 may have a reset signal generation circuit inside. The reset signal generation circuit uses the stable rise of the power supply voltage to make the logic circuit 8
This is a circuit for generating a reset signal of 09.

The demodulation circuit 807 is a circuit for demodulating the input AC signal by envelope detection and generating a demodulated signal. The modulation circuit 808 is a circuit for performing modulation according to the data output from the antenna 804.

The logic circuit 809 is a circuit for analyzing the demodulated signal and performing processing. The memory circuit 810 is a circuit which holds input information and includes a row decoder, a column decoder, a memory area, and the like. Further, the ROM 811 is a circuit for storing a unique number (ID) and the like and outputting it according to processing.

Note that the above circuits can be appropriately discarded.

The memory device described above can be used for the memory circuit 810. The storage device according to one embodiment of the present invention can hold information even when power is off, and thus is suitable for an RF tag. Further, in the memory device according to one embodiment of the present invention, power (voltage) required for writing data is lower than that of a conventional nonvolatile memory; therefore, a difference in maximum communication distance between data reading and data writing does not occur. It is also possible. Further, it is possible to suppress the occurrence of malfunction or erroneous writing due to insufficient power when writing data.

The memory device according to one embodiment of the present invention can be used as a nonvolatile memory and thus can be applied to the ROM 811. In this case, it is preferable that the producer separately prepares a command for writing data in the ROM 811, so that the user cannot freely rewrite the command. By shipping the product after the manufacturer writes the unique number before shipping, it is possible to assign the unique number only to the good product to be shipped, instead of assigning the unique number to all the manufactured RF tags, The unique numbers of the products after shipping do not become discontinuous, and the customer management corresponding to the products after shipping becomes easy.

An example of using the RF tag according to one embodiment of the present invention will be described with reference to FIGS. Although the RF tag has a wide range of uses, for example, bills, coins, securities, bearer bonds, certificates such as driver's licenses and resident cards (see FIG. 54A), recording media such as DVD software and video tape ( 54B.), containers such as plates, cups, and bottles (see FIG. 54C), packaging items such as wrapping paper, boxes, ribbons, and moving bodies such as bicycles (see FIG. 54D). .), personal belongings such as bags and glasses, plants, animals, human bodies, clothing, daily necessities, medical products including drugs and medicines, or electronic devices (for example, liquid crystal display devices, EL display devices, television devices, or mobile phones). It can be used by being provided on an article such as a telephone) or a tag attached to each article (see FIGS. 54E and 54F).

The RF tag 800 according to one embodiment of the present invention is fixed to an article by being attached to the surface or embedded. For example, a book is embedded in a paper, and a package made of an organic resin is embedded in the organic resin and fixed to each article. Since the RF tag 800 according to one embodiment of the present invention achieves small size, thinness, and lightness, the design of the article itself is not damaged even after being fixed to the article. Further, a bill, a coin, a securities, a bearer bond, a certificate, or the like can be provided with an authentication function by the RF tag 800 according to one embodiment of the present invention. By utilizing this authentication function, forgery can be prevented. You can Further, by attaching the RF tag 800 according to one embodiment of the present invention to a packaging container, a recording medium, personal belongings, clothes, household goods, an electronic device, or the like, efficiency of a system such as an inspection system can be achieved. .. Also,
By attaching the RF tag 800 according to one embodiment of the present invention to a moving object, security against theft or the like can be improved. As described above, the RF tag 800 according to one embodiment of the present invention can be used for each application as described above.

This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.

(Embodiment 5)
<Package using a lead frame type interposer>
FIG. 55A is a perspective view showing a cross-sectional structure of a package using a lead frame type interposer. In the package illustrated in FIG. 55A, a chip 551 corresponding to a semiconductor device of one embodiment of the present invention is connected to a terminal 552 over an interposer 550 by a wire bonding method. The terminal 552 is arranged on the surface of the interposer 550 on which the chip 551 is mounted. Although the chip 551 may be sealed with the mold resin 553, the chip 551 is sealed with a part of each terminal 552 exposed.

FIG. 55B illustrates a structural example of an electronic device in which a package is mounted on a circuit board. The electronic device illustrated in FIG. 55B is mounted in, for example, a mobile phone. In the electronic device illustrated in FIG. 55B, a package 562 and a battery 564 are mounted on a printed wiring board 561. Further, the printed wiring board 561 is mounted on the panel 560 provided with the display element by the FP.
It is implemented by C563.

Note that this embodiment can be combined with any of the other embodiments and examples in this specification as appropriate.

(Embodiment 6)
In this embodiment, examples of electronic devices each including the semiconductor device of one embodiment of the present invention will be described.

As an electronic device including the semiconductor device according to one embodiment of the present invention, a display device such as a television or a monitor, a lighting device, a desktop or notebook personal computer, a word processor, or a storage medium such as a DVD (Digital Versatile Disc) is stored. Image reproduction device for reproducing still images or moving images, portable CD player, radio, tape recorder, headphone stereo, stereo, table clock, wall clock, cordless telephone handset, transceiver, car phone, mobile phone, personal digital assistant, tablet -Type terminals, portable game machines, stationary game machines such as pachinko machines, calculators, electronic organizers, electronic book terminals, electronic translators, voice input devices, video cameras, digital still cameras, electric shavers, microwave ovens, etc. Equipment, electric rice cooker, electric washing machine, vacuum cleaner, water heater, fan, hair dryer,
Air conditioners, air conditioners such as humidifiers, dehumidifiers, dishwashers, tableware dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric freezers, DNA storage freezers,
Examples include flashlights, tools such as chainsaws, smoke detectors, medical equipment such as dialysis machines.
Further, there may be mentioned industrial equipment such as guide lights, traffic lights, belt conveyors, elevators, escalators, industrial robots, power storage systems, power leveling and power storage devices for smart grids. Further, an engine using fuel, a moving body propelled by an electric motor using electric power from a power storage unit, and the like may be included in the category of electronic devices. Examples of the moving body include an electric vehicle (EV), a hybrid vehicle (HEV) having both an internal combustion engine and an electric motor, a plug-in hybrid vehicle (PHEV), and a tracked vehicle in which the tire wheels of these vehicles are changed to an endless track.
Motorized bicycles including electric assisted bicycles, motorcycles, electric wheelchairs, golf carts,
Examples include small or large vessels, submarines, helicopters, aircraft, rockets, artificial satellites, space probes, planetary probes, and spacecraft.

A portable game machine 2900 illustrated in FIG. 56A includes a housing 2901, a housing 2902, a display portion 2903, a display portion 2904, a microphone 2905, a speaker 2906, operation keys 290.
It has 7 mag. Note that the portable game machine illustrated in FIG. 25A includes two display portions 2903 and 2904, but the number of display portions is not limited to this. Display unit 2903
Is provided with a touch screen as an input device and can be operated by a stylus 2908 or the like.

An information terminal 2910 illustrated in FIG. 56B includes a housing 2911, a display portion 2912, a microphone 2, and the like.
917, a speaker portion 2914, a camera 2913, an external connection portion 2916, operation buttons 2915, and the like. The display portion 2912 includes a display panel using a flexible substrate and a touch screen. The information terminal 2910 can be used as, for example, a smartphone, a mobile phone, a tablet information terminal, a tablet personal computer, an electronic book terminal, or the like.

A laptop personal computer 2920 illustrated in FIG. 56C includes a housing 2921, a display portion 2922, a keyboard 2923, a pointing device 2924, and the like.

A video camera 2940 illustrated in FIG. 56D includes a housing 2941, a housing 2942, and a display portion 2.
943, an operation key 2944, a lens 2945, a connection portion 2946, and the like. The operation key 2944 and the lens 2945 are provided in the housing 2941, and the display portion 2943 is provided in the housing 2942. The housing 2941 and the housing 2942 are connected to each other by a connecting portion 2946.
And the angle between the housings 2941 and 2942 can be changed by the connecting portion 2946. Depending on the angle of the housing 2942 with respect to the housing 2941, the orientation of the image displayed on the display portion 2943 can be changed and the display/non-display of the image can be switched.

FIG. 56E shows an example of a bangle type information terminal. The information terminal 2950 includes a housing 295.
1 and a display portion 2952 and the like. The display portion 2952 is supported by a housing 2951 having a curved surface. Since the display portion 2952 includes a display panel including a flexible substrate, a flexible, lightweight, and easy-to-use information terminal 2950 can be provided.

FIG. 56F shows an example of a wrist watch type information terminal. The information terminal 2960 includes a housing 2961.
, A display unit 2962, a band 2963, a buckle 2964, operation buttons 2965, an input/output terminal 2966, and the like. The information terminal 2960 can execute various applications such as mobile phone, electronic mail, text browsing and creation, music playback, Internet communication, and computer games.

The display surface of the display portion 2962 is curved, and display can be performed along the curved display surface. The display portion 2962 includes a touch sensor and can be operated by touching the screen with a finger, a stylus, or the like. For example, the application can be started by touching the icon 2967 displayed on the display unit 2962. The operation button 2965 can have various functions such as power on/off operation, wireless communication on/off operation, manner mode execution/cancellation, and power saving mode execution/cancellation in addition to time setting. .. For example, the operating button 296 is operated by the operating system incorporated in the information terminal 2960.
5 functions can be set.

Further, the information terminal 2960 can execute short-range wireless communication that is a communication standard. For example, by communicating with a headset capable of wireless communication, a hands-free call can be made. The information terminal 2960 has an input/output terminal 2966 and can directly exchange data with another information terminal via a connector. Input/output terminal 29
Charging can also be done via 66. Note that the charging operation may be performed by wireless power feeding without using the input/output terminal 2966.

FIG. 56G illustrates an electric refrigerator as an example of household electric appliances. The electric refrigerator 2970 includes a housing 2971, a refrigerator compartment door 2972, a freezer compartment door 2973, and the like.

FIG. 56H is an external view illustrating an example of an automobile. Car 2980, car body 2981
, Wheels 2982, dashboard 2983, lights 2984, and the like.

The above-described transistor, the above-described semiconductor device, or the like is mounted on the electronic device described in this embodiment.

This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.

(Embodiment 7)
In this embodiment mode, a film formation apparatus (sputtering apparatus) having a film formation chamber in which a sputtering target can be installed will be described. The film forming apparatus shown in this embodiment mode is
It can be used for a parallel plate type sputtering device, a facing target type sputtering device, and the like.

In film formation using a facing target type sputtering apparatus, damage to the formation surface can be reduced, and thus a film with high crystallinity can be easily obtained. That is, it may be preferable to use a facing target type sputtering apparatus for forming a film of the CAAC-OS or the like.

The film formation method using the parallel plate type sputtering apparatus was applied to PESP (Parallel).
It can also be referred to as Electrode Sputtering). In addition, a film forming method using a facing target type sputtering apparatus is applied to a VDSP (Vapor Deposition
on Sputtering).

First, the structure of a film formation apparatus in which impurities are less likely to be mixed into the film at the time of film formation will be described with reference to FIGS. 57 and 58.

FIG. 57 schematically shows a top view of a single-wafer multi-chamber film forming apparatus 2700. The film forming apparatus 2700 includes an atmosphere-side substrate supply chamber 2701 including a cassette port 2761 for accommodating a substrate and an alignment port 2762 for aligning the substrate, and an atmosphere-side substrate for transporting the substrate from the atmosphere-side substrate supply chamber 2701. A transfer chamber 2702, a load lock chamber 2703a for carrying in a substrate and switching the pressure in the chamber from atmospheric pressure to a reduced pressure or from a reduced pressure to the atmospheric pressure, and carrying out a substrate and changing the pressure in the chamber from a reduced pressure to the atmospheric pressure, Alternatively, an unload lock chamber 2703b for switching from atmospheric pressure to decompression and a transfer chamber 2 for transferring a substrate in vacuum
704, a substrate heating chamber 2705 for heating a substrate, a film formation chamber 2706a in which a target is arranged and a film is formed, a film formation chamber 2706b, and a film formation chamber 2706c. Note that for the film formation chambers 2706a, 2706b, and 2706c, the above-described structure of the film formation chamber can be referred to.

The atmosphere-side substrate transfer chamber 2702 is connected to the load lock chamber 2703a and the unload lock chamber 2703b, and the load lock chamber 2703a and the unload lock chamber 270 are connected.
3b is connected to the transfer chamber 2704, and the transfer chamber 2704 includes the substrate heating chamber 2705 and the film forming chamber 2
706a, the film formation chamber 2706b, and the film formation chamber 2706c.

A gate valve 2764 is provided at the connection of each chamber, and the atmosphere side substrate supply chamber 2
With the exception of 701 and the atmosphere-side substrate transfer chamber 2702, each chamber can be maintained in a vacuum state independently. In addition, the atmosphere-side substrate transfer chamber 2702 and the transfer chamber 2704 are the transfer robot 276.
3, the substrate can be transported.

It is preferable that the substrate heating chamber 2705 also serve as a plasma treatment chamber. Film forming apparatus 2700
Since the substrate can be transported between treatments without being exposed to the atmosphere, adsorption of impurities on the substrate can be suppressed. In addition, the order of film formation and heat treatment can be freely constructed. Note that the number of transfer chambers, film formation chambers, load lock chambers, unload lock chambers, and substrate heating chambers is not limited to the above number, and an appropriate number can be provided according to the installation space and process conditions.

Next, FIG. 58 shows cross sections corresponding to dashed-dotted line X1-X2, dashed-dotted line Y1-Y2, and dashed-dotted line Y2-Y3 in the film forming apparatus 2700 shown in FIG.

FIG. 58A shows a cross section of the substrate heating chamber 2705 and the transfer chamber 2704, and the substrate heating chamber 2705 has a plurality of heating stages 2765 which can accommodate a substrate. The substrate heating chamber 2705 is connected to the vacuum pump 2770 via a valve.
As the vacuum pump 2770, for example, a dry pump, a mechanical booster pump, or the like can be used.

The heating mechanism that can be used in the substrate heating chamber 2705 may be, for example, a heating mechanism that heats using a resistance heating element or the like. Alternatively, a heating mechanism for heating by heat conduction or heat radiation from a medium such as a heated gas may be used. For example, GRTA, L
RTA such as RTA can be used.

In addition, the substrate heating chamber 2705 is connected to the refiner 27 via the mass flow controller 2780.
81 is connected. It should be noted that the mass flow controller 2780 and the refiner 2781 are provided by the number of gas species, but only one is shown for easy understanding. Substrate heating chamber 2705
A gas having a dew point of −80° C. or lower, preferably −100° C. or lower, can be used as the gas introduced into, for example, oxygen gas, nitrogen gas, and a rare gas (argon gas or the like) are used.

The transfer chamber 2704 has a transfer robot 2763. The transfer robot 2763 can transfer a substrate to each chamber. The transfer chamber 2704 is connected to the vacuum pump 2770 and the cryopump 2771 via a valve. With such a structure, the transfer chamber 2704 is evacuated from the atmospheric pressure to a low vacuum or a medium vacuum (about 0.1 to several hundred Pa) by using the vacuum pump 2770, and the valve is switched to a high vacuum from the medium vacuum. Vacuum or ultra-high vacuum (0.1 Pa to 1×10 ⁻⁷ Pa) is exhausted using the cryopump 2771.

Further, for example, two or more cryopumps 2771 may be connected in parallel to the transfer chamber 2704. With such a configuration, even when one cryopump is being regenerated, the remaining cryopumps can be used to exhaust the gas. In addition, the above-mentioned regeneration refers to a process of releasing molecules (or atoms) accumulated in the cryopump. The cryopump has a reduced exhaust capacity if it accumulates molecules (or atoms) too much.
Regeneration is done regularly.

FIG. 58B shows a film formation chamber 2706b, a transfer chamber 2704, and a load lock chamber 2703a.
The cross section of FIG.

Here, details of the film formation chamber (sputtering chamber) are described with reference to FIG. A deposition chamber 2706b illustrated in FIG. 58B includes a target 2766a and a target 276.
6b, a target shield 2767a, a target shield 2767b, a magnet unit 2790a, a magnet unit 2790b, a substrate holder 2768, and a power supply 2791. Although not shown, the target 2766a and the target 276
Each of 6b is fixed to the target holder via a backing plate. A power supply 2791 is electrically connected to the targets 2766a and 2766b. The magnet unit 2790a and the magnet unit 2790b are arranged on the back surfaces of the target 2766a and the target 2766b, respectively. The target shield 2767a and the target shield 2767b are respectively the target 2766.
a and the target 2766b are arranged so as to surround the ends thereof. Note that here, the substrate 2769 is supported by the substrate holder 2768. The substrate holder 2768 is a variable member 27.
It is fixed to the film forming chamber 2706b via 84. The target 2 by the variable member 2784
The substrate holder 2768 can be moved to a region between the 766a and the target 2766b (also referred to as an inter-target region). For example, by arranging the substrate holder 2768 supporting the substrate 2769 in the inter-target region, it may be possible to reduce damage due to plasma. Although not shown, the substrate holder 2768 may include a substrate holding mechanism that holds the substrate 2769, a heater that heats the substrate 2769 from the back surface, and the like.

Further, the target shield 2767 can prevent particles sputtered from the target 2766 from being deposited in an unnecessary region. The target shield 2767
It is desirable to process so that the accumulated sputtered particles are not separated. For example, blast treatment for increasing the surface roughness or unevenness may be provided on the surface of the target shield 2767.

In addition, the film formation chamber 2706b is connected to the mass flow controller 2 via the gas heating mechanism 2782.
The gas heating mechanism 2782 is connected to the refiner 2781 via the mass flow controller 2780. By the gas heating mechanism 2782, the gas introduced into the film formation chamber 2706b can be heated to 40 °C to 400 °C inclusive, preferably 50 °C to 200 °C inclusive. Note that the gas heating mechanism 2782, the mass flow controller 2780, and the refiner 2781 are provided by the number of gas species, but only one is shown for easy understanding. As the gas introduced into the film formation chamber 2706b, a gas having a dew point of −80° C. or lower, preferably −100° C. or lower can be used. For example, oxygen gas, nitrogen gas, and a rare gas (eg, argon gas) can be used. To use.

When a refiner is provided immediately before the gas inlet, the length of the pipe from the refiner to the film forming chamber 2706b is 10 m or less, preferably 5 m or less, and more preferably 1 m or less. By setting the length of the pipe to 10 m or less, 5 m or less, or 1 m or less, the influence of the gas discharged from the pipe can be reduced according to the length. Further, as the gas pipe, it is preferable to use a metal pipe whose inside is coated with iron fluoride, aluminum oxide, chromium oxide or the like. The above-mentioned piping is, for example, SUS
As compared with the 316L-EP pipe, the amount of released gas containing impurities is small, and the entry of impurities into the gas can be reduced. For piping joints, high performance ultra-small metal gasket joints (UPG
It is recommended to use a joint). In addition, it is preferable to configure the pipes entirely of metal because it is possible to reduce the influence of the released gas and the external leakage, as compared with the case of using a resin or the like.

The film formation chamber 2706b is connected to the turbo molecular pump 2772 and the vacuum pump 2770 via a valve.

A cryotrap 2751 is provided in the film formation chamber 2706b.

The cryotrap 2751 is a mechanism capable of adsorbing molecules (or atoms) having a relatively high melting point such as water. The turbo-molecular pump 2772 stably excretes large-sized molecules (or atoms) and the frequency of maintenance is low. Therefore, the turbo-molecular pump 2772 is excellent in productivity, but has low exhaust capability of hydrogen or water. Therefore, in order to enhance the exhaust capability for water and the like, the cryotrap 2751 is connected to the film formation chamber 2706b. Cryotrap 2751
The temperature of the refrigerator is 100 K or lower, preferably 80 K or lower. Further, in the case where the cryotrap 2751 has a plurality of refrigerators, it is preferable to change the temperature for each refrigerator because efficient exhaust can be performed. For example, the temperature of the first-stage refrigerator is set to 100K or less, and 2
The temperature of the stage refrigerator may be set to 20K or lower. In some cases, a higher vacuum can be obtained by using a titanium sublimation pump instead of the cryotrap. Further, it may be possible to further increase the vacuum by using an ion pump instead of the cryopump or the turbo molecular pump.

Note that the exhaust method of the film formation chamber 2706b is not limited to this, and may be the same as the exhaust method shown in the previous transfer chamber 2704 (exhaust method of a cryopump and a vacuum pump). Needless to say, the method of exhausting the transfer chamber 2704 may be the same as that of the film formation chamber 2706b (exhaust method of turbo molecular pump and vacuum pump).

Note that the back pressure (total pressure) of the transfer chamber 2704, the substrate heating chamber 2705, and the film formation chamber 2706b, and the partial pressure of each gas molecule (atom) described above are preferably set as follows. In particular, since there is a possibility that impurities may be mixed into the formed film, the back pressure of the film formation chamber 2706b,
Also, it is necessary to pay attention to the partial pressure of each gas molecule (atom).

The back pressure (total pressure) of each chamber described above is 1×10 ⁻⁴ Pa or less, preferably 3×10 ⁻⁵ Pa.
Hereafter, it is more preferably 1×10 ⁻⁵ Pa or less. Mass-to-charge ratio of each chamber (m/
The partial pressure of a gas molecule (atom) whose z) is 18 is 3×10 ⁻⁵ Pa or less, preferably 1×1.
0 ^-5 Pa, more preferably not more than 3 × ¹⁰ -6 Pa. Further, the partial pressure of gas molecules (atoms) having m/z of 28 in each of the above-mentioned chambers is 3×10 ⁻⁵ Pa or less, preferably 1×.
It is 10 ⁻⁵ Pa or less, more preferably 3×10 ⁻⁶ Pa or less. Further, the partial pressure of the gas molecules (atoms) whose m/z is 44 in each of the above-mentioned chambers is 3×10 ⁻⁵ Pa or less, preferably 1
It is not more than ×10 ⁻⁵ Pa, more preferably not more than 3×10 ⁻⁶ Pa.

The total pressure and partial pressure in the vacuum chamber can be measured using a mass spectrometer. For example, a quadrupole mass spectrometer (also referred to as Q-mass) Qu manufactured by ULVAC, Inc.
Lee CGM-051 may be used.

Further, it is desirable that the above-described transfer chamber 2704, the substrate heating chamber 2705, and the film formation chamber 2706b have a structure with less external leakage or internal leakage.

For example, the leak rates of the transfer chamber 2704, the substrate heating chamber 2705, and the film formation chamber 2706b described above are 3×10 ⁻⁶ Pa·m ³ /s or less, preferably 1×10 ⁻⁶ Pa·m ³ /.
s or less. Also, the leak rate of gas molecules (atoms) having m/z of 18 is 1×10 ^{−.
It is 7} Pa·m ³ /s or less, preferably 3×10 ⁻⁸ Pa·m ³ /s or less. Also, m/
The leak rate of gas molecules (atoms) having z of 28 is 1×10 ⁻⁵ Pa·m ³ /s or less, preferably 1×10 ⁻⁶ Pa·m ³ /s or less. In addition, a gas molecule (m/z is 44 (
(Atom) leak rate is 3×10 ⁻⁶ Pa·m ³ /s or less, preferably 1×10 ⁻⁶ Pa
・M ³ /s or less.

The leak rate may be derived from the total pressure and partial pressure measured using the above-mentioned mass spectrometer.

The leak rate depends on the external and internal leaks. External leakage is the inflow of gas from outside the vacuum system due to minute holes or poor sealing. The internal leak is caused by a leak from a partition such as a valve in a vacuum system or a gas released from an internal member. In order to keep the leak rate below the above-mentioned value, it is necessary to take measures from both aspects of external leak and internal leak.

For example, the opening/closing portion of the film formation chamber 2706b may be sealed with a metal gasket. For the metal gasket, it is preferable to use a metal coated with iron fluoride, aluminum oxide, or chromium oxide. The metal gasket has higher adhesion than the O-ring and can reduce external leakage. Further, by using the passivation of the metal coated with iron fluoride, aluminum oxide, chromium oxide or the like, the released gas containing the impurities released from the metal gasket is suppressed, and the internal leak can be reduced.

Further, aluminum, chromium, titanium, zirconium, nickel, or vanadium, which emits a small amount of gas containing impurities, is used as a member included in the film formation apparatus 2700. Further, the above-mentioned member may be used by being coated with an alloy containing iron, chromium, nickel and the like. Alloys containing iron, chromium, nickel, etc. are rigid, heat-resistant, and suitable for processing. Here, if the surface irregularities of the member are reduced by polishing or the like to reduce the surface area, the released gas can be reduced.

Alternatively, the above member of the film forming apparatus 2700 may be coated with iron fluoride, aluminum oxide, chromium oxide, or the like.

It is preferable that the member of the film forming apparatus 2700 be made of only metal as much as possible. For example, even when a viewing window made of quartz or the like is installed, the surface of the film is made of iron fluoride in order to suppress the released gas.
A thin coating of aluminum oxide or chromium oxide is recommended.

The adsorbate existing in the film forming chamber does not affect the pressure in the film forming chamber because it is adsorbed on the inner wall or the like, but it causes gas release when the film forming chamber is exhausted. Therefore, although there is no correlation between the leak rate and the exhaust speed, it is important to use a pump having a high exhaust capacity to desorb the adsorbate present in the film forming chamber as much as possible and to exhaust it in advance. Note that the film formation chamber may be baked in order to promote desorption of the adsorbate. By baking, the desorption rate of the adsorbate can be increased about 10 times. The baking may be performed at 100° C. or higher and 450° C. or lower. At this time, if the adsorbate is removed while introducing the inert gas into the film forming chamber, the desorption rate of water or the like, which is difficult to desorb only by exhausting, can be further increased. By heating the introduced inert gas to the same temperature as the baking temperature, the desorption rate of the adsorbed substance can be further increased. Here, it is preferable to use a rare gas as the inert gas. In addition, oxygen or the like may be used instead of the inert gas depending on the kind of film to be formed. For example, when forming an oxide film, it may be preferable to use oxygen as the main component. Note that baking is preferably performed using a lamp.

Alternatively, it is preferable that the pressure in the deposition chamber be increased by introducing an inert gas such as a heated rare gas or oxygen, and that the deposition chamber be evacuated again after a certain period of time. By introducing the heated gas, adsorbed substances in the film formation chamber can be desorbed, and impurities existing in the film formation chamber can be reduced. This treatment is performed 2 to 30 times, preferably 5 to 15 times.
It is effective to repeat the process within the range below. Specifically, by introducing an inert gas or oxygen whose temperature is 40° C. or higher and 400° C. or lower, preferably 50° C. or higher and 200° C. or lower, the pressure in the film formation chamber is 0.1 Pa or higher and 10 kPa or lower, preferably The pressure may be maintained at 1 Pa or more and 1 kPa or less, more preferably 5 Pa or more and 100 Pa or less, and the pressure maintaining period may be 1 minute or more and 300 minutes or less, preferably 5 minutes or more and 120 minutes or less. After that, leave the film formation chamber for 5 minutes or more 300
The exhaust is performed for a period of not more than a minute, preferably 10 minutes to 120 minutes.

Further, the desorption rate of the adsorbate can be further increased by performing the dummy film formation. Dummy film formation is a method of depositing a film on a dummy substrate and the inner wall of the film forming chamber by forming a film on a dummy substrate by a sputtering method or the like, and depositing impurities in the film forming chamber and adsorbed substances on the inner wall of the film forming chamber. It means to lock in. The dummy substrate is preferably a substrate that emits less gas. By performing the dummy film formation, the impurity concentration in the film formed later can be reduced. Note that the dummy film formation may be performed at the same time as the baking.

Next, a transfer chamber 2704 and a load lock chamber 2703a shown in FIG.
Details of the atmosphere-side substrate transfer chamber 2702 and the atmosphere-side substrate supply chamber 2701 shown in FIG. 8C will be described below. Note that FIG. 58C illustrates a cross section of the atmosphere-side substrate transfer chamber 2702 and the atmosphere-side substrate supply chamber 2701.

For the transfer chamber 2704 illustrated in FIG. 58B, the description of the transfer chamber 2704 illustrated in FIG.

The load lock chamber 2703a has a substrate transfer stage 2752. The load lock chamber 2703a raises the pressure from the depressurized state to the atmosphere, and when the pressure in the load lock chamber 2703a becomes atmospheric pressure, the transfer robot 27 provided in the atmosphere side substrate transfer chamber 2702.
The substrate is received from 63 to the substrate transfer stage 2752. After that, the load lock chamber 27
After 03a is evacuated to a reduced pressure state, the transfer robot 2763 provided in the transfer chamber 2704 receives the substrate from the substrate transfer stage 2752.

The load lock chamber 2703a is connected to the vacuum pump 2770 and the cryopump 2771 via valves. Vacuum pump 2770 and cryopump 27
The connection method of the exhaust system of 71 can be connected by referring to the connection method of the transfer chamber 2704, and therefore the description thereof is omitted here. Note that the unload lock chamber 2703b illustrated in FIG. 57 can have the same structure as the load lock chamber 2703a.

The atmosphere-side substrate transfer chamber 2702 has a transfer robot 2763. Transfer robot 2763
Thus, the substrate can be transferred between the cassette port 2761 and the load lock chamber 2703a. Further, a HEPA filter (High Efficiency Particulate A) is provided above the atmosphere side substrate transfer chamber 2702 and the atmosphere side substrate supply chamber 2701.
A mechanism for cleaning dust or particles such as ir filters) may be provided.

The atmosphere-side substrate supply chamber 2701 has a plurality of cassette ports 2761. The cassette port 2761 can accommodate a plurality of substrates.

The surface temperature of the target is 100° C. or lower, preferably 50° C. or lower, more preferably about room temperature (typically 25° C.). A large-area target is often used in a sputtering apparatus for a large-area substrate. However, it is difficult to manufacture a target having a size corresponding to a large area without any joint. In reality, a plurality of targets are arranged in a large shape so that there are as few gaps as possible, but a slight gap is inevitably generated. When the surface temperature of the target rises from such a slight gap, zinc or the like may volatilize and the gap may gradually expand. If the gap is widened, the backing plate or the metal of the bonding material used for joining the backing plate and the target may be sputtered, which becomes a factor of increasing the impurity concentration. Therefore, it is preferable that the target is sufficiently cooled.

Specifically, as a backing plate, a metal (with high conductivity and high heat dissipation (
Specifically, copper) is used. Further, by forming a water channel in the backing plate and flowing a sufficient amount of cooling water in the water channel, the target can be efficiently cooled.

Note that when the target contains zinc, by forming a film in an oxygen gas atmosphere, plasma damage can be reduced and an oxide in which zinc is less likely to volatilize can be obtained.

By using the above-described film forming apparatus, the hydrogen concentration can be changed to secondary ion mass spectrometry (SIMS:S).
2 x 10 in the Econdary Ion Mass Spectrometry)
²⁰ atoms/cm ³ or less, preferably 5×10 ¹⁹ atoms/cm ³ or less, more preferably 1×10 ¹⁹ atoms/cm ³ or less, further preferably 5×10 ¹⁸ atoms.
An oxide semiconductor having a density of s/cm ³ or less can be formed.

Further, the nitrogen concentration in SIMS is less than 5×10 ¹⁹ atoms/cm ³ , preferably 1×10 ¹⁹ atoms/cm ³ or less, and more preferably 5×10 ¹⁸ atoms/c.
It is possible to form an oxide semiconductor with m ³ or less, more preferably 1×10 ¹⁸ atoms/cm ³ or less.

The carbon concentration in SIMS is less than 5×10 ¹⁹ atoms/cm ³ , preferably 5×10 ¹⁸ atoms/cm ³ or less, and more preferably 1×10 ¹⁸ atoms/c 3.
An oxide semiconductor having a thickness of m ³ or less, more preferably 5×10 ¹⁷ atoms/cm ³ or less can be formed.

In addition, thermal desorption gas spectroscopy (TDS: Thermal Desorption Speech)
a gas molecule (atom) whose m/z is 2 (hydrogen molecule, etc.) according to ctrocopy analysis,
Gas molecules (atoms) with m/z=18, gas molecules (atoms) with m/z=28 and m/z
It is possible to form an oxide semiconductor in which the amount of released gas molecules (atoms) in which z is 44 is 1×10 ¹⁹ pieces/cm ³ or less, preferably 1×10 ¹⁸ pieces/cm ³ or less.

By using the above film forming apparatus, entry of impurities into the oxide semiconductor can be suppressed. Further, by forming a film in contact with the oxide semiconductor by using the above film formation apparatus, entry of impurities into the oxide semiconductor from the film in contact with the oxide semiconductor can be suppressed.

This embodiment can be implemented in appropriate combination with any of the structures described in the other embodiments.

100 Transistor 100a Transistor 100d Structure 101 Substrate 102 Insulator 102a Insulator 103 Insulator 103a Insulator 103b Insulator 103c Insulator 104 Oxide layer 104a Oxide layer 104b Oxide layer 104c Oxide layer 104d Oxide layer 104e Oxide Layer 104f Oxide layer 105 Insulator 105a Electrode 105b Electrode 105d Insulator 106 Conductor 106d Conductor 107 Insulator 107d Insulator 108 Insulator 108b Insulator 108d Insulator 109a Conductor 109b Conductor 109c Conductor 109d Conductor 109e Conductor Body 109j Conductor 109k Conductor 109l Conductor 109m Conductor 109n Conductor 109o Conductor 110 Insulator 110b Insulator 110d Insulator 111 Insulator 111a Insulator 112 Insulator 112d Contact plug 113a Contact plug 113b Contact plug 113c Contact plug 113d Contact plug 114 Conductor 114a Conductor 114b Conductor 114c Conductor 117 Conductor 117d Conductor 118 Insulator 119 Conductor 126 Conductive layer 131 Metal element 135 Region 141 Capacitive element 142 Capacitive element 145 Mixed layer 150 Transistor 160 Transistor 220 Well 221 p-type semiconductor 223 n-type semiconductor 224 opening 225 opening 251 wiring 252 wiring 253 wiring 254 wiring 255 wiring 256 node 257 capacitance element 260 circuit 270 circuit 273 electrode 280 circuit 281 transistor 281a transistor 281b transistor 282 transistor 282a transistor 282b transistor 283 channel formation region 284 Low-concentration p-type impurity region 285 High-concentration p-type impurity region 286 Insulator 287 Conductor 288 Structure 289 Transistor 290 Circuit 291 Transistor 300 Structure 300d Structure 301 Mask 302 Mask 303 Mask 306 Opening 307 Opening 308 Opening 311 Length 312 Length 313 Length 314 Length 315 End 316 End 382 Ec
383a Ec
383b Ec
383c Ec
386 Ec
390 Trap level 400 Semiconductor device 401 Substrate 402 Insulator 403 Insulator 404 Insulator 405 Insulator 406 Contact plug 406a Contact plug 406b Contact plug 406c Contact plug 407 Insulator 407a Insulator 410 Semiconductor device 412 Insulator 413 Capacitive element 413a Conductivity Body 413b Conductor 413c Conductor 413d Conductor 414 Element isolation layer 415 Insulator 420 Semiconductor device 421 Conductor 422 Conductor 427 Conductor 429 Conductor 430 Semiconductor device 442 Insulator 477 Partition 487 Wiring 487a Conductor 487b Conductor 488 Conductor Body 489 Contact plug 550 Interposer 551 Chip 552 Terminal 553 Mold resin 560 Panel 561 Printed wiring board 562 Package 563 FPC
564 battery 585 insulator 600 imaging device 601 photoelectric conversion element 602 transistor 603 transistor 604 transistor 605 transistor 606 capacitance element 607 node 608 wiring 609 wiring 610 pixel driving circuit 611 wiring 621 pixel portion 622 pixel 622B pixel 622G pixel 622R pixel 623 pixel 624 filter 624B filter 624G filter 624R filter 625 lens 626 wiring group 660 light 681 photoelectric conversion layer 682 translucent conductive layer 686 conductor 686a conductor 686b conductor 701 circuit 702 circuit 703 switch 704 switch 706 logic element 707 capacitance element 708 capacitance element 709 Transistor 710 Transistor 713 Transistor 714 Transistor 720 Circuit 730 Storage element 800 RF tag 801 Communication device 802 Antenna 803 Radio signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulation circuit 808 Modulation circuit 809 Logic circuit 810 Storage circuit 811 ROM
1189 ROM interface 1190 Board 1191 ALU
1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM
1281 transistor 1283 channel formation region 1284 low concentration n-type impurity region 1285 high concentration n-type impurity region 2700 film forming apparatus 2701 atmosphere side substrate supply chamber 2702 atmosphere side substrate transfer chamber 2703a load lock chamber 2703b unload lock chamber 2704 transfer chamber 2705 substrate Heating chamber 2706a Film forming chamber 2706b Film forming chamber 2706c Film forming chamber 2751 Cryotrap 2752 Stage 2761 Cassette port 2762 Alignment port 2763 Transfer robot 2764 Gate valve 2765 Heating stage 2766 Target 2766a Target 2766b Target 2767 Target shield 2767a Target shield 2767b Target shield 2768 Substrate holder 2769 Substrate 2770 Vacuum pump 2771 Cryopump 2772 Turbo molecular pump 2780 Mass flow controller 2781 Purifier 2782 Gas heating mechanism 2784 Variable member 2790a Magnet unit 2790b Magnet unit 2791 Power source 2900 Portable game machine 2901 Housing 2902 Housing 2903 Display 2904 Display unit 2905 Microphone 2906 Speaker 2907 Operation key 2908 Stylus 2910 Information terminal 2911 Housing 2912 Display unit 2913 Camera 2914 Speaker unit 2915 Button 2916 External connection unit 2917 Microphone 2920 Notebook type personal computer 2921 Housing 2922 Display unit 2923 Keyboard 2924 Pointing device 2940 Video camera 2941 Housing 2942 Housing 2943 Display unit 2944 Operation keys 2945 Lens 2946 Connection unit 2950 Information terminal 2951 Housing 2952 Display unit 2960 Information terminal 2961 Housing 2962 Display unit 2963 Band 2964 Buckle 2965 Operation button 2966 Input/output terminal 2967 Icon 2970 Electric Refrigerator 2971 Housing 2972 Refrigerator Door 2973 Refrigerator Door 2980 Automobile 2981 Car Body 2982 Wheel 2983 Dashboard 2984 Light 3100 Display Device 3125 Light Emitting Element 3130 Pixel 3131 Display Area 3132 Circuit 3133 Circuit 3135 Scan Line 3136 Scan Line 3137 Pixel 3137 Pixel Circuit 3152 Circuit 3153 Circuit 3232 Transistor 3233 Capacitive element 3431 transistor 3432 liquid crystal element 3434 transistor 3435 node 3436 node 3437 node 4001 substrate 4002 pixel portion 4003 signal line drive circuit 4004 scanning line drive circuit 4005 sealant 4006 substrate 4008 liquid crystal layer 4010 transistor 4011 transistor 4013 liquid crystal element 4014 wiring 4015 electrode 4017 electrode 4018 FPC
4018b FPC
4019 anisotropic conductive layer 4020 capacitive element 4021 electrode 4030 electrode layer 4031 electrode layer 4032 insulating layer 4033 insulating layer 4035 spacer 4102 insulating layer 4103 insulating layer 4110 insulating layer 4111 insulating layer 4112 insulating layer 4510 partition wall 4511 light emitting layer 4513 light emitting element 4514 filling Material 5100 Pellets 5120 Substrate 5161 Area 6000 Display module 6001 Upper cover 6002 Lower cover 6003 FPC
6004 Touch sensor 6005 FPC
6006 Display panel 6007 Backlight unit 6008 Light source 6009 Frame 6010 Printed circuit board 6011 Battery

Claims (3)

A first insulator,
A transistor on the first insulator,
A second insulator covering the transistor,
A third insulator on the transistor and on the second insulator,
The second insulator has an opening reaching the first insulator,
A fourth insulator is disposed in the opening,
A semiconductor device in which the opening is arranged so as to surround four sides of the transistor. In claim 1,
The fourth insulator is a semiconductor device having lower hydrogen permeability than the second insulator. In claim 1 or 2,
At least one of the first insulator and the fourth insulator is a semiconductor device containing a nitride material.