JP2016167590A - Transistor, manufacturing method for transistor, semiconductor device, and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a transistor with the excellent electric characteristics, a transistor with the stable electric characteristics, or a highly integrated semiconductor device.SOLUTION: In a top-gate transistor including an oxide semiconductor in a semiconductor layer where a channel is formed, a metal element is introduced to the semiconductor layer in a self-aligning manner after a gate electrode is formed, and then a side surface of the gate electrode is covered with a structure. The structure preferably contains aluminum oxide. When an insulating layer is formed in the fabrication of the structure, oxygen is introduced to a surface where the insulating layer is formed.SELECTED DRAWING: Figure 1

Description

One embodiment of the present invention relates to a transistor, a semiconductor device, and a manufacturing method thereof.

Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, a manufacture, or a composition (composition of matter).

Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A display device (a liquid crystal display device, a light-emitting display device, or the like), an illumination device, an electro-optical device, a power storage device, a memory device, a semiconductor circuit, an imaging device, an electronic device, or the like may include a semiconductor device.

In recent years, transistors using an oxide semiconductor have attracted attention. An oxide semiconductor can be formed by a sputtering method or the like, and thus can be used for a semiconductor of a transistor included in a large display device. In addition, a transistor including an oxide semiconductor can be used by improving part of a production facility for a transistor using amorphous silicon, and thus has an advantage of suppressing capital investment.

Further, it is known that a transistor including an oxide semiconductor has extremely little leakage current in a non-conduction state. For example, a low power consumption CPU that uses a characteristic that a transistor including an oxide semiconductor has extremely low leakage current is disclosed (see Patent Document 1).

JP 2012-257187 A

An object is to provide a fine transistor. Another object is to provide a transistor with low parasitic capacitance. Another object is to provide a transistor with high frequency characteristics. An object is to provide a transistor with favorable electrical characteristics. Another object is to provide a transistor with stable electrical characteristics. Another object is to provide a transistor with low power consumption. Another object is to provide a highly reliable transistor. Another object is to provide a novel transistor. Another object is to provide a semiconductor device including at least one of these transistors.

Note that the description of these problems does not disturb the existence of other problems. Note that one embodiment of the present invention does not have to solve all of these problems. Issues other than these will be apparent from the description of the specification, drawings, claims, etc., and other issues can be extracted from the descriptions of the specification, drawings, claims, etc. It is.

One embodiment of the present invention includes first to third oxide layers, an insulating layer, first to third electrodes, and a structure, and the first oxide layer is in contact with the second oxide layer. The second oxide layer is in contact with the third oxide layer, and the first to third oxide layers have first regions that overlap with each other, and an insulating layer is interposed on the first region, A first electrode and a structure adjacent to a side surface of the first electrode, and the second oxide layer includes a second region overlapping with the first electrode, and a third region overlapping with the structure. A region, a fourth region in contact with the second electrode, and a fifth region in contact with the third electrode, the structure includes aluminum and oxygen, and the third to fifth regions include 2 is a transistor including an element different from the element included in the region 2.

The element different from the element contained in the second region is, for example, tungsten, titanium, or aluminum. The second oxide layer is preferably a CAAC-OS (C Axis Crystalline Oxide Semiconductor). The second oxide layer preferably contains one or both of In and Zn. It is preferable that a 1st oxide layer and a 3rd oxide layer contain the metal element of the same kind as at least 1 type of metal element among the metal elements contained in a 2nd oxide layer. Note that the CAAC-OS will be described in detail in Embodiment 3.

Alternatively, according to one embodiment of the present invention, the first step of forming the second oxide layer over the first oxide layer and the second step of processing the first and second oxide layers into an island shape A step, a third step of forming a third oxide layer covering the second oxide layer, a fourth step of forming a first insulating layer covering the third oxide layer, A fifth step of forming a first electrode on the first insulating layer, a sixth step of introducing an element into at least part of the second oxide layer using the first electrode as a mask, A seventh step of introducing oxygen into the first insulating layer, an eighth step of performing heat treatment, and a second insulating layer when forming the first insulating layer and the second insulating layer covering the first electrode; An eighth step of processing the layer to form a structure adjacent to the side surface of the first electrode; and a second oxide layer exposing a region that does not overlap the first electrode and the structure. And a tenth step of forming a second electrode and a third electrode in contact with the exposed region of the second oxide layer, wherein the second oxide layer is an oxide semiconductor. This is a method for manufacturing a transistor.

The seventh step is preferably performed by a sputtering method. The structure preferably includes aluminum and oxygen.

Another embodiment of the present invention is an electronic device including the transistor or the semiconductor device, and an antenna, a battery, an operation switch, a microphone, or a speaker.

A fine transistor can be provided. Alternatively, a transistor with low parasitic capacitance can be provided. Alternatively, a transistor with high frequency characteristics can be provided. A transistor with favorable electrical characteristics can be provided. Alternatively, a transistor with stable electric characteristics can be provided. Alternatively, a transistor with low power consumption can be provided. Alternatively, a highly reliable transistor can be provided. Alternatively, a novel transistor can be provided. Alternatively, a semiconductor device including at least one of these transistors can be provided.

Note that the description of these effects does not disturb the existence of other effects. Note that one embodiment of the present invention need not have all of these effects. It should be noted that the effects other than these are naturally obvious from the description of the specification, drawings, claims, etc., and it is possible to extract the other effects from the descriptions of the specification, drawings, claims, etc. It is.

4A and 4B are a top view and cross-sectional views illustrating a transistor according to one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a transistor according to one embodiment of the present invention. The figure explaining an energy band structure. 4A and 4B are a top view and cross-sectional views illustrating a transistor according to one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a transistor according to one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a transistor according to one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a transistor according to one embodiment of the present invention. 10A and 10B illustrate an example of a method for manufacturing a transistor according to one embodiment of the present invention. 10A and 10B illustrate an example of a method for manufacturing a transistor according to one embodiment of the present invention. 10A and 10B illustrate an example of a method for manufacturing a transistor according to one embodiment of the present invention. 10A and 10B illustrate an example of a method for manufacturing a transistor according to one embodiment of the present invention. 10A and 10B illustrate an example of a method for manufacturing a transistor according to one embodiment of the present invention. 10A and 10B illustrate an example of a method for manufacturing a transistor according to one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a transistor according to one embodiment of the present invention. FIG. 6 is a Cs-corrected high-resolution TEM image in a cross section of a CAAC-OS and a schematic cross-sectional view of the CAAC-OS. The Cs correction | amendment high-resolution TEM image in the plane of CAAC-OS. 6A and 6B illustrate structural analysis by XRD of a CAAC-OS and a single crystal oxide semiconductor. The figure which shows the electron diffraction pattern of CAAC-OS. FIG. 6 shows changes in crystal parts of an In—Ga—Zn oxide due to electron irradiation. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 6 is a cross-sectional view illustrating a semiconductor device according to one embodiment of the present invention. FIG. 10 is a circuit diagram of a semiconductor device according to one embodiment of the present invention. FIG. 10 is a circuit diagram of a semiconductor device according to one embodiment of the present invention. The block diagram which shows the structural example of CPU. FIG. 10 is a circuit diagram illustrating an example of a memory element. 2A and 2B illustrate an example of an imaging device. 2A and 2B illustrate an example of an imaging device. 2A and 2B illustrate an example of an imaging device. FIG. 6 illustrates a configuration example of a pixel. FIG. 6 illustrates a configuration example of a pixel. The circuit diagram which shows an example of an imaging device. Sectional drawing which shows the structural example of an imaging device. Sectional drawing which shows the structural example of an imaging device. 10A and 10B are a block diagram and a circuit diagram illustrating an example of a display device. FIG. 10 is a block diagram illustrating an example of a display device. FIG. 6 illustrates an example of a display device. FIG. 6 illustrates an example of a display device. FIG. 6 illustrates an example of a display module. FIG. 6 is a block diagram illustrating an example of an RF tag. 6A and 6B illustrate a usage example of an RF tag. The perspective view which shows the cross-section of the package using a lead frame type interposer. 10A and 10B each illustrate an example of an electronic device. The top view which shows an example of the film-forming apparatus. Sectional drawing which shows an example of the film-forming apparatus. 4A and 4B are a top view and cross-sectional views illustrating a transistor according to one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a transistor according to one embodiment of the present invention. 4A and 4B are a top view and cross-sectional views illustrating a transistor according to one embodiment of the present invention.

Embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it is easily understood by those skilled in the art that modes and details can be variously changed without departing from the spirit and scope of the present invention. Therefore, the present invention should not be construed as being limited to the description of the embodiments below. Note that in the structures of the invention described below, the same portions or portions having similar functions are denoted by the same reference numerals in different drawings, and description thereof is not repeated.

In addition, the position, size, range, and the like of each component illustrated in the drawings and the like may not represent the actual position, size, range, or the like in order to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, range, or the like disclosed in the drawings and the like. For example, in an actual manufacturing process, a layer or a resist mask may be lost unintentionally by a process such as etching, but may be omitted for easy understanding.

In the drawings, some components may be omitted for easy understanding of the invention. Moreover, description of some hidden lines may be omitted.

In the present specification and the like, ordinal numbers such as “first” and “second” are used to avoid confusion between components, and do not indicate any order or order such as process order or stacking order. In addition, even in terms that do not have an ordinal number in this specification and the like, an ordinal number may be added in the claims to avoid confusion between the constituent elements. Further, even terms having an ordinal number in this specification and the like may have different ordinal numbers in the claims. Even in the present specification and the like, terms with ordinal numbers are sometimes omitted in the claims.

Further, in this specification and the like, the terms “electrode” and “wiring” do not functionally limit these components. For example, an “electrode” may be used as part of a “wiring” and vice versa. Furthermore, the terms “electrode” and “wiring” include a case where a plurality of “electrodes” and “wirings” are integrally formed.

In the present specification and the like, the terms “upper” and “lower” do not limit that the positional relationship between the components is directly above or directly below and is in direct contact. For example, the expression “electrode B on the insulating layer A” does not require the electrode B to be formed in direct contact with the insulating layer A, and another configuration between the insulating layer A and the electrode B. Do not exclude things that contain elements.

In addition, since the functions of the source and the drain are switched with each other depending on operating conditions, such as when transistors with different polarities are used, or when the direction of current changes in circuit operation, which is the source or drain is limited. Is difficult. Therefore, in this specification, the terms source and drain can be used interchangeably.

In addition, in this specification and the like, when it is explicitly described that X and Y are connected, X and Y are electrically connected, and X and Y function. And the case where X and Y are directly connected are disclosed in this specification and the like. Therefore, it is not limited to a predetermined connection relationship, for example, the connection relationship shown in the figure or text, and anything other than the connection relation shown in the figure or text is also described in the figure or text.

In addition, in this specification and the like, “electrically connected” includes a case of being connected via “thing having some electric action”. Here, the “thing having some electric action” is not particularly limited as long as it can exchange electric signals between connection targets. Therefore, even in the case of being expressed as “electrically connected”, in an actual circuit, there is a case where there is no physical connection portion and the wiring is merely extended.

Note that the channel length refers to, for example, a region where a semiconductor (or a portion where current flows in the semiconductor when the transistor is on) and a gate electrode overlap with each other in a top view of the transistor, or a region where a channel is formed (Also referred to as “channel formation region”) refers to the distance between the source (source region or source electrode) and the drain (drain region or drain electrode). Note that in one transistor, the channel length is not necessarily the same in all regions. That is, the channel length of one transistor may not be fixed to one value. Therefore, in this specification, the channel length is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

The channel width is, for example, a region in which a semiconductor (or a portion in which a current flows in the semiconductor when the transistor is on) and a gate electrode overlap each other, or a source and a drain in a region where a channel is formed. This is the length of the part. Note that in one transistor, the channel width is not necessarily the same in all regions. That is, the channel width of one transistor may not be fixed to one value. Therefore, in this specification, the channel width is any one of values, the maximum value, the minimum value, or the average value in a region where a channel is formed.

Note that depending on the structure of the transistor, the channel width in a region where a channel is actually formed (also referred to as “effective channel width”) and the channel width (“apparent channel width” shown in the top view of the transistor) May also be different. For example, when the gate electrode covers the side surface of the semiconductor layer, the effective channel width may be larger than the apparent channel width, and the influence may not be negligible. For example, in a fine transistor whose gate electrode covers the side surface of the semiconductor layer, the ratio of the channel region formed on the side surface of the semiconductor layer may increase. In that case, the effective channel width becomes larger than the apparent channel width.

In such a case, it may be difficult to estimate the effective channel width by actual measurement. For example, in order to estimate the effective channel width from the design value, it is necessary to assume that the shape of the semiconductor is known. Therefore, it is difficult to accurately measure the effective channel width when the shape of the semiconductor is not accurately known.

Therefore, in this specification, the apparent channel width may be referred to as “surrounded channel width (SCW)”. In this specification, in the case where the term “channel width” is simply used, it may denote an enclosed channel width or an apparent channel width. Alternatively, in this specification, in the case where the term “channel width” is simply used, it may denote an effective channel width. Note that the channel length, channel width, effective channel width, apparent channel width, enclosed channel width, and the like can be determined by analyzing a cross-sectional TEM image or the like.

Note that in the case where the field-effect mobility of a transistor, the current value per channel width, and the like are calculated and calculated, the calculation may be performed using the enclosed channel width. In that case, the value may be different from that calculated using the effective channel width.

Note that the impurity of the semiconductor means, for example, a component other than the main component constituting the semiconductor. For example, an element having a concentration of less than 0.1 atomic% can be said to be an impurity. When the impurities are included, for example, the DOS (Density of State) of the semiconductor may increase, the carrier mobility may decrease, or the crystallinity may decrease. In the case where the semiconductor is an oxide semiconductor, examples of the impurity that changes the characteristics of the semiconductor include a Group 1 element, a Group 2 element, a Group 13 element, a Group 14 element, a Group 15 element, and an oxide semiconductor. There are transition metals other than the main components of, for example, hydrogen (also included in water), lithium, sodium, silicon, boron, phosphorus, carbon, nitrogen and the like. In the case of an oxide semiconductor, oxygen vacancies may be formed by mixing impurities such as hydrogen, for example. In the case where the semiconductor is silicon, examples of impurities that change the characteristics of the semiconductor include group 1 elements, group 2 elements, group 13 elements, and group 15 elements excluding oxygen and hydrogen.

Further, in this specification, “parallel” means a state in which two straight lines are arranged at an angle of −10 ° to 10 °. Therefore, the case of −5 ° to 5 ° is also included. Further, “substantially parallel” means a state in which two straight lines are arranged at an angle of −30 ° to 30 °. “Vertical” and “orthogonal” mean a state in which two straight lines are arranged at an angle of 80 ° to 100 °. Therefore, the case of 85 ° to 95 ° is also included. Further, “substantially vertical” means a state in which two straight lines are arranged at an angle of 60 ° to 120 °.

In addition, in this specification, etc., the terms “same”, “same”, “equal”, “uniform” (including these synonyms), etc. with respect to the count value and the measured value, unless otherwise specified. And an error of plus or minus 20%.

In this specification, in the case where an etching step is performed after a photolithography step, the resist mask formed in the photolithography step is removed after the etching step is finished unless otherwise specified.

In this specification and the like, the high power supply potential VDD (hereinafter, also simply referred to as “VDD” or “H potential”) indicates a power supply potential higher than the low power supply potential VSS. The low power supply potential VSS (hereinafter also simply referred to as “VSS” or “L potential”) indicates a power supply potential lower than the high power supply potential VDD. Alternatively, the ground potential can be used as VDD or VSS. For example, when VDD is a ground potential, VSS is a potential lower than the ground potential, and when VSS is a ground potential, VDD is a potential higher than the ground potential.

Note that the terms “film” and “layer” can be interchanged with each other depending on the case or circumstances. For example, the term “conductive layer” may be changed to the term “conductive film”. Alternatively, for example, the term “insulating film” may be changed to the term “insulating layer” in some cases.

In this specification, when a crystal is trigonal or rhombohedral, it is represented as a hexagonal system.

(Embodiment 1)
In this embodiment, a structural example of the transistor 100 of one embodiment of the present invention will be described with reference to drawings.

FIG. 1A is a plan view of the transistor 100. 1B is a cross-sectional view taken along dashed-dotted line L1-L2 and dashed-dotted line W1-W2 in FIG. 1B, a cross-sectional view taken along dashed-dotted line L1-L2 is a cross-sectional view in the channel length direction of the transistor 100, and a cross-sectional view taken along dashed-dotted line W1-W2 is a cross-sectional view in the channel width direction of the transistor 100.

The transistor 100 includes the oxide layer 104 (the oxide layer 104a, the oxide layer 104b, and the oxide layer 104c), the insulating layer 105, the electrode 106, the electrode 109a, the electrode 109b, and the structure body 108. The electrode 106 can function as a gate electrode. The insulating layer 105 can function as a gate insulating layer. The electrode 109a can function as one of a source electrode and a drain electrode. The electrode 109b can function as the other of the source electrode and the drain electrode. The transistor 100 is provided over the substrate 101 with the insulating layer 102 and the insulating layer 103 interposed therebetween.

In FIG. 1B, an insulating layer 102 is provided over a substrate 101, and an insulating layer 103 is provided over the insulating layer 102. The insulating layer 103 has a convex portion, and an island-shaped oxide layer 104a and an island-shaped oxide layer 104b are provided over the convex portion. Further, the oxide layer 104c is provided over the oxide layer 104b, and the insulating layer 105 is provided over the oxide layer 104c. The electrode 106 and the structure body 108 are provided over the oxide layer 104b with the oxide layer 104c and the insulating layer 105 interposed therebetween. The structure 108 is provided adjacent to the side surface of the electrode 106.

Further, the electrode 109a is provided in contact with part of the oxide layer 104b over the oxide layer 104b. The electrode 109b is provided over and in contact with the other part of the oxide layer 104b over the oxide layer 104b.

In the oxide layer 104, at least a region overlapping with the structure body 108 and a region overlapping with the electrodes 109a and 109b contain a metal element different from the main component of the oxide layer 104. For example, the metal element may be included in part of each of the insulating layer 105 and the insulating layer 103. A region including the metal element is referred to as a region 135. An end portion of the region 135 is indicated by a broken line in FIG. In FIG. 1B, the region 135 is formed above the broken line indicating the end portion of the region 135.

Note that in the oxide layer 104, the region 135 can function as a source region or a drain region of the transistor 100. Therefore, a region between the regions 135 of the oxide layer 104 can function as a channel formation region.

An insulating layer 107 is provided over the electrode 106. The insulating layer 110 is provided over the electrode 109 a, the electrode 109 b, the structure body 108, and the insulating layer 107. An insulating layer 111 is provided over the insulating layer 110, and an insulating layer 112 is provided over the insulating layer 111.

An electrode 114 a and an electrode 114 b are provided over the insulating layer 112. The electrode 114a is electrically connected to the electrode 109a through the contact plug 113a in an opening provided in part of the insulating layer 112, the insulating layer 111, and the insulating layer 110. The electrode 114b is electrically connected to the electrode 109b through the contact plug 113b in an opening provided in part of the insulating layer 112, the insulating layer 111, and the insulating layer 110.

In addition, as illustrated in FIG. 1B, in the transistor 100, in the cross-sectional view in the channel width direction, the electrode 106 covers the top surface and the side surface of the oxide layer 104b. When the insulating layer 103 has a convex portion, not only the top surface of the oxide layer 104 b but also the side surface can be covered with the electrode 106. In other words, the transistor 100 has a structure in which the oxide layer 104b can be electrically surrounded by the electric field of the electrode 106 (the structure of the transistor that electrically surrounds the semiconductor by the electric field of the conductive layer is referred to as a surrounded channel). (S-channel structure). Therefore, a channel can be formed in the entire oxide layer 104b (bulk). In the s-channel structure, the drain current (current flowing between the source and drain of the transistor) can be increased, and a larger on-current (current flowing between the source and drain when the transistor is on) can be obtained. Can do. Further, the entire region of the channel formation region formed in the oxide layer 104b can be depleted by the electric field of the electrode 106. Therefore, in the s-channel structure, the off-state current of the transistor (current that flows between the source and the drain when the transistor is off) can be further reduced. Note that by reducing the channel width, the effect of increasing the on-current, the effect of reducing the off-current, and the like due to the s-channel structure can be enhanced.

[Oxide layer 104]
The oxide layer 104 has a structure in which an oxide layer 104a, an oxide layer 104b, and an oxide layer 104c are stacked.

For the oxide layer 104, an oxide semiconductor containing indium (In) is preferably used, for example. For example, when the oxide semiconductor contains indium, the carrier mobility (electron mobility) increases. The oxide semiconductor preferably contains the element M.

The element M is preferably aluminum, gallium, yttrium or tin. Other elements applicable to the element M include boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. However, the element M may be a combination of a plurality of the aforementioned elements. The element M is an element having a high binding energy with oxygen, for example. The element M is an element having a function of increasing the energy gap of the oxide semiconductor, for example. The oxide semiconductor preferably contains zinc. An oxide semiconductor may be easily crystallized when it contains zinc.

Note that the oxide layer 104 is not limited to an oxide containing indium. The oxide layer 104 may be, for example, an oxide containing zinc, an oxide containing zinc, an oxide containing tin, or the like that does not contain indium, such as zinc tin oxide, gallium tin oxide, and gallium oxide. Absent.

For the oxide layer 104, an oxide semiconductor with a wide energy gap is used, for example. The energy gap of the oxide semiconductor used for the oxide layer 104 is, for example, 2.5 eV to 4.2 eV, preferably 2.8 eV to 3.8 eV, and more preferably 3 eV to 3.5 eV.

An oxide semiconductor is formed by a sputtering method, a CVD (Chemical Vapor Deposition) method (MOCVD (Metal Organic Chemical Deposition) method, an ALD (Atomic Layer Deposition Method), a thermal CVD method, or a PECVD (Plasma Deposition V method). However, the film formation may be performed using an MBE (Molecular Beam Epitaxy) method or a PLD (Pulsed Laser Deposition) method. In the plasma CVD method, a high-quality film can be obtained at a relatively low temperature. When a film formation method that does not use plasma at the time of film formation, such as an MOCVD method, an ALD method, or a thermal CVD method, a film on which a surface is formed is hardly damaged and a film with few defects is obtained.

The CVD method and the ALD method are film forming methods in which a film is formed by a reaction on the surface of an object to be processed, unlike a film forming method in which particles emitted from a target or the like are deposited. Therefore, it is a film forming method that is not easily affected by the shape of the object to be processed and has good step coverage. In particular, the ALD method has excellent step coverage and excellent thickness uniformity, and thus is suitable for covering the surface of an opening having a high aspect ratio. However, since the ALD method has a relatively low film formation rate, it may be preferable to use it in combination with another film formation method such as a CVD method with a high film formation rate.

In the CVD method and the ALD method, the composition of the obtained film can be controlled by the flow rate ratio of the source gases. For example, in the CVD method and the ALD method, a film having an arbitrary composition can be formed depending on the flow rate ratio of the source gases. Further, for example, in the CVD method and the ALD method, a film whose composition is continuously changed can be formed by changing the flow rate ratio of the source gas while forming the film. When film formation is performed while changing the flow rate ratio of the source gas, the time required for film formation can be shortened by the time required for conveyance and pressure adjustment compared to the case where film formation is performed using a plurality of film formation chambers. it can. Therefore, the productivity of transistors and semiconductor devices may be improved.

For example, when an InGaZnO _x (X> 0) film is formed as the oxide layer 104 by a thermal CVD method, trimethylindium (In (CH ₃ ) ₃ ), trimethylgallium (Ga (CH ₃ ) ₃ ), And dimethylzinc (Zn (CH ₃ ) ₂ ). The invention is not limited to these combinations, triethyl gallium instead of trimethylgallium _{(Ga (C 2 H 5)} 3) can also be used, diethylzinc in place of dimethylzinc _{(Zn (C 2 H 5)} 2) Can also be used.

For example, when an InGaZnO _x (X> 0) film is formed as the oxide layer 104 by ALD, an InO ₂ layer is formed by repeatedly introducing In (CH ₃ ) ₃ gas and O ₃ gas sequentially. Thereafter, Ga (CH ₃ ) ₃ gas and O ₃ gas are sequentially introduced repeatedly to form a GaO layer, and then Zn (CH ₃ ) ₂ gas and O ₃ gas are successively introduced to form a ZnO layer. To do. Note that the order of these layers is not limited to this example. Further, a mixed compound layer such as an InGaO ₂ layer, an InZnO ₂ layer, a GaInO layer, a ZnInO layer, or a GaZnO layer may be formed using these gases. Incidentally, O ₃ may be used of H _{2 O} gas obtained by bubbling water with an inert gas such as Ar in place of the gas, but better to use an O ₃ gas containing no H are preferred. Further, In (C ₂ H ₅ ) ₃ gas or tris (acetylacetonato) indium may be used instead of In (CH ₃ ) ₃ gas. Tris (acetylacetonato) indium is also called In (acac) ₃ . Further, Ga (C ₂ H ₅ ) ₃ gas or tris (acetylacetonato) gallium may be used instead of Ga (CH ₃ ) ₃ gas. Tris (acetylacetonato) gallium is also called Ga (acac) ₃ . Further, Zn (CH ₃ ) ₂ gas or zinc acetate may be used. It is not limited to these gas types.

In the case where an oxide semiconductor is formed by a sputtering method, a target containing indium is preferably used to reduce the number of particles. Further, when an oxide target having a high atomic ratio of the element M is used, the conductivity of the target may be lowered. In the case of using a target containing indium, the conductivity of the target can be increased, and DC discharge and AC discharge are facilitated, so that it is easy to deal with a large-area substrate. Therefore, the productivity of the semiconductor device can be increased.

In the case where an oxide semiconductor is formed by a sputtering method, the target atomic ratio is such that In: M: Zn is 3: 1: 1, 3: 1: 2, 3: 1: 4, or 1: 1: 0. 5, 1: 1: 1, 1: 1: 2, 1: 4: 4, 4: 2: 4.1, etc.

Note that when an oxide semiconductor is formed by a sputtering method, an oxide semiconductor with an atomic ratio that deviates from the atomic ratio of the target may be formed. In particular, in the case of zinc, the atomic number ratio of the formed film may be smaller than the atomic ratio of the target. Specifically, the atomic ratio of zinc contained in the target may be 40 atomic% or more and 90 atomic% or less.

The oxide layer 104a and the oxide layer 104c are preferably formed using a material containing one or more of the same metal elements among elements other than oxygen included in the oxide layer 104b. When such a material is used, interface states can be hardly generated at the interface between the oxide layer 104a and the oxide layer 104b and the interface between the oxide layer 104c and the oxide layer 104b. Thus, carrier scattering and trapping at the interface are unlikely to occur, and the field-effect mobility of the transistor can be improved. In addition, variation in threshold voltage of the transistor can be reduced. Therefore, a semiconductor device having favorable electrical characteristics can be realized.

The thickness of the oxide layer 104a and the oxide layer 104c is 3 nm to 100 nm, preferably 3 nm to 50 nm. The thickness of the oxide layer 104b is 3 nm to 200 nm, preferably 3 nm to 100 nm, more preferably 3 nm to 50 nm.

In addition, when the oxide layer 104b is an In-M-Zn oxide (an oxide containing In, the element M, and Zn), and the oxide layer 104a and the oxide layer 104c are also In-M-Zn oxides, The oxide layer 104a and the oxide layer 104c are formed of In: M: Zn = x ₁ : y ₁ : z ₁ [atomic ratio], and the oxide layer 104b is formed of In: M: Zn = x ₂ : y ₂ : z ₂ [ [Atom Ratio]], the oxide layer 104a, the oxide layer 104c, and the oxide layer 104b in which y ₁ / x ₁ is larger than y ₂ / x ₂ are selected. Preferably, the oxide layer 104a, the oxide layer 104c, and the oxide layer 104b in which y ₁ / x ₁ is 1.5 times or more larger than y ₂ / x ₂ are selected. More preferably, the oxide layer 104a, the oxide layer 104c, and the oxide layer 104b in which y ₁ / x ₁ is twice or more larger than y ₂ / x ₂ are selected. More preferably, the oxide layer 104a, the oxide layer 104c, and the oxide layer 104b in which y ₁ / x ₁ is three times or more larger than y ₂ / x ₂ are selected. At this time, in the oxide layer 104b, it is preferable that y ₁ is x ₁ or more because stable electrical characteristics can be imparted to the transistor. However, when y ₁ is 3 times or more of x ₁ , the field-effect mobility of the transistor is lowered. Therefore, y ₁ is preferably less than 3 times x ₁ . With the above structure of the oxide layer 104a and the oxide layer 104c, the oxide layer 104a and the oxide layer 104c can be layers in which oxygen vacancies are less likely to occur than in the oxide layer 104b.

Note that when the oxide layer 104a is an In-M-Zn oxide and the sum of In and M is 100 atomic%, In is preferably less than 50 atomic%, M is higher than 50 atomic%, and more preferably, In is 25 atomic%. %, M is higher than 75 atomic%. In the case where the oxide layer 104b is an In-M-Zn oxide, when the sum of In and M is 100 atomic%, In is preferably higher than 25 atomic%, M is less than 75 atomic%, and more preferably In is 34 atomic%. % And M is less than 66 atomic%. In the case where the oxide layer 104c is an In—M—Zn oxide, when the sum of In and M is 100 atomic%, In is preferably less than 50 atomic%, M is higher than 50 atomic%, and more preferably In is 25 atomic%. %, M is higher than 75 atomic%. Note that the oxide layer 104c may be formed using the same kind of oxide as the oxide layer 104a.

For example, as the oxide layer 104a containing In or Ga and the oxide layer 104c containing In or Ga, In: Ga: Zn = 1: 3: 2, 1: 3: 4, 1: 3: 6, 1: An In—Ga—Zn oxide formed using a target having an atomic ratio of 6: 4 or 1: 9: 6, or an atomic ratio target such as In: Ga = 1: 9 or 7:93 An In—Ga oxide formed using Si can be used. As the oxide layer 104b, for example, an In—Ga—Zn oxide formed using a target with an atomic ratio of In: Ga: Zn = 1: 1: 1 or 3: 1: 2 is used. it can. Note that the atomic ratios of the oxide layer 104a, the oxide layer 104b, and the oxide layer 104c each include a variation of plus or minus 20% of the above atomic ratio as an error.

As the oxide layer 104b, an oxide having an electron affinity higher than those of the oxide layer 104a and the oxide layer 104c is used. For example, the oxide layer 104b has an electron affinity of 0.07 eV to 1.3 eV, preferably 0.1 eV to 0.7 eV, and more preferably 0.15 eV to 0 than the oxide layer 104a and the oxide layer 104c. An oxide larger than 4 eV is used. Note that the electron affinity is the difference between the vacuum level and the energy at the bottom of the conduction band.

Note that indium gallium oxide has a small electron affinity and a high oxygen blocking property. Therefore, the oxide layer 104c preferably contains indium gallium oxide. The gallium atom ratio [Ga / (In + Ga)] is, for example, 70% or more, preferably 80% or more, and more preferably 90% or more.

However, the oxide layer 104a and / or the oxide layer 104c may be gallium oxide. For example, when gallium oxide is used for the oxide layer 104c, leakage current generated between the electrode 105a or the electrode 105b and the electrode 109 can be reduced. That is, the off-state current of the transistor 100 can be reduced.

The oxide layer 104a and the oxide layer 104c have an electron affinity smaller than that of the oxide layer 104b, and thus are closer to an insulator than the oxide layer 104b. Therefore, when a gate voltage is applied, a channel is likely to be formed in the oxide layer 104b among the oxide layer 104a, the oxide layer 104b, and the oxide layer 104c.

In order to provide stable electrical characteristics to a transistor in which an oxide semiconductor layer is used for a semiconductor layer in which a channel is formed (also referred to as an “OS transistor”), impurities and oxygen vacancies in the oxide semiconductor layer are reduced. It is preferable that the oxide layer 104b be an oxide semiconductor layer which can be regarded as intrinsic or substantially intrinsic by being reduced and highly purified intrinsic. In addition, it is preferable that at least a channel formation region in the oxide layer 104b be an oxide semiconductor layer which can be regarded as intrinsic or substantially intrinsic.

In addition, it is preferable to use CAAC-OS for at least the oxide layer 104b of the oxide layer 104.

In addition, in at least the oxide semiconductor layer used for the oxide layer 104b, a region that is not CAAC (also referred to as atomic void or “AV”) is preferably less than 20% of the entire oxide semiconductor layer.

The CAAC-OS has a dielectric anisotropy. Specifically, the CAAC-OS has a higher dielectric constant in the c-axis direction than that in the a-axis direction and the b-axis direction. A transistor in which a CAAC-OS is used for a semiconductor layer in which a channel is formed and a gate electrode is arranged in the c-axis direction has a large dielectric constant in the c-axis direction, so that an electric field generated from the gate electrode easily reaches the entire CAAC-OS. . Therefore, the subthreshold swing value (S value) can be reduced. Further, in a transistor in which a CAAC-OS is used for a semiconductor layer, an increase in S value due to miniaturization hardly occurs.

In addition, since the CAAC-OS has a small dielectric constant in the a-axis direction and the b-axis direction, the influence of an electric field generated between the source and the drain is reduced. Therefore, a channel length modulation effect, a short channel effect, and the like are hardly generated, and the reliability of the transistor can be improved.

Here, the channel length modulation effect refers to a phenomenon in which when the drain voltage is higher than the threshold voltage, the depletion layer spreads from the drain side, and the effective channel length is shortened. The short channel effect refers to a phenomenon in which deterioration of electrical characteristics such as a decrease in threshold voltage occurs due to a short channel length. The finer the transistor, the easier it is for electrical characteristics to deteriorate due to these phenomena.

[Energy band structure of oxide semiconductor layer]
Here, the function and effect of the oxide layer 104 formed by stacking the oxide layer 104a, the oxide layer 104b, and the oxide layer 104c will be described with reference to the energy band structure diagram in FIG. To do. FIG. 3A illustrates an energy band structure of a portion indicated by a dashed-dotted line in A1-A2 in FIG. That is, FIG. 3A illustrates an energy band structure of a channel formation region of the transistor 100.

In FIG. 3A, Ec382, Ec383a, Ec383b, Ec383c, and Ec386 indicate the energy at the lower end of the conduction band of the insulating layer 103, the oxide layer 104a, the oxide layer 104b, the oxide layer 104c, and the insulating layer 105, respectively. ing.

Here, the electron affinity is a value obtained by subtracting the energy gap from the difference between the vacuum level and the energy at the top of the valence band (also referred to as “ionization potential”). The energy gap can be measured using a spectroscopic ellipsometer (HORIBA JOBIN YVON UT-300). The energy difference between the vacuum level and the upper end of the valence band can be measured using an ultraviolet photoelectron spectroscopy (UPS) apparatus (PHI VersaProbe).

Note that an In—Ga—Zn oxide formed using a target with an atomic ratio of In: Ga: Zn = 1: 3: 2 has an energy gap of approximately 3.5 eV and an electron affinity of approximately 4.5 eV. In addition, an In—Ga—Zn oxide formed using a target with an atomic ratio of In: Ga: Zn = 1: 3: 4 has an energy gap of about 3.4 eV and an electron affinity of about 4.5 eV. In addition, an In—Ga—Zn oxide formed using a target with an atomic ratio of In: Ga: Zn = 1: 3: 6 has an energy gap of about 3.3 eV and an electron affinity of about 4.5 eV. In addition, an In—Ga—Zn oxide formed using a target with an atomic ratio of In: Ga: Zn = 1: 6: 2 has an energy gap of about 3.9 eV and an electron affinity of about 4.3 eV. In addition, an In—Ga—Zn oxide formed using a target with an atomic ratio of In: Ga: Zn = 1: 6: 8 has an energy gap of approximately 3.5 eV and an electron affinity of approximately 4.4 eV. In addition, an In—Ga—Zn oxide formed using a target with an atomic ratio of In: Ga: Zn = 1: 6: 10 has an energy gap of about 3.5 eV and an electron affinity of about 4.5 eV. An In—Ga—Zn oxide formed using a target with an atomic ratio of In: Ga: Zn = 1: 1: 1 has an energy gap of about 3.2 eV and an electron affinity of about 4.7 eV. An In—Ga—Zn oxide formed using a target with an atomic ratio of In: Ga: Zn = 3: 1: 2 has an energy gap of approximately 2.8 eV and an electron affinity of approximately 5.0 eV.

Since the insulating layer 103 and the insulating layer 105 are insulators, Ec382 and Ec386 are closer to a vacuum level (having a lower electron affinity) than Ec383a, Ec383b, and Ec383c.

Ec383a is closer to the vacuum level than Ec383b. Specifically, Ec383a is closer to a vacuum level than Ec383b by 0.07 eV to 1.3 eV, preferably 0.1 eV to 0.7 eV, more preferably 0.15 eV to 0.4 eV. .

Ec383c is closer to the vacuum level than Ec383b. Specifically, Ec383c is preferably closer to a vacuum level than Ec383b by 0.07 eV to 1.3 eV, preferably 0.1 eV to 0.7 eV, more preferably 0.15 eV to 0.4 eV. .

Here, in some cases, there is a mixed region of the oxide layer 104a and the oxide layer 104b between the oxide layer 104a and the oxide layer 104b. Further, in some cases, there is a mixed region of the oxide layer 104b and the oxide layer 104c between the oxide layer 104b and the oxide layer 104c. In the mixed region, the interface state density is low. Therefore, the stack of the oxide layer 104a, the oxide layer 104b, and the oxide layer 104c has a band structure in which energy continuously changes (also referred to as continuous bonding) in the vicinity of each interface.

At this time, electrons move mainly in the oxide layer 104b, not in the oxide layer 104a and the oxide layer 104c. Therefore, by reducing the interface state density at the interface between the oxide layer 104a and the oxide layer 104b and the interface state density at the interface between the oxide layer 104b and the oxide layer 104c, electrons in the oxide layer 104b can be reduced. The movement is hardly inhibited and the on-state current of the transistor 100 can be increased.

Although trap levels 390 due to impurities and defects can be formed at or near the interface between the oxide layer 104a and the insulating layer 103 and near or near the interface between the oxide layer 104c and the insulating layer 105, With the oxide layer 104a and the oxide layer 104c, the oxide layer 104b and the trap level can be kept away from each other.

Note that in the case where the transistor 100 has an s-channel structure, a channel is formed in the entire oxide layer 104b. Therefore, the thicker the oxide layer 104b, the larger the channel region. That is, the thicker the oxide layer 104b, the higher the on-state current of the transistor 100. For example, the oxide layer 104b may have a thickness of 20 nm or more, preferably 40 nm or more, more preferably 60 nm or more, more preferably 100 nm or more. However, since the productivity of the semiconductor device including the transistor 100 may be reduced, for example, the oxide layer 104b having a region with a thickness of 300 nm or less, preferably 200 nm or less, and more preferably 150 nm or less may be used.

In order to increase the on-state current of the transistor 100, the thickness of the oxide layer 104c is preferably as small as possible. For example, the oxide layer 104c may have a region less than 10 nm, preferably 5 nm or less, and more preferably 3 nm or less. On the other hand, the oxide layer 104c has a function of blocking entry of elements other than oxygen (such as hydrogen and silicon) included in the adjacent insulator into the oxide layer 104b where a channel is formed. Therefore, the oxide layer 104c preferably has a certain thickness. For example, the oxide layer 104c may have a thickness of 0.3 nm or more, preferably 1 nm or more, and more preferably 2 nm or more.

In order to increase reliability, the oxide layer 104a is preferably thick and the oxide layer 104c is preferably thin. For example, the oxide layer 104a may have a thickness of 10 nm or more, preferably 20 nm or more, more preferably 40 nm or more, and more preferably 60 nm or more. By increasing the thickness of the oxide layer 104a, the distance from the interface between the adjacent insulator and the oxide layer 104a to the oxide layer 104b where a channel is formed can be increased. However, since the productivity of the semiconductor device including the transistor 100 may be reduced, the oxide layer 104a may have a thickness of 200 nm or less, preferably 120 nm or less, and more preferably 80 nm or less.

Note that silicon in the oxide semiconductor might serve as a carrier trap or a carrier generation source. Therefore, the lower the silicon concentration of the oxide layer 104b, the better. For example, between the oxide layer 104b and the oxide layer 104a, for example, in secondary ion mass spectrometry (SIMS), less than 1 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ The region has a silicon concentration of less than atoms / cm ³ , more preferably less than 2 × 10 ¹⁸ atoms / cm ³ . In addition, in SIMS, the oxide layer 104b and the oxide layer 104c are less than 1 × 10 ¹⁹ atoms / cm ³ , preferably less than 5 × 10 ¹⁸ atoms / cm ³ , and more preferably 2 × 10 ¹⁸ atoms / cm ^3. The region has a silicon concentration of less than cm ³ .

It is preferable to reduce the hydrogen concentration in the oxide layer 104a and the oxide layer 104c in order to reduce the hydrogen concentration in the oxide layer 104b. The oxide layer 104a and the oxide layer 104c each have a SIMS of 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ³ or less. Preferably, the region has a hydrogen concentration of 5 × 10 ¹⁸ atoms / cm ³ or less. In order to reduce the nitrogen concentration in the oxide layer 104b, it is preferable to reduce the nitrogen concentration in the oxide layer 104a and the oxide layer 104c. The oxide layer 104a and the oxide layer 104c are less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, in SIMS. Preferably, it has a region having a nitrogen concentration of 5 × 10 ¹⁷ atoms / cm ³ or less.

Note that when copper is mixed into an oxide semiconductor, an electron trap may be generated. The electron trap may cause the threshold voltage of the transistor to fluctuate in the positive direction. Therefore, the lower the copper concentration on the surface or inside of the oxide layer 104b, the better. For example, the oxide layer 104b preferably includes a region in which the copper concentration is 1 × 10 ¹⁹ atoms / cm ³ or less, 5 × 10 ¹⁸ atoms / cm ³ or less, or 1 × 10 ¹⁸ atoms / cm ³ or less.

The above three-layer structure is an example. For example, a two-layer structure without the oxide layer 104a or the oxide layer 104c may be used. Alternatively, a four-layer structure including any one of the semiconductors exemplified as the oxide layer 104a, the oxide layer 104b, and the oxide layer 104c over or under the oxide layer 104a or over or under the oxide layer 104c I do not care. Alternatively, the oxide layer 104a, the oxide layer 104b, and the oxide layer may be provided at any two or more positions over the oxide layer 104a, under the oxide layer 104a, over the oxide layer 104c, and under the oxide layer 104c. An n-layer structure (n is an integer of 5 or more) including any one of the semiconductors exemplified as 104c may be used.

In particular, the transistor 100 illustrated in this embodiment is formed so that the upper surface and side surfaces of the oxide layer 104b are in contact with the oxide layer 104c and the lower surface of the oxide layer 104b is in contact with the oxide layer 104a in the channel width direction. (See FIG. 1B). In this manner, the structure of the oxide layer 104b covered with the oxide layer 104a and the oxide layer 104c can further reduce the influence of the trap states.

The band gap of the oxide layer 104a and the oxide layer 104c is preferably wider than the band gap of the oxide layer 104b.

According to one embodiment of the present invention, a transistor with little variation in electrical characteristics can be realized. Thus, a semiconductor device with little variation in electrical characteristics can be realized. According to one embodiment of the present invention, a highly reliable transistor can be realized. Therefore, a highly reliable semiconductor device can be realized.

In addition, since the band gap of an oxide semiconductor is 2 eV or more, a transistor in which an oxide semiconductor is used for a semiconductor layer in which a channel is formed can have extremely low off-state current. Specifically, the off-current per channel width of 1 μm is less than 1 × 10 ⁻²⁰ A, less than 1 × 10 ⁻²² A, or 1 at a source-drain voltage of 3.5 V and room temperature (25 ° C.). It may be less than × 10 ⁻²⁴ A. That is, the on / off ratio can be 20 digits or more and 150 digits or less.

According to one embodiment of the present invention, a transistor with low power consumption can be realized. Therefore, a semiconductor device with low power consumption can be realized.

<Modification 1>
FIG. 2 illustrates a transistor 150 in which the oxide layer 104 includes the oxide layer 104b and the oxide layer 104c without providing the oxide layer 104a. FIG. 2B is a cross-sectional view taken along dashed-dotted line L1-L2 and dashed-dotted line W1-W2 shown in FIG. The transistor 150 has the same structure as the transistor 100 except for the structure of the oxide layer 104.

FIG. 3B illustrates an energy band structure of a portion indicated by a dashed-dotted line in B1-B2 in FIG. That is, FIG. 3B illustrates an energy band structure of a channel formation region of the transistor 150. In the transistor 150, since the oxide layer 104a is not provided, the transistor 150 is easily affected by the trap level 390. However, the field effect transfer is higher than that in the case where the oxide layer 104c is not provided and the oxide layer 104b is provided. Degrees can be realized.

<Modification 2>
A transistor 160 illustrated in FIG. 4 is different from the transistor 100 in that an electrode 119 functioning as a back gate electrode is provided between the insulating layer 102 and the insulating layer 103. FIG. 4A is a plan view of the transistor 160. FIG. 4B is a cross-sectional view taken along dashed-dotted line L1-L2 and dashed-dotted line W1-W2 shown in FIG. The electrode 119 can be formed using a material and a method similar to those of the electrode 105a.

In general, the back gate electrode is formed using a conductive layer, and the channel formation region of the semiconductor layer is sandwiched between the gate electrode and the back gate electrode. Therefore, the back gate electrode can function in the same manner as the gate electrode. The potential of the back gate electrode may be the same as that of the gate electrode, or may be a ground potential (GND potential) or an arbitrary potential. In addition, the threshold voltage of the transistor can be changed by changing the potential of the back gate electrode independently of the gate electrode.

Both the electrode 106 and the electrode 119 can function as gate electrodes. Thus, each of the insulating layer 103 and the insulating layer 105 can function as a gate insulating layer.

Note that when one of the electrode 106 and the electrode 119 is referred to as a “gate electrode”, the other is referred to as a “back gate electrode”. For example, in the transistor 160, when the electrode 106 is referred to as a “gate electrode”, the electrode 119 is referred to as a “back gate electrode”. In the case where the electrode 119 is used as a “gate electrode”, the transistor 160 can be regarded as a kind of bottom-gate transistor. One of the electrode 106 and the electrode 119 may be referred to as a “first gate electrode” and the other may be referred to as a “second gate electrode”.

By providing the electrode 106 and the electrode 119 with the oxide layer 104 interposed therebetween, and further by setting the electrode 106 and the electrode 119 to the same potential, a region where carriers flow in the oxide layer 104 becomes larger in the film thickness direction. Therefore, the amount of carrier movement increases. As a result, the on-state current of the transistor 160 is increased and the field effect mobility is increased.

Therefore, the transistor 160 is a transistor having a large on-state current with respect to the occupied area. That is, the area occupied by the transistor 160 can be reduced with respect to the required on-state current. Therefore, a highly integrated semiconductor device can be realized.

In addition, since the gate electrode and the back gate electrode are formed using conductive layers, they have a function of preventing an electric field generated outside the transistor from acting on a semiconductor layer in which a channel is formed (particularly, an electric field shielding function against static electricity). . Note that the electric field shielding function can be improved by forming the back gate electrode larger than the semiconductor layer and covering the semiconductor layer with the back gate electrode.

Since each of the electrode 106 and the electrode 119 has a function of shielding an electric field from the outside, charges such as charged particles generated above the electrode 106 and below the electrode 119 do not affect the channel formation region of the oxide layer 104. As a result, deterioration of a stress test (for example, a gate bias-temperature (GBT) stress test in which a negative charge is applied to the gate) is suppressed. Further, the electrode 106 and the electrode 119 can be blocked so that an electric field generated from the drain electrode does not act on the semiconductor layer. Therefore, fluctuations in the rising current of the on-current due to fluctuations in the drain voltage can be suppressed. Note that this effect is remarkable when a potential is supplied to the electrode 106 and the electrode 119.

Note that the BT stress test is a kind of accelerated test, and it is possible to evaluate a change in characteristics (aging) of a transistor caused by long-term use in a short time. In particular, the amount of change in the threshold voltage of the transistor before and after the BT stress test is an important index for examining reliability. Before and after the BT stress test, the smaller the variation amount of the threshold voltage, the higher the reliability of the transistor.

In addition, since the electrode 106 and the electrode 119 are provided and the electrode 106 and the electrode 119 are set to the same potential, the amount of fluctuation in the threshold voltage is reduced. For this reason, variation in electrical characteristics among a plurality of transistors is also reduced at the same time.

In addition, a transistor having a back gate electrode also has a smaller threshold voltage variation before and after the + GBT stress test in which a positive charge is applied to the gate than a transistor having no back gate electrode.

In addition, when light enters from the back gate electrode side, the back gate electrode is formed using a light-shielding conductive film, whereby light can be prevented from entering the semiconductor layer from the back gate electrode side. Therefore, light deterioration of the semiconductor layer can be prevented, and deterioration of electrical characteristics such as shift of the threshold voltage of the transistor can be prevented.

For example, as illustrated in FIG. 4C, the insulating layer 116 is formed over the electrode 119, the insulating layer 115 is formed over the insulating layer 116, and the insulating layer 103 is formed over the insulating layer 115. Good. The insulating layer 116 and the insulating layer 115 can be formed using a material and a method similar to those of the insulating layer 103.

Note that when the insulating layer 115 is formed using hafnium oxide, aluminum oxide, tantalum oxide, aluminum silicate, or the like, the insulating layer 115 can function as a charge trapping layer. By injecting electrons into the insulating layer 115, the threshold voltage of the transistor can be changed. The injection of electrons into the insulating layer 115 may use the tunnel effect, for example. By applying a positive voltage to the electrode 119, tunnel electrons can be injected into the insulating layer 115.

<Modification 3>
As in the transistor 170 illustrated in FIG. 5, the electrode 119 may be provided between the substrate 101 and the insulating layer 102. FIG. 5A is a plan view of the transistor 170. FIG. 5B is a cross-sectional view taken along dashed-dotted line L1-L2 and dashed-dotted line W1-W2 shown in FIG.

In the case where the electrode 119 is provided between the substrate 101 and the insulating layer 102, the insulating layer 102 can also function as a gate insulating layer.

For example, as illustrated in FIG. 5C, the insulating layer 102 and the insulating layer 116 are formed over the electrode 119, the insulating layer 115 is formed over the insulating layer 116, and the insulating layer 103 is formed over the insulating layer 115. It may be formed.

<Modification 4>
As in the transistor 180 illustrated in FIG. 6, the insulating layer 105 and the oxide layer 104 c may be provided in a region overlapping with the electrode 106 and not provided in a region overlapping with the structure body 108. FIG. 6A is a plan view of the transistor 180. FIG. 6B is a cross-sectional view taken along dashed-dotted line L1-L2 and dashed-dotted line W1-W2 shown in FIG.

<Modification 5>
As in the transistor 190 illustrated in FIGS. 7A and 7B, the oxide layer 104c may be left without being etched. FIG. 7A is a plan view of the transistor 190. FIG. FIG. 7B is a cross-sectional view taken along dashed-dotted line L1-L2 and dashed-dotted line W1-W2 shown in FIG.

<Modification 6>
As in the transistor 191 illustrated in FIG. 47, the insulating layer 105 overlapping with the structure body 108 may be removed so that the structure body 108 and the oxide layer 104c are in contact with each other. FIG. 47A is a plan view of the transistor 191. FIG. 47B is a cross-sectional view taken along dashed-dotted line L1-L2 and dashed-dotted line W1-W2 in FIG.

<Modification 7>
As in the transistor 192 illustrated in FIG. 48, the oxide layer 104 c overlapping with the electrode 106 may be covered with the insulating layer 105. FIG. 48A is a plan view of the transistor 192. FIG. FIG. 48B is a cross-sectional view taken along dashed-dotted line L1-L2 and dashed-dotted line W1-W2 shown in FIG.

<Modification 8>
As in the transistor 193 illustrated in FIG. 49, the oxide layer 104 c may exist beyond the end portion of the structure body 108. FIG. 49A is a plan view of the transistor 193. FIG. FIG. 49B is a cross-sectional view taken along dashed-dotted line L1-L2 and dashed-dotted line W1-W2 shown in FIG.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 2)
In this embodiment, an example of a method for manufacturing the transistor 100 will be described with reference to drawings. 8 to 13 corresponds to a cross section taken along one-dot chain line L1-L2 illustrated in FIG. 8 to 13 corresponds to a cross section taken along alternate long and short dash line W1-W2 in FIG.

First, the insulating layer 102 is formed over the substrate 101, and the insulating layer 103 is formed over the insulating layer 102 (see FIG. 8A).

There is no particular limitation on the material used for the substrate 101, but it is necessary to have heat resistance enough to withstand at least heat treatment performed later. For example, a glass substrate such as barium borosilicate glass or alumino borosilicate glass, a ceramic substrate, a quartz substrate, a sapphire substrate, or the like can be used.

Alternatively, the substrate 101 may be a single crystal semiconductor substrate using silicon, silicon carbide, or the like, a polycrystalline semiconductor substrate, a compound semiconductor substrate using silicon germanium, or the like. Alternatively, an SOI substrate, a semiconductor substrate provided with a semiconductor element such as a strain transistor or a FIN transistor, or the like can be used. Alternatively, gallium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium nitride, indium phosphide, silicon germanium, or the like that can be used for a high electron mobility transistor (HEMT) may be used. That is, the substrate 101 is not limited to a simple support substrate, and may be a substrate on which other devices such as transistors are formed. In this case, at least one of the gate, the source, and the drain of the transistor 100 may be electrically connected to the other device.

Note that a flexible substrate (flexible substrate) may be used as the substrate 101. In the case of using a flexible substrate, a transistor, a capacitor, or the like may be directly formed over the flexible substrate, or a transistor, a capacitor, or the like is formed over another manufacturing substrate, and then the flexible substrate is formed. You may peel and transpose. Note that a separation layer may be provided between the manufacturing substrate and a transistor, a capacitor, or the like in order to separate and transfer from the manufacturing substrate to the flexible substrate.

As the flexible substrate, for example, metal, alloy, resin or glass, or fiber thereof can be used. The flexible substrate used for the substrate 101 is preferably as the linear expansion coefficient is low because deformation due to the environment is suppressed. For the flexible substrate used for the substrate 101, for example, a material having a linear expansion coefficient of 1 × 10 ⁻³ / K or less, 5 × 10 ⁻⁵ / K or less, or 1 × 10 ⁻⁵ / K or less may be used. . Examples of the resin include polyester, polyolefin, polyamide (such as nylon and aramid), polyimide, polycarbonate, and acrylic resin. In particular, since aramid has a low coefficient of linear expansion, it is suitable as a flexible substrate.

The insulating layer 102 includes aluminum nitride, aluminum oxide, aluminum nitride oxide, aluminum oxynitride, magnesium oxide, silicon nitride, silicon oxide, silicon nitride oxide, silicon oxynitride, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, and lanthanum oxide. A material selected from neodymium oxide, hafnium oxide, tantalum oxide, aluminum silicate, or the like is used as a single layer or a stacked layer. Alternatively, a material obtained by mixing a plurality of materials among oxide materials, nitride materials, oxynitride materials, and nitride oxide materials may be used.

Note that in this specification, a nitrided oxide refers to a compound having a higher nitrogen content than oxygen. Further, oxynitride refers to a compound having a higher oxygen content than nitrogen. The content of each element can be measured using, for example, Rutherford Backscattering Spectrometry (RBS).

In particular, the insulating layer 102 is preferably formed using an insulating material which does not easily transmit impurities. For example, an insulating material including boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium or tantalum, in a single layer, or What is necessary is just to use it by lamination | stacking. For example, as an insulating material that hardly permeates impurities, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, tantalum oxide, Examples thereof include silicon nitride. Alternatively, the insulating layer 102 may be made of indium tin zinc oxide (In—Sn—Zn oxide) with high insulating properties.

By using an insulating material that does not easily transmit impurities for the insulating layer 102, diffusion of impurities from the substrate 101 side can be suppressed and the reliability of the transistor can be improved. By using an insulating material that does not easily transmit impurities for the insulating layer 110, diffusion of impurities from the insulating layer 111 side can be suppressed and the reliability of the transistor can be improved.

As the insulating layer 102, a plurality of insulating layers formed using these materials may be stacked. The formation method of the insulating layer 102 is not particularly limited, and various formation methods such as a sputtering method, a CVD method, an MBE method, a PLD method, an ALD method, and a spin coating method can be used. The thickness of the insulating layer 102 and the insulating layer 110 may be 10 nm to 500 nm, preferably 50 nm to 300 nm.

For example, in the case where an aluminum oxide film is formed as the insulating layer 102 using a thermal CVD method, a source gas obtained by vaporizing a liquid (such as trimethylaluminum (TMA)) containing a solvent and an aluminum precursor compound, and an oxidizing agent Two kinds of gases of H ₂ O are used. The chemical formula of TMA is Al (CH ₃ ) ₃ . Other material liquids include tris (dimethylamido) aluminum, triisobutylaluminum, aluminum tris (2,2,6,6-tetramethyl-3,5-heptanedionate) and the like.

The insulating layer 103 can be formed using a material and a method similar to those of the insulating layer 102. In order to prevent an increase in the hydrogen concentration in the oxide layer 104, the hydrogen concentration in the insulating layer 103 is preferably reduced. Specifically, the hydrogen concentration in the insulating layer 103 is 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ³ or less, more preferably 1 × 10 ¹⁹ atoms / cm ^{3 in} SIMS. ³ or less, more preferably 5 × 10 ¹⁸ atoms / cm ³ or less. In order to prevent an increase in nitrogen concentration in the oxide semiconductor, it is preferable to reduce the nitrogen concentration in the insulating layer 103. Specifically, the nitrogen concentration in the insulating layer 103 is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ^{3 in} SIMS. ³ or less, more preferably 5 × 10 ¹⁷ atoms / cm ³ or less.

The insulating layer 103 is preferably formed using an insulating layer from which oxygen is released by heating (also referred to as an “insulating layer containing excess oxygen”). Specifically, the amount of desorbed oxygen converted to oxygen atoms in TDS analysis is 1.0 × 10 ¹⁸ atoms / cm ³ or more, preferably 3.0 × 10 ²⁰ atoms / cm ³ or more. Is preferably used.

The insulating layer containing excess oxygen can also be formed by performing treatment for adding oxygen to the insulating layer. The treatment for adding oxygen can be performed using heat treatment in an oxygen atmosphere, an ion implantation apparatus, an ion doping apparatus, or a plasma treatment apparatus. As a gas for adding oxygen, oxygen gas such as ¹⁶ O ₂ or ¹⁸ O ₂ , nitrous oxide gas, ozone gas, or the like can be used. Note that in this specification, treatment for adding oxygen is also referred to as “oxygen doping treatment”.

The thickness of the insulating layer 103 may be 10 nm to 500 nm, preferably 50 nm to 300 nm.

In this embodiment, a glass substrate is used as the substrate 101. Further, aluminum oxide is used for the insulating layer 102. As the insulating layer 103, silicon oxynitride containing excess oxygen is used.

Next, the oxide layer 124a, the oxide layer 124b, and the insulating layer 125 are formed over the insulating layer 103 (see FIG. 8B). First, the oxide layer 124a is formed over the insulating layer 103, and the oxide layer 124b is formed over the oxide layer 124a.

In this embodiment, a CAAC-OS containing In, Ga, and Zn is formed as the oxide layer 124a by a sputtering method with a target having an atomic ratio of In: Ga: Zn = 1: 3: 4. To do. As the oxide layer 124b, a CAAC-OS containing In, Ga, and Zn is formed using a target with an atomic ratio of In: Ga: Zn = 1: 1: 1. Note that oxygen doping treatment may be performed after the oxide layer 124a is formed. Alternatively, oxygen doping treatment may be performed after the oxide layer 124b is formed.

Next, heat treatment is performed to further reduce impurities such as moisture or hydrogen contained in the oxide layer 124a and the oxide layer 124b so that the oxide layer 124a and the oxide layer 124b are highly purified. preferable.

For example, the amount of moisture when measured using a dew point meter under a reduced pressure atmosphere, an inert atmosphere such as nitrogen or a rare gas, an oxidizing atmosphere, or ultra-dry air (CRDS (cavity ring down laser spectroscopy) method) Heat treatment is performed on the oxide semiconductor layer 124a and the oxide semiconductor layer 124b in an atmosphere of 20 ppm (-55 ° C. in terms of dew point) or less, preferably 1 ppm or less, preferably 10 ppb or less. Note that the oxidizing atmosphere refers to an atmosphere containing 10 ppm or more of an oxidizing gas such as oxygen, ozone, or oxygen nitride. Further, the inert atmosphere refers to an atmosphere filled with nitrogen or a rare gas, in which the oxidizing gas is less than 10 ppm.

In addition, by performing heat treatment, oxygen contained in the insulating layer 103 is diffused into the oxide layer 124a and the oxide layer 124b at the same time as the release of impurities, so that oxygen vacancies in the oxide semiconductor layer are reduced. Can do. Note that after heat treatment in an inert atmosphere, heat treatment may be performed in an atmosphere containing an oxidizing gas of 10 ppm or more, 1% or more, or 10% or more in order to supplement the desorbed oxygen. Note that the heat treatment may be performed at any time after the oxide semiconductor layer 118a and the oxide semiconductor layer 118b are formed. For example, heat treatment may be performed after the oxide layer 104a and the oxide layer 104b are formed. Alternatively, this step may be performed after the oxide layer 104c to be formed later.

There is no particular limitation on a heating device used for the heat treatment, and a device for heating an object to be processed by heat conduction or heat radiation from a heating element such as a resistance heating element may be used. For example, an electric furnace, a rapid thermal annealing (RTTA) apparatus, a rapid thermal annealing (RTA) apparatus such as a GRTA (gas rapid thermal annealing) apparatus, or the like can be used. The LRTA apparatus is an apparatus that heats an object to be processed by radiation of light (electromagnetic waves) emitted from a lamp such as a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure sodium lamp, or a high pressure mercury lamp. The GRTA apparatus is an apparatus that performs heat treatment using a high-temperature gas.

The heat treatment may be performed at 250 ° C to 650 ° C, preferably 300 ° C to 500 ° C. The processing time is within 24 hours. Heat treatment for more than 24 hours is not preferable because it causes a decrease in productivity.

Note that oxygen doping treatment may be performed after the oxide layer 124a is formed. Alternatively, oxygen doping treatment may be performed after the oxide layer 124b is formed.

Next, a resist mask is formed over the oxide layer 124b (not shown). The resist mask can be formed by appropriately using a photolithography method, a printing method, an inkjet method, or the like. When a resist mask is formed by a printing method, an ink jet method, or the like, a photomask is not used, so that manufacturing costs can be reduced.

Formation of the resist mask by photolithography is performed by irradiating the photosensitive resist with light through the photomask and removing the resist in the exposed portion (or the unexposed portion) using a developer. Examples of the light applied to the photosensitive resist include KrF excimer laser light, ArF excimer laser light, and EUV (Extreme Ultraviolet) light. Further, an immersion technique may be used in which exposure is performed by filling a liquid (for example, water) between the substrate and the projection lens. Further, instead of the light described above, an electron beam or an ion beam may be used. Note that when an electron beam or an ion beam is used, a photomask is not necessary. Note that the resist mask can be removed by a dry etching method such as ashing or a wet etching method using a dedicated stripping solution. Both dry etching and wet etching may be used.

Part of the oxide layer 124b and the oxide layer 124a is selectively removed using the resist mask as a mask. At this time, part of the insulating layer 103 may be removed, and a convex portion may be formed in the insulating layer 103. Note that the oxide layer 124b and the oxide layer 124a may be removed (etched) by a dry etching method or a wet etching method, or both of them may be used. In this manner, the island-shaped oxide layer 104a and the island-shaped oxide layer 104b are formed (see FIG. 8C).

Note that in the case where the conductive layer, the semiconductor layer, and the insulating layer are etched by a dry etching method, a gas containing a halogen element can be used as an etching gas. As an example of a gas containing a halogen element, a chlorine-based gas such as chlorine (Cl ₂ ), boron trichloride (BCl ₃ ), silicon tetrachloride (SiCl ₄ ), carbon tetrachloride (CCl ₄ ), or the like is used. Fluorine gas such as carbon fluoride (CF ₄ ), sulfur hexafluoride (SF ₆ ), nitrogen trifluoride (NF ₃ ) or trifluoromethane (CHF ₃ ), hydrogen bromide (HBr), or oxygen as appropriate Can be used. Further, an inert gas may be added to the etching gas used. As an etching gas for etching an oxide semiconductor, a hydrocarbon-based gas such as methane (CH ₄ ), ethane (C ₂ H ₆ ), propane (C ₃ H ₈ ), or butane (C ₄ H ₁₀ ). And a mixed gas of inert gas may be used.

In addition, as a dry etching method, a parallel plate type RIE (Reactive Ion Etching) method, an ICP (Inductively Coupled Plasma) method, a DF-CCP (Dual Frequency Capacitively Coupled Plasma-Pumped Capacitance Two-Pulsed Coupling Plasma Capacitance Plasma-Pumped Capacitance Plasma Two-Piece Capacitance Coupled Plasma Excited Plasma Frequency Capacitor ) Method or the like. Etching conditions (for example, the amount of power applied to the coil-type electrode, the amount of power applied to the substrate-side electrode, the electrode temperature on the substrate side, etc.) may be adjusted as appropriate so that the desired processed shape can be etched. .

Next, the oxide layer 124c is formed over the oxide layer 104a, the oxide layer 104b, and the insulating layer 103, and the insulating layer 125 is formed over the oxide layer 124c (see FIG. 8D). The oxide layer 124c can be formed using a material and a method similar to those of the oxide layer 124a. The insulating layer 125 can be formed using a material and a method similar to those of the insulating layer 103. The thickness of the insulating layer 125 is preferably 1 nm to 50 nm, more preferably 3 nm to 30 nm, and still more preferably 5 nm to 10 nm. An oxygen doping treatment may be performed after the formation of the oxide layer 124c. Alternatively, oxygen doping treatment may be performed after the insulating layer 125 is formed. Further, heat treatment may be performed after the insulating layer 125 is formed. In this embodiment, silicon oxide is formed as the insulating layer 125.

Next, a conductive layer 126 is formed over the insulating layer 125 (see FIG. 9A). Examples of the conductive material for forming the conductive layer 126 include aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, and beryllium. A material containing one or more metal elements selected from the above can be used. Alternatively, a semiconductor with high electrical conductivity typified by polycrystalline silicon containing an impurity element such as phosphorus, or silicide such as nickel silicide may be used. As the conductive layer 126, a plurality of conductive layers formed using these materials may be stacked.

The conductive layer 126 includes indium tin oxide (ITO), indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, and indium tin containing titanium oxide. A conductive material containing oxygen such as oxide, indium zinc oxide, or indium tin oxide to which silicon is added, or a conductive material containing nitrogen such as titanium nitride or tantalum nitride can also be used. Alternatively, a stacked structure in which the above-described material containing a metal element and a conductive material containing oxygen are combined can be employed. Alternatively, a stacked structure in which the above-described material containing a metal element and a conductive material containing nitrogen are combined can be used. A stacked structure in which the above-described material containing a metal element, a conductive material containing oxygen, and a conductive material containing nitrogen can be combined.

The formation method of the conductive layer 126 is not particularly limited, and various formation methods such as an evaporation method, a CVD method, and a sputtering method can be used. The thickness of the conductive layer 126 is preferably 10 nm to 500 nm, more preferably 20 nm to 300 nm, and still more preferably 30 nm to 200 nm. In this embodiment, a stack of titanium nitride and tungsten is used as the conductive layer 126. Specifically, tungsten having a thickness of 150 nm is formed over titanium nitride having a thickness of 10 nm.

Next, an insulating layer 127 is formed over the conductive layer 126 (see FIG. 9A). The insulating layer 127 can be formed using a material and a method similar to those of the insulating layer 125. The thickness of the insulating layer 127 is preferably 5 nm to 100 nm, and more preferably 10 nm to 50 nm.

Next, a resist mask is formed over the insulating layer 127 by a photolithography method or the like (not illustrated), and part of each of the conductive layer 126 and the insulating layer 127 is selectively etched, so that the electrode 106 and the insulating layer are formed. 107 is formed (see FIG. 9B). After the formation of the electrode 106 and the insulating layer 107, the resist mask is removed. The conductive layer 126 and the insulating layer 127 may be etched by a dry etching method or a wet etching method, or both of them may be used.

Next, the metal element 131 is introduced using the electrode 106 and the insulating layer 107 as a mask (see FIG. 9C). Note that in FIG. 9C, the metal element 131 is indicated by an arrow. The metal element 131 can be introduced using an ion implantation method, a plasma doping method, or the like. In FIG. 9C, an end portion of the region 135 into which the metal element 131 is introduced is indicated by a broken line. The depth of the region 135 into which the metal element is introduced and the concentration of the metal element contained in the region 135 can be determined by processing conditions such as an ion implantation method and a plasma doping method.

As the metal element 131, one or more of metal elements such as aluminum, sulfur, titanium, magnesium, tungsten, arsenic, antimony, and vanadium can be used. A metal element other than the above may be used as the metal element 131. The dose of the metal element 131 is 1 × 10 ¹² ions / cm ² or more and 1 × 10 ¹⁶ ions / cm ² or less, preferably 1 × 10 ¹³ ions / cm ² or more and 1 × 10 ¹⁵ ions / cm ² or less. Good. The acceleration voltage when the metal element 131 is introduced may be 5 kV or more and 50 kV or less, preferably 10 kV or more and 30 kV or less. In this embodiment mode, tungsten is used as the metal element 131. When the metal element 131 is introduced using the electrode 106 and the insulating layer 107 as a mask, the region 135 can be provided adjacent to the channel formation region by self-alignment.

When the metal element 131 is introduced into the oxide layer 104, oxygen contained in the oxide layer 104 and the introduced metal element 131 are combined to form a metal oxide. Therefore, oxygen vacancies (also referred to as “Vo”) increase in the region where the metal element 131 of the oxide layer 104 is introduced (region 135). When hydrogen (H) is bonded to Vo to form VoH, the carrier density in the region increases and the resistivity decreases. Further, heat treatment may be performed after the metal element 131 is introduced. The heat treatment is preferably performed at 200 ° C to 500 ° C, more preferably 300 ° C to 450 ° C, and still more preferably 350 ° C to 400 ° C. VoH is easily formed by the heat treatment.

The region 135 in the oxide layer 104 can function as an n-type semiconductor. A region 135 in the oxide layer 104 has a higher carrier density and a lower resistivity than a region overlapping with the electrode 106 of the oxide layer 104 (channel formation region). Thus, the region 135 in the oxide layer 104 may have a lower resistance than a region (channel formation region) that overlaps with the electrode 106 of the oxide layer 104.

In this embodiment mode, tungsten is used as the metal element 131. Further, it is introduced into part of the oxide layer 104 by an ion implantation method. By introducing tungsten, a region containing tungsten oxide is formed in the oxide layer 104.

Next, the insulating layer 128 is formed over the insulating layer 125, the electrode 106, and the insulating layer 107 (see FIG. 10A). The insulating layer 128 can be formed using a material and a method similar to those of the insulating layer 125. The thickness of the insulating layer 128 is preferably larger than the total thickness of the electrode 106 and the insulating layer 107.

In this embodiment, aluminum oxide is formed as the insulating layer 128 by a sputtering method. In addition, a gas containing oxygen is used as a sputtering gas. When the insulating layer 128 is formed by a sputtering method, a mixed layer in which both are mixed is formed at and near the interface between the insulating layer 128 and the surface on which the insulating layer 128 is formed. Specifically, the mixed layer 145 is formed at and near the interface between the insulating layer 125 and the insulating layer 128. In addition, a mixed layer 147 is formed at and near the interface between the insulating layer 107 and the insulating layer 128.

Further, the mixed layer 145 and the mixed layer 147 contain part of the sputtering gas. In this embodiment, a gas containing oxygen is used as a sputtering gas; therefore, the mixed layer 145 and the mixed layer 147 contain oxygen. Therefore, the mixed layer 145 and the mixed layer 147 have excess oxygen.

Next, heat treatment is performed. The heat treatment is preferably performed at 200 ° C to 500 ° C, more preferably 300 ° C to 450 ° C, and still more preferably 350 ° C to 400 ° C. Note that the temperature of the heat treatment performed at this time is equal to or lower than the temperature of the heat treatment performed after the metal element 131 is introduced.

By the heat treatment, oxygen contained in the mixed layer 145 and the mixed layer 147 is diffused. Here, since the mixed layer 147 is covered with the insulating layer 128, excess oxygen contained in the mixed layer 147 diffuses into the insulating layer 107 and the electrode 106.

In addition, excess oxygen contained in the mixed layer 145 diffuses into the oxide layer 104a, the oxide layer 104b, and the oxide layer 104c through the insulating layer 125, the insulating layer 103, and the like. By using a material that does not easily transmit oxygen as the insulating layer 128 and the insulating layer 102, excess oxygen contained in the mixed layer 145 is effectively diffused into the oxide layer 104b through the insulating layer 125, the insulating layer 103, and the like. Can be made. A state in which excess oxygen contained in the mixed layer 145 diffuses is indicated by an arrow in FIG.

Next, the insulating layer 128 is etched by anisotropic dry etching to form a structure 108 adjacent to the side surface of the electrode 106 (see FIG. 11A). At this time, a region of the insulating layer 125 that does not overlap with either the structure body 108 or the electrode 106 is etched, so that the insulating layer 105 is formed. In addition, a region of the oxide layer 124c that does not overlap with either the structure body 108 or the electrode 106 is etched, so that the oxide layer 104c is formed. Thus, part of the oxide layer 104b is exposed when the structure body 108 is formed.

At this time, part of the exposed oxide layer 104b may be etched to form the oxide layer 104b having a convex portion. Here, FIGS. 14A and 14B illustrate the transistor 100 in which a protrusion is formed on the oxide layer 104b. FIG. 14A is a plan view of the transistor 100. FIG. 14B is a cross-sectional view taken along dashed-dotted line L1-L2 and dashed-dotted line W1-W2 shown in FIG.

Next, a conductive layer 129 is formed (see FIG. 11B). The conductive layer 129 can be formed using a material and a method similar to those of the conductive layer 126 (electrode 106). The thickness of the conductive layer 129 is preferably 5 nm to 500 nm, more preferably 10 nm to 200 nm, and still more preferably 15 nm to 100 nm. In this embodiment mode, tungsten with a thickness of 20 nm is used as the conductive layer 129.

Next, part of the conductive layer 129 is selectively removed using a photolithography method or the like, so that the electrodes 109a and 109b are formed (see FIG. 11C). Note that by providing the insulating layer 107 over the electrode 106, the electrode 106 can be protected from being removed when part of the conductive layer 129 is removed.

At this time, if the electrode 109a and the electrode 109b are formed of a material having a property of extracting oxygen from the oxide layer 104, such as tungsten or titanium, Vo in the oxide layer 104 in contact with the electrode 109a and the electrode 109b increases. . Therefore, in the region 135 formed in the oxide layer 104, the carrier density in a region where the electrode 109a and the electrode 109b are in contact with each other increases, and the resistivity decreases. Note that when hydrogen is bonded to Vo to form VoH, the carrier density in the region is further increased, and the resistivity is further decreased.

Therefore, in the oxide layer 104, the carrier density in the region where the electrode 109a and the electrode 109b are in contact with each other may be higher than the carrier density in the region overlapping with the structure body 108. Further, in the oxide layer 104, the resistivity of a region where the electrode 109a and the electrode 109b are in contact with each other may be lower than the resistivity of the region overlapping with the structure body 108. In addition, in the oxide layer 104, the resistance of a region where the electrode 109a and the electrode 109b are in contact with each other may be lower than the resistance of the region overlapping with the structure body 108.

Next, the insulating layer 110 is formed, and the insulating layer 111 is formed over the insulating layer 110 (see FIG. 12A). The insulating layer 110 and the insulating layer 111 can be formed using a material and a method similar to those of the insulating layer 127 (insulating layer 107). Note that the insulating layer 111 is preferably formed using an insulating material which does not easily transmit impurities.

Next, the insulating layer 112 is formed over the insulating layer 111 (see FIG. 12B). The insulating layer 112 can be formed using a material and a method similar to those of the insulating layer 110. For the insulating layer 112, a heat-resistant organic material such as polyimide, acrylic resin, benzocyclobutene resin, polyamide, or epoxy resin can be used. In addition to the organic material, a low dielectric constant material (low-k material), a siloxane resin, PSG (phosphorus glass), BPSG (phosphorus boron glass), or the like can be used. Note that the insulating layer 112 may be formed by stacking a plurality of insulating layers formed using these materials.

Note that the siloxane-based resin corresponds to a resin including a Si—O—Si bond formed using a siloxane-based material as a starting material. Siloxane resins may use organic groups (for example, alkyl groups and aryl groups) and fluoro groups as substituents. The organic group may have a fluoro group.

The formation method of the insulating layer 112 is not particularly limited, and depending on the material, sputtering, SOG, spin coating, dip, spray coating, droplet discharge (such as an inkjet method), printing (screen printing, offset) Etc.) may be used. By combining the baking process of the insulating layer 112 with another heat treatment process, a transistor can be efficiently manufactured.

A chemical mechanical polishing (CMP) process (also referred to as “CMP process”) may be performed on the surface of the insulating layer 112 (see FIG. 11A). By performing the CMP treatment, unevenness on the surface of the sample can be reduced, and the coverage of the insulating layer and the conductive layer to be formed thereafter can be improved.

Next, part of the insulating layer 112, the insulating layer 111, the insulating layer 110, and the insulating layer 107 is selectively removed by photolithography or the like so that the openings 126a and 109b overlap with part of the electrode 109a. An opening 126b that overlaps part and an opening 126c that overlaps part of the electrode 106 are formed (see FIG. 13A). Part of the insulating layer 112, the insulating layer 111, the insulating layer 110, and the insulating layer 107 may be removed (etched) by a dry etching method or a wet etching method, or both of them may be used. When an anisotropic dry etching method is used, an opening having a large aspect ratio can be formed.

Note that when the opening 126a, the opening 126b, and the opening 126c are formed, the electrode 109a, the electrode 109b, and the electrode 106 are partly removed, and a recess may be formed in the electrode 109a, the electrode 109b, and the electrode 106 ( (See FIG. 14B).

Next, the contact plug 113a, the contact plug 113b, and the contact plug 113c are formed in the opening 126a, the opening 126b, and the opening 126c. As the contact plug 113a, the contact plug 113b, and the contact plug 113c, for example, a highly embedded conductive material such as tungsten or polysilicon can be used. Although not shown, the side and bottom surfaces of the material may be covered with a barrier layer (diffusion prevention layer) made of a titanium layer, a titanium nitride layer, or a laminate thereof. In this case, the barrier layer may be referred to as an electrode.

Next, a conductive layer is formed over the insulating layer 112, and part of the conductive layer is selectively removed using a photolithography method or the like, so that the electrode 114a that overlaps the contact plug 113a, the electrode 114b that overlaps the contact plug 113b, And the electrode 114c which overlaps with the contact plug 113c is formed. The conductive layer can be formed using a material and a method similar to those of the conductive layer 129.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 3)
An oxide semiconductor is classified into a single crystal oxide semiconductor and a non-single-crystal oxide semiconductor. As the non-single-crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, an nc-OS (nanocrystalline oxide semiconductor), a quasi-amorphous oxide semiconductor (a-like OS), an amorphous Examples include oxide semiconductors.

From another viewpoint, oxide semiconductors are classified into amorphous oxide semiconductors and other crystalline oxide semiconductors. Examples of a crystalline oxide semiconductor include a single crystal oxide semiconductor, a CAAC-OS, a polycrystalline oxide semiconductor, and an nc-OS.

As the definition of the amorphous structure, it is generally known that it is not fixed in a metastable state, isotropic and does not have a heterogeneous structure, and the like. Moreover, it can be paraphrased as a structure having a flexible bond angle and short-range order, but not long-range order.

In other words, an intrinsically stable oxide semiconductor cannot be referred to as a complete amorphous oxide semiconductor. In addition, an oxide semiconductor that is not isotropic (eg, has a periodic structure in a minute region) cannot be referred to as a completely amorphous oxide semiconductor. However, although the a-like OS has a periodic structure in a minute region, it has a void (also referred to as a “void”) and is an unstable structure. Therefore, it can be said that it is close to an amorphous oxide semiconductor in terms of physical properties.

<CAAC-OS>
The CAAC-OS is one of oxide semiconductors having a plurality of c-axis aligned crystal parts (also referred to as “pellets”).

When a composite analysis image (also referred to as a “high-resolution TEM image”) of a bright-field image and a diffraction pattern of CAAC-OS is observed with a transmission electron microscope (TEM), a plurality of pellets are confirmed. Can do. On the other hand, in the high-resolution TEM image, the boundary between pellets, that is, the crystal grain boundary (also referred to as “grain boundary”) cannot be clearly confirmed. Therefore, it can be said that the CAAC-OS does not easily lower the electron mobility due to the crystal grain boundary.

Hereinafter, a CAAC-OS observed with a TEM will be described. FIG. 15A shows a high-resolution TEM image of a cross section of the CAAC-OS observed from a direction substantially parallel to the sample surface. For observation of the high-resolution TEM image, a spherical aberration correction function was used. A high-resolution TEM image using the spherical aberration correction function is particularly referred to as a Cs-corrected high-resolution TEM image. Acquisition of a Cs-corrected high-resolution TEM image can be performed by, for example, an atomic resolution analytical electron microscope JEM-ARM200F manufactured by JEOL Ltd.

FIG. 15B shows a Cs-corrected high-resolution TEM image obtained by enlarging the region (1) in FIG. FIG. 15B shows that metal atoms are arranged in layers in the pellet. The arrangement of each layer of metal atoms reflects a surface on which a CAAC-OS film is formed (also referred to as a “formation surface”) or an uneven surface, and is parallel to the formation surface or the top surface of the CAAC-OS. .

As shown in FIG. 15B, the CAAC-OS has a characteristic atomic arrangement. FIG. 15C shows a characteristic atomic arrangement with auxiliary lines. From FIG. 15 (B) and FIG. 15 (C), the size of one pellet is 1 nm or more or 3 nm or more, and the size of the gap caused by the inclination between the pellet and the pellet is about 0.8 nm. I know that there is. Therefore, the pellet can also be referred to as a nanocrystal (nc). In addition, the CAAC-OS can be referred to as an oxide semiconductor including CANC (C-Axis aligned nanocrystals).

Here, based on the Cs-corrected high-resolution TEM image, the arrangement of the CAAC-OS pellets 5100 on the substrate 5120 is schematically shown as a structure in which bricks or blocks are stacked (FIG. 15D). reference.). A portion where an inclination is generated between the pellets observed in FIG. 15C corresponds to a region 5161 illustrated in FIG.

FIG. 16A shows a Cs-corrected high-resolution TEM image of the plane of the CAAC-OS observed from a direction substantially perpendicular to the sample surface. The Cs-corrected high-resolution TEM images obtained by enlarging the region (1), the region (2), and the region (3) in FIG. 16 (A) are shown in FIGS. 16 (B), 16 (C), and 16 (D), respectively. Show. From FIG. 16B, FIG. 16C, and FIG. 16D, it can be confirmed that the metal atoms are arranged in a triangular shape, a quadrangular shape, or a hexagonal shape in the pellet. However, there is no regularity in the arrangement of metal atoms between different pellets.

Next, the CAAC-OS analyzed by X-ray diffraction (XRD: X-Ray Diffraction) will be described. For example, when structural analysis by an out-of-plane method is performed on a CAAC-OS including an InGaZnO ₄ crystal, a peak appears at a diffraction angle (2θ) of around 31 ° as illustrated in FIG. There is. Since this peak is attributed to the (009) plane of the InGaZnO ₄ crystal, the CAAC-OS crystal has c-axis orientation, and the c-axis is oriented in a direction substantially perpendicular to the formation surface or the top surface. It can be confirmed.

Note that in structural analysis of the CAAC-OS by an out-of-plane method, in addition to a peak where 2θ is around 31 °, a peak may also appear when 2θ is around 36 °. A peak at 2θ of around 36 ° indicates that a crystal having no c-axis alignment is included in part of the CAAC-OS. In a more preferable CAAC-OS, in the structural analysis by the out-of-plane method, 2θ has a peak in the vicinity of 31 °, and 2θ has no peak in the vicinity of 36 °.

On the other hand, when structural analysis is performed on the CAAC-OS by an in-plane method in which X-rays are incident from a direction substantially perpendicular to the c-axis, a peak appears at 2θ of around 56 °. This peak is attributed to the (110) plane of the InGaZnO ₄ crystal. In the case of CAAC-OS, even when 2θ is fixed at around 56 ° and analysis (φ scan) is performed while rotating the sample with the normal vector of the sample surface as the axis (φ axis), FIG. A clear peak does not appear as shown. In contrast, in the case of a single crystal oxide semiconductor of InGaZnO ₄ , when φ scan is performed with 2θ fixed at around 56 °, it belongs to a crystal plane equivalent to the (110) plane as shown in FIG. 6 peaks are observed. Therefore, structural analysis using XRD can confirm that the CAAC-OS has irregular orientations in the a-axis and the b-axis.

Next, a CAAC-OS analyzed by electron diffraction will be described. For example, when an electron beam with a probe diameter of 300 nm is incident on a CAAC-OS including an InGaZnO ₄ crystal in parallel with a sample surface, a diffraction pattern as illustrated in FIG. May also appear.) This diffraction pattern includes spots caused by the (009) plane of the InGaZnO ₄ crystal. Therefore, electron diffraction shows that the pellets included in the CAAC-OS have c-axis alignment, and the c-axis is in a direction substantially perpendicular to the formation surface or the top surface. On the other hand, FIG. 18B shows a diffraction pattern obtained when an electron beam with a probe diameter of 300 nm is incident on the same sample in a direction perpendicular to the sample surface. From FIG. 18B, a ring-shaped diffraction pattern is confirmed. Therefore, electron diffraction shows that the a-axis and the b-axis of the pellet included in the CAAC-OS have no orientation. Note that the first ring in FIG. 18B is considered to originate from the (010) plane and the (100) plane of the InGaZnO ₄ crystal. Further, the second ring in FIG. 18B is considered to be caused by the (110) plane and the like.

As described above, the CAAC-OS is an oxide semiconductor with high crystallinity. Since the crystallinity of an oxide semiconductor may be deteriorated by entry of impurities, generation of defects, or the like, in reverse, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies).

Note that the impurity means an element other than the main components of the oxide semiconductor, such as hydrogen, carbon, silicon, or a transition metal element. For example, an element such as silicon, which has a stronger bonding force with oxygen than a metal element included in an oxide semiconductor, disturbs the atomic arrangement of the oxide semiconductor by depriving the oxide semiconductor of oxygen, thereby reducing crystallinity. It becomes a factor. In addition, heavy metals such as iron and nickel, argon, carbon dioxide, and the like have large atomic radii (or molecular radii), which disturbs the atomic arrangement of the oxide semiconductor and decreases crystallinity.

In the case where an oxide semiconductor has impurities or defects, characteristics may fluctuate due to light, heat, or the like. For example, an impurity contained in the oxide semiconductor might serve as a carrier trap or a carrier generation source. In addition, oxygen vacancies in the oxide semiconductor may serve as carrier traps or may serve as carrier generation sources by capturing hydrogen.

A CAAC-OS with few impurities and oxygen vacancies is an oxide semiconductor with low carrier density. Specifically, it is less than 8 × 10 ¹¹ pieces / cm ³ , preferably less than 1 × 10 ¹¹ pieces / cm ³ , more preferably less than 1 × 10 ¹⁰ pieces / cm ³ , and 1 × 10 ⁻⁹ pieces / cm 3. An oxide semiconductor having a carrier density of ³ or more can be obtained. Such an oxide semiconductor is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. The CAAC-OS has a low impurity concentration and a low density of defect states. That is, it can be said that the oxide semiconductor has stable characteristics.

<Nc-OS>
The nc-OS has a region where a crystal part can be confirmed and a region where a clear crystal part cannot be confirmed in a high-resolution TEM image. In many cases, a crystal part included in the nc-OS has a size of 1 nm to 10 nm, or 1 nm to 3 nm. Note that an oxide semiconductor in which the size of a crystal part is greater than 10 nm and less than or equal to 100 nm is sometimes referred to as a microcrystalline oxide semiconductor. For example, the nc-OS may not be able to clearly confirm a crystal grain boundary in a high-resolution TEM image. Note that the nanocrystal may have the same origin as the pellet in the CAAC-OS. Therefore, the crystal part of nc-OS is sometimes referred to as a pellet below.

The nc-OS has periodicity in atomic arrangement in a minute region (for example, a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In addition, the nc-OS has no regularity in crystal orientation between different pellets. Therefore, orientation is not seen in the whole film. Therefore, the nc-OS may not be distinguished from an a-like OS or an amorphous oxide semiconductor depending on an analysis method. For example, when an X-ray having a diameter larger than that of the pellet is used for nc-OS, a peak indicating a crystal plane is not detected in the analysis by the out-of-plane method. Further, when electron diffraction using an electron beam having a probe diameter (for example, 50 nm or more) larger than that of the pellet is performed on the nc-OS, a diffraction pattern such as a halo pattern is observed. On the other hand, when nanobeam electron diffraction is performed on the nc-OS using an electron beam having a probe diameter that is close to the pellet size or smaller than the pellet size, spots are observed. Further, when nanobeam electron diffraction is performed on the nc-OS, a region with high luminance may be observed like a circle (in a ring shape). Furthermore, a plurality of spots may be observed in the ring-shaped region.

Thus, since the crystal orientation does not have regularity between pellets (nanocrystals), nc-OS has an oxide semiconductor having RANC (Random Aligned Nanocrystals) or NANC (Non-Aligned nanocrystals). It can also be called an oxide semiconductor.

The nc-OS is an oxide semiconductor that has higher regularity than an amorphous oxide semiconductor. Therefore, the nc-OS has a lower density of defect states than an a-like OS or an amorphous oxide semiconductor. Note that the nc-OS does not have regularity in crystal orientation between different pellets. Therefore, the nc-OS has a higher density of defect states than the CAAC-OS.

<A-like OS>
The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. In the a-like OS, a void may be observed in a high-resolution TEM image. Moreover, in a high-resolution TEM image, it has the area | region which can confirm a crystal part clearly, and the area | region which cannot confirm a crystal part.

Since it has a void, the a-like OS has an unstable structure. Hereinafter, in order to show that the a-like OS has an unstable structure as compared with the CAAC-OS and the nc-OS, changes in the structure due to electron irradiation are shown.

As samples for electron irradiation, a-like OS (referred to as sample A), nc-OS (referred to as sample B), and CAAC-OS (referred to as sample C) are prepared. Each sample is an In—Ga—Zn oxide.

First, a high-resolution cross-sectional TEM image of each sample is acquired. It can be seen from the high-resolution cross-sectional TEM image that each sample has a crystal part.

The determination of which part is regarded as one crystal part may be performed as follows. For example, the unit cell of an InGaZnO ₄ crystal has a structure in which three In—O layers and six Ga—Zn—O layers have a total of nine layers stacked in the c-axis direction. Are known. The spacing between these adjacent layers is approximately the same as the lattice spacing of the (009) plane (also referred to as “d value”), and the value is determined to be 0.29 nm from crystal structure analysis. Therefore, a portion where the interval between lattice fringes is 0.28 nm or more and 0.30 nm or less can be regarded as a crystal part of InGaZnO ₄ . Note that the lattice fringes correspond to the ab plane of the InGaZnO ₄ crystal.

FIG. 19 is an example in which the average size of the crystal parts (22 to 45 locations) of each sample was examined. However, the length of the lattice fringes described above is the size of the crystal part. From FIG. 19, it can be seen that in the a-like OS, the crystal part becomes larger according to the cumulative dose of electrons. Specifically, as indicated by (1) in FIG. 19, a crystal part (also referred to as “initial nucleus”) having a size of about 1.2 nm in the initial stage of observation by TEM is an accumulated electron irradiation dose. Is 4.2 × 10 ⁸ e ⁻ / nm ² , and grows to a size of about 2.6 nm. On the other hand, in the case of the nc-OS and the CAAC-OS, there is no change in the size of the crystal part when the cumulative electron dose is in the range of 4.2 × 10 ⁸ e ⁻ / nm ² from the start of electron irradiation. I understand. Specifically, as indicated by (2) and (3) in FIG. 19, the crystal part sizes of the nc-OS and the CAAC-OS are about 1.4 nm, respectively, regardless of the cumulative electron dose. And about 2.1 nm.

As described above, in the a-like OS, a crystal part may be grown by electron irradiation. On the other hand, in the nc-OS and the CAAC-OS, the crystal part is hardly grown by electron irradiation. That is, it can be seen that the a-like OS has an unstable structure compared to the nc-OS and the CAAC-OS.

In addition, since it has a void, the a-like OS has a lower density than the nc-OS and the CAAC-OS. Specifically, the density of the a-like OS is 78.6% or more and less than 92.3% of the density of the single crystal having the same composition. Further, the density of the nc-OS and the density of the CAAC-OS are 92.3% or more and less than 100% of the density of the single crystal having the same composition. An oxide semiconductor that is less than 78% of the density of a single crystal is difficult to form.

For example, in an oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of single crystal InGaZnO ₄ having a rhombohedral structure is 6.357 g / cm ³ . Thus, for example, in an oxide semiconductor that satisfies In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of a-like OS is 5.0 g / cm ³ or more and less than 5.9 g / cm ^3. . For example, in the oxide semiconductor satisfying In: Ga: Zn = 1: 1: 1 [atomic ratio], the density of the nc-OS and the density of the CAAC-OS is 5.9 g / cm ³ or more and 6.3 g / less than cm ³ .

Note that there may be no single crystal having the same composition. In that case, the density corresponding to the single crystal in a desired composition can be estimated by combining single crystals having different compositions at an arbitrary ratio. What is necessary is just to estimate the density corresponding to the single crystal of a desired composition using a weighted average with respect to the ratio which combines the single crystal from which a composition differs. However, the density is preferably estimated by combining as few kinds of single crystals as possible.

As described above, oxide semiconductors have various structures and various properties. Note that the oxide semiconductor may be a stacked film including two or more of an amorphous oxide semiconductor, an a-like OS, an nc-OS, and a CAAC-OS, for example.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 4)
In this embodiment, an example of a semiconductor device using the transistor disclosed in this specification and the like will be described.

≪Example of semiconductor device structure≫
20A to 20C are cross-sectional views of the semiconductor device 400. FIG. The semiconductor device 400 includes a transistor 100 and a transistor 281. Note that the transistor 100 can be replaced with any of the other transistors described in the above embodiments. 20A is a cross-sectional view in the channel length direction of the transistor 100 and the transistor 281, and FIG. 20B is a cross-sectional view in the channel width direction. FIG. 20C is an enlarged view of the transistor 281 in FIG.

The semiconductor device 400 uses an n-type semiconductor as the substrate 401. The transistor 281 includes a channel formation region 283, a high-concentration p-type impurity region 285, an insulating layer 286, an electrode 287, and a structure 288. In addition, a low-concentration p-type impurity region 284 is provided in a region overlapping with the structure body 288 with the insulating layer 286 interposed therebetween. The insulating layer 286 can function as a gate insulating layer. The electrode 287 can function as a gate electrode. In the transistor 281, a channel formation region 283 is formed in part of the substrate 401.

The low-concentration p-type impurity region 284 can be formed by introducing an impurity element using the electrode 287 as a mask after the electrode 287 is formed and before the structure 288 is formed. That is, the low concentration p-type impurity region 284 can be formed by self-alignment. After the structure 288 is formed, a high concentration p-type impurity region 285 is formed. Note that the low-concentration p-type impurity region 284 has the same conductivity type as the high-concentration p-type impurity region 285, and the concentration of the impurity imparting conductivity is lower than that of the high-concentration p-type impurity region 285. Further, the low-concentration p-type impurity region 284 may not be provided depending on the situation.

The transistor 281 is electrically isolated from other transistors by the element isolation layer 414. The element isolation region can be formed by a LOCOS method (Local Oxidation of Silicon), an STI method (Shallow Trench Isolation), or the like.

The transistor 281 can function as a p-channel transistor. An insulating layer 403 is formed over the transistor 282, and an insulating layer 404 is formed over the insulating layer 403. The insulating layer 403 and the insulating layer 404 can be formed using a material and a method similar to those of the insulating layer 111. Note that the insulating layer 403 and the insulating layer 404 are preferably formed using an insulating material having a function of preventing diffusion of impurities such as oxygen, hydrogen, water, alkali metal, and alkaline earth metal. Note that one of the insulating layer 403 and the insulating layer 404 may be omitted, or an insulating layer may be further stacked.

In addition, the semiconductor device 400 includes an insulating layer 405 having a flat surface over the insulating layer 404. The insulating layer 405 can be formed using a material and a method similar to those of the insulating layer 112. Further, CMP treatment may be performed on the surface of the insulating layer 405.

Over the insulating layer 405, an electrode 413a, an electrode 413b, and an electrode 413c are formed. The electrode 413a, the electrode 413b, and the electrode 413c can be manufactured using a material and a method similar to those of the electrode 109a.

The electrode 413a is electrically connected to one of the high-concentration p-type impurity regions 285 through a contact plug 406a. The electrode 413b is electrically connected to the other of the high concentration p-type impurity region 285 through a contact plug 406b. The electrode 413c is electrically connected to the electrode 287 through a contact plug 406c.

An insulating layer 407 is formed so as to cover the electrode 413a, the electrode 413b, and the electrode 413c. The insulating layer 407 can be formed using a material and a method similar to those of the insulating layer 405. Further, CMP treatment may be performed on the surface of the insulating layer 407.

In addition, the insulating layer 102 is formed over the insulating layer 407. The structure above the insulating layer 407 can be understood with reference to the above embodiment. Therefore, detailed description in this embodiment is omitted. The electrode 109b is electrically connected to the electrode 413b through the contact plug 112d.

<Modification 1>
An n-channel transistor may be provided over the substrate 401. FIG. 21A and FIG. 21B are cross-sectional views of the semiconductor device 410. The semiconductor device 410 has a structure in which an n-channel transistor 282 is added to the semiconductor device 400. 21A is a cross-sectional view of the transistor 100, the transistor 281, and the transistor 282 in the channel length direction, and FIG. 21B is an enlarged view of the transistor 282.

In the transistor 282, a channel formation region 1283 is formed in the well 220. The transistor 282 includes a channel formation region 1283, a high-concentration n-type impurity region 1285, an insulating layer 286, an electrode 287, and a structure 288. A low-concentration n-type impurity region 1284 is provided in a region overlapping with the structure body 288 with the insulating layer 286 interposed therebetween.

The low-concentration n-type impurity region 1284 can be formed by introducing an impurity element using the electrode 287 as a mask after the electrode 287 is formed and before the structure 288 is formed. That is, the low concentration n-type impurity region 1284 can be formed by self-alignment. After the structure 288 is formed, a high concentration n-type impurity region 1285 is formed. Note that the low-concentration n-type impurity region 1284 has the same conductivity type as the high-concentration n-type impurity region 1285, and the concentration of the impurity imparting conductivity is lower than that of the high-concentration n-type impurity region 1285. Further, the low-concentration n-type impurity region 1284 may not be provided depending on the situation.

<Modification 2>
A transistor 100 may be further provided above the transistor 100. FIG. 22 is a cross-sectional view of the semiconductor device 420. The semiconductor device 420 includes a transistor 100 a having a structure similar to that of the transistor 100 over the semiconductor device 410. The transistor 100a is provided over the insulating layer 112 with the insulating layer 407a and the insulating layer 102a interposed therebetween. The insulating layer 407a and the insulating layer 102a can be provided using a material and a method similar to those of the insulating layer 407 and the insulating layer 102, respectively. Further, the transistor 100a can be manufactured similarly to the transistor 100.

In addition, the semiconductor device 420 includes a capacitor 141 and a capacitor 142. One electrode 413c included in the capacitor 141 can be provided in the same layer as the electrode 413a and the electrode 413b by using part of a conductive layer for forming the electrode 413a and the electrode 413b. The other electrode 109c included in the capacitor 141 can be provided in the same layer as the electrode 109a and the electrode 109b by using part of the conductive layer for forming the electrode 109a and the electrode 109b. The insulating layer sandwiched between the electrode 109c and the electrode 413c can function as a dielectric layer of the capacitor 141.

<Modification 3>
23A to 23C are cross-sectional views of the semiconductor device 430. FIG. The semiconductor device 430 has a structure in which the transistor 281 included in the semiconductor device 400 is replaced with a Fin-type transistor 291. By using a Fin type transistor, the effective channel width can be increased and the on-state characteristics of the transistor can be improved. In addition, since the contribution of the electric field of the gate electrode to the channel formation region can be increased, the off characteristics of the transistor can be improved.

[Semiconductor circuit]
The transistors disclosed in this specification and the like include logic circuits such as an OR circuit, an AND circuit, a NAND circuit, and a NOR circuit, an inverter circuit, a buffer circuit, a shift register circuit, a flip-flop circuit, an encoder circuit, a decoder circuit, and an amplifier circuit It can be used for various semiconductor circuits such as analog switch circuits, integration circuits, differentiation circuits, and memory elements.

In this embodiment, an example of a CMOS circuit or the like that can be used for a peripheral circuit and a pixel circuit is described with reference to FIGS. Note that in a circuit diagram and the like referred to in this specification and the like, “OS” is attached to a circuit symbol of a transistor to which an OS transistor is preferably applied.

The CMOS circuit illustrated in FIG. 24A illustrates an example of a structure of an inverter circuit in which a p-channel transistor 281 and an n-channel transistor 282 are connected in series and gates thereof are connected.

The CMOS circuit illustrated in FIG. 24B illustrates a configuration example of an analog switch circuit in which a p-channel transistor 281 and an n-channel transistor 282 are connected in parallel.

The CMOS circuit illustrated in FIG. 24C illustrates a configuration example of a NAND circuit including the transistor 281a, the transistor 281b, the transistor 282a, and the transistor 282b. In the NAND circuit, the output potential changes depending on the combination of the potentials input to the input terminal IN_A and the input terminal IN_B.

〔Storage device〕
The circuit illustrated in FIG. 25A illustrates a configuration example of a memory device in which one of the source and the drain of the transistor 289 is connected to the gate of the transistor 1281 and one electrode of the capacitor 257. The circuit illustrated in FIG. 25B illustrates a configuration example of a memory device in which one of a source and a drain of the transistor 289 is connected to one electrode of the capacitor 257.

In the circuits illustrated in FIGS. 25A and 25B, the charge input from the other of the source and the drain of the transistor 289 can be held in the node 256. By using an OS transistor as the transistor 289, the charge of the node 256 can be held for a long time.

Although a p-channel transistor is illustrated as the transistor 1281 in FIG. 25A, an n-channel transistor may be used. For example, the transistor 281 or the transistor 282 may be used as the transistor 1281. Further, an OS transistor may be used as the transistor 1281.

Here, the semiconductor device (memory device) illustrated in FIGS. 25A and 25B will be described in detail.

A semiconductor device illustrated in FIG. 25A includes a transistor 1281 using a first semiconductor, a transistor 289 using a second semiconductor, and a capacitor 257.

The transistor 289 is the OS transistor disclosed in the above embodiment. Since the off-state current of the transistor 289 is small, stored data can be held in a specific node of the semiconductor device for a long time. That is, a refresh operation is not required or the frequency of the refresh operation can be extremely low, so that the semiconductor device with low power consumption is obtained.

In FIG. 25A, a wiring 251 is electrically connected to one of a source and a drain of the transistor 1281, and a wiring 252 is electrically connected to the other of the source and the drain of the transistor 1281. The wiring 253 is electrically connected to one of a source and a drain of the transistor 289, and the wiring 254 is electrically connected to the gate of the transistor 289. The gate of the transistor 1281, the other of the source and the drain of the transistor 289, and one of the electrodes of the capacitor 257 are electrically connected to the node 256. The wiring 255 is electrically connected to the other electrode of the capacitor 257.

The semiconductor device illustrated in FIG. 25A can hold charge applied to the node 256, so that data can be written, held, and read as described below.

[Write and hold operations]
Information writing and holding will be described. First, the potential of the wiring 254 is set to a potential at which the transistor 289 is turned on. Accordingly, the potential of the wiring 253 is supplied to the node 256. That is, a predetermined charge is given to the node 256 (writing). Here, it is assumed that one of two charges (hereinafter, referred to as “Low level charge” and “High level charge”) that gives two different potential levels is given. After that, the potential of the wiring 254 is set to a potential at which the transistor 289 is turned off, so that charge is held at the node 256.

Note that the high-level charge is a charge that applies a higher potential to the node 256 than the low-level charge. In the case where a p-channel transistor is used as the transistor 1281, the high-level charge and the low-level charge are both charges that give a potential higher than the threshold voltage of the transistor. In the case where an n-channel transistor is used as the transistor 1281, the high-level charge and the low-level charge are both lower than the threshold voltage of the transistor. That is, both the high-level charge and the low-level charge are charges that give a potential at which the transistor is turned off.

Since the off-state current of the transistor 289 is extremely small, the charge of the node 256 is held for a long time.

[Read operation]
Next, reading of information will be described. A predetermined potential different from the potential of the wiring 252 to the wiring 251 in a state that gave (constant potential), given a read potential V _R to the wiring 255, it is possible to read the information stored in the node 256.

High level potential _V H given by the charge and the potential supplied by the Low level charge and _{V L,} the read potential _{V R may} be the {(Vth-V H) + (Vth + V L)} / 2. Note that the potential of the wiring 255 when information is not read is higher than V _H when a p-channel transistor is used as the transistor 1281 and lower than _VL when an n-channel transistor is used as the transistor 1281. What is necessary is just a potential.

For example, when using a p-channel transistor in the transistor 1281, Vth of the transistor 1281 is -2 V, the _{V H} 1V, when the _{V L} and -1 V, the _{V R} may be set to -2 V. When potential written to the node 256 is _{V H,} the _{V R} is applied to the wiring 255, the gate to _V R + _{V H} of the transistor 1281, i.e. -1V is applied. Since −1V is higher than Vth, the transistor 1281 is not turned on. Therefore, the potential of the wiring 252 does not change. Also, potential written to the node 256 when the _{V L,} when _{V R} is applied to the wiring 255, the gate of the transistor 1281 _V R + _{V L,} i.e. -3V is applied. Since −3 V is lower than Vth, the transistor 1281 is turned on. Accordingly, the potential of the wiring 252 changes.

In the case of using an n-channel transistor in the transistor 1281, Vth of the transistor 1281 is 2V, the _{V H} 1V, when the _{V L} and -1 V, the _{V R} may be set to 2V. When potential written to the node 256 is _{V H,} the _{V R} is applied to the wiring 255, _V R + _{V H} to the gate of the transistor 1281, i.e. 3V is applied. Since 3V is higher than Vth, the transistor 1281 is turned on. Accordingly, the potential of the wiring 252 changes. Also, potential written to the node 256 when the _{V L,} when _{V R} is applied to the wiring 255, the gate of the transistor 1281 _V R + _{V L,} i.e. 1V is applied. Since 1V is lower than Vth, the transistor 1281 is not turned on. Therefore, the potential of the wiring 252 does not change.

By determining the potential of the wiring 252, information held in the node 256 can be read.

The semiconductor device illustrated in FIG. 25B is different from the semiconductor device illustrated in FIG. 25A in that the transistor 1281 is not provided. In this case as well, information can be written and held by an operation similar to that of the semiconductor device illustrated in FIG.

Information reading in the semiconductor device illustrated in FIG. 25B is described. When a potential at which the transistor 289 is turned on is applied to the wiring 254, the floating wiring 253 and the capacitor 257 are brought into conduction, and charge is redistributed between the wiring 253 and the capacitor 257. As a result, the potential of the wiring 253 changes. The amount of change in potential of the wiring 253 varies depending on the potential of the node 256 (or the charge accumulated in the node 256).

For example, when the potential of the node 256 is V, the capacitance of the capacitor 257 is C, the capacitance component of the wiring 253 is CB, and the potential of the wiring 253 before the charge is redistributed is VB0, the charge is redistributed. The potential of the wiring 253 is (CB × VB0 + C × V) / (CB + C). Therefore, if the potential of the node 256 takes two states of V1 and V0 (V1> V0) as the state of the memory cell, the potential of the wiring 253 when the potential V1 is held (= (CB × VB0 + C × It can be seen that (V1) / (CB + C)) is higher than the potential of the wiring 253 when the potential V0 is held (= (CB × VB0 + C × V0) / (CB + C)).

Then, information can be read by comparing the potential of the wiring 253 with a predetermined potential.

In the semiconductor device described above, by using a transistor with an extremely small off-state current that uses an oxide semiconductor, stored data can be held for a long time. That is, a refresh operation is unnecessary or the frequency of the refresh operation can be extremely low, so that a semiconductor device with low power consumption can be realized. In addition, stored data can be held for a long time even when power is not supplied (note that a potential is preferably fixed).

In addition, since the semiconductor device does not require a high voltage for writing information, the element hardly deteriorates. For example, unlike the conventional nonvolatile memory, since electrons are not injected into the floating gate and electrons are not extracted from the floating gate, there is no problem of deterioration of the insulator. In other words, the semiconductor device according to one embodiment of the present invention is a semiconductor device in which the number of rewritable times which is a problem in the conventional nonvolatile memory is not limited and the reliability is drastically improved. Further, since data is written depending on the conductive state and non-conductive state of the transistor, high-speed operation is possible.

[CPU]
In this embodiment, a CPU will be described as an example of a semiconductor device using the above-described transistor. FIG. 26 is a block diagram illustrating a configuration example of a CPU in which some of the above-described transistors are used.

26 includes an ALU 1191 (ALU: arithmetic logic unit), an ALU controller 1192, an instruction decoder 1193, an interrupt controller 1194, a timing controller 1195, a register 1196, a register controller 1197, and a bus interface 1198. (Bus I / F), a rewritable ROM 1199, and a ROM interface 1189 (ROM I / F). As the substrate 1190, a semiconductor substrate, an SOI substrate, a glass substrate, or the like is used. The ROM 1199 and the ROM interface 1189 may be provided in separate chips. Needless to say, the CPU illustrated in FIG. 26 is just an example in which the configuration is simplified, and an actual CPU may have various configurations depending on the application. For example, the configuration including the CPU or the arithmetic circuit illustrated in FIG. 26 may be a single core, and a plurality of the cores may be included so that each core operates in parallel. Further, the number of bits that the CPU can handle with the internal arithmetic circuit or the data bus can be, for example, 8 bits, 16 bits, 32 bits, 64 bits, or the like.

Instructions input to the CPU via the bus interface 1198 are input to the instruction decoder 1193, decoded, and then input to the ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195.

The ALU controller 1192, interrupt controller 1194, register controller 1197, and timing controller 1195 perform various controls based on the decoded instructions. Specifically, the ALU controller 1192 generates a signal for controlling the operation of the ALU 1191. The interrupt controller 1194 determines and processes an interrupt request from an external input / output device or a peripheral circuit from the priority or mask state during execution of the CPU program. The register controller 1197 generates an address of the register 1196, and reads and writes the register 1196 according to the state of the CPU.

In addition, the timing controller 1195 generates a signal for controlling the operation timing of the ALU 1191, the ALU controller 1192, the instruction decoder 1193, the interrupt controller 1194, and the register controller 1197. For example, the timing controller 1195 includes an internal clock generation unit that generates an internal clock signal based on the reference clock signal, and supplies the internal clock signal to the various circuits.

In the CPU illustrated in FIG. 26, a memory cell is provided in the register 1196. As the memory cell of the register 1196, the above-described transistor, memory device, or the like can be used.

In the CPU illustrated in FIG. 26, the register controller 1197 selects a holding operation in the register 1196 in accordance with an instruction from the ALU 1191. That is, whether to hold data by a flip-flop or to hold data by a capacitor in a memory cell included in the register 1196 is selected. When data retention by the flip-flop is selected, the power supply voltage is supplied to the memory element in the register 1196. When holding of data in the capacitor is selected, data is rewritten to the capacitor and supply of power supply voltage to the memory cells in the register 1196 can be stopped.

FIG. 27 is an example of a circuit diagram of a memory element that can be used as the register 1196. The memory element 730 includes a circuit 701 in which stored data is volatilized by power shutdown, a circuit 702 in which stored data is not volatilized by power shutdown, a switch 703, a switch 704, a logic element 706, a capacitor 707, and a selection function. Circuit 720 having. The circuit 702 includes a capacitor 708, a transistor 709, and a transistor 710. Note that the memory element 730 may further include other elements such as a diode, a resistance element, and an inductor as necessary.

Here, the memory device described above can be used for the circuit 702. When supply of power supply voltage to the memory element 730 is stopped, the gate of the transistor 709 in the circuit 702 is continuously input with a ground potential (0 V) or a potential at which the transistor 709 is turned off. For example, the gate of the transistor 709 is grounded through a load such as a resistor.

The switch 703 is configured using a transistor 713 of one conductivity type (eg, n-channel type), and the switch 704 is configured using a transistor 714 of conductivity type (eg, p-channel type) opposite to that of the transistor 713. An example is shown. Here, the first terminal of the switch 703 corresponds to one of the source and the drain of the transistor 713, the second terminal of the switch 703 corresponds to the other of the source and the drain of the transistor 713, and the switch 703 is the gate of the transistor 713. In accordance with the control signal RD input to the first terminal, the conduction or non-conduction between the first terminal and the second terminal (that is, the on state or the off state of the transistor 713) is selected. The first terminal of the switch 704 corresponds to one of the source and the drain of the transistor 714, the second terminal of the switch 704 corresponds to the other of the source and the drain of the transistor 714, and the switch 704 is input to the gate of the transistor 714. The control signal RD selects conduction or non-conduction between the first terminal and the second terminal (that is, the on state or the off state of the transistor 714).

One of a source and a drain of the transistor 709 is electrically connected to one of a pair of electrodes of the capacitor 708 and a gate of the transistor 710. Here, the connection part is referred to as a node M2. One of a source and a drain of the transistor 710 is electrically connected to a wiring (eg, a GND line) that can supply a low power supply potential, and the other is connected to a first terminal of the switch 703 (a source and a drain of the transistor 713). On the other hand). The second terminal of the switch 703 (the other of the source and the drain of the transistor 713) is electrically connected to the first terminal of the switch 704 (one of the source and the drain of the transistor 714). A second terminal of the switch 704 (the other of the source and the drain of the transistor 714) is electrically connected to a wiring that can supply the power supply potential VDD. A second terminal of the switch 703 (the other of the source and the drain of the transistor 713), a first terminal of the switch 704 (one of a source and a drain of the transistor 714), an input terminal of the logic element 706, and the capacitor 707 One of the pair of electrodes is electrically connected. Here, the connection part is referred to as a node M1. The other of the pair of electrodes of the capacitor 707 can have a structure in which a constant potential is input. For example, a low power supply potential (such as GND) or a high power supply potential (such as VDD) can be input. The other of the pair of electrodes of the capacitor 707 is electrically connected to a wiring (eg, a GND line) that can supply a low power supply potential. The other of the pair of electrodes of the capacitor 708 can have a structure in which a constant potential is input. For example, a low power supply potential (such as GND) or a high power supply potential (such as VDD) can be input. The other of the pair of electrodes of the capacitor 708 is electrically connected to a wiring that can supply a low power supply potential (eg, a GND line).

Note that the capacitor 707 and the capacitor 708 can be omitted by actively using a parasitic capacitance of a transistor or a wiring.

A control signal WE is input to the gate electrode of the transistor 709. The switch 703 and the switch 704 are selected to be in a conduction state or a non-conduction state between the first terminal and the second terminal by a control signal RD different from the control signal WE. When the terminals of the other switch are in a conductive state, the first terminal and the second terminal of the other switch are in a non-conductive state.

A signal corresponding to data held in the circuit 701 is input to the other of the source and the drain of the transistor 709. FIG. 27 illustrates an example in which the signal output from the circuit 701 is input to the other of the source and the drain of the transistor 709. A signal output from the second terminal of the switch 703 (the other of the source and the drain of the transistor 713) is an inverted signal whose logic value is inverted by the logic element 706 and is input to the circuit 701 through the circuit 720. .

Note that FIG. 27 illustrates an example in which a signal output from the second terminal of the switch 703 (the other of the source and the drain of the transistor 713) is input to the circuit 701 through the logic element 706 and the circuit 720. It is not limited to. A signal output from the second terminal of the switch 703 (the other of the source and the drain of the transistor 713) may be input to the circuit 701 without inversion of the logical value. For example, when there is a node in the circuit 701 that holds a signal in which the logical value of the signal input from the input terminal is inverted, the second terminal of the switch 703 (the other of the source and the drain of the transistor 713) An output signal can be input to the node.

As the transistor 709 in FIG. 27, the transistor 150 described in Embodiment 1 can be used. Further, the control signal WE can be input to the gate electrode, and the control signal WE2 can be input to the back gate electrode. The control signal WE2 may be a signal having a constant potential. As the constant potential, for example, a ground potential GND or a potential lower than the source potential of the transistor 709 is selected. The control signal WE2 is a potential signal for controlling the threshold voltage of the transistor 709, and the drain current of the transistor 709 when the gate voltage is 0 V can be further reduced. Note that as the transistor 709, a transistor having no second gate can be used.

In FIG. 27, among the transistors used for the memory element 730, a transistor other than the transistor 709 can be a transistor in which a channel is formed in a layer made of a semiconductor other than an oxide semiconductor or the substrate 1190. For example, a transistor in which a channel is formed in a silicon layer or a silicon substrate can be used. Further, all the transistors used for the memory element 730 can be transistors in which a channel is formed using an oxide semiconductor layer. Alternatively, in the memory element 730, a transistor other than the transistor 709 is combined with a transistor whose channel is formed using an oxide semiconductor layer and a transistor whose channel is formed in a layer formed using a semiconductor other than an oxide semiconductor or the substrate 1190. It may be used.

For the circuit 701 in FIG. 27, for example, a flip-flop circuit can be used. As the logic element 706, for example, an inverter, a clocked inverter, or the like can be used.

In the semiconductor device of one embodiment of the present invention, data stored in the circuit 701 can be held in the node M2 by the capacitor 708 provided in the circuit 702 while the power supply voltage is not supplied to the memory element 730. .

In addition, as described above, a transistor in which a channel is formed in the oxide semiconductor layer has extremely low off-state current. For example, the off-state current of a transistor in which a channel is formed in an oxide semiconductor layer is significantly lower than the off-state current of a transistor in which a channel is formed in crystalline silicon. Therefore, when the transistor is used as the transistor 709, the signal held in the capacitor 708 is maintained for a long time even when the power supply voltage is not supplied to the memory element 730. In this manner, the memory element 730 can hold the memory content (data) even while the supply of power supply voltage is stopped.

Further, by providing the switch 703 and the switch 704, it is possible to shorten the time until the circuit 701 retains the original data again after the supply of the power supply voltage is resumed.

In the circuit 702, the signal held at the node M2 is input to the gate of the transistor 710. Therefore, after the supply of the power supply voltage to the memory element 730 is restarted, the signal held in the node M2 can be converted into the state of the transistor 710 (on state or off state) and read from the circuit 702. . Therefore, the original signal can be accurately read even if the potential corresponding to the signal held at the node M2 slightly fluctuates.

By using such a storage element 730 for a storage device such as a register or a cache memory included in the CPU, it is possible to prevent data in the storage device from being lost due to supply of power supply voltage being stopped. In addition, after the supply of the power supply voltage is resumed, the state before the power supply stop can be restored in a short time. Therefore, the power supply can be stopped for a short time in the entire CPU or in one or a plurality of logic circuits constituting the CPU, and the frequency of power supply stop can be increased, so that power consumption can be suppressed.

In this embodiment, the storage element 730 is described as an example of using the CPU. However, the storage element 730 is an LSI such as a DSP (Digital Signal Processor), a custom LSI, or a PLD (Programmable Logic Device), and an RF (Radio Frequency) tag. It can also be applied to.

[Imaging device]
An imaging device will be described as an example of a semiconductor device using the above-described transistor.

<Configuration Example of Imaging Device 600>
FIG. 28A is a plan view illustrating a configuration example of the imaging device 600. FIG. The imaging device 600 includes a pixel portion 621, a first circuit 260, a second circuit 270, a third circuit 280, and a fourth circuit 290. Note that in this specification and the like, the first circuit 260 to the fourth circuit 290 and the like may be referred to as “peripheral circuits” or “drive circuits”. For example, the first circuit 260 can be said to be part of the peripheral circuit.

FIG. 28B is a diagram illustrating a configuration example of the pixel portion 621. The pixel portion 621 includes a plurality of pixels 622 (imaging elements) arranged in a matrix of p columns and q rows (p and q are natural numbers of 2 or more). Note that n in FIG. 28B is a natural number of 1 to p, and m is a natural number of 1 to q.

For example, when the pixels 622 are arranged in a 1920 × 1080 matrix, the imaging device 600 capable of imaging at a resolution of so-called full high vision (also referred to as “2K resolution”, “2K1K”, “2K”, and the like) is realized. Can do. For example, when the pixels 622 are arranged in a matrix of 4096 × 2160, an imaging device 600 that can capture images with a resolution of so-called ultra high vision (also referred to as “4K resolution”, “4K2K”, “4K”, etc.) is realized. can do. Further, for example, when the pixels 622 are arranged in a matrix of 8192 × 4320, an imaging device 600 that can capture an image with a resolution of so-called super high vision (also referred to as “8K resolution”, “8K4K”, “8K”, or the like) is realized. can do. By increasing the number of display elements, it is also possible to realize the imaging device 600 that can capture images with a resolution of 16K or 32K.

The first circuit 260 and the second circuit 270 are connected to the plurality of pixels 622 and have a function of supplying signals for driving the plurality of pixels 622. In addition, the first circuit 260 may have a function of processing an analog signal output from the pixel 622. The third circuit 280 may have a function of controlling operation timing of the peripheral circuits. For example, it may have a function of generating a clock signal. Further, it may have a function of converting the frequency of a clock signal supplied from the outside. The third circuit 280 may have a function of supplying a reference potential signal (eg, a ramp wave signal).

The peripheral circuit includes at least one of a logic circuit, a switch, a buffer, an amplifier circuit, and a conversion circuit. Further, a transistor or the like used for the peripheral circuit may be formed using part of a semiconductor formed for manufacturing a pixel driver circuit 610 described later. A semiconductor device such as an IC may be used for part or all of the peripheral circuit.

Note that at least one of the first circuit 260 to the fourth circuit 290 may be omitted as the peripheral circuit. For example, the function of one of the first circuit 260 or the fourth circuit 290 is added to the other of the first circuit 260 or the fourth circuit 290, and one of the first circuit 260 or the fourth circuit 290 is added. May be omitted. Further, for example, the function of one of the second circuit 270 or the third circuit 280 is added to the other of the second circuit 270 or the third circuit 280 so that the second circuit 270 or the third circuit 280 is added. One of these may be omitted. Further, for example, another peripheral circuit may be omitted by adding the function of another peripheral circuit to any one of the first circuit 260 to the fourth circuit 290.

In addition, as illustrated in FIG. 29, a first circuit 260 to a fourth circuit 290 may be provided along the outer periphery of the pixel portion 621. Further, the pixel 622 may be disposed at an angle in the pixel portion 621 included in the imaging device 600. By arranging the pixels 622 at an angle, the pixel interval (pitch) in the row direction and the column direction can be shortened. Thereby, the quality of the image imaged with the imaging device 600 can be improved more.

In addition, as illustrated in FIG. 30, the pixel portion 621 may be provided over the first circuit 260 to the fourth circuit 290. FIG. 30A is a top view of an imaging device 600 in which a pixel portion 621 is formed over the first circuit 260 to the fourth circuit 290. FIG. 30B is a perspective view for explaining the structure of the imaging device 600 shown in FIG.

By providing the pixel portion 621 over the first circuit 260 to the fourth circuit 290, the area occupied by the pixel portion 621 with respect to the size of the imaging device 600 can be increased. Therefore, the light receiving sensitivity of the imaging device 600 can be improved. In addition, the dynamic range of the imaging apparatus 600 can be improved. In addition, the resolution of the imaging device 600 can be improved. In addition, the reproducibility of the image captured by the imaging apparatus 600 can be improved. In addition, the degree of integration of the imaging device 600 can be improved.

[Color filters, etc.]
The pixel 622 included in the imaging device 600 is used as a sub-pixel, and information for realizing color image display is obtained by providing each of the plurality of pixels 622 with a filter (color filter) that transmits light in different wavelength ranges. be able to.

FIG. 31A is a plan view illustrating an example of a pixel 623 for acquiring a color image. FIG. 31A illustrates a pixel 622 (hereinafter, also referred to as “pixel 622R”) provided with a color filter that transmits light in the red (R) wavelength region, and light in the green (G) wavelength region. A pixel 622 provided with a color filter (hereinafter also referred to as “pixel 622G”) and a pixel 622 provided with a color filter that transmits light in the blue (B) wavelength range (hereinafter also referred to as “pixel 622B”). Have. The pixels 622R, 622G, and 622B are combined to function as one pixel 623.

Note that the color filter used for the pixel 623 is not limited to red (R), green (G), and blue (B), and is a color filter that transmits light of cyan (C), yellow (Y), and magenta (M). May be used. A full-color image can be acquired by providing a pixel 622 that detects light of at least three different wavelength ranges in one pixel 623.

FIG. 31B illustrates a color filter that transmits yellow (Y) light in addition to the pixel 622 provided with color filters that transmit red (R), green (G), and blue (B) light, respectively. The pixel 623 having the pixel 622 provided with is illustrated. FIG. 31C illustrates a color filter that transmits blue (B) light in addition to a pixel 622 provided with a color filter that transmits cyan (C), yellow (Y), and magenta (M) light, respectively. The pixel 623 having the pixel 622 provided with is illustrated. By providing the pixel 622 that detects light of four or more different wavelength ranges in one pixel 623, it is possible to further improve the color reproducibility of the acquired image.

Further, the pixel number ratio (or the light receiving area ratio) of the pixels 622R, 622G, and 622B is not necessarily 1: 1: 1. As shown in FIG. 31D, a Bayer array in which the pixel number ratio (light-receiving area ratio) is red: green: blue = 1: 2: 1 may be used. The pixel number ratio (light receiving area ratio) may be red: green: blue = 1: 6: 1.

Note that one pixel 622 may be used for the pixel 623, but two or more are preferable. For example, by providing two or more pixels 622 that detect light in the same wavelength region, redundancy can be increased and the reliability of the imaging device 600 can be increased.

In addition, an imaging device 600 that detects infrared light is realized by using an IR (Infrared) filter that absorbs or reflects light having a wavelength equal to or smaller than that of visible light and transmits infrared light as a filter. can do. Further, an imaging device 600 that detects ultraviolet light is realized by using a UV (Ultra Violet) filter that absorbs or reflects light having a wavelength longer than that of visible light and transmits ultraviolet light as a filter. be able to. Further, by using a scintillator that converts radiation into ultraviolet light or visible light as a filter, the imaging apparatus 600 can also function as a radiation detector that detects X-rays, γ-rays, and the like.

Further, when an ND (ND: Neutral Density) filter (a neutral density filter) is used as a filter, a phenomenon in which the output is saturated when a large amount of light is incident on the photoelectric conversion element (light receiving element) (hereinafter referred to as “output”). (Also called “saturation”). By using a combination of ND filters having different light reduction amounts, the dynamic range of the imaging apparatus can be increased.

In addition to the filter described above, a lens may be provided for the pixel 622. Here, an arrangement example of the pixel 622, the filter 624, and the lens 625 will be described with reference to the cross-sectional view of FIG. By providing the lens 625, incident light can be efficiently received by the photoelectric conversion element. Specifically, as illustrated in FIG. 32A, light 660 is converted into a photoelectric conversion element 601 through a lens 625 formed in the pixel 622, a filter 624 (filter 624R, filter 624G, filter 624B), a pixel driver circuit 610, and the like. It can be set as the structure made to enter in.

However, as illustrated in a region surrounded by a two-dot chain line, part of the light 660 indicated by an arrow may be shielded by part of the wiring group 626, a transistor, and / or a capacitor. Therefore, as illustrated in FIG. 32B, a structure may be employed in which a lens 625 and a filter 624 are formed on the photoelectric conversion element 601 side so that incident light is efficiently received by the photoelectric conversion element 601. By making the light 660 incident from the photoelectric conversion element 601 side, the imaging device 600 with high light receiving sensitivity can be provided.

FIG. 33A to FIG. 33C illustrate an example of a pixel driver circuit 610 that can be used for the pixel portion 621. A pixel driver circuit 610 illustrated in FIG. 33A includes a transistor 602, a transistor 604, and a capacitor 606, and is connected to the photoelectric conversion element 601. One of a source and a drain of the transistor 602 is electrically connected to the photoelectric conversion element 601, and the other of the source and the drain of the transistor 602 is electrically connected to the gate of the transistor 604 through a node 607 (charge storage portion). Yes.

An OS transistor is preferably used as the transistor 602. Since the OS transistor can extremely reduce off-state current, the capacitor 606 can be reduced. Alternatively, as illustrated in FIG. 33B, the capacitor 606 can be omitted. In addition, when an OS transistor is used as the transistor 602, the potential of the node 607 hardly changes. Therefore, it is possible to realize an imaging device that is hardly affected by noise. Note that an OS transistor may be used as the transistor 604.

As the photoelectric conversion element 601, a diode element in which a pn-type or pin-type junction is formed in a silicon substrate can be used. Alternatively, a pin-type diode element using an amorphous silicon film, a microcrystalline silicon film, or the like may be used. Alternatively, a diode-connected transistor may be used. Alternatively, a variable resistor using a photoelectric effect may be formed using silicon, germanium, selenium, or the like.

Alternatively, the photoelectric conversion element may be formed using a material that can absorb radiation and generate charges. Examples of materials that can generate charges by absorbing radiation include lead iodide, mercury iodide, gallium arsenide, CdTe, and CdZn.

A pixel driver circuit 610 illustrated in FIG. 33C includes a transistor 602, a transistor 603, a transistor 604, a transistor 605, and a capacitor 606, and is connected to the photoelectric conversion element 601. Note that the pixel driver circuit 610 illustrated in FIG. 33C illustrates the case where a photodiode is used as the photoelectric conversion element 601. One of a source and a drain of the transistor 602 is electrically connected to the cathode of the photoelectric conversion element 601 and the other is electrically connected to the node 607. The anode of the photoelectric conversion element 601 is electrically connected to the wiring 611. One of a source and a drain of the transistor 603 is electrically connected to the node 607 and the other is electrically connected to the wiring 608. A gate of the transistor 604 is electrically connected to the node 607, one of a source and a drain is electrically connected to the wiring 609, and the other is electrically connected to one of the source and the drain of the transistor 605. The other of the source and the drain of the transistor 605 is electrically connected to the wiring 608. One electrode of the capacitor 606 is electrically connected to the node 607 and the other electrode is electrically connected to the wiring 611.

The transistor 602 can function as a transfer transistor. A transfer signal TX is supplied to the gate of the transistor 602. The transistor 603 can function as a reset transistor. A reset signal RST is supplied to the gate of the transistor 603. The transistor 604 can function as an amplification transistor. The transistor 605 can function as a selection transistor. A selection signal SEL is supplied to the gate of the transistor 605. In addition, VDD is supplied to the wiring 608 and VSS is supplied to the wiring 611.

Next, operation of the pixel driver circuit 610 illustrated in FIG. 33C is described. First, the transistor 603 is turned on, and VDD is supplied to the node 607 (reset operation). After that, when the transistor 603 is turned off, VDD is held at the node 607. Next, when the transistor 602 is turned on, the potential of the node 607 changes according to the amount of light received by the photoelectric conversion element 601 (accumulation operation). After that, when the transistor 602 is turned off, the potential of the node 607 is held. Next, when the transistor 605 is turned on, a potential corresponding to the potential of the node 607 is output to the wiring 609 (selection operation). By detecting the potential of the wiring 609, the amount of light received by the photoelectric conversion element 601 can be known.

An OS transistor is preferably used for the transistors 602 and 603. As described above, since the off-state current of the OS transistor can be extremely small, the capacitor 606 can be small. Alternatively, the capacitor 606 can be omitted. In addition, when an OS transistor is used as the transistor 602 and the transistor 603, the potential of the node 607 hardly changes. Therefore, it is possible to realize an imaging device that is hardly affected by noise.

By arranging the pixels 622 using any one of the pixel driver circuits 610 shown in FIGS. 33A to 33C in a matrix, an imaging device with high resolution can be realized.

For example, when the pixel driving circuit 610 is arranged in a 1920 × 1080 matrix, an imaging device capable of imaging at a resolution of so-called full high vision (also referred to as “2K resolution”, “2K1K”, “2K”, etc.) is realized. be able to. Further, for example, when the pixel driver circuit 610 is arranged in a 4096 × 2160 matrix, an imaging device capable of imaging at a resolution of so-called ultra high vision (also referred to as “4K resolution”, “4K2K”, “4K”, etc.). Can be realized. Further, for example, when the pixel driver circuit 610 is arranged in a matrix of 8192 × 4320, an imaging device capable of imaging at a resolution of so-called super high vision (also referred to as “8K resolution”, “8K4K”, “8K”, or the like). Can be realized. By increasing the pixel driving circuit 610, it is possible to realize an imaging device capable of imaging at a resolution of 16K or 32K.

A structural example of the pixel 622 using the above-described transistor is illustrated in FIG. FIG. 34 is a cross-sectional view of part of the pixel 622.

A pixel 622 illustrated in FIG. 34 uses an n-type semiconductor as the substrate 401. Further, the p-type semiconductor 221 of the photoelectric conversion element 601 is provided in the substrate 401. Further, part of the substrate 401 functions as the n-type semiconductor 223 of the photoelectric conversion element 601.

The transistor 604 is provided over the substrate 401. The transistor 604 can function as an n-channel transistor. A p-type semiconductor well 220 is provided in a part of the substrate 401. The well 220 can be provided by a method similar to the formation of the p-type semiconductor 221. The well 220 and the p-type semiconductor 221 can be formed at the same time. Note that as the transistor 604, the above-described transistor 282 can be used, for example.

An insulating layer 403, an insulating layer 404, and an insulating layer 405 are formed over the photoelectric conversion element 601 and the transistor 604. An opening 224 is formed in a region where the insulating layer 403 to the insulating layer 405 overlap with the substrate 401 (n-type semiconductor 223), and an opening 225 is formed in the region where the insulating layer 403 to the insulating layer 405 overlaps with the p-type semiconductor 221. In addition, contact plugs 406 are formed in the openings 224 and 225. The contact plug 406 can be provided in the same manner as the contact plug 113a described above. Note that the number and arrangement of the openings 224 and 225 are not particularly limited. Therefore, an imaging device with a high degree of freedom in layout can be realized.

In addition, an electrode 421, an electrode 422, and an electrode 429 are formed over the insulating layer 405. The electrode 421 is electrically connected to the n-type semiconductor 223 (substrate 401) through a contact plug 406 provided in the opening 224. The electrode 429 is electrically connected to the p-type semiconductor 221 through a contact plug 406 provided in the opening 225. The electrode 422 can function as one electrode of the capacitor 606.

An insulating layer 407 is formed so as to cover the electrode 421, the electrode 429, and the electrode 422. The insulating layer 407 can be formed using a material and a method similar to those of the insulating layer 405. Further, the surface of the insulating layer 407 may be subjected to CMP treatment. By performing the CMP treatment, unevenness on the surface of the sample can be reduced, and the coverage of the insulating layer and the conductive layer to be formed thereafter can be improved. The electrode 421, the electrode 422, and the electrode 429 can be formed using a material and a method similar to those of the electrode 114a described above.

The insulating layer 102 is formed over the insulating layer 407, and the electrode 427, the electrode 119, and the electrode 273 are formed over the insulating layer 102. The electrode 427 is electrically connected to the electrode 429 through a contact plug. The electrode 119 can function as a back gate of the transistor 602. The electrode 273 can function as the other electrode of the capacitor 606. As the transistor 602, for example, the above-described transistor 160 can be used.

The electrode 109a is electrically connected to the electrode 427 through a contact plug.

<Modification 1>
A configuration example of the pixel 622 different from that in FIG. 34 is shown in FIG. FIG. 35 is a cross-sectional view of part of the pixel 622.

A pixel 622 illustrated in FIG. 35 includes a transistor 604 and a transistor 605 provided over a substrate 401. The transistor 604 can function as an n-channel transistor. The transistor 605 can function as a p-channel transistor. Note that as the transistor 604, the above-described transistor 282 can be used, for example. For example, the above-described transistor 281 can be used as the transistor 605.

Electrodes 413 a to 413 d are formed over the insulating layer 405. The electrode 413a is electrically connected to one of a source and a drain of the transistor 604, and an electrode 413b is electrically connected to the other of the source and the drain of the transistor 604. The electrode 413c is electrically connected to the gate of the transistor 604. The electrode 413b is electrically connected to one of a source and a drain of the transistor 605, and an electrode 413d is electrically connected to the other of the source and the drain of the transistor 605.

The electrode 109b and the electrode 413c are electrically connected through a contact plug 112d. An insulating layer 415 is formed over the electrode 114a, the electrode 114b, and the insulating layer 112. The insulating layer 415 can be formed using a material and a method similar to those of the insulating layer 111.

In the pixel 622 illustrated in FIG. 35, the photoelectric conversion element 601 is provided over the insulating layer 415. An insulating layer 442 is provided over the photoelectric conversion element 601, and an electrode 488 is provided over the insulating layer 442. The insulating layer 442 can be formed using a material and a method similar to those of the insulating layer 415.

A photoelectric conversion element 601 illustrated in FIG. 35 includes a photoelectric conversion layer 681 between an electrode 686 formed using a metal material or the like and a light-transmitting conductive layer 682. FIG. 35 shows a mode in which a selenium-based material is used for the photoelectric conversion layer 681. A photoelectric conversion element 601 using a selenium-based material has a characteristic that external quantum efficiency with respect to visible light is high. The photoelectric conversion element can be a highly sensitive sensor with a large amplification of electrons with respect to the amount of incident light due to the avalanche phenomenon. Further, since the selenium-based material has a high light absorption coefficient, it has an advantage that the photoelectric conversion layer 681 can be easily thinned.

As the selenium-based material, amorphous selenium or crystalline selenium can be used. For example, crystalline selenium can be obtained by heat-treating amorphous selenium after film formation. Note that by making the crystal grain size of crystalline selenium smaller than the pixel pitch, it is possible to reduce the characteristic variation of each pixel. Crystalline selenium has higher spectral sensitivity to visible light and higher light absorption coefficient than amorphous selenium.

Although the photoelectric conversion layer 681 is illustrated as a single layer, gallium oxide or cerium oxide is provided as a hole injection blocking layer on the light-receiving surface side of the selenium-based material, and nickel oxide is used as an electron injection blocking layer on the electrode 686 side. Or it can also be set as the structure which provides antimony sulfide etc.

Further, the photoelectric conversion layer 681 may be a layer containing a compound of copper, indium, and selenium (CIS). Alternatively, it may be a layer containing a compound of copper, indium, gallium, and selenium (CIGS). In CIS and CIGS, a photoelectric conversion element that can utilize an avalanche phenomenon as in the case of a single layer of selenium can be formed.

CIS and CIGS are p-type semiconductors, and n-type semiconductors such as cadmium sulfide and zinc sulfide may be provided in contact with each other to form a junction.

In order to generate the avalanche phenomenon, it is preferable to apply a relatively high voltage (for example, 10 V or more) to the photoelectric conversion element. Since the OS transistor has a higher drain withstand voltage than the Si transistor, it is easy to apply a relatively high voltage to the photoelectric conversion element. Therefore, by combining an OS transistor with a high drain withstand voltage and a photoelectric conversion element using a selenium-based material as a photoelectric conversion layer, an imaging device with high sensitivity and high reliability can be obtained.

The light-transmitting conductive layer 682 includes, for example, indium tin oxide, indium tin oxide containing silicon, indium oxide containing zinc, zinc oxide, zinc oxide containing gallium, zinc oxide containing aluminum, tin oxide, or fluorine. Tin oxide containing, tin oxide containing antimony, graphene, or the like can be used. The light-transmitting conductive layer 682 is not limited to a single layer, and may be a stack of different films. 35 shows a structure in which the light-transmitting conductive layer 682 and the wiring 487 are electrically connected to each other through the electrode 488 and the contact plug 489, the light-transmitting conductive layer 682 and the wiring 487 are directly connected to each other. You may touch.

Further, the electrode 686, the wiring 487, and the like may have a structure in which a plurality of conductive layers are stacked. For example, the electrode 686 can be two layers of the conductive layer 686a and the conductive layer 686b, and the wiring 487 can be two layers of the conductive layer 487a and the conductive layer 487b. For example, the conductive layer 686a and the conductive layer 487a may be formed using a low-resistance metal or the like, and the conductive layer 686b and the conductive layer 487b may be formed using a metal or the like having good contact characteristics with the photoelectric conversion layer 681. . By setting it as such a structure, the electrical property of a photoelectric conversion element can be improved. In addition, some metals may cause electrolytic corrosion when in contact with the light-transmitting conductive layer 682. Even when such a metal is used for the conductive layer 487a, electrolytic corrosion can be prevented through the conductive layer 487b.

For the conductive layer 686b and the conductive layer 487b, for example, molybdenum, tungsten, or the like can be used. For the conductive layer 686a and the conductive layer 487a, for example, aluminum, titanium, or a stack in which aluminum is sandwiched between titanium can be used.

Alternatively, the insulating layer 442 may have a multilayer structure. The partition wall 477 can be formed using an inorganic insulator, an insulating organic resin, or the like. The partition wall 477 may be colored black or the like for shielding light from a transistor or the like and / or for determining an area of a light receiving portion per pixel.

As the photoelectric conversion element 601, a pin-type diode element using an amorphous silicon film, a microcrystalline silicon film, or the like may be used. The photodiode has a configuration in which an n-type semiconductor layer, an i-type semiconductor layer, and a p-type semiconductor layer are sequentially stacked. Amorphous silicon is preferably used for the i-type semiconductor layer. For the p-type semiconductor layer and the n-type semiconductor layer, amorphous silicon or microcrystalline silicon containing a dopant imparting each conductivity type can be used. A photodiode using amorphous silicon as a photoelectric conversion layer has high sensitivity in the wavelength region of visible light and can easily detect weak visible light.

Note that the pn-type or pin-type diode element is preferably provided so that the p-type semiconductor layer serves as a light receiving surface. By using the p-type semiconductor layer as the light receiving surface, the output current of the photoelectric conversion element 601 can be increased.

The photoelectric conversion element 601 formed using the above-described selenium-based material, amorphous silicon, or the like can be manufactured using a general semiconductor manufacturing process such as a film formation process, a lithography process, or an etching process.

[Display device]
A display device will be described as an example of a semiconductor device using the above-described transistor. A display device (a liquid crystal display device, a light-emitting display device, or the like) that is a device having a display element can have various modes or have various elements.

Display devices include, for example, EL (electroluminescence) elements (EL elements including organic substances and inorganic substances, organic EL elements, inorganic EL elements), LED chips (white LED chips, red LED chips, green LED chips, blue LED chips, etc.) , Transistors (transistors that emit light in response to current), electron-emitting devices, display devices using carbon nanotubes, liquid crystal devices, electronic ink, electrowetting devices, electrophoretic devices, MEMS (micro electro mechanical systems) Display elements used (for example, grating light valve (GLV), digital micromirror device (DMD), DMS (digital micro shutter), MIRASOL (registered trademark), IMOD (interference modulation) element MEMS display element shutter method, MEMS display element employing optical interferometry, such as a piezoelectric ceramic display), or has at least one and quantum dots.

In addition to these, the display device may include a display medium in which contrast, luminance, reflectance, transmittance, and the like change due to an electrical or magnetic action. For example, the display device may be a plasma display (PDP).

An example of a display device using an EL element is an EL display. As an example of a display device using an electron-emitting device, there is a field emission display (FED), a SED type flat display (SED: Surface-Conduction Electron-Emitter Display), or the like.

An example of a display device using a quantum dot for each pixel is a quantum dot display. Note that the quantum dots may be provided not in the display element but in part of a backlight used for a liquid crystal display device or the like. By using quantum dots, display with high color purity can be performed.

As an example of a display device using a liquid crystal element, there is a liquid crystal display device (a transmissive liquid crystal display, a transflective liquid crystal display, a reflective liquid crystal display, a direct view liquid crystal display, or a projection liquid crystal display).

Note that in the case of realizing a transflective liquid crystal display or a reflective liquid crystal display, part or all of the pixel electrode may have a function as a reflective electrode. For example, part or all of the pixel electrode may have aluminum, silver, or the like. Further, in that case, a memory circuit such as an SRAM can be provided under the reflective electrode. Thereby, power consumption can be further reduced.

An example of a display device using electronic ink, electronic powder fluid (registered trademark), or an electrophoretic element is electronic paper.

Note that, when an LED chip is used for a display element or the like, graphene or graphite may be disposed under the LED chip electrode or nitride semiconductor. Graphene or graphite may be a multilayer film in which a plurality of layers are stacked. Thus, by providing graphene or graphite, a nitride semiconductor, for example, an n-type GaN semiconductor layer having a crystal can be easily formed thereon. Furthermore, a p-type GaN semiconductor layer having a crystal or the like can be provided thereon to form an LED chip. Note that an AlN layer may be provided between graphene or graphite and an n-type GaN semiconductor layer having a crystal. Note that the GaN semiconductor layer of the LED chip may be formed by MOCVD. However, by providing graphene, the GaN semiconductor layer of the LED chip can be formed by a sputtering method.

In a display element using MEMS, a space in which the display element is sealed (for example, between an element substrate on which the display element is disposed and a counter substrate disposed to face the element substrate). In addition, a desiccant may be disposed. By arranging the desiccant, it is possible to prevent the MEMS and the like from becoming difficult to move due to moisture or from being easily deteriorated.

<Pixel circuit configuration example>
Next, a more specific configuration example of the display device will be described with reference to FIG. FIG. 36A is a block diagram for describing a structure of the display device 3100. The display device 3100 includes a display area 3131, a circuit 3132, and a circuit 3133. The circuit 3132 functions as a scan line driver circuit, for example. The circuit 3133 functions as a signal line driver circuit, for example.

In addition, the display device 3100 is arranged substantially in parallel with each other and m scanning lines 3135 whose potentials are controlled by the circuit 3132, and each of the display devices 3100 is arranged substantially in parallel, and the potential is supplied by the circuit 3133. N signal lines 3136 to be controlled. Further, the display region 3131 includes a plurality of pixels 3130 arranged in a matrix of m rows and n columns. Note that m and n are both natural numbers of 2 or more.

In the display region 3131, each scanning line 3135 is electrically connected to n pixels 3130 arranged in any row of the pixels 3130. Each signal line 3136 is electrically connected to m pixels 3130 arranged in any column of the pixels 3130.

As shown in FIG. 37A, a circuit 3152 may be provided at a position facing the circuit 3132 with the display region 3131 interposed therebetween. As shown in FIG. 37B, a circuit 3153 may be provided at a position facing the circuit 3133 with the display region 3131 interposed therebetween. 37A and 37B illustrate an example in which the circuit 3152 is connected to the scan line 3135 in the same manner as the circuit 3132. However, the present invention is not limited to this. For example, the circuit 3132 and the circuit 3152 connected to the scanning line 3135 may be changed every several rows. FIG. 37B illustrates an example in which the circuit 3153 is connected to the signal line 3136 similarly to the circuit 3133. However, the present invention is not limited to this. For example, the circuit 3133 and the circuit 3153 connected to the signal line 3136 may be changed every several rows. The circuit 3132, the circuit 3133, the circuit 3152, and the circuit 3153 may have functions other than driving the pixel 3130.

Further, the circuit 3132, the circuit 3133, the circuit 3152, and the circuit 3153 may be referred to as a driver circuit portion. The pixel 3130 includes a pixel circuit 3137 and a display element. The pixel circuit 3137 is a circuit for driving a display element. The transistor included in the driver circuit portion can be formed at the same time as the transistor included in the pixel circuit 3137. Alternatively, part or all of the driver circuit portion may be formed over another substrate and electrically connected to the display device 3100. For example, part or all of the driver circuit portion may be formed using a single crystal substrate and electrically connected to the display device 3100.

FIG. 36B and FIG. 36C illustrate circuit configurations that can be used for the pixel 3130 of the display device 3100.

<Example of pixel circuit for light-emitting display device>
FIG. 36B illustrates an example of a pixel circuit that can be used for the light-emitting display device. A pixel circuit 3137 illustrated in FIG. 36B includes a transistor 3431, a capacitor 3233, a transistor 3232, and a transistor 3434. In addition, the pixel circuit 3137 is electrically connected to a light-emitting element 3125 that can function as a display element.

One of a source electrode and a drain electrode of the transistor 3431 is electrically connected to an n-th column signal line 3136 (hereinafter referred to as a signal line DL_n) to which a data signal is supplied. Further, the gate electrode of the transistor 3431 is electrically connected to an m-th scanning line 3135 (hereinafter referred to as a scanning line GL_m) to which a gate signal is supplied.

The transistor 3431 has a function of controlling writing of a data signal to the node 3435.

One of the pair of electrodes of the capacitor 3233 is electrically connected to the node 3435 and the other is electrically connected to the node 3437. The other of the source electrode and the drain electrode of the transistor 3431 is electrically connected to the node 3435.

The capacitor 3233 has a function as a storage capacitor that stores data written to the node 3435.

One of a source electrode and a drain electrode of the transistor 3232 is electrically connected to the potential supply line VL_a, and the other is electrically connected to a node 3437. Further, the gate electrode of the transistor 3232 is electrically connected to the node 3435.

One of a source electrode and a drain electrode of the transistor 3434 is electrically connected to the potential supply line VL_c, and the other is electrically connected to a node 3437. Further, the gate electrode of the transistor 3434 is electrically connected to the scan line GL_m.

One of an anode and a cathode of the light-emitting element 3125 is electrically connected to the potential supply line VL_b, and the other is electrically connected to the node 3437.

As the light-emitting element 3125, for example, an organic electroluminescence element (also referred to as an organic EL element) or the like can be used. However, it is not limited to this, For example, you may use the inorganic EL element which consists of inorganic materials.

For example, the potential supply line VL_a has a function of supplying VDD. The potential supply line VL_b has a function of supplying VSS. In addition, the potential supply line VL_c has a function of supplying VSS.

Here, an example of operation of the display device including the pixel circuit 3137 in FIG. 36B will be described. First, the pixel circuit 3137 in each row is sequentially selected by the circuit 3132, the transistor 3431 is turned on, and a data signal (potential) is written to the node 3435. Next, the transistor 3434 is turned on and the potential of the node 3437 is set to VSS.

After that, the data signal written to the node 3435 is held with the transistor 3431 turned off. Next, the transistor 3434 is turned off. The amount of current flowing between the source and drain of the transistor 3232 is determined in accordance with the data signal written to the node 3435. Therefore, the light emitting element 3125 emits light with luminance corresponding to the amount of current flowing. By sequentially performing this for each row, an image can be displayed.

In addition, a color image can be displayed by using a plurality of pixels 3130 as sub-pixels and emitting light in different wavelength ranges from the respective sub-pixels. For example, a pixel 3130 that emits light in the red wavelength region, a pixel 3130 that emits light in the green wavelength region, and a pixel 3130 that emits light in the blue wavelength region are used as one pixel.

The wavelength range of the combined light is not limited to red, green, and blue, and may be cyan, yellow, and magenta. A color image can be displayed by providing subpixels that emit light of at least three different wavelength ranges in one pixel.

In addition, one or more of yellow, cyan, magenta, white, and the like may be added to red, green, and blue. For example, in addition to red, green, and blue, subpixels that emit light in the yellow wavelength range may be added. One or more of red, green, blue, white, etc. may be added to cyan, yellow, and magenta. For example, in addition to cyan, yellow, and magenta, subpixels that emit light in the blue wavelength region may be added. By providing subpixels that emit light in four or more different wavelength ranges in one pixel, the color reproducibility of an image to be displayed can be further improved.

Further, the number ratio (or light emission area ratio) of red, green, and blue used for one pixel is not necessarily 1: 1: 1. For example, the pixel number ratio (light emission area ratio) may be red: green: blue = 1: 1: 2. Further, the pixel number ratio (light emission area ratio) may be red: green: blue = 1: 2: 3.

In addition, color display can be realized by combining color filters such as red, green, and blue with sub-pixels that emit white light. A color filter that transmits light in the red, green, or blue wavelength region may be combined with each of the sub-pixels that emit light in the red, green, or blue wavelength region.

However, the present invention is not limited to a display device for color display, and can also be applied to a display device for monochrome display.

<Example of pixel circuit for liquid crystal display device>
FIG. 36C illustrates an example of a pixel circuit that can be used for a liquid crystal display device. A pixel circuit 3137 illustrated in FIG. 36C includes a transistor 3431 and a capacitor 3233. In addition, the pixel circuit 3137 is electrically connected to a liquid crystal element 3432 that can function as a display element.

One potential of the pair of electrodes of the liquid crystal element 3432 is set as appropriate depending on the specification of the pixel circuit 3137. The alignment state of the liquid crystal included in the liquid crystal element 3432 is set by data written to the node 3436. Note that a common potential (common potential) may be applied to one of the pair of electrodes of the liquid crystal element 3432 included in each of the plurality of pixel circuits 3137.

As a mode of the liquid crystal element 3432, for example, a TN mode, an STN mode, a VA mode, an ASM (Axial Symmetrical Aligned Micro-cell) mode, an OCB (Optically Compensated Birefringence) mode, and an FLC (Ferroelectric AF) mode. A Crystal (B) mode, an MVA mode, a PVA (Patterned Vertical Alignment) mode, an IPS mode, an FFS mode, or a TBA (Transverse Bend Alignment) mode may be used. Other examples include ECB (Electrically Controlled Birefringence) mode, PDLC (Polymer Dispersed Liquid Crystal) mode, PNLC (Polymer Network Liquid Crystal) mode, and guest host mode. However, the present invention is not limited to this, and various modes can be used.

In the pixel circuit 3137 in the m-th row and the n-th column, one of a source electrode and a drain electrode of the transistor 3431 is electrically connected to the signal line DL_n, and the other is electrically connected to a node 3436. A gate electrode of the transistor 3431 is electrically connected to the scan line GL_m. The transistor 3431 has a function of controlling writing of a data signal to the node 3436.

One of the pair of electrodes of the capacitor 3233 is electrically connected to a wiring to which a specific potential is supplied (hereinafter also referred to as “capacitor line CL”), and the other is electrically connected to a node 3436. . The other of the pair of electrodes of the liquid crystal element 3432 is electrically connected to the node 3436. Note that the value of the potential of the capacitor line CL is set as appropriate in accordance with the specifications of the pixel circuit 3137. The capacitor 3233 functions as a storage capacitor that stores data written in the node 3436.

Here, an example of operation of the display device including the pixel circuit 3137 in FIG. 36C is described. First, the pixel circuit 3137 in each row is sequentially selected by the circuit 3132, the transistor 3431 is turned on, and a data signal is written to the node 3436.

Next, the data signal written to the node 3436 is held with the transistor 3431 turned off. The amount of light transmitted through the liquid crystal element 3432 is determined in accordance with the data signal written to the node 3436. By sequentially performing this for each row, an image can be displayed in the display area 3131.

<Configuration example of display device>
With the use of the transistor described in any of the above embodiments, part or all of a driver circuit including a transistor can be formed over the same substrate as the pixel portion, so that a system-on-panel can be formed. A structure example of a display device in which the transistor described in any of the above embodiments can be used will be described with reference to FIGS.

[Liquid crystal display device and light emitting display device]
As an example of a display device, a display device using a liquid crystal element and a display device using a light emitting element will be described. In FIG. 38A, a sealant 4005 is provided so as to surround the pixel portion 4002 provided over the first substrate 4001 and sealed with the second substrate 4006. In FIG. 38A, a signal line formed using a single crystal semiconductor or a polycrystalline semiconductor over a separately prepared substrate in a region different from the region surrounded by the sealant 4005 over the first substrate 4001. A driver circuit 4003 and a scan line driver circuit 4004 are mounted. In addition, various signals and potentials supplied to the signal line driver circuit 4003, the scan line driver circuit 4004, or the pixel portion 4002 are supplied from an FPC (Flexible Printed Circuit) 4018a and an FPC 4018b.

38B and 38C, a sealant 4005 is provided so as to surround the pixel portion 4002 provided over the first substrate 4001 and the scan line driver circuit 4004. A second substrate 4006 is provided over the pixel portion 4002 and the scan line driver circuit 4004. Therefore, the pixel portion 4002 and the scan line driver circuit 4004 are sealed together with the display element by the first substrate 4001, the sealant 4005, and the second substrate 4006. 38B and 38C, a single crystal semiconductor or a polycrystalline semiconductor is provided over a separately prepared substrate in a region different from the region surrounded by the sealant 4005 over the first substrate 4001. A signal line driver circuit 4003 formed in (1) is mounted. 38B and 38C, a variety of signals and potentials are supplied to the signal line driver circuit 4003, the scan line driver circuit 4004, or the pixel portion 4002 from an FPC 4018.

FIGS. 38B and 38C illustrate an example in which the signal line driver circuit 4003 is formed separately and mounted on the first substrate 4001; however, the present invention is not limited to this structure. The scan line driver circuit may be separately formed and mounted, or only part of the signal line driver circuit or only part of the scan line driver circuit may be separately formed and mounted.

Note that a connection method of a driver circuit which is separately formed is not particularly limited, and wire bonding, COG (Chip On Glass), TCP (Tape Carrier Package), COF (Chip On Film), or the like can be used. FIG. 38A illustrates an example in which the signal line driver circuit 4003 and the scanning line driver circuit 4004 are mounted by COG, and FIG. 38B illustrates an example in which the signal line driver circuit 4003 is mounted by COG. (C) is an example in which the signal line driver circuit 4003 is mounted by TCP.

In some cases, the display device includes a panel in which the display element is sealed, and a module in which an IC including a controller or the like is mounted on the panel.

The pixel portion and the scan line driver circuit provided over the first substrate include a plurality of transistors, and the transistors described in the above embodiments can be used.

39A and 39B are cross-sectional views illustrating a cross-sectional structure of a portion indicated by the chain line N1-N2 in FIG. 38B. The display device illustrated in FIGS. 39A and 39B includes an electrode 4015, and the electrode 4015 is electrically connected to a terminal included in the FPC 4018 through an anisotropic conductive layer 4019. The electrode 4015 is electrically connected to the wiring 4014 in an opening formed in the insulating layer 4112, the insulating layer 4111, and the insulating layer 4110.

The electrode 4015 is formed using the same conductive layer as the first electrode layer 4030, and the wiring 4014 is formed using the same conductive layer as the source electrode and the drain electrode of the transistor 4010 and the transistor 4011.

The pixel portion 4002 and the scan line driver circuit 4004 provided over the first substrate 4001 include a plurality of transistors. In FIGS. 39A and 39B, transistors included in the pixel portion 4002 are included. 4010 and a transistor 4011 included in the scan line driver circuit 4004 are illustrated. In FIG. 39A, an insulating layer 4112, an insulating layer 4111, and an insulating layer 4110 are provided over the transistor 4010 and the transistor 4011. In FIG. 39B, a partition wall 4510 is formed over the insulating layer 4112. Yes.

In addition, the transistor 4010 and the transistor 4011 are provided over the insulating layer 4102. The transistor 4010 and the transistor 4011 each include an electrode 4017 formed over the insulating layer 4102, and the insulating layer 4103 is formed over the electrode 4017.
The electrode 4017 can function as a back gate electrode.

As the transistor 4010 and the transistor 4011, any of the transistors described in the above embodiments can be used. In the transistor described in the above embodiment, the fluctuation in electric characteristics is suppressed and the transistor is electrically stable. Therefore, the display device in this embodiment illustrated in FIGS. 39A and 39B can be a highly reliable display device.

Note that FIGS. 39A and 39B illustrate the case where a transistor having a structure similar to that of the transistor 160 described in the above embodiment is used as the transistor 4010 and the transistor 4011.

In addition, the display device illustrated in FIGS. 39A and 39B includes a capacitor 4020. The capacitor 4020 has a region where the electrode 4021 overlaps with part of one of the source electrode and the drain electrode of the transistor 4010 with the insulating layer 4103 interposed therebetween. The electrode 4021 is formed using the same conductive layer as the electrode 4017.

In general, the capacitance of a capacitor provided in a display device is set so that charges can be held for a predetermined period in consideration of leakage current of a transistor arranged in a pixel portion. The capacity of the capacitor may be set in consideration of the off-state current of the transistor.

For example, by using an OS transistor in the pixel portion of the liquid crystal display device, the capacitance of the capacitor can be reduced to 1/3 or less, more preferably 1/5 or less of the liquid crystal capacitance. By using the OS transistor, the formation of the capacitor can be omitted.

A transistor 4010 provided in the pixel portion 4002 is electrically connected to the display element. FIG. 39A illustrates an example of a liquid crystal display device using a liquid crystal element as a display element. In FIG. 39A, a liquid crystal element 4013 which is a display element includes a first electrode layer 4030, a second electrode layer 4031, and a liquid crystal layer 4008. Note that an insulating layer 4032 and an insulating layer 4033 which function as alignment films are provided so as to sandwich the liquid crystal layer 4008. The second electrode layer 4031 is provided on the second substrate 4006 side, and the first electrode layer 4030 and the second electrode layer 4031 overlap with each other with the liquid crystal layer 4008 interposed therebetween.

The spacer 4035 is a columnar spacer obtained by selectively etching the insulating layer, and is provided to control the distance (cell gap) between the first electrode layer 4030 and the second electrode layer 4031. Yes. A spherical spacer may be used.

When a liquid crystal element is used as the display element, a thermotropic liquid crystal, a low molecular liquid crystal, a polymer liquid crystal, a polymer dispersed liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, or the like can be used. These liquid crystal materials exhibit a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, and the like depending on conditions.

Alternatively, a liquid crystal exhibiting a blue phase for which an alignment film is unnecessary may be used. The blue phase is one of the liquid crystal phases. When the temperature of the cholesteric liquid crystal is increased, the blue phase appears immediately before the transition from the cholesteric phase to the isotropic phase. Since the blue phase appears only in a narrow temperature range, a liquid crystal composition mixed with 5% by weight or more of a chiral agent is used for the liquid crystal layer in order to improve the temperature range. A liquid crystal composition including a liquid crystal exhibiting a blue phase and a chiral agent has a response speed as short as 1 msec or less and is optically isotropic, so that alignment treatment is unnecessary and viewing angle dependency is small. Further, since it is not necessary to provide an alignment film, a rubbing process is not required, so that electrostatic breakdown caused by the rubbing process can be prevented, and defects or breakage of the liquid crystal display device during the manufacturing process can be reduced. . Therefore, the productivity of the liquid crystal display device can be improved.

Further, a method called multi-domain or multi-domain design in which pixels (pixels) are divided into several regions (sub-pixels) and molecules are tilted in different directions can be used.

The specific resistance of the liquid crystal material is 1 × 10 ⁹ Ω · cm or more, preferably 1 × 10 ¹¹ Ω · cm or more, and more preferably 1 × 10 ¹² Ω · cm or more. In addition, the value of the specific resistance in this specification shall be the value measured at 20 degreeC.

The OS transistor used in this embodiment can have a low current value in an off state (off-state current value). Therefore, the holding time of an electric signal such as an image signal can be increased, and the writing interval can be set longer in the power-on state. Therefore, since the frequency of the refresh operation can be reduced, there is an effect of suppressing power consumption.

In addition, the OS transistor can be driven at high speed because relatively high field-effect mobility can be obtained. Therefore, a high-quality image can be provided by using the transistor in the pixel portion of the display device. In addition, since a driver circuit portion or a pixel portion can be separately manufactured over the same substrate, the number of components of the display device can be reduced.

In the display device, a black matrix (light-shielding layer), an optical member (optical substrate) such as a polarizing member, a retardation member, and an antireflection member, and the like may be provided as appropriate. For example, circularly polarized light using a polarizing substrate and a retardation substrate may be used. Further, a backlight, a sidelight, or the like may be used as the light source.

Alternatively, a light-emitting element utilizing electroluminescence (also referred to as an “EL element”) can be used as a display element included in the display device. An EL element includes a layer containing a light-emitting compound (also referred to as an “EL layer”) between a pair of electrodes. When a potential difference larger than the threshold voltage of the EL element is generated between the pair of electrodes, holes are injected into the EL layer from the anode side and electrons are injected from the cathode side. The injected electrons and holes are recombined in the EL layer, and the light-emitting substance contained in the EL layer emits light.

The EL element is distinguished depending on whether the light emitting material is an organic compound or an inorganic compound, and the former is generally called an organic EL element and the latter is called an inorganic EL element.

In the organic EL element, by applying a voltage, electrons from one electrode and holes from the other electrode are injected into the EL layer. Then, these carriers (electrons and holes) recombine, whereby the light-emitting organic compound forms an excited state, and emits light when the excited state returns to the ground state. Due to such a mechanism, such a light-emitting element is referred to as a current-excitation light-emitting element.

Note that in addition to the light-emitting compound, the EL layer includes a substance having a high hole-injecting property, a substance having a high hole-transporting property, a hole blocking material, a substance having a high electron-transporting property, a substance having a high electron-injecting property, or a bipolar layer. Material (a material having a high electron transporting property and a high hole transporting property) may be included.

The EL layer can be formed by a method such as a vapor deposition method (including a vacuum vapor deposition method), a transfer method, a printing method, an ink jet method, or a coating method.

Inorganic EL elements are classified into a dispersion-type inorganic EL element and a thin-film inorganic EL element depending on the element structure. The dispersion-type inorganic EL element has a light-emitting layer in which particles of a light-emitting material are dispersed in a binder, and the light emission mechanism is donor-acceptor recombination light emission using a donor level and an acceptor level. The thin-film inorganic EL element has a structure in which a light emitting layer is sandwiched between dielectric layers and further sandwiched between electrodes, and the light emission mechanism is localized light emission utilizing inner-shell electron transition of metal ions. Note that description is made here using an organic EL element as a light-emitting element.

In order to extract light emitted from the light-emitting element, at least one of the pair of electrodes may be transparent. Then, a transistor and a light emitting element are formed on a substrate, and a top emission structure that extracts light from a surface opposite to the substrate, a bottom emission structure that extracts light from a surface on the substrate side, There is a light emitting element having a dual emission structure in which light emission is extracted from both sides, and any light emitting element having an emission structure can be applied.

FIG. 39B illustrates an example of a light-emitting display device (also referred to as an “EL display device”) using a light-emitting element as a display element. A light-emitting element 4513 which is a display element is electrically connected to a transistor 4010 provided in the pixel portion 4002. Note that the structure of the light-emitting element 4513 is a stacked structure of the first electrode layer 4030, the light-emitting layer 4511, and the second electrode layer 4031; however, the structure is not limited to this structure. The structure of the light-emitting element 4513 can be changed as appropriate depending on the direction in which light is extracted from the light-emitting element 4513, or the like.

A partition wall 4510 is formed using an organic insulating material or an inorganic insulating material. In particular, it is preferable to use a photosensitive resin material and form an opening on the first electrode layer 4030 so that the side surface of the opening is an inclined surface formed with a continuous curvature.

The light emitting layer 4511 may be composed of a single layer or a plurality of layers stacked.

A protective layer may be formed over the second electrode layer 4031 and the partition wall 4510 so that oxygen, hydrogen, moisture, carbon dioxide, or the like does not enter the light-emitting element 4513. As the protective layer, silicon nitride, silicon nitride oxide, aluminum oxide, aluminum nitride, aluminum oxynitride, aluminum nitride oxide, DLC (Diamond Like Carbon), or the like can be formed. In addition, a filler 4514 is provided in a space sealed by the first substrate 4001, the second substrate 4006, and the sealant 4005 and sealed. As described above, it is preferable to package (enclose) the protective film with a protective film (bonded film, ultraviolet curable resin film, or the like) or a cover material that has high hermeticity and little degassing so as not to be exposed to the outside air.

As the filler 4514, an ultraviolet curable resin or a thermosetting resin can be used in addition to an inert gas such as nitrogen or argon. PVC (polyvinyl chloride), acrylic resin, polyimide, epoxy resin, silicone resin, PVB ( Polyvinyl butyral) or EVA (ethylene vinyl acetate) can be used. Further, the filler 4514 may contain a desiccant.

As the sealant 4005, a glass material such as glass frit, or a resin material such as a two-component mixed resin, a curable resin that cures at normal temperature, a photocurable resin, or a thermosetting resin can be used. Further, the sealing material 4005 may contain a desiccant.

If necessary, an optical film such as a polarizing plate, a circular polarizing plate (including an elliptical polarizing plate), a retardation plate (λ / 4 plate, λ / 2 plate), a color filter, or the like is provided on the light emitting element exit surface. You may provide suitably. Further, an antireflection film may be provided on the polarizing plate or the circularly polarizing plate. For example, anti-glare treatment can be performed that diffuses reflected light due to surface irregularities and reduces reflection.

In addition, when the light-emitting element has a microcavity structure, light with high color purity can be extracted. Further, by combining the microcavity structure and the color filter, the reflection can be reduced and the visibility of the display image can be improved.

In the first electrode layer and the second electrode layer (also referred to as a pixel electrode layer, a common electrode layer, a counter electrode layer, or the like) that applies a voltage to the display element, the direction of light to be extracted, the place where the electrode layer is provided, and What is necessary is just to select translucency and reflectivity by the pattern structure of an electrode layer.

The first electrode layer 4030 and the second electrode layer 4031 include indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide, and indium containing titanium oxide. A light-transmitting conductive material such as tin oxide, indium zinc oxide, or indium tin oxide to which silicon oxide is added can be used.

The first electrode layer 4030 and the second electrode layer 4031 are tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), and tantalum (Ta). , Chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), silver (Ag) and other metals, or alloys thereof, or One or more metal nitrides can be used.

Alternatively, the first electrode layer 4030 and the second electrode layer 4031 can be formed using a conductive composition including a conductive high molecule (also referred to as a conductive polymer). As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, a copolymer of two or more of aniline, pyrrole, and thiophene or a derivative thereof can be given.

In addition, since the transistor is easily broken by static electricity or the like, it is preferable to provide a protective circuit for protecting the driving circuit. The protection circuit is preferably configured using a non-linear element.

By using the transistor described in the above embodiment, a highly reliable display device can be provided. Further, with the use of the transistor described in any of the above embodiments, a display device with high display quality and high definition can be provided. In addition, a display device with reduced power consumption can be provided.

[Display module]
A display module will be described as an example of a semiconductor device using the above-described transistor. A display module 6000 illustrated in FIG. 40 includes a touch sensor 6004 connected to the FPC 6003, a display panel 6006 connected to the FPC 6005, a backlight unit 6007, a frame 6009, and a printed board 6010 between the upper cover 6001 and the lower cover 6002. The battery 6011 is included. Note that the backlight unit 6007, the battery 6011, the touch sensor 6004, and the like may not be provided.

The semiconductor device of one embodiment of the present invention can be used for, for example, a touch sensor 6004, a display panel 6006, an integrated circuit mounted on a printed circuit board 6010, or the like. For example, the display device described above can be used for the display panel 6006.

The shapes and dimensions of the upper cover 6001 and the lower cover 6002 can be changed as appropriate in accordance with the sizes of the touch sensor 6004, the display panel 6006, and the like.

As the touch sensor 6004, a resistive touch sensor or a capacitive touch sensor can be used by being superimposed on the display panel 6006. It is also possible to add a touch sensor function to the display panel 6006. For example, a touch sensor electrode may be provided in each pixel of the display panel 6006 to add a capacitive touch panel function. Alternatively, an optical sensor can be provided in each pixel of the display panel 6006 to add an optical touch sensor function.

The backlight unit 6007 has a light source 6008. The light source 6008 may be provided at the end of the backlight unit 6007 and a light diffusing plate may be used. In the case where a light-emitting display device or the like is used for the display panel 6006, the backlight unit 6007 can be omitted.

In addition to the protective function of the display panel 6006, the frame 6009 has a function as an electromagnetic shield for blocking electromagnetic waves generated from the printed circuit board 6010 side. The frame 6009 may have a function as a heat sink.

The printed board 6010 includes a power supply circuit, a signal processing circuit for outputting a video signal and a clock signal, and the like. The power source for supplying power to the power supply circuit may be a battery 6011 or a commercial power source. Note that the battery 6011 can be omitted when a commercial power source is used as the power source.

Further, a member such as a polarizing plate, a retardation plate, or a prism sheet may be additionally provided in the display module 6000.

Note that this embodiment can be combined with any of the other embodiments and examples in this specification as appropriate.

[RF tag]
An RF tag is described as an example of a semiconductor device using the above-described transistor.

An RF tag according to one embodiment of the present invention includes a storage circuit (storage device) inside, stores information in the storage circuit, and exchanges information with the outside using non-contact means, for example, wireless communication. is there. Because of these characteristics, the RF tag can be used in an individual authentication system that identifies an article by reading individual information about the article. In addition, high reliability is required for use in these applications.

The configuration of the RF tag will be described with reference to FIG. FIG. 41 is a block diagram illustrating a configuration example of an RF tag.

As shown in FIG. 41, the RF tag 800 includes an antenna 804 that receives a radio signal 803 transmitted from an antenna 802 connected to a communication device 801 (also referred to as an interrogator or a reader / writer). The above-described transistor may be used for the communication device 801. The RF tag 800 includes a rectifier circuit 805, a constant voltage circuit 806, a demodulation circuit 807, a modulation circuit 808, a logic circuit 809, a storage circuit 810, and a ROM 811. Note that for example, an oxide semiconductor capable of sufficiently suppressing reverse current may be used for the semiconductor of the transistor that exhibits the rectifying action included in the demodulation circuit 807. Thereby, the fall of the rectification effect | action resulting from a reverse current can be suppressed, and it can prevent that the output of a demodulation circuit is saturated. That is, the output of the demodulation circuit with respect to the input of the demodulation circuit can be made closer to linear. Note that there are three major data transmission formats: an electromagnetic coupling method in which a pair of coils are arranged facing each other to perform communication by mutual induction, an electromagnetic induction method in which communication is performed by an induction electromagnetic field, and a radio wave method in which communication is performed using radio waves. Separated. The RF tag 800 can be used for any of the methods.

Next, the configuration of each circuit will be described. The antenna 804 is for transmitting and receiving a radio signal 803 to and from the antenna 802 connected to the communication device 801. The rectifier circuit 805 rectifies an input AC signal generated by receiving a radio signal by the antenna 804, for example, half-wave double-voltage rectification, and smoothes the rectified signal by a subsequent capacitive element. This is a circuit for generating an input potential. Note that a limiter circuit may be provided on the input side or the output side of the rectifier circuit 805. The limiter circuit is a circuit for controlling not to input more than a certain amount of power to a subsequent circuit when the amplitude of the input AC signal is large and the internally generated voltage is large.

The constant voltage circuit 806 is a circuit for generating a stable power supply voltage from the input potential and supplying it to each circuit. Note that the constant voltage circuit 806 may include a reset signal generation circuit. The reset signal generation circuit is a circuit for generating a reset signal of the logic circuit 809 using a stable rise of the power supply voltage.

The demodulation circuit 807 is a circuit for demodulating an input AC signal by detecting an envelope and generating a demodulated signal. The modulation circuit 808 is a circuit for performing modulation according to data output from the antenna 804.

A logic circuit 809 is a circuit for analyzing and processing the demodulated signal. The memory circuit 810 is a circuit that holds input information and includes a row decoder, a column decoder, a storage area, and the like. The ROM 811 is a circuit for storing a unique number (ID) or the like and outputting it according to processing.

Note that each circuit described above can be appropriately discarded.

The above memory device can be used for the memory circuit 810. The memory device according to one embodiment of the present invention is suitable for an RF tag because it can retain information even when the power is turned off. Furthermore, since the power (voltage) necessary for data writing is lower than that of a conventional nonvolatile memory, the memory device according to one embodiment of the present invention does not cause a difference in maximum communication distance between data reading and writing. It is also possible. Furthermore, it is possible to suppress the occurrence of malfunction or erroneous writing due to insufficient power during data writing.

Further, the memory device according to one embodiment of the present invention can be used as a nonvolatile memory, and thus can be applied to the ROM 811. In that case, it is preferable that the producer separately prepares a command for writing data in the ROM 811 so that the user cannot freely rewrite the command. By shipping the product after the producer writes the unique number before shipping, it is possible to assign a unique number only to the good products to be shipped, rather than assigning a unique number to all the produced RF tags, The unique number of the product after shipment does not become discontinuous, and customer management corresponding to the product after shipment becomes easy.

An example of use of the RF tag according to one embodiment of the present invention is described with reference to FIGS. Applications of RF tags are wide-ranging. For example, bills, coins, securities, bearer bonds, certificates such as driver's licenses and resident's cards (see FIG. 42A), recording media such as DVD software and video tape ( 42 (B)), containers such as dishes, cups and bottles (see FIG. 42 (C)), packaging articles such as wrapping paper, boxes and ribbons, and moving bodies such as bicycles (see FIG. 42 (D)). .), Personal items such as bags and glasses, plants, animals, human bodies, clothing, daily necessities, medical products including drugs and drugs, or electronic devices (for example, liquid crystal display devices, EL display devices, television devices, or mobile phones) Etc., or a tag attached to each article (see FIG. 42E and FIG. 42F) can be used.

The RF tag 800 according to one embodiment of the present invention is fixed to an article by being attached to a surface or embedded. For example, a book is embedded in paper, and a package made of an organic resin is embedded in the organic resin and fixed to each article. The RF tag 800 according to one embodiment of the present invention achieves small size, thinness, and light weight, and thus does not impair the design of the article itself even after being fixed to the article. In addition, an authentication function can be given to banknotes, coins, securities, bearer bonds, certificates, etc. by the RF tag 800 according to one embodiment of the present invention, and forgery can be prevented by utilizing this authentication function. Can do. Further, by attaching the RF tag 800 according to one embodiment of the present invention to a packaging container, a recording medium, personal items, clothing, daily life, electronic equipment, or the like, the efficiency of a system such as an inspection system can be improved. . In addition, by attaching the RF tag 800 according to one embodiment of the present invention to a moving object, security against theft or the like can be improved. As described above, the RF tag 800 according to one embodiment of the present invention can be used for each application as described above.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 5)
<Package using lead frame type interposer>
FIG. 43A is a perspective view showing a cross-sectional structure of a package using a lead frame type interposer. In a package illustrated in FIG. 43A, a chip 551 corresponding to a semiconductor device according to one embodiment of the present invention is connected to a terminal 552 over an interposer 550 by a wire bonding method. The terminal 552 is disposed on the surface on which the chip 551 of the interposer 550 is mounted. The chip 551 may be sealed with a mold resin 553, but is sealed with a part of each terminal 552 exposed.

An example of a structure of the electronic device in which the package is mounted on the circuit board is illustrated in FIG. The electronic device illustrated in FIG. 43B is mounted on, for example, a mobile phone. In the electronic device illustrated in FIG. 43B, a package 562 and a battery 564 are mounted on a printed wiring board 561. In addition, a printed wiring board 561 is mounted with an FPC 563 on a panel 560 provided with a display element.

Note that this embodiment can be combined with any of the other embodiments and examples in this specification as appropriate.

(Embodiment 6)
In this embodiment, an example of an electronic device including the semiconductor device according to one embodiment of the present invention will be described.

As an electronic device using a semiconductor device according to one embodiment of the present invention, a display device such as a television or a monitor, a lighting device, a desktop or laptop personal computer, a word processor, or a DVD (Digital Versatile Disc) is stored in a recording medium Playback device for playing back still images or moving images, portable CD player, radio, tape recorder, headphone stereo, stereo, table clock, wall clock, cordless telephone cordless handset, transceiver, car phone, mobile phone, personal digital assistant, tablet Type game consoles, portable game machines, fixed game machines such as pachinko machines, calculators, electronic notebooks, electronic books, electronic translators, voice input devices, video cameras, digital still cameras, electric shavers, microwave ovens, etc. , Electric rice cooker, electric washing Air conditioner such as rinsing machine, electric vacuum cleaner, water heater, electric fan, hair dryer, air conditioner, humidifier, dehumidifier, dishwasher, dish dryer, clothing dryer, futon dryer, electric refrigerator, electric freezer, electricity Examples include freezer refrigerators, DNA storage freezers, flashlights, tools such as chainsaws, medical devices such as smoke detectors and dialysis machines. Further examples include industrial equipment such as guide lights, traffic lights, belt conveyors, elevators, escalators, industrial robots, power storage systems, power storage devices for power leveling and smart grids. In addition, an engine using fuel, a moving body driven by an electric motor using electric power from a power storage device, and the like may be included in the category of electronic devices. Examples of the moving body include an electric vehicle (EV), a hybrid vehicle (HEV) having both an internal combustion engine and an electric motor, a plug-in hybrid vehicle (PHEV), a tracked vehicle in which these tire wheels are changed to an endless track, and electric assist. Examples include motorbikes including bicycles, motorcycles, electric wheelchairs, golf carts, small or large ships, submarines, helicopters, aircraft, rockets, artificial satellites, space probes, planetary probes, and space ships.

A portable game machine 2900 illustrated in FIG. 44A includes a housing 2901, a housing 2902, a display portion 2903, a display portion 2904, a microphone 2905, a speaker 2906, operation keys 2907, and the like. Note that although the portable game machine illustrated in FIG. 44A includes two display portions 2903 and 2904, the number of display portions is not limited thereto. The display portion 2903 is provided with a touch screen as an input device and can be operated with a stylus 2908 or the like.

An information terminal 2910 illustrated in FIG. 44B includes a housing 2911, a display portion 2912, a microphone 2917, a speaker portion 2914, a camera 2913, an external connection portion 2916, an operation button 2915, and the like. The display portion 2912 includes a display panel using a flexible substrate and a touch screen. The information terminal 2910 can be used as, for example, a smartphone, a mobile phone, a tablet information terminal, a tablet personal computer, an electronic book terminal, or the like.

A laptop personal computer 2920 illustrated in FIG. 44C includes a housing 2921, a display portion 2922, a keyboard 2923, a pointing device 2924, and the like.

A video camera 2940 illustrated in FIG. 44D includes a housing 2941, a housing 2942, a display portion 2944, operation keys 2944, a lens 2945, a connection portion 2946, and the like. The operation keys 2944 and the lens 2945 are provided on the housing 2941, and the display portion 2944 is provided on the housing 2942. The housing 2941 and the housing 2942 are connected to each other by a connection portion 2946. The angle between the housing 2941 and the housing 2942 can be changed by the connection portion 2946. Depending on the angle of the housing 2942 with respect to the housing 2941, the orientation of the image displayed on the display portion 2943 can be changed, and display / non-display of the image can be switched.

FIG. 44E illustrates an example of a bangle information terminal. The information terminal 2950 includes a housing 2951, a display portion 2952, and the like. The display portion 2952 is supported by a housing 2951 having a curved surface. Since the display portion 2952 includes a display panel using a flexible substrate, an information terminal 2950 that is flexible, light, and easy to use can be provided.

FIG. 44F illustrates an example of a wristwatch type information terminal. The information terminal 2960 includes a housing 2961, a display portion 2962, a band 2963, a buckle 2964, operation buttons 2965, an input / output terminal 2966, and the like. The information terminal 2960 can execute various applications such as mobile phone, e-mail, text browsing and creation, music playback, Internet communication, and computer games.

The display surface of the display portion 2962 is curved, and display can be performed along the curved display surface. The display portion 2962 includes a touch sensor and can be operated by touching the screen with a finger, a stylus, or the like. For example, an application can be started by touching an icon 2967 displayed on the display unit 2962. The operation button 2965 can have various functions such as power on / off operation, wireless communication on / off operation, manner mode execution / cancellation, and power saving mode execution / cancellation in addition to time setting. . For example, the function of the operation button 2965 can be set by an operating system incorporated in the information terminal 2960.

In addition, the information terminal 2960 can execute short-range wireless communication that is a communication standard. For example, it is possible to talk hands-free by communicating with a headset capable of wireless communication. Further, the information terminal 2960 includes an input / output terminal 2966, and can directly exchange data with other information terminals via a connector. Charging can also be performed via the input / output terminal 2966. Note that the charging operation may be performed by wireless power feeding without using the input / output terminal 2966.

FIG. 44G illustrates an electric refrigerator-freezer as an example of a home appliance. The electric refrigerator-freezer 2970 includes a housing 2971, a refrigerator door 2972, a freezer door 2973, and the like.

FIG. 44H is an external view illustrating an example of an automobile. The automobile 2980 includes a vehicle body 2981, wheels 2982, a dashboard 2983, lights 2984, and the like.

The electronic device described in this embodiment includes the above-described transistor, the above-described semiconductor device, or the like.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

(Embodiment 7)
In this embodiment, a film formation apparatus (sputtering apparatus) including a film formation chamber in which a sputtering target can be set is described. The film formation apparatus described in this embodiment can be used for a parallel plate sputtering apparatus, a counter target sputtering apparatus, or the like.

In film formation using a facing target sputtering apparatus, damage to a formation surface can be reduced, and thus a film with high crystallinity is easily obtained. That is, in some cases, it is preferable to use an opposing target sputtering apparatus for film formation of the CAAC-OS or the like.

Note that a film forming method using a parallel plate sputtering apparatus can also be referred to as PESP (Parallel Electrode Sputtering). In addition, a film formation method using an opposed target sputtering apparatus can also be referred to as VDSP (Vapor Deposition Sputtering).

First, a structure of a film formation apparatus in which impurities are hardly mixed in a film during film formation is described with reference to FIGS.

FIG. 45 schematically shows a top view of a single-wafer multi-chamber film forming apparatus 2700. The film formation apparatus 2700 includes an atmosphere-side substrate supply chamber 2701 that includes a cassette port 2761 that accommodates a substrate and an alignment port 2762 that aligns the substrate, and an atmosphere-side substrate that transports the substrate from the atmosphere-side substrate supply chamber 2701. A transfer chamber 2702, a load lock chamber 2703a for carrying in a substrate and changing the pressure in the chamber from atmospheric pressure to reduced pressure, or switching from reduced pressure to atmospheric pressure, a substrate for carrying out the substrate, and reducing the pressure in the chamber from reduced pressure to atmospheric pressure. Alternatively, an unload lock chamber 2703b for switching from atmospheric pressure to reduced pressure, a transfer chamber 2704 for transferring a substrate in a vacuum, a substrate heating chamber 2705 for heating the substrate, and a film formation chamber 2706a for forming a film with a target disposed. A film formation chamber 2706b and a film formation chamber 2706c. Note that the film formation chamber 2706a, the film formation chamber 2706b, and the film formation chamber 2706c can refer to the structure of a film formation chamber described later.

The atmosphere-side substrate transfer chamber 2702 is connected to the load lock chamber 2703a and the unload lock chamber 2703b, the load lock chamber 2703a and the unload lock chamber 2703b are connected to the transfer chamber 2704, and the transfer chamber 2704 is heated to the substrate. The chamber 2705, the film formation chamber 2706a, the film formation chamber 2706b, and the film formation chamber 2706c are connected.

Note that a gate valve 2764 is provided at a connection portion of each chamber, and each chamber can be kept in a vacuum state independently of the atmosphere-side substrate supply chamber 2701 and the atmosphere-side substrate transfer chamber 2702. In addition, the atmosphere-side substrate transfer chamber 2702 and the transfer chamber 2704 have a transfer robot 2763 and can transfer a substrate.

The substrate heating chamber 2705 is preferably used also as a plasma processing chamber. The film formation apparatus 2700 can transport the substrate between the processes without being exposed to the atmosphere, and thus can suppress the adsorption of impurities to the substrate. In addition, the order of film formation and heat treatment can be established freely. Note that the number of transfer chambers, film formation chambers, load lock chambers, unload lock chambers, and substrate heating chambers is not limited to the above-described numbers, and an optimal number can be provided as appropriate according to installation space and process conditions.

Next, FIG. 46 shows a cross section corresponding to one-dot chain line X1-X2, one-dot chain line Y1-Y2, and one-dot chain line Y2-Y3 shown in FIG.

FIG. 46A shows a cross section of the substrate heating chamber 2705 and the transfer chamber 2704. The substrate heating chamber 2705 includes a plurality of heating stages 2765 that can accommodate substrates. Note that the substrate heating chamber 2705 is connected to a vacuum pump 2770 through a valve. As the vacuum pump 2770, for example, a dry pump, a mechanical booster pump, or the like can be used.

As a heating mechanism that can be used for the substrate heating chamber 2705, for example, a heating mechanism that heats using a resistance heating element or the like may be used. Alternatively, a heating mechanism that heats by heat conduction or heat radiation from a medium such as a heated gas may be used. For example, RTA such as GRTA and LRTA can be used.

The substrate heating chamber 2705 is connected to a purifier 2781 via a mass flow controller 2780. Note that the mass flow controller 2780 and the purifier 2781 are provided as many as the number of gas types, but only one is shown for easy understanding. As the gas introduced into the substrate heating chamber 2705, a gas having a dew point of −80 ° C. or lower, preferably −100 ° C. or lower can be used. For example, oxygen gas, nitrogen gas, and rare gas (such as argon gas) can be used. Use.

The transfer chamber 2704 has a transfer robot 2863. The transfer robot 2763 can transfer a substrate to each chamber. The transfer chamber 2704 is connected to a vacuum pump 2770 and a cryopump 2771 through valves. With such a configuration, the transfer chamber 2704 is evacuated using a vacuum pump 2770 from atmospheric pressure to low vacuum or medium vacuum (about 0.1 to several hundred Pa), and the valve is switched to switch from medium vacuum to high vacuum. A vacuum or ultra-high vacuum (0.1 Pa to 1 × 10 ⁻⁷ Pa) is exhausted using a cryopump 2771.

For example, two or more cryopumps 2771 may be connected in parallel to the transfer chamber 2704. With such a configuration, even if one cryopump is being regenerated, the remaining cryopump can be used to exhaust. In addition, the regeneration mentioned above refers to the process which discharge | releases the molecule | numerator (or atom) accumulated in the cryopump. The cryopump is periodically regenerated because the exhaust capacity is reduced if molecules (or atoms) are accumulated too much.

FIG. 46B illustrates a cross section of the deposition chamber 2706b, the transfer chamber 2704, and the load lock chamber 2703a.

Here, the details of the film formation chamber (sputtering chamber) will be described with reference to FIG. A film formation chamber 2706b shown in FIG. 46B includes a target 2766a, a target 2766b, a target shield 2767a, a target shield 2767b, a magnet unit 2790a, a magnet unit 2790b, a substrate holder 2768, a power supply 2791, Have Although not shown, the target 2766a and the target 2766b are each fixed to a target holder via a backing plate. A power source 2791 is electrically connected to the target 2766a and the target 2766b. Magnet unit 2790a and magnet unit 2790b are arranged on the back of target 2766a and target 2766b, respectively. Target shield 2767a and target shield 2767b are arranged to surround the ends of target 2766a and target 2766b, respectively. Here, a substrate 2769 is supported by the substrate holder 2768. The substrate holder 2768 is fixed to the film formation chamber 2706b through the variable member 2784. By the variable member 2784, the substrate holder 2768 can be moved to an area between the targets 2766a and 2766b (also referred to as an inter-target area). For example, by placing a substrate holder 2768 supporting the substrate 2769 in the inter-target region, damage due to plasma may be reduced. Although not shown, the substrate holder 2768 may include a substrate holding mechanism that holds the substrate 2769, a heater that heats the substrate 2769 from the back surface, and the like.

Further, the target shield 2767 can suppress deposition of particles sputtered from the target 2766 in an unnecessary region. The target shield 2767 is desirably processed so that accumulated sputtered particles do not peel off. For example, blast treatment for increasing the surface roughness, or unevenness may be provided on the surface of the target shield 2767.

In addition, the film formation chamber 2706b is connected to the mass flow controller 2780 via the gas heating mechanism 2782, and the gas heating mechanism 2784 is connected to the purifier 2781 via the mass flow controller 2780. The gas introduced into the film formation chamber 2706b can be heated to 40 ° C. or higher and 400 ° C. or lower, preferably 50 ° C. or higher and 200 ° C. or lower by the gas heating mechanism 2782. Note that the gas heating mechanism 2782, the mass flow controller 2780, and the purifier 2781 are provided as many as the number of gas types, but only one is shown for easy understanding. As the gas introduced into the film formation chamber 2706b, a gas having a dew point of −80 ° C. or lower, preferably −100 ° C. or lower can be used. For example, oxygen gas, nitrogen gas, and a rare gas (such as argon gas) are used. Use.

Note that in the case where a purifier is provided immediately before the gas inlet, the length of the pipe from the purifier to the film formation chamber 2706b is 10 m or less, preferably 5 m or less, and more preferably 1 m or less. By setting the length of the pipe to 10 m or less, 5 m or less, or 1 m or less, the influence of the gas released from the pipe can be reduced according to the length. Further, a metal pipe whose inside is covered with iron fluoride, aluminum oxide, chromium oxide or the like may be used for the gas pipe. The above-described piping has a smaller amount of gas containing impurities compared to, for example, SUS316L-EP piping, and can reduce the entry of impurities into the gas. Moreover, it is good to use a high performance ultra-small metal gasket joint (UPG joint) for the joint of piping. In addition, it is preferable that the pipes are all made of metal, because the influence of the generated released gas and external leakage can be reduced as compared with the case where resin or the like is used.

The film formation chamber 2706b is connected to a turbo molecular pump 2772 and a vacuum pump 2770 through valves.

The film formation chamber 2706b is provided with a cryotrap 2751.

The cryotrap 2751 is a mechanism that can adsorb molecules (or atoms) having a relatively high melting point such as water. The turbo molecular pump 2772 stably exhausts large-sized molecules (or atoms) and has a low maintenance frequency, so that it is excellent in productivity, but has a low exhaust capability of hydrogen or water. Therefore, a cryotrap 2751 is connected to the film formation chamber 2706b in order to increase the exhaust capability of water or the like. The temperature of the cryotrap 2751 refrigerator is 100K or less, preferably 80K or less. Further, in the case where the cryotrap 2751 has a plurality of refrigerators, it is preferable to change the temperature for each refrigerator because exhaust can be efficiently performed. For example, the temperature of the first stage refrigerator may be 100K or less, and the temperature of the second stage refrigerator may be 20K or less. In some cases, a higher vacuum can be achieved by using a titanium sublimation pump instead of the cryotrap. In some cases, an even higher vacuum can be achieved by using an ion pump instead of the cryopump or the turbo molecular pump.

Note that the exhaust method of the film formation chamber 2706b is not limited thereto, and a structure similar to the exhaust method (exhaust method of a cryopump and a vacuum pump) described in the above transfer chamber 2704 may be employed. Needless to say, the evacuation method of the transfer chamber 2704 may have a configuration similar to that of the film formation chamber 2706b (evacuation method using a turbo molecular pump and a vacuum pump).

Note that the back pressure (total pressure) of the transfer chamber 2704, the substrate heating chamber 2705, and the film formation chamber 2706b, and the partial pressure of each gas molecule (atom) are preferably as follows. In particular, since impurities may be mixed into the formed film, it is necessary to pay attention to the back pressure of the film formation chamber 2706b and the partial pressure of each gas molecule (atom).

The back pressure (total pressure) of each chamber described above is 1 × 10 ⁻⁴ Pa or less, preferably 3 × 10 ⁻⁵ Pa or less, and more preferably 1 × 10 ⁻⁵ Pa or less. The partial pressure of gas molecules (atoms) having a mass-to-charge ratio (m / z) of 18 in each chamber described above is 3 × 10 ⁻⁵ Pa or less, preferably 1 × 10 ⁻⁵ Pa or less, more preferably 3 ×. 10 ⁻⁶ Pa or less. Moreover, the partial pressure of the gas molecule (atom) whose m / z of each chamber is 28 is 3 × 10 ⁻⁵ Pa or less, preferably 1 × 10 ⁻⁵ Pa or less, more preferably 3 × 10 ^−6. Pa or less. Moreover, the partial pressure of the gas molecule (atom) whose m / z of each chamber is 44 is 3 × 10 ⁻⁵ Pa or less, preferably 1 × 10 ⁻⁵ Pa or less, more preferably 3 × 10 ^−6. Pa or less.

In addition, the total pressure and partial pressure in a vacuum chamber can be measured using a mass spectrometer. For example, a quadrupole mass spectrometer (also referred to as Q-mass) Qulee CGM-051 manufactured by ULVAC, Inc. may be used.

In addition, the transfer chamber 2704, the substrate heating chamber 2705, and the film formation chamber 2706b described above preferably have a structure with little external or internal leakage.

For example, the leakage rate of the transfer chamber 2704, the substrate heating chamber 2705, and the film formation chamber 2706b described above is 3 × 10 ⁻⁶ Pa · m ³ / s or less, preferably 1 × 10 ⁻⁶ Pa · m ³ / s or less. It is. The leak rate of gas molecules (atoms) having an m / z of 18 is 1 × 10 ⁻⁷ Pa · m ³ / s or less, preferably 3 × 10 ⁻⁸ Pa · m ³ / s or less. The leak rate of gas molecules (atoms) having an m / z of 28 is 1 × 10 ⁻⁵ Pa · m ³ / s or less, preferably 1 × 10 ⁻⁶ Pa · m ³ / s or less. Further, the leak rate of gas molecules (atoms) having an m / z of 44 is 3 × 10 ⁻⁶ Pa · m ³ / s or less, preferably 1 × 10 ⁻⁶ Pa · m ³ / s or less.

The leak rate may be derived from the total pressure and partial pressure measured using the mass spectrometer described above.

The leak rate depends on the external leak and the internal leak. An external leak is a gas flowing from outside the vacuum system due to a minute hole or a seal failure. The internal leak is caused by leakage from a partition such as a valve in the vacuum system or gas released from an internal member. In order to make the leak rate below the above-mentioned numerical value, it is necessary to take measures from both the external leak and the internal leak.

For example, the open / close portion of the film formation chamber 2706b may be sealed with a metal gasket. The metal gasket is preferably a metal covered with iron fluoride, aluminum oxide, or chromium oxide. Metal gaskets have higher adhesion than O-rings and can reduce external leakage. In addition, by using the passivation of a metal covered with iron fluoride, aluminum oxide, chromium oxide, or the like, emission gas containing impurities released from the metal gasket can be suppressed, and internal leakage can be reduced.

Further, aluminum, chromium, titanium, zirconium, nickel, or vanadium that emits less impurities and contains less impurities is used as a member that forms the film formation apparatus 2700. Further, the above-described member may be used by being coated with an alloy containing iron, chromium, nickel and the like. Alloys containing iron, chromium, nickel, etc. are rigid, heat resistant and suitable for processing. Here, if the surface irregularities of the member are reduced by polishing or the like in order to reduce the surface area, the emitted gas can be reduced.

Alternatively, the member of the film formation apparatus 2700 described above may be covered with iron fluoride, aluminum oxide, chromium oxide, or the like.

The member of the film forming apparatus 2700 is preferably made of only metal as much as possible. For example, when a viewing window made of quartz or the like is installed, the surface is made of iron fluoride, aluminum oxide, It is good to coat thinly with chromium oxide.

The adsorbate present in the film forming chamber does not affect the pressure in the film forming chamber because it is adsorbed on the inner wall or the like, but causes gas emission when the film forming chamber is exhausted. Therefore, although there is no correlation between the leak rate and the exhaust speed, it is important to desorb the adsorbate present in the film formation chamber as much as possible and exhaust it in advance using a pump having a high exhaust capability. Note that the deposition chamber may be baked to promote desorption of the adsorbate. Baking can increase the desorption rate of the adsorbate by about 10 times. Baking may be performed at 100 ° C to 450 ° C. At this time, if the adsorbate is removed while introducing the inert gas into the film formation chamber, the desorption rate of water or the like that is difficult to desorb only by exhausting can be further increased. In addition, by heating the inert gas to be introduced to the same degree as the baking temperature, the desorption rate of the adsorbate can be further increased. Here, it is preferable to use a rare gas as the inert gas. Further, depending on the type of film to be formed, oxygen or the like may be used instead of the inert gas. For example, when an oxide film is formed, it may be preferable to use oxygen which is a main component. Note that baking is preferably performed using a lamp.

Alternatively, it is preferable to perform a process of increasing the pressure in the deposition chamber by introducing an inert gas such as a heated rare gas or oxygen, and exhausting the deposition chamber again after a predetermined time. By introducing the heated gas, the adsorbate in the deposition chamber can be desorbed, and impurities present in the deposition chamber can be reduced. In addition, it is effective when this treatment is repeated 2 times or more and 30 times or less, preferably 5 times or more and 15 times or less. Specifically, by introducing an inert gas or oxygen having a temperature of 40 ° C. or higher and 400 ° C. or lower, preferably 50 ° C. or higher and 200 ° C. or lower, the pressure in the deposition chamber is 0.1 Pa or higher and 10 kPa or lower, preferably The pressure may be 1 Pa or more and 1 kPa or less, more preferably 5 Pa or more and 100 Pa or less, and the period for maintaining the pressure may be 1 minute or more and 300 minutes or less, preferably 5 minutes or more and 120 minutes or less. After that, the film formation chamber is evacuated for a period of 5 minutes to 300 minutes, preferably 10 minutes to 120 minutes.

Further, the desorption rate of the adsorbate can be further increased by performing dummy film formation. Dummy film formation is performed by depositing a film on the dummy substrate by sputtering or the like, thereby depositing a film on the dummy substrate and the inner wall of the film forming chamber, and depositing impurities on the film forming chamber and adsorbed material on the inner wall of the film forming film. It means confining inside. The dummy substrate is preferably a substrate that emits less gas. By performing dummy film formation, the impurity concentration in a film to be formed later can be reduced. The dummy film formation may be performed simultaneously with baking.

Next, details of the transfer chamber 2704 and the load lock chamber 2703a shown in FIG. 46B and the atmosphere-side substrate transfer chamber 2702 and the atmosphere-side substrate supply chamber 2701 shown in FIG. 46C will be described below. Note that FIG. 46C illustrates a cross section of the atmosphere-side substrate transfer chamber 2702 and the atmosphere-side substrate supply chamber 2701.

For the transfer chamber 2704 illustrated in FIG. 46B, the description of the transfer chamber 2704 illustrated in FIG.

The load lock chamber 2703 a has a substrate transfer stage 2752. The load lock chamber 2703a raises the pressure from the reduced pressure state to the atmosphere, and when the pressure in the load lock chamber 2703a reaches the atmospheric pressure, the transfer robot 2763 provided in the atmosphere side substrate transfer chamber 2702 moves to the substrate transfer stage 2752. Receive the board. After that, the load lock chamber 2703a is evacuated to a reduced pressure state, and then the transfer robot 2762 provided in the transfer chamber 2704 receives the substrate from the substrate transfer stage 2752.

The load lock chamber 2703a is connected to a vacuum pump 2770 and a cryopump 2771 through valves. Since the connection method of the exhaust system of the vacuum pump 2770 and the cryopump 2771 can be connected by referring to the connection method of the transfer chamber 2704, description thereof is omitted here. Note that the unload lock chamber 2703b shown in FIG. 45 can have the same configuration as the load lock chamber 2703a.

The atmosphere-side substrate transfer chamber 2702 has a transfer robot 2763. The transfer robot 2763 can transfer the substrate between the cassette port 2761 and the load lock chamber 2703a. Further, a mechanism for cleaning dust or particles such as a HEPA filter (High Efficiency Particulate Air Filter) may be provided above the atmosphere side substrate transfer chamber 2702 and the atmosphere side substrate supply chamber 2701.

The atmosphere side substrate supply chamber 2701 has a plurality of cassette ports 2761. The cassette port 2761 can accommodate a plurality of substrates.

The target has a surface temperature of 100 ° C. or lower, preferably 50 ° C. or lower, more preferably about room temperature (typically 25 ° C.). In a sputtering apparatus corresponding to a large area substrate, a large area target is often used. However, it is difficult to seamlessly produce a target having a size corresponding to a large area. In reality, a large number of targets are arranged side by side with as little gap as possible, but a slight gap is inevitably generated. From such a slight gap, the surface temperature of the target is increased, so that zinc and the like are volatilized, and the gap may gradually widen. When the gap is widened, the backing plate or the metal of the bonding material used for joining the backing plate and the target may be sputtered, which increases the impurity concentration. Therefore, it is preferable that the target is sufficiently cooled.

Specifically, a metal (specifically, copper) having high conductivity and high heat dissipation is used as the backing plate. Moreover, a target can be efficiently cooled by forming a water channel in the backing plate and flowing a sufficient amount of cooling water through the water channel.

Note that in the case where the target contains zinc, by forming a film in an oxygen gas atmosphere, plasma damage is reduced, and an oxide that hardly causes volatilization of zinc can be obtained.

By using the above-described film formation apparatus, the hydrogen concentration is 2 × 10 ²⁰ atoms / cm ³ or less, preferably 5 × 10 ¹⁹ atoms / cm ^{3 in} secondary ion mass spectrometry (SIMS). Hereinafter, an oxide semiconductor with a thickness of 1 × 10 ¹⁹ atoms / cm ³ or less, more preferably 5 × 10 ¹⁸ atoms / cm ³ or less can be formed.

Further, the nitrogen concentration in SIMS is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 1 × 10 ¹⁹ atoms / cm ³ or less, more preferably 5 × 10 ¹⁸ atoms / cm ³ or less, and further preferably 1 × 10 9. ^An oxide semiconductor with a density of ¹⁸ atoms / cm ³ or less can be formed.

In addition, the carbon concentration in SIMS is less than 5 × 10 ¹⁹ atoms / cm ³ , preferably 5 × 10 ¹⁸ atoms / cm ³ or less, more preferably 1 × 10 ¹⁸ atoms / cm ³ or less, and even more preferably 5 × 10. ^An oxide semiconductor with a density of ¹⁷ atoms / cm ³ or less can be formed.

In addition, a gas molecule (atom) in which m / z is 2 (such as a hydrogen molecule) by a temperature desorption gas spectroscopy (TDS) analysis, a gas molecule (atom) in which m / z is 18, m The release amount of gas molecules (atoms) with / z of 28 and gas molecules (atoms) with m / z of 44 is 1 × 10 ¹⁹ pieces / cm ³ or less, preferably 1 × 10 ¹⁸ pieces / cm ^{3, respectively.} The following oxide semiconductor can be formed.

By using the above film formation apparatus, entry of impurities into the oxide semiconductor can be suppressed. Further, by using the above deposition apparatus to form a film in contact with the oxide semiconductor, the entry of impurities from the film in contact with the oxide semiconductor into the oxide semiconductor can be suppressed.

This embodiment can be implemented in appropriate combination with the structures described in the other embodiments.

100 Transistor 101 Substrate 102 Insulating layer 103 Insulating layer 104 Oxide layer 105 Insulating layer 106 Electrode 107 Insulating layer 108 Structure 109 Electrode 110 Insulating layer 111 Insulating layer 112 Insulating layer 115 Insulating layer 116 Insulating layer 119 Electrode 125 Insulating layer 126 Conducting layer 127 insulating layer 128 insulating layer 129 conductive layer 131 metal element 135 region 141 capacitor element 142 capacitor element 145 mixed layer 147 mixed layer 150 transistor 160 transistor 170 transistor 180 transistor 190 transistor 191 transistor 192 transistor 193 transistor 220 well 221 p-type semiconductor 223 n Type semiconductor 224 opening 225 opening 251 wiring 252 wiring 253 wiring 254 wiring 255 wiring 256 node 257 capacitive element 260 circuit 270 circuit 2 73 Electrode 280 Circuit 281 Transistor 282 Transistor 283 Channel formation region 284 Low-concentration p-type impurity region 285 High-concentration p-type impurity region 286 Insulating layer 287 Electrode 288 Structure 289 Transistor 290 Circuit 291 Transistor 382 Ec
386 Ec
390 trap level 400 semiconductor device 401 substrate 403 insulating layer 404 insulating layer 405 insulating layer 406 contact plug 407 insulating layer 410 semiconductor device 414 element isolation layer 415 insulating layer 420 semiconductor device 421 electrode 422 electrode 427 electrode 429 electrode 430 semiconductor device 442 insulating Layer 477 Partition wall 487 Wire 488 Electrode 489 Contact plug 550 Interposer 551 Chip 552 Terminal 553 Mold resin 560 Panel 561 Printed wiring board 562 Package 563 FPC
564 Battery 600 Imaging device 601 Photoelectric conversion element 602 Transistor 603 Transistor 604 Transistor 605 Transistor 606 Capacitance element 607 Node 608 Wiring 609 Wiring 610 Pixel drive circuit 611 Wiring 621 Pixel portion 622 Pixel 623 Pixel 624 Filter 625 Lens 626 Wiring group 660 Light 681 Photoelectric Conversion layer 682 Translucent conductive layer 686 Electrode 701 Circuit 702 Circuit 703 Switch 704 Switch 706 Logic element 707 Capacitance element 708 Capacitance element 709 Transistor 710 Transistor 713 Transistor 714 Transistor 720 Circuit 730 Storage element 800 RF tag 801 Communication device 802 Antenna 803 Wireless Signal 804 Antenna 805 Rectifier circuit 806 Constant voltage circuit 807 Demodulator circuit 808 Modulator circuit 809 Logic Circuit 810 Memory circuit 811 ROM
1189 ROM interface 1190 board 1191 ALU
1192 ALU Controller 1193 Instruction Decoder 1194 Interrupt Controller 1195 Timing Controller 1196 Register 1197 Register Controller 1198 Bus Interface 1199 ROM
1281 Transistor 1283 Channel formation region 1284 Low-concentration n-type impurity region 1285 High-concentration n-type impurity region 2700 Film formation apparatus 2701 Atmosphere-side substrate supply chamber 2702 Atmosphere-side substrate transfer chamber 2704 Transfer chamber 2705 Substrate heating chamber 2751 Cryo trap 2752 Stage 2761 Cassette Port 2762 Alignment port 2763 Transport robot 2764 Gate valve 2765 Heating stage 2766 Target 2767 Target shield 2768 Substrate holder 2769 Substrate 2770 Vacuum pump 2771 Cryo pump 2772 Turbo molecular pump 2780 Mass flow controller 2781 Refining machine 2782 Gas heating mechanism 2784 Variable member 2791 Power supply 2900 Mobile Game machine 2901 Case 2902 Case 2903 Display 2904 Table 2905 Microphone 2906 Speaker 2907 Operation key 2908 Stylus 2910 Information terminal 2911 Housing 2912 Display unit 2913 Camera 2914 Speaker unit 2915 Button 2916 External connection unit 2917 Microphone 2920 Notebook personal computer 2921 Housing 2922 Display unit 2923 Keyboard 2924 Pointing device 2940 Video Camera 2941 Housing 2942 Housing 2943 Display unit 2944 Operation key 2945 Lens 2946 Connection unit 2950 Information terminal 2951 Housing 2952 Display unit 2960 Information terminal 2961 Housing 2962 Display unit 2963 Band 2964 Buckle 2965 Operation button 2966 Input / output terminal 2967 Icon 2970 Electric refrigerator-freezer 2971 Housing 2972 Refrigeration room door 2993 Freezing room Door 2980 Car 2981 Car body 2982 Wheel 2983 Dashboard 2984 Light 3100 Display device 3125 Light emitting element 3130 Pixel 3131 Display area 3132 Circuit 3133 Circuit 3135 Scan line 3136 Signal line 3137 Pixel circuit 3152 Circuit 3153 Circuit 3232 Transistor 3233 Capacitor element 3431 Transistor 3432 Liquid crystal element 3434 Transistor 3435 Node 3436 Node 3437 Node 5100 Pellet 5120 Substrate 5161 Region 6000 Display module 6001 Upper cover 6002 Lower cover 6003 FPC
6004 Touch sensor 6005 FPC
6006 Display panel 6007 Backlight unit 6008 Light source 6009 Frame 6010 Printed circuit board 6011 Battery 100a Transistor 102a Insulating layer 104a Oxide layer 104b Oxide layer 104c Oxide layer 105a Electrode 105b Electrode 109a Electrode 109b Electrode 109c Electrode 112d Contact plug 113a Contact plug 113b Contact plug 113c Contact plug 114a Electrode 114b Electrode 114c Electrode 118a Oxide semiconductor layer 118b Oxide semiconductor layer 124a Oxide layer 124b Oxide layer 124c Oxide layer 126a Opening 126b Opening 126c Opening 2703a Load lock chamber 2703b Unload lock chamber 2706a Formation Film chamber 2706b Film formation chamber 2706c Film formation chamber 2766a Target 2766b Target 2767a Target shield 2767b Target shield 2790a Magnet unit 2790b Magnet unit 281a Transistor 281b Transistor 282a Transistor 282b Transistor 383a Ec
383b Ec
383c Ec
406a Contact plug 406b Contact plug 406c Contact plug 407a Insulating layer 413a Electrode 413b Electrode 413c Electrode 413d Electrode 487a Conductive layer 487b Conductive layer 622B Pixel 622G Pixel 622R Pixel 624B Filter 624G Filter 624R Filter 686a Conductive layer 686b Conductive layer

Claims (18)

Having first to third oxide layers, insulating layers, first to third electrodes, and a structure;
The first oxide layer is in contact with the second oxide layer;
The second oxide layer is in contact with the third oxide layer;
The first to third oxide layers have first regions overlapping each other,
On the first region, the first electrode and the structure adjacent to the side surface of the first electrode through the insulating layer,
The second oxide layer includes: a second region overlapping with the first electrode; a third region overlapping with the structure; a fourth region in contact with the second electrode; and the third region A fifth region in contact with the electrode,
The structure includes aluminum and oxygen;
The third to fifth regions are transistors including an element different from the element included in the second region. In claim 1,
A transistor in which the element is tungsten, titanium, or aluminum. In claim 1 or claim 2,
The second oxide layer is a transistor that is a CAAC-OS (C Axis Crystallized Oxide Semiconductor). In any one of Claims 1 thru | or 3,
The transistor is characterized in that the second oxide layer contains one or both of In and Zn. In any one of Claims 1 thru | or 4,
The transistor including the first oxide layer and the third oxide layer including a metal element of the same type as at least one metal element among metal elements included in the second oxide layer. A transistor according to any one of claims 1 to 5,
A semiconductor device having a capacitor or a resistor. A semiconductor device according to claim 6;
Antenna, battery, operation switch, microphone, or speaker,
Electronic equipment having A transistor according to any one of claims 1 to 5,
Antenna, battery, operation switch, microphone, or speaker,
Electronic equipment having A first step of forming a second oxide layer on the first oxide layer;
A second step of processing the first and second oxide layers into island shapes;
A third step of forming a third oxide layer covering the second oxide layer;
A fourth step of forming a first insulating layer covering the third oxide layer;
A fifth step of forming a first electrode on the first insulating layer;
Using the first electrode as a mask,
A sixth step of introducing an element into at least part of the second oxide layer;
When forming the second insulating layer covering the first insulating layer and the first electrode,
A seventh step of introducing oxygen into the first insulating layer;
An eighth step of performing heat treatment;
An eighth step of processing the second insulating layer to form a structure adjacent to a side surface of the first electrode;
A ninth step of exposing a region of the second oxide layer that does not overlap the first electrode and the structure;
And a tenth step of forming a second electrode and a third electrode in contact with the exposed region of the second oxide layer,
The method for manufacturing the transistor, wherein the second oxide layer is an oxide semiconductor. In claim 9,
The seventh step is a method for manufacturing a transistor, which is performed by a sputtering method. In claim 9 or claim 10,
The structure body is a method for manufacturing a transistor including aluminum and oxygen. In any one of Claim 9 thru | or Claim 11,
The method for manufacturing a transistor, wherein the element is tungsten, titanium, or aluminum. In any one of Claims 9-12,
The method for manufacturing the transistor, in which the second oxide layer is a CAAC-OS. In any one of claims 9 to 13,
The method for manufacturing a transistor is characterized in that the second oxide layer contains one or both of In and Zn. In any one of claims 9 to 14,
The method for manufacturing a transistor, wherein the first oxide layer and the third oxide layer include at least one kind of metal element among metal elements contained in the second oxide layer. A transistor manufactured by the manufacturing method according to any one of claims 9 to 15,
A semiconductor device having a capacitor or a resistor. A semiconductor device according to claim 16;
Antenna, battery, operation switch, microphone, or speaker,
Electronic equipment having A transistor manufactured by the manufacturing method according to any one of claims 9 to 15, an antenna, a battery, an operation switch, a microphone, or a speaker;
Electronic equipment having