JP2022024525A - Semiconductor device - Google Patents

Abstract

To provide a semiconductor device that can suppress current collapse and a leakage current.SOLUTION: A semiconductor device includes a substrate, a semiconductor laminated structure of a nitride semiconductor provided above the substrate, and a source electrode, a gate electrode, and a drain electrode provided above the semiconductor laminated structure. The semiconductor laminated structure includes a donor-containing layer provided above the substrate, an electron traveling layer provided above the donor-containing layer, and an electron supply layer provided above the electron traveling layer. An opening is formed in the electron supply layer, the electron traveling layer, and the donor-containing layer. The gate electrode is also provided in the opening.SELECTED DRAWING: Figure 3

Description

The present disclosure relates to semiconductor devices.

Nitride semiconductors such as gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), and their mixed crystals have excellent material properties such as high dielectric strength and high saturation rate. Conventionally, the development of a semiconductor device capable of high output and high voltage operation using a nitride semiconductor has been promoted. As a semiconductor device using a nitride semiconductor, many reports have been made on field effect transistors, particularly high electron mobility transistors (HEMTs). As a HEMT using a nitride semiconductor, a HEMT using a GaN layer as an electron traveling layer and an AlGaN layer as an electron supply layer is known. In such a GaN-based HEMT, strain due to the difference in lattice constant between AlGaN and GaN occurs in the AlGaN layer, and piezopolarization occurs with this strain, resulting in high-concentration two-dimensional electron gas. : 2DEG) is generated near the upper surface of the GaN layer under the AlGaN layer. Therefore, application of GaN-based HEMT to high-power amplifiers is expected.

Japanese Unexamined Patent Publication No. 2006-253559 Special Table 2019-525499 Gazette

With conventional semiconductor devices, it is difficult to suppress current collapse and leakage current.

An object of the present disclosure is to provide a semiconductor device capable of suppressing current collapse and leakage current.

According to one embodiment of the present disclosure, a substrate, a semiconductor laminated structure of a nitride semiconductor provided above the substrate, and a source electrode, a gate electrode, and a drain electrode provided above the semiconductor laminated structure are provided. The semiconductor laminated structure has a donor-containing layer provided above the substrate, an electron traveling layer provided above the donor-containing layer, and an electron supply layer provided above the electron traveling layer. A semiconductor device is provided in which an opening is formed in the electron supply layer, the electron traveling layer, and the donor-containing layer, and the gate electrode is also provided in the opening.

According to the present disclosure, current collapse and leakage current can be suppressed.

It is a top view which shows the semiconductor device which concerns on 1st Embodiment. It is sectional drawing (the 1) which shows the semiconductor device which concerns on 1st Embodiment. It is sectional drawing (the 2) which shows the semiconductor device which concerns on 1st Embodiment. It is a top view (the 1) which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a top view (No. 2) which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a top view (No. 3) which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a top view (the 4) which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a top view (No. 5) which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing (the 1) which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing (the 2) which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing (the 3) which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing (the 4) which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing (the 5) which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing (6) which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing (the 7) which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing (the 8) which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is sectional drawing (9) which shows the manufacturing method of the semiconductor device which concerns on 1st Embodiment. It is a top view which shows the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing (the 1) which shows the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing (the 2) which shows the semiconductor device which concerns on 2nd Embodiment. It is a top view (the 1) which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a top view (No. 2) which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a top view (No. 3) which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a top view (the 4) which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing (the 1) which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing (the 2) which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing (the 3) which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is sectional drawing (the 4) which shows the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. It is a top view which shows the semiconductor device which concerns on 3rd Embodiment. It is sectional drawing (the 1) which shows the semiconductor device which concerns on 3rd Embodiment. It is sectional drawing (the 2) which shows the semiconductor device which concerns on 3rd Embodiment. It is a top view (the 1) which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment. It is a top view (No. 2) which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment. It is a top view (No. 3) which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment. It is a top view (the 4) which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment. It is sectional drawing (the 1) which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment. It is sectional drawing (the 2) which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment. It is sectional drawing (the 3) which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment. It is sectional drawing (the 4) which shows the manufacturing method of the semiconductor device which concerns on 3rd Embodiment. It is a top view which shows the semiconductor device which concerns on 4th Embodiment. It is sectional drawing (the 1) which shows the semiconductor device which concerns on 4th Embodiment. It is sectional drawing (the 2) which shows the semiconductor device which concerns on 4th Embodiment. It is a figure which shows the discrete package which concerns on 5th Embodiment. It is a wiring diagram which shows the PFC circuit which concerns on 6th Embodiment. It is a wiring diagram which shows the power supply device which concerns on 7th Embodiment. It is a wiring diagram which shows the amplifier which concerns on 8th Embodiment. It is sectional drawing which shows the semiconductor device which concerns on a reference example. It is a figure which shows the IV characteristic of a reference example.

The inventors of the present application have diligently studied the configuration for suppressing current collapse and leakage current. As a result, it was clarified that the current collapse can be suppressed by providing the donor-containing layer containing the donor between the substrate and the electron traveling layer. It was also clarified that when the donor-containing layer is provided, the leakage current tends to increase when the transistor is on.

Here, the current collapse and the leak current will be described with reference to a reference example. FIG. 47 is a cross-sectional view showing a semiconductor device according to a reference example.

In the semiconductor device 900 according to the reference example, as shown in FIG. 47, the nitride semiconductor laminated structure 910 is formed on the substrate 901 in the Z direction. The Z direction is the direction perpendicular to the main surface of the substrate 901. The nitride semiconductor laminated structure 910 includes a donor-containing layer 902 of GaN, an initial layer 903 of GaN, an electron traveling layer 904 of GaN, and an electron supply layer 905 of AlGaN.

An element separation region defining an element region is formed in the nitride semiconductor laminated structure 910, and a source electrode 901s and a drain electrode 901d extending in the Y direction are formed on the nitride semiconductor laminated structure 910 in the element region. There is. A dielectric layer 921 covering the nitride semiconductor laminated structure 910 is formed. The dielectric layer 921 is a layer of Si nitride (SiN). A gate electrode 901 g extending in the Y direction is formed on the dielectric layer 921.

The semiconductor device 900 according to the reference example has such a configuration. FIG. 48 is a diagram showing the IV characteristics of the reference example. FIG. 48 (a) shows the IV characteristics when the density of the donor contained in the donor-containing layer 902 is 1 × 10 ¹⁸ cm ^-3 or more, and FIG. 48 (b) shows the characteristics of the donor contained in the donor-containing layer 902. The IV characteristics when the density is less than 1 × 10 ¹⁸ cm ^-3 are shown. The solid line in FIG. 48 shows the IV characteristic when stress is applied, and the broken line shows the IV characteristic when stress is not applied. FIG. 48 shows the IV characteristics corresponding to the five types of gate voltages Vg. The relationship of V1 <V2 <V3 <V4 <V5 is established between V1, V2, V3, V4 and V5 in FIG. 48.

As shown in FIG. 48 (a), when the donor density is 1 × 10 ¹⁸ cm ^-3 or more, the difference in IV characteristics between when stress is applied and when stress is not applied is small. .. This means that the current collapse is small. However, when the source-drain voltage Vds becomes 40 V or more, the source-drain current Ids increases. This means that the leakage current is large.

As shown in FIG. 48 (b), when the donor density is less than 1 × 10 ¹⁸ cm ^-3 , the source-drain current Ids increases even if the source-drain voltage Vds is 40 V or more. Not. This means that the leakage current is small. However, there is a large difference in IV characteristics between when stress is applied and when stress is not applied. This means that the current collapse is large.

As described above, in the semiconductor device 900 according to the reference example, it is difficult to suppress both the current collapse and the leak current. Therefore, the inventors of the present application have diligently studied a configuration for suppressing a leak current while suppressing a current collapse. As a result, we came up with a configuration in which the depletion layer spreads from the gate electrode to the donor-containing layer when it is turned on.

Hereinafter, embodiments of the present disclosure will be specifically described with reference to the accompanying drawings. In the present specification and the drawings, components having substantially the same functional configuration may be designated by the same reference numerals to omit duplicate explanations.

(First Embodiment)
The first embodiment will be described. The first embodiment relates to a semiconductor device including a high electron mobility transistor (HEMT). FIG. 1 is a plan view showing a semiconductor device according to the first embodiment. 2 and 3 are cross-sectional views showing a semiconductor device according to the first embodiment. FIG. 2A is a cross-sectional view taken along the line IIa-IIa in FIG. FIG. 2B is a cross-sectional view taken along the line IIb-IIb in FIG. FIG. 3 is a cross-sectional view taken along the line III-III in FIG.

In the semiconductor device 100 according to the first embodiment, as shown in FIGS. 1 to 3, the nitride semiconductor laminated structure 110 is formed on the substrate 101 in the Z direction. The Z direction is a direction perpendicular to the main surface of the substrate 101. The nitride semiconductor laminated structure 110 includes a donor-containing layer 102, an initial layer 103, an electron traveling layer (channel layer) 104, and an electron supply layer (barrier layer) 105. The donor-containing layer 102 is formed on the substrate 101. The initial layer 103 is formed on the donor-containing layer 102. The electronic traveling layer 104 is formed on the initial layer 103. The electron supply layer 105 is formed on the electron traveling layer 104.

The substrate 101 is, for example, a GaN substrate. The donor-containing layer 102 is, for example, a GaN layer containing a donor. The donor-containing layer 102 contains, for example, Si or Ge or a combination thereof as a donor. The density of donors in the donor-containing layer 102 is, for example, 1 × 10 ¹⁸ cm ^-3 or more and 1 × 10 ²⁰ cm ^-3 or less. The donor-containing layer 102 having a high donor density is in a state in which a leak current easily flows due to the presence of many freely moving electrons. The initial layer 103 is a GaN layer in which impurities are not intentionally injected, that is, an i-type GaN layer, and serves as a spacer for suppressing the scattering of electrons by the donor-containing layer 102 having a high donor density. Function. When the material configurations of the substrate 101 and the electron traveling layer 104 are different, the initial layer 103 plays a role of alleviating physical stress due to the difference in the lattice constants. Further, the initial layer 103 plays a role of doping impurities such as Fe to increase the resistance. The electron traveling layer 104 is a GaN layer in which impurities are not intentionally injected, that is, an i-type GaN layer. The electron supply layer 105 is an AlGaN layer in which impurities are not intentionally injected, that is, an i-type AlGaN layer. Two-dimensional electron gas (2DEG) is generated in the vicinity of the interface between the electron traveling layer 104 and the electron supply layer 105.

An element separation region defining an element region is formed in the nitride semiconductor laminated structure 110, and a source electrode 1s and a drain electrode 1d extending in the Y direction are formed on the nitride semiconductor laminated structure 110 in the element region. There is. The source electrode 1s and the drain electrode 1d are arranged side by side in the X direction. The source electrode 1s and the drain electrode 1d include, for example, a Ti film having a thickness of 2 nm to 50 nm and an Al film having a thickness of 100 nm to 300 nm thereof, and are in ohmic contact with the electron supply layer 105. The Y direction is an example of the first direction.

A plurality of openings 120 are formed in the nitride semiconductor laminated structure 110 between the source electrode 1s and the drain electrode 1d. The opening 120 has a rectangular planar shape. The opening 120 is formed so as to penetrate the electron supply layer 105, the electron traveling layer 104, the initial layer 103, and the donor-containing layer 102 in the Z direction and enter the substrate 101. The plurality of openings 120 are formed intermittently side by side in the Y direction. That is, the opening 120 is formed at the position of a stepping stone, so to speak. The plurality of openings 120 are formed, for example, at regular intervals. The dimension of the portion of the donor-containing layer 102 sandwiched between two adjacent openings 120 in the Y direction is, for example, 50 nm or more and 400 nm or less.

A dielectric layer 121 is formed to cover the nitride semiconductor laminated structure 110. The dielectric layer 121 also covers the bottom surface and the side wall surface of the opening 120. The dielectric layer 121 may cover the source electrode 1s and the drain electrode 1d. The dielectric layer 121 is, for example, a layer of Si nitride (SiN) having a thickness of about 5 nm to 100 nm. The thickness of the dielectric layer 121 referred to here is the thickness on the side wall surface of the opening 120. The thickness of the dielectric layer 121 on the upper surface of the electron supply layer 105 is equivalent to the thickness on the side wall surface of the opening 120.

A gate electrode 1g extending in the Y direction is formed on the dielectric layer 121. The gate electrode 1g is also formed in each opening 120. The gate electrode 1g is in contact with at least a part of the dielectric layer 121 in the opening 120. For example, the dielectric layer 121 has a first portion 121A parallel to the ZX plane in the side wall surface of the opening 120 and a second portion 121B parallel to the YZ plane in the side wall surface of the opening 120. The gate electrode 1g extending in the Y direction is in contact with at least a part of the first portion 121A. The gate electrode 1 g includes, for example, a Ni film having a thickness of 5 nm to 30 nm and an Au film having a thickness of 100 nm to 300 nm on the Ni film.

In the semiconductor device 100 according to the first embodiment, the donor-containing layer 102 is provided between the substrate 101 and the electron traveling layer 104. Current collapse occurs when electrons are captured somewhere in the electron traveling layer 104 and behave as a fixed charge. Due to the presence of the donor-containing layer 102 having a high density of donors, fixed charges are not generated or are immediately released even if they are captured, so that current collapse can be suppressed.

Further, the donor-containing layer 102 having a high donor density is in a state in which a leak current easily flows due to the presence of many freely moving electrons. Since the gate electrode 1g is also contained in the opening 120, when a voltage is applied to the gate electrode 1g, the potential on the semiconductor surface rises and the freely moving electrons are depleted, and the donor-containing layer 102 is depleted of electrons. The depletion layer, which is an area, spreads. Therefore, if the potential is further increased, the depletion layer expands and the leak path via the donor-containing layer 102 can be narrowed.

Therefore, according to the semiconductor device 100, it is possible to suppress the current collapse while suppressing the leak current. By suppressing the current collapse, the output and efficiency can be improved.

Next, a method for manufacturing the semiconductor device 100 according to the first embodiment will be described. 4 to 8 are plan views showing a manufacturing method of the semiconductor device 100 according to the first embodiment. 9 to 17 are cross-sectional views showing a method of manufacturing the semiconductor device 100 according to the first embodiment. 9 (a) to 13 (a) are cross-sectional views taken along the lines IXa-IXa to XIIIa-XIIIa in FIGS. 4 to 8, respectively. 9 (b) to 13 (b) are cross-sectional views taken along the lines IXb-IXb to XIIIb-XIIIb in FIGS. 4 to 8, respectively. 14 to 17 are cross-sectional views taken along the lines XIV-XIV to XVII-XVII in FIGS. 4 to 8, respectively.

First, as shown in FIGS. 4, 9 and 14, a nitride semiconductor laminated structure 110 is formed on the substrate 101. In the formation of the nitride semiconductor laminated structure 110, the donor-containing layer 102, the initial layer 103, the electron traveling layer 104, and the electron supply layer 105 are crystal-grown, for example, by a metal organic vapor phase epitaxy (MOVPE) method or the like. Epitaxially grow by the method. When forming the nitride semiconductor laminated structure 110 and growing the GaN layer, a mixed gas of trimethylgallium (TMGa) gas as a Ga source and ammonia (NH ₃ ) gas as an N source is used as a raw material gas. When the AlN layer is grown, a mixed gas of trimethylaluminum (TMAl) gas and _NH3 gas, which are Al sources, is used as a raw material gas. When the AlGaN layer is grown, a mixed gas of trimethylaluminum (TMAl) gas, TMGa gas, and _NH3 gas, which are Al sources, is used as the raw material gas. Depending on the composition of the nitride semiconductor layer to be grown, the presence or absence of supply of TMAl gas and TMGa gas and the flow rate are appropriately set. Hydrogen (H ₂ ) gas or nitrogen (N ₂ ) gas is used as the carrier gas. For example, the growth pressure is about 1 kPa to 100 kPa, and the growth temperature is about 700 ° C. to 1200 ° C. When growing the donor-containing layer 102, for example, silane (SiH ₄ ) gas, which is a Si source, is added to the mixed gas at a predetermined flow rate, and Si is doped into GaN. The doping concentration of Si is, for example, 1 × 10 ¹⁸ cm ^-3 or more and 1 × 10 ²⁰ cm ^-3 or less. Si may be contained in GaN from siloxane contained in the atmosphere. Si contained in the abrasive grains may be contained in GaN during chemical mechanical polishing (CMP) of the surface of the substrate 101 after the substrate 101 is cut out from the ingot.

Next, an element separation region that defines the element region is formed in the nitride semiconductor laminated structure 110. In the formation of the device separation region, for example, a photoresist pattern that exposes the region where the device separation region is to be formed is formed on the nitride semiconductor laminated structure 110, and ion implantation such as Ar is performed using this pattern as a mask. Reactive ion etching (RIE) using a chlorine-based gas may be performed using this pattern as an etching mask. After forming the device separation region, the photoresist pattern is removed using an organic solvent or the like. The photoresist pattern can be removed by immersing it in an organic solvent or the like.

Then, as shown in FIGS. 5, 10 and 15, a plurality of openings 120 which are intermittently arranged in the Y direction are formed. In the formation of the opening 120, for example, a photoresist pattern that exposes the region where the opening 120 is to be formed is formed on the nitride semiconductor laminated structure 110. Then, the nitride semiconductor laminated structure 110 is processed by performing dry etching such as RIE using a chlorine-based gas using this pattern as an etching mask. The opening 120 is preferably formed so that the interface between the donor-containing layer 102 and the substrate 101 is exposed, and for example, the substrate 101 is overetched. After forming the opening 120, the photoresist pattern is removed using an organic solvent or the like.

Subsequently, as shown in FIGS. 6 and 11, the source electrode 1s and the drain electrode 1d are formed on the nitride semiconductor laminated structure 110. The source electrode 1s and the drain electrode 1d can be formed by, for example, a lift-off method. That is, a photoresist pattern that exposes the region where the source electrode 1s and the drain electrode 1d are to be formed is formed, a metal film is formed by a vacuum vapor deposition method using this pattern as a growth mask, and this pattern is used as a metal film on the photoresist. Remove with. In the formation of the metal film, for example, a Ti film is formed and an Al film is formed on the Ti film. Then, for example, heat treatment is performed at 500 ° C. to 900 ° C. in a nitrogen atmosphere to establish ohmic contact.

Next, as shown in FIGS. 7, 12 and 16, a dielectric layer 121 is formed on the source electrode 1s, the drain electrode 1d, and the nitride semiconductor laminated structure 110. The dielectric layer 121 can be formed, for example, by a plasma chemical vapor deposition (CVD) method. The dielectric layer 121 is formed so as to cover the bottom surface and the side wall surface of the opening 120. The dielectric layer 121 has a first portion 121A parallel to the ZX plane in the side wall surface of the opening 120 and a second portion 121B parallel to the YZ plane in the side wall surface of the opening 120.

Then, as shown in FIGS. 8, 13 and 17, a gate electrode 1 g is formed on the dielectric layer 121. The gate electrode 1g can be formed by, for example, a lift-off method. That is, a pattern of a photoresist that exposes a region where the gate electrode 1 g is to be formed is formed, a metal film is formed by a vacuum vapor deposition method using this pattern as a growth mask, and this pattern is removed together with the metal film on the pattern. In the formation of the metal film, for example, a Ni film is formed and an Au film is formed on the Ni film. The gate electrode 1g is formed so as to be in contact with at least a part of the first portion 121A of the dielectric layer 121.

In this way, the semiconductor device 100 according to the first embodiment can be manufactured.

(Second Embodiment)
The second embodiment will be described. The second embodiment relates to a semiconductor device including a HEMT. FIG. 18 is a plan view showing the semiconductor device according to the second embodiment. 19 and 20 are cross-sectional views showing a semiconductor device according to the second embodiment. FIG. 19A is a cross-sectional view taken along the line XIXa-XIXa in FIG. FIG. 19B is a cross-sectional view taken along the line XIXb-XIXb in FIG. FIG. 20 is a cross-sectional view taken along the line XX-XX in FIG.

In the semiconductor device 200 according to the second embodiment, as shown in FIGS. 18 to 20, the nitride semiconductor laminated structure 110 extends in the X direction in place of the opening 120 in the semiconductor device 100 according to the first embodiment. The opening 220 is formed. The opening 220 extends from below the gate electrode 1g to below the source electrode 1s and below the drain electrode 1d. The opening 220 is formed so as to penetrate the electron supply layer 105, the electron traveling layer 104, the initial layer 103, and the donor-containing layer 102 in the Z direction and enter the substrate 101. The plurality of openings 220 are formed intermittently side by side in the Y direction. That is, the opening 220 is formed in a striped shape. The plurality of openings 220 are formed, for example, at regular intervals. The dimension of the portion of the donor-containing layer 102 sandwiched between two adjacent openings 220 in the Y direction is, for example, 50 nm or more and 400 nm or less. Other configurations are the same as in the first embodiment.

The same effect as that of the first embodiment can be obtained by the second embodiment.

Next, a method of manufacturing the semiconductor device 200 according to the second embodiment will be described. 21 to 24 are plan views showing a manufacturing method of the semiconductor device 200 according to the second embodiment. 25 to 28 are cross-sectional views showing a method of manufacturing the semiconductor device 200 according to the second embodiment. 25 (a) to 28 (a) are cross-sectional views taken along the lines IXa-XIa to XIIIa-XIIIa in FIGS. 21 to 24, respectively. 25 (b) to 28 (b) are cross-sectional views taken along the lines IXb-IXb to XIIIb-XIIIb in FIGS. 21 to 24, respectively.

First, in the same manner as in the first embodiment, the process up to the formation of the nitride semiconductor laminated structure 110 and the element separation region is performed (see FIGS. 4, 9 and 14). Then, as shown in FIGS. 21 and 25, a plurality of openings 220 extending in the X direction and intermittently arranged in the Y direction are formed. The opening 220 can be formed in the same manner as the opening 120.

After that, as shown in FIGS. 22 and 26, the source electrode 1s and the drain electrode 1d are formed on the nitride semiconductor laminated structure 110. Subsequently, as shown in FIGS. 23 and 27, the dielectric layer 121 is formed on the source electrode 1s, the drain electrode 1d, and the nitride semiconductor laminated structure 110. The dielectric layer 121 is formed so as to cover the bottom surface and the side wall surface of the opening 220. Next, as shown in FIGS. 24 and 28, a gate electrode 1 g is formed on the dielectric layer 121.

In this way, the semiconductor device 200 according to the second embodiment can be manufactured.

(Third Embodiment)
The third embodiment will be described. A third embodiment relates to a semiconductor device including a HEMT. FIG. 29 is a plan view showing the semiconductor device according to the third embodiment. 30 and 31 are cross-sectional views showing a semiconductor device according to the third embodiment. FIG. 30A is a cross-sectional view taken along the line XXXa-XXXa in FIG. 29. FIG. 30B is a cross-sectional view taken along the line XXXb-XXXb in FIG. 29. FIG. 31 is a cross-sectional view taken along the line XXXI-XXXI in FIG. 29.

In the semiconductor device 300 according to the third embodiment, as shown in FIGS. 29 to 31, the nitride semiconductor laminated structure 110 has a rectangular planar shape instead of the opening 120 in the semiconductor device 100 according to the first embodiment. In terms of shape, an opening 320 is formed in which the dimension in the X direction is smaller than the dimension in the X direction (gate length) of the gate electrode 1g. The opening 320 is located inside the contour of the gate electrode 1g in a plan view. The opening 320 is formed so as to penetrate the electron supply layer 105, the electron traveling layer 104, the initial layer 103, and the donor-containing layer 102 in the Z direction and enter the substrate 101. The plurality of openings 320 are formed intermittently side by side in the Y direction. That is, the opening 320 is formed in a dot shape. The plurality of openings 320 are formed, for example, at regular intervals. The dimension of the portion of the donor-containing layer 102 sandwiched between two adjacent openings 320 in the Y direction is, for example, 50 nm or more and 400 nm or less. Other configurations are the same as in the first embodiment.

The same effect as that of the first embodiment can be obtained by the third embodiment. Further, since the range of the opening 320 can be narrower than the range of the opening 120, a larger on-current can be passed.

Next, a method for manufacturing the semiconductor device 300 according to the third embodiment will be described. 32 to 35 are plan views showing a manufacturing method of the semiconductor device 300 according to the third embodiment. 36 to 39 are cross-sectional views showing a method of manufacturing the semiconductor device 300 according to the third embodiment. 36 (a) to 39 (a) are cross-sectional views taken along the lines XXXVIa-XXXVIa to XXXIXa-XXXIXa in FIGS. 32 to 35, respectively. 36 (b) to 39 (b) are cross-sectional views taken along the lines XXXVIb-XXXVIb to XXXIXb-XXXIXb in FIGS. 32 to 35, respectively.

First, in the same manner as in the first embodiment, the process up to the formation of the nitride semiconductor laminated structure 110 and the element separation region is performed (see FIGS. 4, 9 and 14). Next, as shown in FIGS. 32 and 36, a plurality of openings 320 having a rectangular planar shape and intermittently arranged in the Y direction are formed. The opening 320 can be formed in the same manner as the opening 120.

After that, as shown in FIGS. 33 and 37, the source electrode 1s and the drain electrode 1d are formed on the nitride semiconductor laminated structure 110. Subsequently, as shown in FIGS. 34 and 38, the dielectric layer 121 is formed on the source electrode 1s, the drain electrode 1d, and the nitride semiconductor laminated structure 110. The dielectric layer 121 is formed so as to cover the bottom surface and the side wall surface of the opening 220. Next, as shown in FIGS. 35 and 39, a gate electrode 1 g is formed on the dielectric layer 121.

In this way, the semiconductor device 300 according to the third embodiment can be manufactured.

(Fourth Embodiment)
The fourth embodiment will be described. A fourth embodiment relates to a semiconductor device including a HEMT. FIG. 40 is a plan view showing the semiconductor device according to the fourth embodiment. 41 and 42 are cross-sectional views showing the semiconductor device according to the fourth embodiment. FIG. 41 (a) is a cross-sectional view taken along the line XLIa-XLIa in FIG. 40. FIG. 41 (b) is a cross-sectional view taken along the line XLIb-XLIb in FIG. 40. FIG. 42 is a cross-sectional view taken along the line XLII-XLII in FIG. 40.

As shown in FIGS. 40 to 42, the semiconductor device 400 according to the fourth embodiment does not include the dielectric layer 121, and the gate electrode 1 g is in direct contact with the nitride semiconductor laminated structure 110. The gate electrode 1g is in direct contact with the electron supply layer 105, the electron traveling layer 104, the initial layer 103, and the donor-containing layer 102 on the side wall surface of the opening 120. Other configurations are the same as in the first embodiment.

The same effect as that of the first embodiment can be obtained by the fourth embodiment. Further, 1 g of the gate electrode is in Schottky contact with the nitride semiconductor laminated structure 110, so that more excellent gate controllability can be obtained and amplification performance at high frequencies can be improved.

In the manufacturing of the semiconductor device 400 according to the fourth embodiment, for example, in the manufacturing method of the semiconductor device 100, the formation of the dielectric layer 121 is omitted, and the gate electrode 1g is formed.

In the second embodiment and the third embodiment, as in the fourth embodiment, the gate electrode 1 g is in Schottky contact with the nitride semiconductor laminated structure 110 without forming the dielectric layer 121, and is brought into the donor-containing layer 102. It may be in direct contact.

In the present disclosure, the dimension of the portion sandwiched between two adjacent openings of the donor-containing layer is preferably 50 nm or more. If this dimension is less than 50 nm, the current path between the source electrode and the drain electrode is narrow in the electron traveling layer above the donor-containing layer, and the electric resistance may increase. This dimension is more preferably 100 nm or more. Further, this dimension is preferably 400 nm or less. If this dimension exceeds 400 nm, a region in which the depletion layer is not formed remains widely in the donor-containing layer when a voltage is applied to the gate electrode, and the leakage current may increase. This dimension is more preferably 300 nm or less.

(Fifth Embodiment)
Next, the fifth embodiment will be described. A fifth embodiment relates to a discrete package of HEMTs. FIG. 43 is a diagram showing a discrete package according to the fifth embodiment.

In the fifth embodiment, as shown in FIG. 43, the back surface of the semiconductor device 1210 having the same structure as that of any one of the first to fourth embodiments is a land (die pad) 1233 using a die attachant 1234 such as solder. It is fixed to. Further, a wire 1235d such as an Al wire is connected to the drain pad 1226d to which the drain electrode 1d is connected, and the other end of the wire 1235d is connected to the drain lead 1232d integrated with the land 1233. A wire 1235s such as an Al wire is connected to the source pad 1226s connected to the source electrode 1s, and the other end of the wire 1235s is connected to a source lead 1232s independent of the land 1233. A wire 1235 g such as an Al wire is connected to a gate pad 1226 g connected to the gate electrode 1 g, and the other end of the wire 1235 g is connected to a gate lead 1232 g independent of the land 1233. The land 1233, the semiconductor device 1210, and the like are packaged with the mold resin 1231 so that a part of the gate lead 1232g, a part of the drain lead 1232d, and a part of the source lead 1232s project.

Such a discrete package can be manufactured, for example, as follows. First, the semiconductor device 1210 is fixed to the land 1233 of the lead frame using a die attachant 1234 such as solder. The gate pad 1226g is then connected to the lead frame gate lead 1232g, the drain pad 1226d is connected to the lead frame drain lead 1232d, and the source pad 1226s is the lead frame source by bonding with wires 1235g, 1235d and 1235s. Connect to the lead 1232s. After that, sealing is performed using the mold resin 1231 by the transfer molding method. Then, the lead frame is separated.

(Sixth Embodiment)
Next, the sixth embodiment will be described. A sixth embodiment relates to a PFC (Power Factor Correction) circuit including HEMT. FIG. 44 is a wiring diagram showing the PFC circuit according to the sixth embodiment.

The PFC circuit 1250 is provided with a switch element (transistor) 1251, a diode 1252, a choke coil 1253, capacitors 1254 and 1255, a diode bridge 1256, and an alternating current power supply (AC) 1257. Then, the drain electrode of the switch element 1251 and the anode terminal of the diode 1252 and one terminal of the choke coil 1253 are connected. The source electrode of the switch element 1251 is connected to one terminal of the capacitor 1254 and one terminal of the capacitor 1255. The other terminal of the capacitor 1254 and the other terminal of the choke coil 1253 are connected. The other terminal of the capacitor 1255 and the cathode terminal of the diode 1252 are connected. Further, a gate driver is connected to the gate electrode of the switch element 1251. AC1257 is connected between both terminals of the capacitor 1254 via a diode bridge 1256. A direct current (DC) is connected between both terminals of the capacitor 1255. In the present embodiment, the switch element 1251 uses a semiconductor device having the same structure as that of any of the first to fourth embodiments.

In manufacturing the PFC circuit 1250, for example, the switch element 1251 is connected to the diode 1252, the choke coil 1253, etc. by using solder or the like.

(7th Embodiment)
Next, the seventh embodiment will be described. A seventh embodiment relates to a power supply device including a HEMT, which is suitable for a server power supply. FIG. 45 is a wiring diagram showing a power supply device according to the seventh embodiment.

The power supply device is provided with a high voltage primary side circuit 1261 and a low voltage secondary side circuit 1262, and a transformer 1263 disposed between the primary side circuit 1261 and the secondary side circuit 1262.

The primary side circuit 1261 is provided with an inverter circuit connected between both terminals of the PFC circuit 1250 according to the sixth embodiment and the capacitor 1255 of the PFC circuit 1250, for example, a full bridge inverter circuit 1260. The full-bridge inverter circuit 1260 is provided with a plurality of (four in this case) switch elements 1264a, 1264b, 1264c, and 1264d.

The secondary circuit 1262 is provided with a plurality of (three in this case) switch elements 1265a, 1265b, and 1265c.

In the present embodiment, the switch element 1251 of the PFC circuit 1250 constituting the primary side circuit 1261 and the switch elements 1264a, 1264b, 1264c and 1264d of the full bridge inverter circuit 1260 are the same as those of the first to fourth embodiments. A semiconductor device having a structure is used. On the other hand, ordinary MIS type FETs (field effect transistors) using silicon are used for the switch elements 1265a, 1265b and 1265c of the secondary circuit 1262.

(8th Embodiment)
Next, the eighth embodiment will be described. Eighth embodiment relates to an amplifier including a HEMT. FIG. 46 is a wiring diagram showing the amplifier according to the eighth embodiment.

The amplifier is provided with a digital predistortion circuit 1271, mixers 1272a and 1272b, and a power amplifier 1273.

The digital predistortion circuit 1271 compensates for the non-linear distortion of the input signal. The mixer 1272a mixes the input signal compensated for the non-linear distortion and the AC signal. The power amplifier 1273 includes a semiconductor device having a structure similar to that of any one of the first to fourth embodiments, and amplifies an AC signal and a mixed input signal. In the present embodiment, for example, the output side signal can be mixed with the AC signal by the mixer 1272b and sent to the digital predistortion circuit 1271 by switching the switch. This amplifier can be used as a high frequency amplifier and a high output amplifier. The high frequency amplifier can be used, for example, in a transmitter / receiver for a mobile phone base station, a radar device, and a microwave generator.

In the present disclosure, a silicon carbide (SiC) substrate, a sapphire substrate, a silicon substrate, an AlN substrate, a GaN substrate, or a diamond substrate may be used as the substrate. The substrate may be conductive, semi-insulating or insulating. If the electronic traveling layer can be formed on the substrate, the substrate may be used as a base.

The structures of the gate electrode, the source electrode and the drain electrode are not limited to those of the above-described embodiment. For example, these may be composed of a single layer. Further, these forming methods are not limited to the lift-off method. Further, if ohmic characteristics can be obtained, the heat treatment after the formation of the source electrode and the drain electrode may be omitted. Heat treatment may be performed after the formation of the gate electrode.

In the present disclosure, the composition of the semiconductor layer is not limited to that described in the above embodiment. For example, other nitride semiconductors such as InAlN and InGaAlN may be used. When the semiconductor layer containing In is grown, a mixed gas containing trimethylindium (TMIn) gas and _NH3 gas is used as a raw material gas. This raw material gas may further contain TMAl gas, may further contain TMGa gas, and may further contain TMAl gas and TMGa gas.

Although the preferred embodiments and the like have been described in detail above, they are not limited to the above-described embodiments and the like, and various embodiments and the like described above can be applied without departing from the scope of the claims. Modifications and substitutions can be added.

Hereinafter, various aspects of the present disclosure will be described together as an appendix.

(Appendix 1)
With the board
A semiconductor laminated structure of a nitride semiconductor provided above the substrate,
A source electrode, a gate electrode, and a drain electrode provided above the semiconductor laminated structure, and
Have,
The semiconductor laminated structure is
A donor-containing layer provided above the substrate and
An electron traveling layer provided above the donor-containing layer and
An electron supply layer provided above the electron traveling layer and
Have,
An opening is formed in the electron supply layer, the electron traveling layer, and the donor-containing layer.
A semiconductor device characterized in that the gate electrode is also provided in the opening.
(Appendix 2)
The semiconductor device according to Appendix 1, wherein the donor-containing layer contains Si or Ge or any combination thereof.
(Appendix 3)
The semiconductor device according to Appendix 1 or 2, wherein the density of donors in the donor-containing layer is 1 × 10 ¹⁸ cm ^-3 or more and 1 × 10 ²⁰ cm ^-3 or less.
(Appendix 4)
The gate electrode extends in a first direction perpendicular to the thickness direction of the substrate.
The semiconductor device according to any one of Supplementary note 1 to 3, wherein the openings are formed in a plurality of intermittently in the first direction.
(Appendix 5)
The semiconductor device according to Appendix 4, wherein the dimension of the portion sandwiched between the openings adjacent to the donor-containing layer in the first direction is 50 nm or more and 400 nm or less.
(Appendix 6)
The semiconductor device according to any one of Supplementary note 1 to 5, further comprising a dielectric layer provided between the gate electrode and the donor-containing layer in the opening.
(Appendix 7)
The semiconductor device according to Appendix 6, wherein the thickness of the portion sandwiched between the gate electrode and the donor-containing layer in the opening of the dielectric layer is 50 nm or less.
(Appendix 8)
The semiconductor device according to any one of Supplementary note 1 to 7, wherein the gate electrode in the opening is in direct contact with the donor-containing layer.
(Appendix 9)
The semiconductor device according to any one of Supplementary note 1 to 8, wherein the opening is located inside the contour of the gate electrode in a plan view.
(Appendix 10)
An amplifier comprising the semiconductor device according to any one of Supplementary note 1 to 9.
(Appendix 11)
A power supply device comprising the semiconductor device according to any one of Supplementary note 1 to 9.

1s: Source electrode 1d: Drain electrode 1g: Gate electrode 100, 200: Semiconductor device 101: Substrate 102: Donor-containing layer 103: Initial layer 104: Electron traveling layer 105: Electron supply layer 110: Nitride semiconductor laminated structure 120, 220 , 320: Opening 121: Dielectric layer

Claims (7)

With the board
A semiconductor laminated structure of a nitride semiconductor provided above the substrate,
A source electrode, a gate electrode, and a drain electrode provided above the semiconductor laminated structure, and
Have,
The semiconductor laminated structure is
A donor-containing layer provided above the substrate and
An electron traveling layer provided above the donor-containing layer and
An electron supply layer provided above the electron traveling layer and
Have,
An opening is formed in the electron supply layer, the electron traveling layer, and the donor-containing layer.
A semiconductor device characterized in that the gate electrode is also provided in the opening. The semiconductor device according to claim 1, wherein the donor-containing layer contains Si or Ge or any combination thereof. The semiconductor device according to claim 1 or 2, wherein the density of donors in the donor-containing layer is 1 × 10 ¹⁸ cm ^-3 or more and 1 × 10 ²⁰ cm ^-3 or less. The gate electrode extends in a first direction perpendicular to the thickness direction of the substrate.
The semiconductor device according to any one of claims 1 to 3, wherein the openings are formed in a plurality of intermittently in the first direction. The semiconductor device according to claim 4, wherein the dimension of the portion sandwiched between the openings adjacent to the donor-containing layer in the first direction is 50 nm or more and 400 nm or less. The semiconductor device according to any one of claims 1 to 5, further comprising a dielectric layer provided between the gate electrode and the donor-containing layer in the opening. The semiconductor device according to any one of claims 1 to 6, wherein the gate electrode in the opening is in direct contact with the donor-containing layer.

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