JP2022019449A - Inspection method for array substrate, display device, and inspection jig - Google Patents

Abstract

To provide an inspection method for an array substrate by which the characteristics of an array substrate on which a light-emitting element is not mounted yet can be inspected properly, a display device, and an inspection jig.SOLUTION: An inspection method for an array substrate includes the steps of: preparing an array substrate on which a plurality of light-emitting elements are not mounted yet; by using an inspection jig including a first connection terminal, a second connection terminal, and an inspection capacitor provided between the first connection terminal and the second connection terminal, connecting the first connection terminal on a mount electrode and connecting the second connection terminal to a pixel cathode electrode; and supplying an inspection signal to the transistor on the basis of a control signal from an inspection control circuit that controls the inspection of the array substrate and detecting an output signal output from the transistor in accordance with the inspection signal.SELECTED DRAWING: Figure 11

Description

The present invention relates to an array substrate inspection method, a display device, and an inspection jig.

A display device using a minute-sized light emitting diode (micro LED) as a display element is attracting attention (see, for example, Patent Documents 1 and 2). A display device using a light emitting diode is difficult to manufacture due to the small size of the light emitting diode, such as mounting the light emitting diode on a substrate, and tends to cause a defect of the light emitting diode. Patent Document 1 describes a method for inspecting a plurality of LEDs formed on a sapphire substrate. Further, Patent Document 2 describes an inspection method for detecting the threshold voltage of a pixel in real time.

Japanese Unexamined Patent Publication No. 2019-78685 U.S. Patent Application Publication No. 2017/0103702

When inspecting after mounting a plurality of light emitting elements on an array board, if a defect is found in the circuit or wiring of the array board, a large number of already mounted light emitting elements may be discarded. Patent Documents 1 and 2 do not describe a method for inspecting the electrical characteristics of an array substrate on which a light emitting element is not mounted.

An object of the present invention is to provide an array substrate inspection method, a display device, and an inspection jig capable of satisfactorily inspecting the electrical characteristics of an array substrate on which a light emitting element is not mounted.

The method for inspecting an array substrate according to one aspect of the present invention is a method for inspecting an array substrate on which a plurality of light emitting elements are mounted, wherein the array substrate includes a plurality of transistors provided corresponding to a plurality of pixels and a plurality of transistors. It has a plurality of mounting electrodes electrically connected to the transistor and on which the light emitting element is mounted, and a pixel cathode electrode provided adjacent to the plurality of mounting electrodes and electrically connected to a reference potential. A step of preparing the array substrate on which the plurality of light emitting elements are not mounted is provided between the first connection terminal, the second connection terminal, the first connection terminal, and the second connection terminal. An inspection that controls the inspection of the array substrate and the step of connecting the first connection terminal to the mounting electrode and the second connection terminal to the pixel cathode electrode using an inspection jig including an inspection capacitance. A step of supplying an inspection signal to the transistor based on a control signal from the control circuit and detecting an output signal output from the transistor in response to the inspection signal.

The display device of one aspect of the present invention includes an array board, a plurality of light emitting elements mounted on the array board, and a drive IC mounted on the array board and supplying a video signal to the plurality of light emitting elements. The drive IC has correction data for each pixel acquired from the array substrate on which the plurality of light emitting elements are not mounted, and the corrected video signal based on the correction data is added to the video signal supplied from the outside. Is supplied to the light emitting element.

The inspection jig according to one aspect of the present invention is an inspection jig for inspecting an array substrate on which a light emitting element is not mounted, and includes a first connection terminal, a second connection terminal, and the first connection terminal. A first electrode in contact with the connection terminal and a second electrode in contact with the second connection terminal are provided, and the first electrode and the second electrode face each other with a dielectric layer interposed therebetween. It has an opening at a position where it does not overlap with the first electrode, and the second electrode and the second connection terminal come into contact with each other at the opening.

FIG. 1 is a plan view schematically showing a display device according to an embodiment. FIG. 2 is a plan view showing a plurality of pixels. FIG. 3 is a circuit diagram showing a pixel circuit. FIG. 4 is a cross-sectional view taken along the line IV-IV'of FIG. FIG. 5 is a plan view showing an example of a connection configuration of a plurality of pixel cathode electrodes. FIG. 6 is a cross-sectional view taken along the line VI-VI'of FIG. FIG. 7 is a block diagram showing a configuration example of an inspection system for a display device according to an embodiment. FIG. 8 is a cross-sectional view schematically showing the inspection jig. FIG. 9 is a plan view schematically showing the inspection jig. FIG. 10 is a circuit diagram for explaining an inspection method of an array substrate. FIG. 11 is a flowchart for explaining an inspection method of an array substrate according to an embodiment. FIG. 12 is an explanatory diagram illustrating an example of a method of selecting a light emitting element suitable for a pixel. FIG. 13 is a block diagram for explaining a lighting inspection of the light emitting element.

An embodiment (embodiment) for carrying out the present invention will be described in detail with reference to the drawings. The disclosure is not limited by the content described in the following embodiments. In addition, the components described below include those that can be easily assumed by those skilled in the art and those that are substantially the same. Furthermore, the components described below can be combined as appropriate. It should be noted that the disclosure is merely an example, and those skilled in the art can easily conceive of appropriate changes while maintaining the gist of the present disclosure are naturally included in the scope of the present disclosure. In addition, in order to clarify the explanation, the drawings may schematically represent the width, thickness, shape, etc. of each part as compared with the actual embodiment, but this is just an example, and the interpretation of the present disclosure is used. It is not limited. Further, in the present disclosure and each figure, the same elements as those described above with respect to the above-mentioned figures may be designated by the same reference numerals, and detailed description thereof may be omitted as appropriate.

In the present specification and the scope of patent claims, when expressing an aspect of arranging another structure on one structure, when the term "above" is simply used, the structure shall be used unless otherwise specified. It includes both the case where another structure is placed directly above the structure so as to be in contact with each other and the case where another structure is placed above one structure via another structure.

FIG. 1 is a plan view schematically showing a display device according to an embodiment. As shown in FIG. 1, the display device 1 includes an array substrate 2, a pixel Pix, a drive circuit 12, a drive IC (Integrated Circuit) 210, and a cathode wiring 60. The array board 2 is a drive circuit board for driving each pixel Pix, and is also called a backplane or an active matrix board. The array substrate 2 has a substrate 21, a plurality of transistors, a plurality of capacitances, various wirings, and the like.

As shown in FIG. 1, the display device 1 has a display area AA and a peripheral area GA. The display area AA is an area that is arranged so as to overlap with the plurality of pixels Pix and displays an image. The peripheral region GA is an region that does not overlap with the plurality of pixels Pix, and is arranged outside the display region AA.

The plurality of pixels Pix are arranged in the first direction Dx and the second direction Dy in the display area AA of the substrate 21. The first direction Dx and the second direction Dy are directions parallel to the surface of the substrate 21. The first direction Dx is orthogonal to the second direction Dy. However, the first direction Dx may intersect with the second direction Dy without being orthogonal to each other. The third direction Dz is a direction orthogonal to the first direction Dx and the second direction Dy. The third direction Dz corresponds to, for example, the normal direction of the substrate 21. In the following, the plan view indicates the positional relationship when viewed from the third direction Dz.

The drive circuit 12 has a plurality of gate lines (for example, a reset control signal line L5, an output control signal line L6, a pixel control signal line L7, and an initialization control signal line L8 (see FIG. 3) based on various control signals from the drive IC 210. )) Is a circuit that drives. The drive circuit 12 sequentially or simultaneously selects a plurality of gate lines and supplies a gate drive signal to the selected gate lines. As a result, the drive circuit 12 selects a plurality of pixels Pix connected to the gate line.

The drive IC 210 is a circuit that controls the display of the display device 1. The drive IC 210 is mounted as a COG (Chip On Glass) in the peripheral region GA of the substrate 21. Not limited to this, the drive IC 210 may be mounted as a COF (Chip On Film) on a flexible printed circuit board or a rigid board connected to the peripheral region GA of the board 21.

The cathode wiring 60 is provided in the peripheral region GA of the substrate 21. The cathode wiring 60 is provided so as to surround the plurality of pixels Pix in the display area AA and the drive circuit 12 in the peripheral area GA. The cathodes of the plurality of light emitting elements 3 are connected to a common cathode wiring 60, and a reference potential (for example, a ground potential) is supplied. More specifically, the cathode terminal 32 (see FIG. 4) of the light emitting element 3 is connected to the cathode wiring 60 via the cathode electrode 22.

FIG. 2 is a plan view showing a plurality of pixels. As shown in FIG. 2, one pixel Pix includes a plurality of pixels 49. For example, the pixel Pix has a pixel 49R, a pixel 49G, and a pixel 49B. The pixel 49R displays the primary color red as the first color. The pixel 49G displays the primary color green as the second color. Pixel 49B displays the primary color blue as the third color. As shown in FIG. 2, in one pixel Pix, the pixels 49R and the pixels 49G are arranged in the second direction Dy. Further, the pixels 49R and the pixels 49B are arranged in the first direction Dx. The first color, the second color, and the third color are not limited to red, green, and blue, respectively, and any color such as a complementary color can be selected. In the following, when it is not necessary to distinguish between the pixel 49R, the pixel 49G, and the pixel 49B, it is simply referred to as the pixel 49.

Each of the pixels 49 has a light emitting element 3 and a mounting electrode 24. The display device 1 displays an image by emitting different light for each of the light emitting elements 3R, 3G, and 3B in the pixels 49R, the pixels 49G, and the pixels 49B. The light emitting element 3 is an inorganic light emitting diode (LED) chip having a size of about 3 μm or more and about 300 μm or less in a plan view, and is called a micro LED. The display device 1 provided with a micro LED in each pixel is also referred to as a micro LED display device. The micro of the micro LED does not limit the size of the light emitting element 3.

The plurality of light emitting elements 3 may emit four or more different colors of light. Further, the arrangement of the plurality of pixels 49 is not limited to the configuration shown in FIG. For example, the pixel 49R may be adjacent to the pixel 49B in the second direction Dy. Further, the pixels 49R, the pixels 49G and the pixels 49B may be repeatedly arranged in the first direction Dx in this order.

The pixel Pix further includes a pixel cathode electrode 24S. The pixel cathode electrode 24S is provided adjacent to the plurality of mounting electrodes 24 and is provided for each pixel Pix. The pixel cathode electrode 24S is connected to a reference potential (for example, a ground potential). More specifically, the pixel cathode electrode 24S is electrically connected to the cathode terminal 32 (see FIG. 4) of the light emitting element 3 via the cathode electrode 22 (see FIG. 4). The pixel cathode electrode 24S is aligned with the mounting electrode 24G of the pixel 49G in the first direction Dx. The pixel cathode electrode 24S is aligned with the mounting electrode 24B of the pixel 49B in the second direction Dy. The pixel cathode electrode 24S is aligned with the mounting electrode 24R of the pixel 49R in an oblique direction intersecting the first direction Dx and the second direction Dy.

FIG. 3 is a circuit diagram showing a pixel circuit. FIG. 3 shows a pixel circuit PICA provided in one pixel 49, and the pixel circuit PICA is provided in each of a plurality of pixels 49. As shown in FIG. 3, the pixel circuit PICA includes a light emitting element 3, five transistors, and two capacitances. Specifically, the pixel circuit PICA includes a drive transistor DRT, an output transistor BCT, an initialization transistor IST, a pixel selection transistor SST, and a reset transistor RST. The drive transistor DRT, output transistor BCT, initialization transistor IST, pixel selection transistor SST, and reset transistor RST are each composed of an n-type TFT (Thin Film Transistor). Further, the pixel circuit PICA includes a first capacitance Cs1 and a second capacitance Cs2.

The cathode (cathode terminal 32) of the light emitting element 3 is connected to the cathode power supply line L10. Further, the anode (anode terminal 33) of the light emitting element 3 is connected to the anode power supply line L1 via the drive transistor DRT and the output transistor BCT. The anode power supply potential P VDD is supplied to the anode power supply line L1. The cathode power supply potential PVSS is supplied to the cathode power supply line L10 via the cathode wiring 60 and the cathode electrode 22. The anode power supply potential Pldap has a higher potential than the cathode power supply potential PVSS.

The anode power supply line L1 supplies the pixel 49 with the anode power supply potential P VDD, which is a driving potential. Specifically, the light emitting element 3 is ideally supplied with a forward current (driving current) by a potential difference (P VDD-PVSS) between the anode power supply potential P whether and the cathode power supply potential PVSS to emit light. That is, the anode power supply potential P VDD has a potential difference that causes the light emitting element 3 to emit light with respect to the cathode power supply potential PVSS. The anode terminal 33 of the light emitting element 3 is electrically connected to the anode electrode 23, and the second capacitance Cs2 is connected as an equivalent circuit between the anode electrode 23 and the anode power supply line L1.

The source electrode of the drive transistor DRT is connected to the anode terminal 33 of the light emitting element 3 via the anode electrode 23, and the drain electrode is connected to the source electrode of the output transistor BCT. The gate electrode of the drive transistor DRT is connected to the first capacitance Cs1, the drain electrode of the pixel selection transistor SST, and the drain electrode of the initialization transistor IST. The drive transistor DRT supplies a forward current (drive current) based on the potential difference (P VDD-PVSS) to the light emitting element 3.

The gate electrode of the output transistor BCT is connected to the output control signal line L6. The output control signal BG is supplied to the output control signal line L6. The drain electrode of the output transistor BCT is connected to the anode power supply line L1.

The source electrode of the initialization transistor IST is connected to the initialization power line L4. The initialization potential Vini is supplied to the initialization power line L4. The gate electrode of the initialization transistor IST is connected to the initialization control signal line L8. The initialization control signal IG is supplied to the initialization control signal line L8. That is, the initialization power supply line L4 is connected to the gate electrode of the drive transistor DRT via the initialization transistor IST.

The source electrode of the pixel selection transistor SST is connected to the video signal line L2. The video signal Vsig is supplied to the video signal line L2. A pixel control signal line L7 is connected to the gate electrode of the pixel selection transistor SST. The pixel control signal SG is supplied to the pixel control signal line L7.

The source electrode of the reset transistor RST is connected to the reset power line L3. The reset power supply potential Vrst is supplied to the reset power supply line L3. The gate electrode of the reset transistor RST is connected to the reset control signal line L5. A reset control signal RG is supplied to the reset control signal line L5. The drain electrode of the reset transistor RST is connected to the anode electrode 23 (anode terminal 33 of the light emitting element 3) and the source electrode of the drive transistor DRT. By the reset operation of the reset transistor RST, the voltage held in the first capacitance Cs1 and the second capacitance Cs2 is reset. In other words, the reset transistor RST supplies the reset power supply potential Vrst to the light emitting element 3.

A first capacitance Cs1 is provided as an equivalent circuit between the drain electrode of the reset transistor RST and the gate electrode of the drive transistor DRT. The pixel circuit PICA can suppress the fluctuation of the gate voltage due to the parasitic capacitance of the drive transistor DRT and the leakage current by the first capacitance Cs1 and the second capacitance Cs2.

In the following description, the anode power supply line L1 and the cathode power supply line L10 may be simply referred to as power supply lines. The video signal line L2, the reset power line L3, and the initialization power line L4 may be referred to as signal lines. The reset control signal line L5, the output control signal line L6, the pixel control signal line L7, and the initialization control signal line L8 may be referred to as a gate line.

A potential corresponding to the video signal Vsig (or gradation signal) is supplied to the gate electrode of the drive transistor DRT. That is, the drive transistor DRT supplies a current corresponding to the video signal Vsig to the light emitting element 3 based on the anode power supply potential P VDD supplied via the output transistor BCT. In this way, the anode power supply potential P VDD supplied to the anode power supply line L1 drops by the drive transistor DRT and the output transistor BCT, so that a potential lower than the anode power supply potential P VDD is supplied to the anode terminal 33 of the light emitting element 3. Will be done.

The anode power supply potential P VDD is supplied to one electrode of the second capacitance Cs2 via the anode power supply line L1, and a potential lower than the anode power supply potential P VDD is supplied to the other electrode of the second capacitance Cs2. That is, one electrode of the second capacitance Cs2 is supplied with a higher potential than the other electrode of the second capacitance Cs2. One electrode of the second capacitance Cs2 is, for example, the counter electrode 26 connected to the anode power supply line L1 shown in FIG. 4, and the other electrode of the second capacitance Cs2 is the source of the drive transistor DRT shown in FIG. The connected anode electrode 23.

In the display device 1, the drive circuit 12 (see FIG. 1) selects a plurality of pixel rows in order from the first row (for example, the pixel row located at the top in the display area AA in FIG. 1). The drive IC 210 writes a video signal Vsig (video writing potential) to the pixels 49 of the selected pixel row, and causes the light emitting element 3 to emit light. The drive IC 210 supplies the video signal Vsig to the video signal line L2, supplies the reset power supply potential Vrst to the reset power supply line L3, and supplies the initialization potential Vini to the initialization power supply line L4 every one horizontal scanning period. The display device 1 repeats these operations for each frame of the image.

Next, the cross-sectional configuration of the display device 1 will be described. FIG. 4 is a cross-sectional view taken along the line IV-IV'of FIG. As shown in FIG. 4, the light emitting element 3 is provided on the array substrate 2. The array substrate 2 has a substrate 21, various transistors, various wirings, and various insulating films. The substrate 21 is an insulating substrate, and for example, a glass substrate, a resin substrate, a resin film, or the like is used.

In the present specification, the direction from the substrate 21 toward the light emitting element 3 in the direction perpendicular to the surface of the substrate 21 is referred to as "upper side" or simply "upper side". Further, the direction from the light emitting element 3 toward the substrate 21 is defined as "lower side" or simply "lower side".

The drive transistor DRT and the output transistor BCT are provided on one surface side of the substrate 21. The semiconductor layers 61 and 65 are provided on the substrate 21. An undercoat film may be provided between the semiconductor layers 61 and 65 and the substrate 21. The insulating film 91 is provided on the substrate 21 so as to cover the semiconductor layers 61 and 65. The insulating film 91 is, for example, a silicon oxide film.

The gate electrodes 64 and 66 are provided on the insulating film 91. In the example shown in FIG. 4, each transistor has a so-called top gate structure. However, each transistor may have a bottom gate structure in which a gate electrode is provided on the lower side of the semiconductor layer, or a dual gate structure in which gate electrodes are provided on both the upper side and the lower side of the semiconductor layer.

The insulating film 92 is provided on the insulating film 91 so as to cover the gate electrodes 64 and 66. The insulating film 92 has, for example, a laminated structure of a silicon nitride film and a silicon oxide film. The source electrode 62, the drain electrode 67, and the anode power supply line L1 are provided on the insulating film 92. The source electrode 62 is electrically connected to the semiconductor layer 61 via a contact hole penetrating the insulating films 91 and 92. Further, the drain electrode 67 is electrically connected to the semiconductor layer 65 via the contact holes provided in the insulating films 91 and 92.

A plurality of insulating films (first organic insulating film 93, insulating film 94, insulating film 95, and second organic insulating film 96) are provided so as to cover each transistor. As the first organic insulating film 93 and the second organic insulating film 96, an organic material such as photosensitive acrylic is used. Organic materials such as photosensitive acrylic are superior in coverage of wiring steps and surface flatness as compared with inorganic insulating materials formed by CVD or the like. The insulating film 94 and the insulating film 95 are inorganic insulating films, and the same materials as the above-mentioned insulating films 91 and 92, for example, a silicon nitride film, can be used.

Specifically, the first organic insulating film 93 is provided on the insulating film 92 so as to cover the source electrode 62, the drain electrode 67, and the anode power supply line L1. The counter electrode 26, the insulating film 94, and the anode electrode 23 are laminated in this order on the first organic insulating film 93. The counter electrode 26 is made of a translucent conductive material such as ITO (Indium Tin Oxide). The counter electrode 26 is connected to the anode power supply line L1 at the bottom of the contact hole CH1 provided in the first organic insulating film 93.

The insulating film 94 is provided so as to cover the counter electrode 26. The anode electrode 23 faces the counter electrode 26 via the insulating film 94. The first organic insulating film 93 and the insulating film 94 are provided with contact holes CH2 and CH3 having a source electrode 62 as a bottom surface. The anode electrode 23 is electrically connected to the source electrode 62 via the contact holes CH2 and CH3. As a result, the anode electrode 23 is electrically connected to the drive transistor DRT.

The anode electrode 23 has, for example, a laminated structure of titanium (Ti) and aluminum (Al). However, the present invention is not limited to this, and the anode electrode 23 may be a material containing any one or more of molybdenum and titanium metals. Alternatively, the anode electrode 23 may be an alloy containing any one or more of molybdenum and titanium, or a translucent conductive material. Further, the second capacitance Cs2 is formed between the anode electrode 23 and the facing electrode 26 facing each other via the insulating film 94.

The insulating film 95 is provided on the insulating film 94 so as to cover the anode electrode 23. The second organic insulating film 96 is provided on the insulating film 95. That is, the first organic insulating film 93 is provided on the drive transistor DRT, and the second organic insulating film 96 is laminated on the upper side of the first organic insulating film 93. The insulating film 95 is provided between the first organic insulating film 93 and the second organic insulating film 96. The second organic insulating film 96 is provided with a contact hole CH4. The insulating film 95 is provided with the contact hole CH5 so as to overlap with the contact hole CH4. An anode electrode 23 is provided at the bottom of the contact holes CH4 and CH5. Further, the anode electrode 23 is provided so as to face at least a part of the mounting electrode 24.

The mounting electrode 24 is provided on the second organic insulating film 96 and is electrically connected to the anode electrode 23 via the contact holes CH4 and CH5. That is, the mounting electrode 24 is an electrode that is electrically connected to the drive transistor DRT via the anode electrode 23 and on which the light emitting element 3 is mounted. Like the anode electrode 23, the mounting electrode 24 has a laminated structure of titanium and aluminum. However, the mounting electrode 24 may use a conductive material different from that of the anode electrode 23. Further, as the second organic insulating film 96, an organic material different from that of the first organic insulating film 93 may be used.

The light emitting elements 3R, 3G, and 3B are mounted on the corresponding mounting electrodes 24R, 24G, and 24B, respectively. Each light emitting element 3 is mounted so that the anode terminal 33 is in contact with the mounting electrode 24. The bonding member 25 between the anode terminal 33 and the mounting electrode 24 of each light emitting element 3 is not particularly limited as long as good conduction can be ensured between them and the formation on the array substrate 2 is not damaged. .. The joining member 25 is, for example, solder or a conductive paste. Examples of the bonding between the anode terminal 33 and the mounting electrode 24 include a reflow process using a solder material that is melted at a low temperature, and a method in which the light emitting element 3 is placed on the array substrate 2 via a conductive paste and then fired and bonded.

Here, it is also possible to mount the light emitting element 3 directly on the anode electrode 23 without providing the second organic insulating film 96 and the mounting electrode 24 on the array substrate 2. However, by providing the second organic insulating film 96 and the mounting electrode 24, it is possible to prevent the insulating film 94 from being damaged by the force applied when the light emitting element 3 is mounted. That is, it is possible to suppress the occurrence of dielectric breakdown between the anode electrode 23 forming the second capacitance Cs2 and the counter electrode 26.

The light emitting element 3 is a face-up type light emitting element, and the lower part of the light emitting element 3 is connected to the anode electrode 23, and the upper part of the light emitting element 3 is connected to the cathode electrode 22. The light emitting device 3 has a semiconductor layer 31, a cathode terminal 32, and an anode terminal 33. As the semiconductor layer 31, a configuration in which an n-type clad layer 37, an active layer 36, and a p-type clad layer 35 (see FIG. 6) are laminated can be adopted. As the semiconductor layer 31, for example, a compound semiconductor such as gallium nitride (GaN), aluminum indium phosphide (AlInP), or indium gallium nitride (InGaN) is used. For the semiconductor layer 31, different materials may be used for each of the light emitting elements 3R, 3G, and 3B. Further, as the active layer, a multiple quantum well structure (MQW structure) in which a well layer composed of several atomic layers and a barrier layer are periodically laminated may be adopted for high efficiency. Further, the light emitting element 3 may have a configuration in which the semiconductor layer 31 is formed on the semiconductor substrate.

An element insulating film 97 is provided between the plurality of light emitting elements 3. The element insulating film 97 is made of a resin material. The element insulating film 97 covers the side surface of the light emitting element 3, and the cathode terminal 32 of the light emitting element 3 is exposed from the element insulating film 97. The element insulating film 97 is formed flat so that the upper surface of the element insulating film 97 and the upper surface of the cathode terminal 32 form the same surface. However, the position of the upper surface of the element insulating film 97 may be different from the position of the upper surface of the cathode terminal 32.

The cathode electrode 22 covers the plurality of light emitting elements 3 and the element insulating film 97, and is electrically connected to the plurality of light emitting elements 3. For the cathode electrode 22, a conductive material having translucency such as ITO is used. As a result, the light emitted from the light emitting element 3 can be efficiently taken out to the outside. The cathode electrode 22 is electrically connected to the cathode terminals 32 of the plurality of light emitting elements 3 mounted in the display region AA. The cathode electrode 22 is a contact portion provided outside the display area AA and is connected to the cathode wiring 60 provided on the array substrate 2 side.

As described above, the display device 1 using the light emitting element 3 as the display element is configured. The display device 1 may have an overcoat layer or a cover substrate laminated on the cathode electrode 22 as needed. Further, the display device 1 may be provided with a protective insulating film, a circular polarizing plate, a touch panel, or the like on the upper side of the cathode electrode 22.

Next, a connection configuration between the cathode terminal 32 of the light emitting element 3 and the pixel cathode electrode 24S provided on each pixel Pix will be described. FIG. 5 is a plan view showing an example of a connection configuration of a plurality of pixel cathode electrodes.

As shown in FIG. 5, the array substrate 2 is provided with a pixel cathode wiring LVSS. The pixel cathode wiring LVSS extends in the first direction Dx and is provided over a plurality of pixel Pix arranged in the first direction Dx. Here, a pixel group in one row including a plurality of pixel Pix arranged in the first direction Dx is referred to as a pixel row PixL. The plurality of pixel rows PixL are arranged in the second direction Dy. The pixel cathode wiring LVSS is provided for each pixel row PixL and is arranged in the second direction Dy.

Each of the plurality of pixel cathode wiring LVSS is electrically connected to the plurality of pixel cathode electrodes 24S belonging to the pixel row PixL. Each of the plurality of pixel cathode wiring LVSS is connected to the cathode wiring 60 provided in the peripheral region GA, and the cathode power supply potential PVSS is supplied. Further, the plurality of pixel cathode wiring LVSSs are connected to the cathode electrode 22 via the contact hole CH6 provided for each pixel Pix.

FIG. 6 is a cross-sectional view taken along the line VI-VI'of FIG. Note that FIG. 6 is a diagram schematically shown for explaining the connection configuration of the cathode electrode 22, the light emitting element 3 (light emitting element 3R), and the pixel cathode electrode 24S.

As shown in FIG. 6, the light emitting element 3R is laminated on the mounting electrode 24R and the bonding member 25 in the order of the p-type electrode 34, the p-type clad layer 35, the active layer 36, and the n-type clad layer 37. Further, the light emitting element 3R has a high resistance layer 38 laminated on the n-type clad layer 37. The high resistance layer 38 is formed of, for example, gallium nitride (GaN) which is not doped with impurities. The sheet resistance value of the high resistance layer 38 is larger than the sheet resistance value of the n-type clad layer 37.

The high resistance layer 38 has an area smaller than that of the n-type clad layer 37 in a plan view, and the high resistance layer 38 is not laminated on the peripheral edge of the n-type clad layer 37. The cathode electrode 22 is provided so as to cover the high resistance layer 38 and the n-type clad layer 37. The n-type clad layer 37 and the cathode electrode 22 are connected to each other at the peripheral edge of the upper surface of the n-type clad layer 37. In other words, the peripheral edge of the upper surface of the n-type clad layer 37 functions as the cathode terminal 32 (see FIG. 4). Further, the p-type clad layer 35, the active layer 36, and the n-type clad layer 37 correspond to the semiconductor layer 31 (see FIG. 4), and the p-type electrode 34 corresponds to the anode terminal 33 (see FIG. 4).

The pixel cathode electrode 24S is provided on the second organic insulating film 96 in the same layer as the mounting electrode 24. Further, the joining member 25S is provided on the pixel cathode electrode 24S. The element insulating film 97 is provided with a contact hole CH 6 in a region overlapping with the pixel cathode electrode 24S. The cathode electrode 22 is electrically connected to the pixel cathode electrode 24S via the joining member 25S at the bottom of the contact hole CH6.

As described above, the plurality of light emitting elements 3 are electrically connected to the pixel cathode electrodes 24S provided for each pixel Pix. Then, the plurality of pixel cathode electrodes 24S are connected to the pixel cathode wiring LVSS commonly provided in the pixel row PixL. As a result, the cathode power supply potential PVSS (reference potential) is supplied to the plurality of light emitting elements 3 via the pixel cathode electrode 24S for each pixel Pix, so that the variation in the cathode power supply potential PVSS supplied to each pixel Pix can be varied. It can be suppressed.

Next, an inspection method for the array substrate 2 will be described. FIG. 7 is a block diagram showing a configuration example of an inspection system for a display device according to an embodiment. As shown in FIG. 7, the inspection system 100 of the present embodiment includes an array substrate 2 on which the light emitting element 3 is not mounted, an inspection jig 7, an inspection control circuit 101, an inspection drive circuit 104, and a detection circuit. It has 105, an arithmetic circuit 102, and a storage circuit 103.

As the array substrate 2 to be inspected by the inspection system 100, the array substrate 2 on which the light emitting element 3 is not mounted, that is, the array substrate 2 before the light emitting element 3 is mounted is used. In the array substrate 2 on which the light emitting element 3 is not mounted, the mounting electrode 24 and the pixel cathode electrode 24S are provided on the outermost surface.

The inspection control circuit 101 is a circuit that controls various inspections of the array board 2. The inspection control circuit 101 may be included in the drive IC 210 (see FIG. 1), or may be individually provided as an inspection IC separate from the drive IC 210. The inspection drive circuit 104 is a circuit that supplies an inspection signal VTG to each pixel Pix of the array substrate 2 via the video signal line L2 based on the control signal from the inspection control circuit 101. The inspection signal VTG is a voltage signal corresponding to the video signal Vsig supplied to the video signal line L2 at the time of display.

The detection circuit 105 is a circuit for detecting the output signal Vo output from the array board 2. The detection circuit 105 detects the electrical characteristics of each pixel Pix based on the output signal Vo. The electrical characteristics are, for example, the current value of the current Ids flowing through the drive transistor DRT. The inspection control circuit 101 acquires the characteristics of each pixel Pix based on the output signal Vo from the detection circuit 105 in a state where the light emitting element 3 is not mounted.

The storage circuit 103 is a circuit that stores the electrical characteristics of each pixel Pix based on the output signal Vo detected by the detection circuit 105. The calculation circuit 102 is a circuit that calculates the correction value of each pixel Pix based on the electrical characteristics of each pixel Pix. Further, the arithmetic circuit 102 can compare the electrical characteristics of each pixel Pix with the characteristics of the light emitting element 3 acquired from the light emitting element inspection device 200, and select a light emitting element 3 suitable for each pixel Pix.

The inspection jig 7 is a jig for inspecting the characteristics of the pixel Pix. More specifically, FIG. 8 is a cross-sectional view schematically showing an inspection jig. FIG. 9 is a plan view schematically showing the inspection jig. As shown in FIG. 8, the inspection jig 7 includes an inspection substrate 71, a first connection terminal 72, a second connection terminal 73, a first electrode 74, a second electrode 75, and a dielectric layer 76. ,including. The inspection board 71 is an insulating board and is arranged so as to face the array board 2. The second electrode 75, the dielectric layer 76, and the first electrode 74 are laminated in this order on the surface of the inspection board 71 facing the array board 2. The first electrode 74 and the second electrode 75 are provided so as to face each other with the dielectric layer 76 interposed therebetween, and an inspection capacitance Can is formed between the first electrode 74 and the second electrode 75. The dielectric layer 76 has an opening 76a that exposes the second electrode 75 at a position that does not overlap the first electrode 74, and the second electrode 75 and the second connection terminal 73 are in contact with each other at the opening 76a. ..

The first connection terminal 72 and the second connection terminal 73 are each formed in a columnar shape protruding in a direction perpendicular to the surface of the inspection board 71 facing the array board 2. The first connection terminal 72 is connected to the first electrode 74. The second connection terminal 73 is connected to the second electrode 75. With such a configuration, an inspection capacitance Can is formed between the first connection terminal 72 and the second connection terminal 73. The inspection system 100 electrically connects the first connection terminal 72 to the mounting electrode 24 of the array substrate 2, and electrically connects the second connection terminal 73 to the pixel cathode electrode 24S.

Further, in FIG. 8, a joining member 25 is provided between the mounting electrode 24 and the first connection terminal 72, and a joining member 25S is provided between the pixel cathode electrode 24S and the second connection terminal 73. Not limited to the example, the inspection substrate 71 may be applied to the array substrate 2 before the joining members 25 and 25S are formed on the mounting electrode 24 and the pixel cathode electrode 24S. In that case, the first connection terminal 72 comes into direct contact with the mounting electrode 24, and the second connection terminal 73 comes into direct contact with the pixel cathode electrode 24S. Then, after the inspection by the inspection jig 7, the joining members 25 and 25S are coated and formed on the mounting electrode 24 and the pixel cathode electrode 24S, and each light emitting element 3 is mounted.

As shown in FIG. 9, when the inspection jig 7 is connected to the array substrate 2, the first electrode 74 is provided so as to face the plurality of mounting electrodes 24. For example, the first electrode 74 is formed in an L shape so as to overlap with the plurality of mounting electrodes 24R, 24G, and 24B, and is provided so as not to overlap with the pixel cathode electrode 24S. One first electrode 74 is electrically connected to a plurality of mounting electrodes 24R, 24G, 24B.

Further, each of the mounting electrodes 24 is provided with a connecting portion 24a for inspection. The connection portion 24a is provided at a position where it does not overlap with the light emitting element 3, and is formed so as to project from one side of the mounting electrode 24. Since a plurality of connection portions 24a are provided, it is possible to secure the connection between the mounting electrode 24 and the first connection terminal 72 even when the inspection jig 7 and the array substrate 2 are misaligned. can.

The second electrode 75 is arranged so as to face the plurality of mounting electrodes 24 and the pixel cathode electrode 24S. The second electrode 75 overlaps with the first electrode 74 and has a larger area than the first electrode 74. With such a configuration, the inspection jig 7 can make the capacity value of the inspection capacity Can larger than the first capacity Cs1 and the second capacity Cs2 of the pixel circuit PICA. Further, the inspection jig 7 can inspect the array substrate 2 by using the inspection jig 7 even when the shapes of the mounting electrode 24 and the pixel cathode electrode 24S are different.

Further, in FIGS. 8 and 9, the inspection jig 7 is connected to one pixel Pix. However, the present invention is not limited to this, and the inspection jig 7 may be connected to a plurality of pixels Pix. That is, the inspection board 71 is provided so as to cover the plurality of pixels Pix with a large area, and the first connection terminal 72, the second connection terminal 73, the first electrode 74, the second electrode 75, and the dielectric layer 76 are provided. , Pixels may be separated and arranged on the inspection substrate 71. Even in this case, the inspection system 100 can acquire the characteristics of each pixel Pix by driving the pixel circuit PICA for each pixel Pix.

Further, the first electrode 74 is electrically connected to a plurality of mounting electrodes 24 included in one pixel Pix, but the present invention is not limited to this. The first electrode 74 may be provided separately for each mounting electrode 24, and the inspection system 100 can also detect the characteristics for each pixel 49 (sub-pixel). That is, in the following description, "for each pixel Pix" can be read as "for each pixel 49 (sub-pixel)".

FIG. 10 is a circuit diagram for explaining an inspection method of an array substrate. As shown in FIG. 10, in the inspection of the array substrate 2, the inspection jig 7 is connected to the array substrate 2 on which the light emitting element 3 is not mounted. That is, in the pixel circuit PICA shown in FIG. 3, the inspection capacitance Can is connected instead of the light emitting element 3. As shown in FIG. 10, one end side (first connection terminal 72) of the inspection capacitance Can is electrically connected to the drive transistor DRT, the reset transistor RST, and the like via the anode electrode 23. The other end side (second connection terminal 73) of the inspection capacitance Can is connected to the cathode power supply potential PVSS via the cathode power supply line L10.

In the array substrate 2 to which the light emitting element 3 is not mounted, if the inspection jig 7 is not connected, the space between the anode side (mounting electrode 24) and the cathode side (pixel cathode electrode 24S) is open (open state). Will be done. Therefore, it is difficult to detect the characteristics of the pixel Pix (for example, the characteristics of the drive transistor DRT) on the array substrate 2 on which the light emitting element 3 is not mounted. In the present embodiment, by connecting the inspection jig 7 to the array substrate 2 on which the light emitting element 3 is not mounted, the mounting electrode 24 on which the light emitting element 3 is mounted and the pixel cathode electrode 24S are electrically connected. It becomes possible to inspect the characteristics of the pixel Pix.

As an example of the inspection method of the array substrate 2, the inspection control circuit 101 (see FIG. 7) operates the drive circuit 12 of the array substrate 2, and the output transistor BCT, the initialization transistor IST, and the pixel selection transistor are operated from the drive circuit 12. A drive signal is supplied to the SST and the reset transistor RST. As a result, the inspection control circuit 101 controls turning on and off of each transistor of the pixel Pix. For example, the inspection control circuit 101 turns on the output transistor BCT and the pixel selection transistor SST (conducting state) and turns off the initialization transistor IST and the reset transistor RST (non-conducting state) during the writing period T1.

Then, the inspection drive circuit 104 supplies the inspection signal VTG to the video signal line L2 during the writing period T1. The inspection signal VTG is supplied to the gate of the drive transistor DRT via the pixel selection transistor SST. At this time, since the output transistor BCT is turned on, the current Ids corresponding to the inspection signal VTG flows through the drive transistor DRT. The current Ids flows to the inspection capacity Can of the inspection jig 7 via the anode electrode 23, and the electric charge is accumulated in the inspection capacity Can.

Next, the inspection control circuit 101 turns off the output transistor BCT, the initialization transistor IST, and the pixel selection transistor SST (non-conducting state) and turns on the reset transistor RST (conducting state) during the read period T2. Further, the detection circuit 105 is connected to the reset power line L3. As a result, a signal extraction path is formed via the cathode power supply line L10, the inspection capacitance Can, the anode electrode 23, the reset transistor RST, and the reset power supply line L3. The electric charge accumulated in the inspection capacitance Can in the write period T1 is output to the detection circuit 105 as an output signal Vo via the reset transistor RST and the reset power supply line L3 in the read period T2.

As described above, the inspection system 100 can acquire the characteristics for each pixel Pix (for example, the characteristics related to the current Ids flowing through the drive transistor DRT) by detecting the output signal Vo output from the array substrate 2. .. In other words, the inspection system 100 can acquire variations in the characteristics of the pixel Pix caused only by the array substrate 2 (pixel circuit PICA) in a state where the light emitting element 3 is not mounted. Alternatively, the inspection drive circuit 104 may supply inspection signals VTGs having different voltages to acquire the threshold voltage Vth of the drive transistor DRT and the relationship between the inspection signal VTGs and the current Ids. Further, the inspection system 100 can also detect the presence or absence of a short circuit between the anode and the cathode of the array substrate 2 (short circuit between the mounting electrode 24 and the pixel cathode electrode 24S) based on the output signal Vo.

Further, the inspection system 100 acquires the characteristics of each pixel Pix by connecting the inspection jig 7 to the array substrate 2 and sharing the pixel circuit PICA used for displaying the pixel Pix as an inspection circuit. Can be done. Therefore, only the inspection capacity Can is formed in the inspection jig 7, and the configuration of the inspection jig 7 is simplified as compared with the case where the inspection jig 7 is provided with an inspection element such as a transistor for inspection. can do.

FIG. 11 is a flowchart for explaining an inspection method of an array substrate according to an embodiment. As shown in FIG. 11, the inspection system 100 includes an array substrate inspection step (steps ST11 to ST14) and a light emitting element inspection step (steps ST15 to ST17) as an inspection method for the array substrate 2.

In the array substrate inspection step, the inspection system 100 prepares the array substrate 2 on which the light emitting element 3 is not mounted (step ST11).

Next, the inspection system 100 inspects the array substrate 2 (step ST12). Specifically, as shown in FIGS. 8 to 10, the inspection system 100 is located between the first connection terminal 72, the second connection terminal 73, and the first connection terminal 72 and the second connection terminal 73. The first connection terminal 72 is connected to the mounting electrode 24 and the second connection terminal 73 is connected to the pixel cathode electrode 24S by using the inspection jig 7 including the provided inspection capacity Can. In this way, the inspection system 100 connects the inspection jig 7 to the array substrate 2 on which the light emitting element 3 is not mounted, and the inspection drive circuit 104 drives the pixel circuit PICA for each pixel Pix. The inspection drive circuit 104 supplies the inspection signal VTG to the drive transistor DRT based on the control signal from the inspection control circuit 101.

The detection circuit 105 detects the output signal Vo output from the drive transistor DRT according to the inspection signal VTG for each pixel Pix. As a result, the inspection system 100 acquires the characteristics of each pixel Pix based on the output signal Vo (step ST13). The characteristics of each pixel Pix are stored in the storage circuit 103, for example, as the table TA shown in FIG.

Further, the inspection control circuit 101 acquires correction data for each pixel Pix based on the output signal Vo (step ST14). The correction data for each pixel Pix is data for correcting the variation caused by the array substrate 2. The correction data for each pixel Pix is stored in the storage circuit as, for example, a corrected video signal ΔVsig (see table TA in FIG. 12). The calculation circuit 102 calculates the corrected video signal ΔVsig for each pixel Pix based on the output signal Vo. The corrected video signal ΔVsig is a signal that corrects the video signal Vsig supplied from the host IC, and is calculated for each pixel Pix so as to supplement the characteristic variation of the drive transistor DRT calculated based on the output signal Vo. This is the information that was given.

The inspection system 100 may perform a light emitting element inspection step in addition to the array substrate inspection step shown in steps ST11 to ST14. In the light emitting element inspection step, first, the light emitting element 3 is formed on the support substrate (step ST15). The support substrate is, for example, a sapphire substrate.

Next, the light emitting element inspection device 200 (see FIG. 7) inspects the characteristics of the light emitting element 3 on the support substrate (step ST16). The characteristics of the light emitting element 3 are, for example, the rising voltage Vf of the light emitting element 3, the main wavelength, and the like.

The inspection control circuit 101 acquires the characteristics of each light emitting element 3 from the light emitting element inspection device 200 (step ST17). The characteristics of each light emitting element 3 are stored in the storage circuit 103 as, for example, the table TB shown in FIG. The inspection control circuit 101 may individually store information such as the rising voltage Vf of the light emitting element 3 and the main wavelength in the storage circuit 103, or the characteristics of the light emitting element 3 such as the characteristics a, b, and c. May be stored by ranking in a predetermined range.

The inspection system 100 may acquire the information regarding the characteristics of the light emitting element 3 acquired in advance as the table TB without performing the light emitting element inspection step. Further, the characteristic is not limited to the case where the characteristics of the light emitting element 3 are individually acquired, and the characteristics may be acquired for each of a plurality of light emitting elements 3 as a group.

Next, the inspection system 100 selects a light emitting element 3 that matches the pixel Pix based on the characteristics of each pixel Pix and the characteristics of each light emitting element 3 (step ST21). FIG. 12 is an explanatory diagram illustrating an example of a method of selecting a light emitting element suitable for a pixel. As shown in the table TA of FIG. 12, the pixels Pix are ranked as characteristics A, B, and C according to the characteristics (for example, the current value of the current Ids flowing through the drive transistor DRT). For example, it is assumed that the characteristics A, B, and C are ranked so that the current Ids becomes smaller in this order. Further, the characteristic NG is a pixel Pix in which a defect of the pixel Pix has occurred and the light emitting element 3 is not mounted.

As shown in the table TB of FIG. 12, the light emitting element 3 is ranked as the characteristics a, b, and c according to the characteristics (for example, the voltage value of the rising voltage Vf and the main wavelength). For example, in the example shown in FIG. 12, it is assumed that the characteristics a, b, and c are ranked so that the rising voltage Vf becomes smaller in this order.

The inspection system 100 selects the light emitting element 3 so that the variation in the display image quality for each pixel Pix is small. For example, for the pixel Pix (1, 1) having the characteristic A having a large current Ids, the light emitting element 3-1 having the characteristic a having a large rising voltage Vf is selected. For the pixel Pix (1, 2) having the characteristic C having a small current Ids, the light emitting element 3-3 having the characteristic c having a small rising voltage Vf is selected. For the pixel Pix (m, n) having the characteristic B having a medium current Ids, the light emitting element 3-2 having the characteristic b having a medium rising voltage Vf is selected. The light emitting element 3 is not selected for the NG pixel Pix (2, 1).

Next, returning to FIG. 11, the manufacturing apparatus mounts the light emitting element 3 selected by the inspection system 100 on the array substrate 2 (step ST22). As a result, it is possible to suppress variations in display image quality due to variations in characteristics for each pixel Pix. Further, the NG pixel Pix (2, 1) is subjected to a blinding point process without mounting the light emitting element 3. As a result, the manufacturing cost of the display device 1 can be suppressed.

Next, the inspection system 100 inspects the lighting of the light emitting element 3 (step ST23). In step ST23, the lighting inspection is performed in a state where the light emitting element 3 is mounted on the array substrate 2 and the element insulating film 97 and the cathode electrode 22 (see FIG. 4) are not provided.

FIG. 13 is a block diagram for explaining a lighting inspection of the light emitting element. The inspection system 100 may perform a lighting inspection of the light emitting element 3 mounted on the array substrate 2, and may also repair the light emitting element 3 if necessary. As shown in FIG. 13, the inspection system 100 further includes a lighting inspection device 7A, a light detection device 106, an image processing circuit 107, a press device 220, a laser device 230, and a heater power supply 240.

The lighting inspection device 7A is an inspection board for performing a lighting inspection of a plurality of light emitting elements 3. The lighting inspection device 7A has an inspection substrate 71A and an inspection electrode 72A. The inspection board 71A faces the array board 2. The inspection electrode 72A is provided on the surface of the inspection substrate 71A facing the array substrate 2. The inspection electrode 72A is connected to the cathodes (n-type clad layer 37 (see FIG. 6)) of the plurality of light emitting elements 3. The inspection electrode 72A functions as the cathode electrode 22 of the light emitting element 3 during the lighting inspection.

The inspection drive circuit 104 supplies the anode power supply potential P VDD to the array substrate 2 and supplies the cathode power supply potential PVSS to the lighting inspection device 7A based on the control signal from the inspection control circuit 101. A current corresponding to the potential difference between the anode power supply potential P whether and the cathode power supply potential PVSS flows through each light emitting element 3 to emit light. The inspection drive circuit 104 may supply a potential for lighting the light emitting element 3 as an inspection drive signal, and may supply a potential different from the anode power supply potential P whether and the cathode power supply potential PVSS in the display of the display device 1. good.

The photodetector 106 detects the light emitted from each of the plurality of light emitting elements 3. The photodetector 106 is an image sensor having an image pickup device such as a CCD. The image processing circuit 107 receives a detection signal (image data) from the light detection device 106 and performs image processing to analyze the lighting state (for example, brightness) of each of the plurality of light emitting elements 3. The image processing circuit 107 outputs information regarding the lighting state of the plurality of light emitting elements 3 to the inspection control circuit 101.

The inspection control circuit 101 determines the lighting state of each of the plurality of light emitting elements 3 based on the information from the image processing circuit 107. For example, if the brightness of the light emitted from the light emitting element 3 is within a predetermined range, the inspection control circuit 101 determines that the lighting state of the light emitting element 3 is good. The inspection control circuit 101 determines that the light emitting element 3 is not lit when the brightness of the light emitted from the light emitting element 3 is smaller than the reference value. Further, the inspection control circuit 101 calculates the ratio of the number of non-lighting light emitting elements 3 to the total number of light emitting elements 3 as the connection failure rate. Further, the inspection control circuit 101 calculates the positions of the light emitting element 3 in the lit state and the light emitting element 3 in the non-lighted state.

The inspection control circuit 101 is at least the press device 220, the laser device 230, and the heater power supply 240 when the connection failure rate is larger than a predetermined reference value, that is, when a predetermined number of non-lighting light emitting elements 3 are present. A control signal is output to one or more to repair the light emitting element 3. The press device 220 pressurizes a plurality of light emitting elements 3 having a defect on the array substrate 2 side to connect the plurality of light emitting elements 3 and the mounting electrode 24. Further, the laser device 230 and the heater power supply 240 heat the plurality of light emitting elements 3 and the array substrate 2 in a state where the plurality of light emitting elements 3 are pressurized by the press device 220, thereby causing the plurality of light emitting elements 3 and the mounting electrodes. 24 is connected.

The inspection system 100 may not have the press device 220, the laser device 230, and the heater power supply 240 shown in FIG. 13, and may only inspect the lighting of the plurality of light emitting elements 3.

Next, returning to FIG. 11, the manufacturing apparatus forms the element insulating film 97 and the cathode electrode 22 (see FIG. 4) (step ST24). Then, the manufacturing apparatus mounts the drive IC 210 (see FIG. 1) on the array substrate 2 (step ST25).

The inspection system 100 writes correction data for each pixel Pix to the drive IC 210 and inspects the lighting of the light emitting element 3 (step ST26). The drive IC 210 supplies a signal obtained by adding the corrected video signal ΔVsig based on the correction data for each pixel Pix to the video signal Vsig supplied from the host IC to each light emitting element 3 of the pixel circuit PICA. As a result, the display device 1 can suppress variations in display image quality due to variations in characteristics for each pixel Pix of the array substrate 2.

The inspection method shown in FIG. 11 is merely an example and can be changed as appropriate. For example, the inspection system 100 may omit either step ST21 for selecting the light emitting element 3 for each pixel Pix or step ST26 for writing correction data.

As described above, the inspection method of the array substrate 2 of the present embodiment is the inspection method of the array substrate 2 on which a plurality of light emitting elements 3 are mounted, and the array substrate 2 corresponds to a plurality of pixels Pix. A plurality of provided transistors (drive transistor DRT, reset transistor RST, etc.), a plurality of mounting electrodes 24 electrically connected to the transistors and on which the light emitting element 3 is mounted, and a plurality of mounting electrodes 24 are provided adjacent to each other. It has a pixel cathode electrode 24S, which is electrically connected to a reference potential (cathode power supply potential PVSS). The inspection method of the array board 2 includes step ST11 for preparing the array board 2 in which a plurality of light emitting elements 3 are not mounted, the first connection terminal 72, the second connection terminal 73, the first connection terminal 72, and the second connection. A step of connecting the first connection terminal 72 to the mounting electrode 24 and connecting the second connection terminal 73 to the pixel cathode electrode 24S using an inspection jig 7 including an inspection capacitance Can provided between the terminal 73. The inspection signal VTG is supplied to the drive transistor DRT based on the control signal from ST12 and the inspection control circuit 101 that controls the inspection of the array substrate 2, and the output signal output from the drive transistor DRT according to the inspection signal VTG. It has a step ST13 for detecting Vo.

According to this, by connecting the inspection jig 7 to the array substrate 2, it is possible to inspect the characteristics of the array substrate 2 (for example, the characteristics of the drive transistor DRT) in a state where the light emitting element 3 is not arranged. Therefore, since the light emitting element 3 can be selected according to the characteristics of each pixel Pix of the array substrate 2 or the correction data for each pixel Pix can be acquired, it is possible to suppress the variation in the display image quality of the pixel Pix. As a result, the yield of the panel can be improved. Further, the manufacturing cost can be reduced by not mounting the light emitting element 3 on the defective pixel Pix. Therefore, according to the inspection method of the array substrate 2 of the present embodiment, the characteristics of the array substrate 2 in which the light emitting element 3 is not mounted can be satisfactorily detected.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various changes can be made without departing from the spirit of the present invention. Appropriate changes made without departing from the spirit of the present invention naturally belong to the technical scope of the present invention. At least one of the various omissions, substitutions and modifications of the components may be made without departing from the gist of each of the embodiments and modifications described above.

1 Display device 2 Array board 3, 3R, 3G, 3B, 3-1, 3-2, 3-3 Light emitting element 7 Inspection jig 12 Drive circuit 21 Board 24, 24R, 24G, 24B Mounting electrode 24S Pixel cathode electrode 25 , 25S Joining member 60 Cathode wiring 71 Inspection board 72 1st connection terminal 73 2nd connection terminal 74 1st electrode 75 2nd electrode 76 Dielectric layer 100 Inspection system 210 Drive IC
Can inspection capacity DRT drive transistor RST reset transistor

Claims (7)

This is an inspection method for an array board on which multiple light emitting elements are mounted.
The array board is
Multiple transistors provided for multiple pixels and
A plurality of mounting electrodes electrically connected to the transistor and to which the light emitting element is mounted,
It has a pixel cathode electrode, which is provided adjacent to the plurality of mounting electrodes and is electrically connected to a reference potential.
A step of preparing the array board on which the plurality of light emitting elements are not mounted, and
The first connection terminal is mounted by using an inspection jig including a first connection terminal, a second connection terminal, and an inspection capacity provided between the first connection terminal and the second connection terminal. The step of connecting to the electrode and connecting the second connection terminal to the pixel cathode electrode,
A step of supplying an inspection signal to the transistor based on a control signal from an inspection control circuit that controls inspection of the array substrate and detecting an output signal output from the transistor according to the inspection signal. How to inspect the array substrate you have. The inspection jig has a first electrode connected to the first connection terminal and a second electrode facing the first electrode with a dielectric layer interposed therebetween and connected to the second connection terminal. death,
The method for inspecting an array substrate according to claim 1, wherein the first electrode faces the plurality of mounting electrodes, and the second electrode is arranged so as to face the plurality of mounting electrodes and the pixel cathode electrodes. The inspection control circuit acquires the characteristics of each pixel based on the output signal, and based on the characteristics of the plurality of light emitting elements and the characteristics of each pixel, the light emitting element suitable for the pixel is obtained. The method for inspecting an array substrate according to claim 1 or claim 2 to be selected. The method for inspecting an array substrate according to any one of claims 1 to 3, wherein the inspection control circuit acquires correction data for each pixel based on the output signal. The plurality of transistors include a drive transistor that supplies a current to the light emitting element and a reset transistor that supplies a reset potential to the light emitting element.
The inspection signal is supplied to the gate of the drive transistor and is supplied.
The method for inspecting an array substrate according to any one of claims 1 to 4, wherein the output signal is output to the detection circuit via the reset transistor. With the array board
A plurality of light emitting elements mounted on the array substrate and
It has a drive IC mounted on the array substrate and supplying a video signal to a plurality of light emitting elements.
The drive IC has correction data for each pixel acquired from the array substrate on which the plurality of light emitting elements are not mounted, and adds a correction video signal based on the correction data to the video signal supplied from the outside. A display device that supplies the signal to the light emitting element. It is an inspection jig for inspecting an array board on which a light emitting element is not mounted.
A first connection terminal, a second connection terminal, a first electrode in contact with the first connection terminal, and a second electrode in contact with the second connection terminal are provided.
The first electrode and the second electrode face each other with a dielectric layer interposed therebetween.
An inspection jig in which the dielectric layer has an opening at a position where it does not overlap with the first electrode, and the second electrode and the second connection terminal come into contact with each other at the opening.

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