JP7438813B2 - Array substrate inspection method and display device - Google Patents

Description

The present invention relates to an array substrate inspection method and a display device.

In recent years, inorganic EL displays using inorganic light emitting diodes (micro LEDs), ie, inorganic light emitting elements, have been attracting attention as display elements. For example, Patent Document 1 describes an inspection jig for testing the lighting of inorganic light emitting elements.

China Patent Application Publication No. 109686828

When inspecting a plurality of light emitting elements mounted on an array substrate, if a defect is discovered in the circuits or wiring of the array substrate, many of the light emitting elements already mounted may be discarded. Furthermore, it is necessary to test the electrical characteristics of each pixel circuit in which a plurality of light emitting elements are mounted, which may increase the steps and time required for testing. Therefore, manufacturing costs may increase.

SUMMARY OF THE INVENTION An object of the present invention is to provide an array substrate inspection method and a display device that can efficiently inspect the electrical characteristics of an array substrate on which light emitting elements are not mounted.

A method for inspecting an array substrate according to one embodiment of the present invention is a method for inspecting an array substrate on which a plurality of light emitting elements are mounted, wherein the array substrate includes a plurality of transistors provided corresponding to a plurality of pixels; a plurality of mounting electrodes electrically connected to the transistor and on which a plurality of the light emitting elements are mounted; and a plurality of inspection terminals electrically connected to the plurality of mounting electrodes; a step of preparing the array substrate on which no elements are mounted; a plurality of inspection tools having a support section extending over a plurality of pixels; and a plurality of inspection probes arranged in an extending direction of the support section; arranging a tool for each pixel row consisting of a plurality of said pixels arranged in a first direction, and bringing a plurality of said test probes into contact with each of said plurality of said test terminals arranged in said first direction; and inspecting electrical characteristics for each of the pixel rows using a plurality of the inspection jigs.

A method for inspecting an array substrate according to one embodiment of the present invention is a method for inspecting an array substrate on which a plurality of light emitting elements are mounted, wherein the array substrate includes a plurality of transistors provided corresponding to a plurality of pixels; A plurality of mounting electrodes electrically connected to the transistor and on which the light emitting elements are mounted are provided for each pixel row consisting of a plurality of the pixels arranged in a first direction, and a reference potential is applied to the plurality of light emitting elements. and a plurality of cathode test terminals electrically connected to the plurality of cathode power supply lines, and on which the plurality of light emitting elements are not mounted. and a test jig having a support part extending over the plurality of pixels and a plurality of test probes provided on the support part, and the plurality of test probes are arranged for each pixel row. , contacting each of the plurality of cathode test terminals arranged in a second direction intersecting the first direction, and the plurality of test probes to contact at least the cathode test terminal and the cathode for each pixel row. The method includes a step of testing continuity between the wiring and the wiring.

A display device according to one embodiment of the present invention includes an array substrate and a plurality of light emitting elements mounted on the array substrate, and the array substrate includes a plurality of transistors provided corresponding to a plurality of pixels; It has a plurality of mounting electrodes electrically connected to the transistor and on which the light emitting element is mounted, and a plurality of test terminals electrically connected to the mounting electrodes.

FIG. 1 is a plan view schematically showing a display device according to a first embodiment. FIG. 2 is a plan view showing one pixel Pix. FIG. 3 is a circuit diagram showing a pixel circuit. FIG. 4 is a plan view schematically showing a plurality of pixels. FIG. 5 is an enlarged plan view showing two adjacent pixels in FIG. FIG. 6 is a sectional view taken along line VI-VI' in FIG. FIG. 7 is a cross-sectional view schematically showing an array substrate on which light emitting elements are not mounted. FIG. 8 is an explanatory diagram for explaining the array substrate inspection method according to the first embodiment. FIG. 9 is a flowchart for explaining the array substrate inspection method according to the first embodiment. FIG. 10 is an explanatory diagram for explaining a method for inspecting each pixel row of an array substrate according to the second embodiment. FIG. 11 is an explanatory diagram for explaining a method for inspecting each pixel column of an array substrate according to the second embodiment. FIG. 12 is a flowchart for explaining an array substrate inspection method according to the second embodiment. FIG. 13 is a flowchart for explaining an array substrate inspection method according to the third embodiment. FIG. 14 is an explanatory diagram for explaining an array substrate inspection method according to the fourth embodiment.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Modes (embodiments) for carrying out the present invention will be described in detail with reference to the drawings. The present invention is not limited to the contents described in the following embodiments. Further, the constituent elements described below include those that can be easily assumed by those skilled in the art and those that are substantially the same. Furthermore, the components described below can be combined as appropriate. It should be noted that the disclosure is merely an example, and any modifications that can be easily made by those skilled in the art while maintaining the gist of the invention are naturally included within the scope of the present invention. In addition, in order to make the explanation clearer, the drawings may schematically represent the width, thickness, shape, etc. of each part compared to the actual aspect, but these are only examples, and the interpretation of the present invention is It is not limited. In addition, in this specification and each figure, the same elements as those described above with respect to the previously shown figures are denoted by the same reference numerals, and detailed explanations may be omitted as appropriate.

In this specification and the claims, when expressing a mode in which another structure is placed on top of a certain structure, when it is simply expressed as "above", unless otherwise specified, This includes both a case in which another structure is placed directly above a certain structure so as to be in contact with the structure, and a case in which another structure is placed above a certain structure via another structure.

(First embodiment)
FIG. 1 is a plan view schematically showing a display device according to a first embodiment. As shown in FIG. 1, the display device 1 includes an array substrate 2, a pixel Pix, a drive circuit 12, a drive IC (Integrated Circuit) 210, and a cathode wiring 60. The array substrate 2 is a drive circuit board for driving each pixel Pix, and is also called a backplane or an active matrix substrate. The array substrate 2 includes a substrate 21, a plurality of transistors, a plurality of capacitors, various wirings, and the like. Although not particularly illustrated, a flexible printed circuit board (FPC) or the like may be connected to the array substrate 2 for inputting control signals and power for driving the drive circuit 12 and the drive IC 210.

As shown in FIG. 1, the display device 1 has a display area AA and a peripheral area GA. The display area AA is an area that is arranged to overlap with a plurality of pixels Pix and displays an image. The peripheral area GA is an area that does not overlap with the plurality of pixels Pix, and is arranged outside the display area AA.

The plurality of pixels Pix are arranged in the first direction Dx and the second direction Dy in the display area AA of the substrate 21. Note that the first direction Dx and the second direction Dy are directions parallel to the surface of the substrate 21. The first direction Dx is orthogonal to the second direction Dy. However, the first direction Dx may intersect with the second direction Dy without being perpendicular to it. The third direction Dz is a direction orthogonal to the first direction Dx and the second direction Dy. The third direction Dz corresponds to the normal direction of the substrate 21, for example. Note that, hereinafter, a plan view refers to a positional relationship when viewed from the third direction Dz.

The drive circuit 12 is a circuit that drives the plurality of gate lines GL (see FIG. 3) based on the drive IC 210 or various control signals from the outside. The drive circuit 12 selects a plurality of gate lines GL sequentially or simultaneously and supplies a gate drive signal to the selected gate lines GL. Thereby, the drive circuit 12 selects a plurality of pixels Pix connected to the gate line GL.

The drive IC 210 is a circuit that controls the display of the display device 1. The drive IC 210 is mounted in the peripheral area GA of the substrate 21 as a COG (Chip On Glass). The present invention is not limited thereto, and the drive IC 210 may be mounted on a flexible printed circuit board or a rigid circuit board connected to the peripheral area GA of the substrate 21.

The cathode wiring 60 is provided in the peripheral area GA of the substrate 21. The cathode wiring 60 is provided surrounding the plurality of pixels Pix in the display area AA and the drive circuit 12 in the peripheral area GA. The cathodes of the plurality of light emitting elements 3 are electrically connected to a common cathode wiring 60 and supplied with a reference potential (eg, ground potential). More specifically, the cathode terminal 32 (see FIG. 6) of the light emitting element 3 is connected to the cathode wiring 60 via the cathode electrode 22 and the cathode power line LVSS.

FIG. 2 is a plan view showing one pixel Pix. As shown in FIG. 2, one pixel Pix includes a plurality of sub-pixels 49. For example, the pixel Pix includes a first sub-pixel 49R, a second sub-pixel 49G, and a third sub-pixel 49B. The first sub-pixel 49R displays the primary color red as the first color. The second sub-pixel 49G displays the primary color green as the second color. The third sub-pixel 49B displays the primary color blue as the third color. As shown in FIG. 2, in one pixel Pix, the first sub-pixel 49R, the second sub-pixel 49G, and the third sub-pixel 49B are lined up in the first direction Dx. Note that the first color, second color, and third color are not limited to red, green, and blue, respectively, and any color such as a complementary color can be selected. In the following, when there is no need to distinguish between the first sub-pixel 49R, the second sub-pixel 49G, and the third sub-pixel 49B, they will be referred to as sub-pixels 49.

The first subpixel 49R, the second subpixel 49G, and the third subpixel 49B each include a first light emitting element 3R, a second light emitting element 3G, a third light emitting element 3B, and an anode electrode 23. The display device 1 emits different light for each of the first light emitting element 3R, the second light emitting element 3G, and the third light emitting element 3B in the first subpixel 49R, the second subpixel 49G, and the third subpixel 49B. Display images. The first light emitting element 3R emits red light. The second light emitting element 3G emits green light. The third light emitting element 3B emits blue light. In addition, in the following description, when it is not necessary to distinguish and explain the 1st light emitting element 3R, the 2nd light emitting element 3G, and the 3rd light emitting element 3B, they are simply expressed as the light emitting element 3.

The light emitting element 3 is provided in each of the plurality of subpixels 49. The light emitting element 3 is a light emitting diode (LED) chip having a size of approximately 3 μm or more and 300 μm or less in plan view. Although not strictly defined, devices with a chip size of less than 100 μm are called micro LEDs. The display device 1 including a micro LED in each pixel is also called a micro LED display device. Note that the size of the light emitting element 3 is not limited to the size of the micro LED.

Note that the plurality of light emitting elements 3 may emit light of four or more different colors. Further, the arrangement of the plurality of sub-pixels 49 is not limited to the configuration shown in FIG. 2. For example, the first sub-pixel 49R may be adjacent to the second sub-pixel 49G in the first direction Dx. The first sub-pixel 49R, the second sub-pixel 49G, and the third sub-pixel 49B may be arranged in a triangular lattice shape. Further, the arrangement order of the first sub-pixel 49R, the second sub-pixel 49G, and the third sub-pixel 49B in the first direction Dx may also be different.

FIG. 3 is a circuit diagram showing a pixel circuit. The pixel circuit shown in FIG. 3 is a circuit that is provided on the substrate 21 and supplies a drive signal (current) to each light emitting element 3. As shown in FIG. 3, the plurality of gate lines GL each extend in the first direction Dx and are connected to the plurality of first sub-pixels 49R, second sub-pixels 49G, and third sub-pixels 49B. The plurality of first signal lines SL-1, second signal lines SL-2, and third signal lines SL-3 each extend in the second direction Dy. The first signal line SL-1 is connected to a plurality of first sub-pixels 49R arranged in the second direction Dy. The second signal line SL-2 is connected to a plurality of second sub-pixels 49G arranged in the second direction Dy. The third signal line SL-3 is connected to a plurality of third sub-pixels 49B arranged in the second direction Dy. In the following description, unless it is necessary to distinguish between the first signal line SL-1, the second signal line SL-2, and the third signal line SL-3, they will simply be referred to as signal lines SL.

As shown in FIG. 3, each subpixel 49 includes two transistors and one capacitor. Specifically, each subpixel 49 includes a drive transistor DRT, a write transistor SST, and a capacitor Cs. Each subpixel 49 further includes an anode test terminal 51 (test terminal) and a cathode test terminal 52.

Each of the plurality of transistors included in each subpixel 49 is composed of an n-type TFT (Thin Film Transistor). However, the present invention is not limited thereto, and each transistor may be composed of a p-type TFT.

The gate of drive transistor DRT is connected to the drain of write transistor SST. The source of drive transistor DRT is connected to anode power supply line LVDD. The drain of the drive transistor DRT is connected to the anode of the light emitting element 3 and the anode test terminal 51. The cathode of the light emitting element 3 is connected to a cathode power line LVSS and a cathode test terminal 52, and is supplied with a reference potential.

The gate of write transistor SST is connected to gate line GL. A source of write transistor SST is connected to signal line SL. The drain of write transistor SST is connected to the gate of drive transistor DRT.

The capacitor Cs has one end connected to the gate of the drive transistor DRT and the drain of the write transistor SST, and the other end connected to the common wiring LCs. The common line LCs is electrically connected to the cathode power supply line LVSS and supplied with a reference potential. The capacitor Cs is added to the pixel circuit in order to suppress fluctuations in gate voltage due to parasitic capacitance and leakage current of the drive transistor DRT.

Write transistor SST functions as a switching element that selects conduction or non-conduction between two nodes. The drive transistor DRT functions as a current control element that controls the current flowing through the light emitting element 3 according to the voltage between the gate and the drain.

Specifically, the drive circuit 12 selects a plurality of gate lines GL and supplies a gate drive signal to the selected gate lines GL. When the potential of the gate line GL becomes H (high) level due to the gate drive signal, the write transistor SST is turned on. As a result, charge is accumulated in the capacitor Cs based on the video signal supplied from the signal line SL. The voltage between the gate and drain of the drive transistor DRT is determined according to the amount of charge in the capacitor Cs.

A current flows through the drive transistor DRT based on the anode power supply potential PVDD supplied from the anode power supply line LVDD. The drive transistor DRT supplies a current to the light emitting element 3 according to the voltage between the gate and the drain. The light emitting element 3 emits light with a brightness corresponding to this current. Furthermore, even after the write transistor SST is turned off, current is supplied to the light emitting element 3 from the anode power supply line LVDD via the drive transistor DRT.

Next, a specific example of the configuration of the pixel Pix in plan view will be described. FIG. 4 is a plan view schematically showing a plurality of pixels. In FIG. 4, eight pixels Pix arranged in 2 rows and 4 columns are shown in an enlarged manner among a plurality of pixels Pix arranged in the display area AA. Specifically, as shown in FIG. 4, the pixels Pix (1, 1), Pix (2, 1), Pix (3, 1), and Pix (4, 1) are arranged in the first direction Dx. . Furthermore, the pixels Pix (1, 1) and Pix (1, 2) are arranged in the second direction Dy. Pixels Pix (2, 1) and Pix (2, 2) are arranged in the second direction Dy. Pixels Pix (3, 1) and Pix (3, 2) are arranged in the second direction Dy. Pixels Pix (4, 1) and Pix (4, 2) are arranged in the second direction Dy. Note that the pixels Pix (1, 1), Pix (2, 1), Pix (3, 1), Pix (4, 1), Pix (1, 2), Pix (2, 2), Pix (3, 2 ), Pix (4, 2), if it is not necessary to explain them separately, they will simply be expressed as pixel Pix.

The plurality of pixels Pix each include a first light emitting element 3R (first subpixel 49R), a second light emitting element 3G (second subpixel 49G), a third light emitting element 3B (third subpixel 49B), and a first signal. It has a line SL-1, a second signal line SL-2, a third signal line SL-3, and a gate line GL. The first light emitting element 3R is electrically connected to the first signal line SL-1. The second light emitting element 3G is electrically connected to the second signal line SL-2. The third light emitting element 3B is electrically connected to the third signal line SL-3.

In this embodiment, a plurality of light emitting elements 3 and a plurality of signal lines SL (signal line group SLG) are arranged close to each other in two pixels Pix adjacent to each other in the first direction Dx. One adjacent pixel Pix and the other pixel Pix are arranged in an inverted positional relationship with an imaginary line parallel to the second direction Dy as an axis of symmetry.

Two pixels Pix (for example, pixel Pix (2, 2) and pixel Pix (3, 2)) adjacent in the first direction Dx are connected to two signal line groups SLG adjacent in the first direction Dx, and This is a region surrounded by Dy and two adjacent gate lines GL.

In the display device 1, the area of the light-transmitting area CA is larger than the area of the non-light-transmitting area NCA. That is, the display device 1 is a so-called transparent display that is used so that the other side of the display area AA can be seen through. However, the display device 1 is not limited to this, and may be a display device in which the area of the light-transmitting region CA is small and the arrangement density of the light emitting elements 3 is increased. Note that the non-transparent area NCA is an area in which various wirings such as the signal line SL and gate line GL, and various electrodes such as the anode electrode 23 connected to the light emitting element 3 are provided, and the transparent area CA is This is an area where various wirings and various electrodes are not provided.

Next, a specific example of the configuration of each pixel Pix will be described, focusing on the pixel Pix (1, 1) and the pixel Pix (2, 1) that are adjacent to each other in the first direction Dx. FIG. 5 is an enlarged plan view showing two adjacent pixels in FIG. In the following description, one of the first directions Dx (right side in FIG. 5) may be expressed as +Dx direction, and the other direction Dx (left side in FIG. 5) may be expressed as -Dx direction. Similarly, one of the second directions Dy (the upper direction in FIG. 5) may be expressed as the +Dy direction, and the other direction of the second direction Dy (the lower direction in FIG. 5) may be expressed as the −Dy direction.

The signal line group SLG includes a plurality of signal lines SL adjacent to each other in the first direction Dx. Specifically, three signal lines SL connected to the pixel Pix (1, 1) on the left side of FIG. 5, and three signal lines SL connected to the pixel Pix (2, 1) on the right side of FIG. are arranged adjacent to each other in the first direction Dx, and are formed as a single signal line group SLG.

In each of the plurality of pixels Pix, the first light emitting element 3R, the second light emitting element 3G, and the third light emitting element 3B are arranged adjacent to each other in the first direction Dx, and are located at the intersection of the signal line group SLG and the gate line GL. Located nearby. Specifically, in the first direction Dx, the signal line group SLG includes a plurality of light emitting elements 3 forming a pixel Pix (1, 1) and a plurality of light emitting elements 3 forming a pixel Pix (2, 1). provided between. Further, the gate line GL intersecting the signal line group SLG in the second direction Dy connects the plurality of light emitting elements 3 forming the pixel Pix (1, 1) and the plurality of light emitting elements 3 forming the pixel Pix (2, 1). It is provided between the element 3 and the element 3.

The first light emitting element 3R, second light emitting element 3G, and third light emitting element 3B that constitute the pixel Pix (1, 1) are arranged in this order in the first direction Dx, and the signal line group SLG and the first direction Dx ( -Dx direction). Further, the first light emitting element 3R, the second light emitting element 3G, and the third light emitting element 3B that constitute the pixel Pix (1, 1) are arranged adjacent to each other in the -Dy direction of the gate line GL that intersects the signal line group SLG. be done.

The first light emitting element 3R, second light emitting element 3G, and third light emitting element 3B that constitute the pixel Pix (2, 1) are arranged in this order in the first direction Dx, and the signal line group SLG and the first direction Dx ( +Dx direction). Further, the first light emitting element 3R, the second light emitting element 3G, and the third light emitting element 3B that constitute the pixel Pix (2, 1) are arranged adjacent to each other in the +Dy direction of the gate line GL. The plurality of light emitting elements 3 of the pixel Pix (1, 1) and the plurality of light emitting elements 3 of the pixel Pix (2, 1) are arranged in the same arrangement relationship in the first direction Dx. However, the order of arrangement of the plurality of light emitting elements 3 may be different for each pixel Pix.

The light emitting elements 3 are each connected to each signal line SL via the semiconductor layer 71 of the write transistor SST. Further, each light emitting element 3 is electrically connected to an anode power supply line LVDD via a contact hole H4. The anode power line LVDD and the cathode power line LVSS are provided to overlap with the gate line GL and extend in the first direction Dx. Note that in FIGS. 4 and 5, the anode power line LVDD and the cathode power line LVSS are represented by two-dot chain lines in order to make the drawings easier to read.

The light emitting elements 3 are each provided on the mounting electrode 24. The anode test terminal 51 is connected to the mounting electrode 24 in the second direction Dy. The plurality of mounting electrodes 24 are arranged in the first direction Dx, and the plurality of anode test terminals 51 are also arranged in the first direction Dx. The cathode test terminal 52 is connected to the cathode power supply line LVSS. The plurality of cathode test terminals 52 are arranged in the first direction Dx along the cathode power supply line LVSS. Note that the anode test terminal 51 is directly connected to the mounting electrode 24 and formed as an integrated electrode. The cathode test terminal 52 is directly connected to the cathode power supply line LVSS. However, the present invention is not limited to this, and the anode test terminal 51 may be electrically connected to the mounting electrode 24 via a connection wiring or the like, and the cathode test terminal 52 may also be connected to the cathode power supply line LVSS via a connection wiring or the like. It may be electrically connected to.

Note that the arrangement of each pixel Pix shown in FIGS. 4 and 5 is merely an example, and may be changed as appropriate. For example, the plurality of light emitting elements 3 of the pixel Pix (1, 1) and the plurality of light emitting elements 3 of the pixel Pix (2, 1) shown in FIG. 5 may be arranged in the first direction Dx.

Next, the cross-sectional structure of the display device 1 will be explained. FIG. 6 is a sectional view taken along line VI-VI' in FIG. FIG. 7 is a cross-sectional view schematically showing an array substrate on which light emitting elements are not mounted. Note that FIG. 7 is a cross-sectional view taken in a direction perpendicular to the line VI-VI' in FIG.

As shown in FIGS. 6 and 7, the light emitting elements 3 are provided on the array substrate 2. As shown in FIGS. The array substrate 2 includes a substrate 21, an anode electrode 23, a mounting electrode 24, a counter electrode 25, various transistors, various wirings, and various insulating films. The various wirings include, for example, wirings such as a plurality of gate lines GL and a plurality of signal lines SL connected to a plurality of transistors (write transistors SST).

The substrate 21 is an insulating substrate, and for example, a glass substrate such as quartz or alkali-free glass, or a resin substrate such as polyimide is used. When a flexible resin substrate is used as the substrate 21, the display device 1 can be configured as a sheet display. Further, the substrate 21 is not limited to polyimide, and other resin materials may be used.

Note that in this specification, the direction from the substrate 21 toward the light emitting element 3 in the direction perpendicular to the surface of the substrate 21 is referred to as "upper side" or simply "upper". Further, the direction from the light emitting element 3 toward the substrate 21 is referred to as "lower side" or simply "lower side."

An undercoat film 91 is provided on the substrate 21 . Drive transistor DRT and write transistor SST are provided on undercoat film 91. The semiconductor layer 61 and the semiconductor layer 71 (see FIG. 7) are provided on the undercoat film 91.

Gate insulating film 92 is provided on undercoat film 91 to cover semiconductor layers 61 and 71 . The gate insulating film 92 is, for example, a silicon oxide film. The gate electrode 64 and the gate line GL (see FIG. 7) are provided on the gate insulating film 92.

In the example shown in FIGS. 6 and 7, the drive transistor DRT has a top gate structure in which the gate electrode 64 is provided above the semiconductor layer 61. However, the present invention is not limited to this, and the drive transistor DRT may have a bottom gate structure in which the gate electrode 64 is provided below the semiconductor layer 61, or may have a bottom gate structure in which the gate electrode 64 is provided both above and below the semiconductor layer 61. A dual gate structure may also be used. The same structure as the drive transistor DRT can be adopted for the write transistor SST as well.

Interlayer insulating film 93 is provided on gate insulating film 92 to cover gate electrode 64 and gate line GL. The source electrode 62 (see FIG. 7), the drain electrode 63, the signal line SL (source electrode 72), and the drain electrode 73 are provided on the interlayer insulating film 93.

As shown in FIG. 7, the drain electrode 63 is connected to the drain region of the semiconductor layer 61 via a contact hole H1 penetrating the gate insulating film 92 and the interlayer insulating film 93. The source electrode 62 is connected to the source region of the semiconductor layer 61 via a contact hole H2 penetrating the gate insulating film 92 and the interlayer insulating film 93.

As shown in FIGS. 6 and 7, the first organic insulating film 94 is provided on the interlayer insulating film 93, covering the drive transistor DRT, write transistor SST, and signal line SL. As the first organic insulating film 94, an organic material such as photosensitive acrylic is used. The first organic insulating film 94 and the second organic insulating film 96 are flattening films that flatten the surface of the array substrate 2 .

On the first organic insulating film 94, the counter electrode 25, the capacitive insulating film 95, and the anode electrode 23 are laminated in this order. The counter electrode 25 is made of a light-transmitting conductive material such as ITO (Indium Tin Oxide).

Capacitive insulating film 95 is provided to cover counter electrode 25 and has an opening in a region overlapping with contact holes H3 and H4 (see FIG. 7). The capacitor insulating film 95 is, for example, a silicon nitride film. Anode electrode 23 faces counter electrode 25 with capacitive insulating film 95 interposed therebetween. Anode electrode 23 is electrically connected to drain electrode 63 via contact hole H3. Thereby, the anode electrode 23 is electrically connected to the drive transistor DRT.

A capacitor Cs is formed between the anode electrode 23 and the counter electrode 25, which face each other with the capacitor insulating film 95 interposed therebetween. The second organic insulating film 96 is provided on the anode electrode 23. The mounting electrode 24 is provided on the second organic insulating film 96 and is electrically connected to the anode electrode 23 via a contact hole H6 (see FIG. 7).

As shown in FIG. 7, the anode test terminal 51 is provided on the second organic insulating film 96 in the same layer as the mounting electrode 24. The anode test terminal 51 is electrically connected to the anode electrode 23 and the drive transistor DRT via the mounting electrode 24. Further, the cathode power supply line LVSS and the cathode test terminal 52 are provided on the second organic insulating film 96 in the same layer as the mounting electrode 24 and the anode test terminal 51. The cathode power line LVSS is electrically connected to the cathode electrode 22 (see FIG. 6) at an arbitrary location.

As shown in FIG. 6, the light emitting elements 3 (the first light emitting element 3R, the second light emitting element 3G, and the third light emitting element 3B) are mounted on the corresponding mounting electrodes 24. The connection between the anode terminal 33 of each light emitting element 3 and the mounting electrode 24 is not particularly limited as long as good conduction can be ensured between the two and the structure formed on the array substrate 2 is not damaged. The anode terminal 33 and the mounting electrode 24 may be bonded by, for example, a reflow process using a low-temperature melting solder material, or a method in which the light emitting element 3 is placed on the array substrate 2 via a conductive paste and then bonded by firing.

Here, it is also possible to directly mount the light emitting element 3 on the anode electrode 23 without providing the second organic insulating film 96 and the mounting electrode 24 on the array substrate 2. However, by providing the second organic insulating film 96 and the mounting electrode 24, it is possible to suppress damage to the capacitive insulating film 95 due to the force applied when mounting the light emitting element 3. In other words, it is possible to suppress the occurrence of dielectric breakdown between the anode electrode 23 and the counter electrode 25 that form the capacitance Cs.

As shown in FIG. 6, the light emitting element 3 has a semiconductor layer 31, a cathode terminal 32, and an anode terminal 33. The semiconductor layer 31 can adopt a structure in which an n-type cladding layer, an active layer, and a p-type cladding layer are stacked. For the semiconductor layer 31, a compound semiconductor such as gallium nitride (GaN), aluminum indium phosphorus (AlInP), or indium gallium nitride (InGaN) is used, for example. Different materials may be used for the semiconductor layer 31 for each of the first light emitting element 3R, the second light emitting element 3G, and the third light emitting element 3B. In addition, a multiple quantum well structure (MQW structure) in which well layers and barrier layers each consisting of several atomic layers are periodically laminated may be adopted as the active layer in order to improve efficiency.

An element insulating film 97 is provided between the plurality of light emitting elements 3. The element insulating film 97 is formed of a resin material. The element insulating film 97 covers at least the side surfaces of the light emitting element 3 , and the cathode terminal 32 of the light emitting element 3 is exposed from the element insulating film 97 . The element insulating film 97 is formed flat so that the upper surface of the element insulating film 97 and the upper surface of the cathode terminal 32 form the same plane. However, the position of the upper surface of the element insulating film 97 may be different from the position of the upper surface of the cathode terminal 32.

The cathode electrode 22 is provided to cover the plurality of light emitting elements 3 and the element insulating film 97, and is electrically connected to the cathode terminals 32 of the plurality of light emitting elements 3. For the cathode electrode 22, a light-transmitting conductive material such as ITO is used. Thereby, the light emitted from the light emitting element 3 can be efficiently extracted to the outside.

Next, a method for inspecting the array substrate 2 will be described with reference to FIGS. 7 to 9. FIG. 8 is an explanatory diagram for explaining the array substrate inspection method according to the first embodiment. FIG. 9 is a flowchart for explaining the array substrate inspection method according to the first embodiment.

As shown in FIG. 8, the inspection system 10 of this embodiment includes the array substrate 2 on which the light emitting elements 3 are not mounted, the inspection jig 80, the inspection control circuit 100, the inspection drive circuit 101, and the detection circuit 102. , and a memory circuit 103.

As shown in FIG. 7, the array substrate 2 to be inspected by the inspection system 10 is an array substrate 2 on which the light emitting elements 3 are not mounted, that is, an array substrate 2 before the light emitting elements 3 are mounted. In the array substrate 2, a mounting electrode 24, a cathode power supply line LVSS, an anode test terminal 51, and a cathode test terminal 52 are provided on the outermost surface.

As shown in FIG. 8, a plurality of pixels Pix arranged in the first direction Dx are defined as a pixel row PXA. Pixel rows PXA(n), PXA(n+1), and PXA(n+2) indicate the n-th, n+1-th, and n+2-th pixel rows PXA, respectively. Similarly, a plurality of pixels Pix (sub-pixels 49) arranged in the second direction Dy are defined as a pixel column PXB. Pixel rows PXB(m), PXB(m+1), and PXA(m+2) indicate pixel columns PXB in the m-th row, m+1-th row, and m+2-th row, respectively.

The inspection jig 80 is provided for each pixel row PXA, and each includes a support section 81 and a plurality of inspection probes 82. Inspection jigs 80(n), 80(n+1), and 80(n+2) are arranged in pixel rows PXA(n), PXA(n+1), and PXA(n+2), respectively. Each of the plurality of test probes 82 of the test jig 80(n) contacts the anode test terminal 51 of each pixel Pix (sub-pixel 49) belonging to the pixel row PXA(n) arranged in the first direction Dx. . Similarly, each of the plurality of test probes 82 of the test jig 80 (n+1) is connected to the anode test terminal 51 of each pixel Pix (sub-pixel 49) belonging to the pixel row PXA (n+1) arranged in the first direction Dx. come into contact with. The plurality of test probes 82 of the test jig 80 (n+2) each contact the anode test terminal 51 of each pixel Pix (sub-pixel 49) belonging to the pixel row PXA (n+2) arranged in the first direction Dx. .

The support portion 81 is a rod-shaped member that extends across a plurality of pixels Pix belonging to the pixel row PXA. The support portion 81 is made of a conductive material that electrically connects the plurality of test probes 82. A plurality of test probes 82 provided on one test jig 80 are electrically connected via a support portion 81. Further, the inspection jigs 80(n), 80(n+1), and 80(n+2) provided for each pixel column PXA are insulated from each other.

The plurality of inspection probes 82 are arranged along the extending direction of the support section 81. The arrangement pitch of the plurality of pixels Pix and the plurality of inspection probes 82 is equal to the arrangement pitch of the sub-pixels 49 in the first direction Dx. Thereby, the plurality of test probes 82 come into contact with the anode test terminals 51 arranged in the first direction Dx. Furthermore, the plurality of inspection jigs 80 are arranged for each pixel row PXA, and can detect electrical characteristics for each pixel row PXA.

The inspection control circuit 100 is a circuit that controls various inspections of the array substrate 2. The test control circuit 100 may be included in the drive IC 210 (FIG. 1), or may be provided separately as a test IC separate from the drive IC 210. The test drive circuit 101 is a circuit that supplies a test signal VTG to each pixel Pix of the array substrate 2 via the signal line SL based on a control signal from the test control circuit 100. The test signal VTG is a voltage signal corresponding to a video signal supplied to the signal line SL during display.

The detection circuit 102 is a circuit that detects the output signal Vo output from the inspection jig 80. The detection circuit 102 detects the electrical characteristics of each pixel Pix based on the output signal Vo. The electrical characteristics include, for example, the value of current flowing through the pixel circuit, the presence or absence of short circuits between wirings, the presence or absence of short circuits between pixels Pix, and the like. The inspection control circuit 100 determines whether each pixel Pix is defective or not, based on the output signal Vo from the detection circuit 102, in a state where the light emitting element 3 is not mounted.

The storage circuit 103 is a circuit that stores the electrical characteristics of each pixel Pix based on the output signal Vo detected by the detection circuit 102.

In the inspection method of the inspection system 10 shown in FIGS. 8 and 9, each pixel Pix is driven under conditions similar to actual display to check the operation of the pixel Pix. Specifically, as shown in FIG. 9, the inspection system 10 first prepares the array substrate 2 on which the light emitting elements 3 are not mounted (step ST10).

The inspection system 10 arranges the inspection jig 80 for each pixel row PXA, and brings the plurality of inspection probes 82 into contact with each of the plurality of anode inspection terminals 51 arranged in the first direction Dx (step ST11). As a result, as shown in FIG. 7, a recess 51a is formed in the anode test terminal 51 after the test is brought into contact with the test probe 82. Further, when the cathode test terminal 52 is tested, a recess 52a is similarly formed in the cathode test terminal 52 by contact with the test probe 82.

The inspection system 10 drives the gate line GL for each pixel row PXA (step ST12). Specifically, the drive circuit 12 sequentially supplies gate drive signals to the gate lines GL based on control signals from the inspection control circuit 100. As a result, a plurality of pixel rows PXA are sequentially selected as inspection targets. A case where pixel row PXA(n) is selected from among the plurality of pixel rows PXA will be described below.

Next, the test drive circuit 101 supplies the test signal VTG to the signal line SL for each pixel column PXB (step ST13). As a result, the test signal VTG is sequentially supplied to the plurality of pixels Pix belonging to the pixel row PXA(n) selected by the drive circuit 12. A voltage signal corresponding to the anode power supply potential PVDD is supplied to the anode power supply line LVDD, and a reference potential (cathode power supply potential) is supplied to the inspection jig 80. As a result, each pixel Pix in the pixel row PXA(n) is driven even in the array substrate 2 where the light emitting element 3 is not mounted, and a current according to the test signal VTG flows through the test jig 80.

The detection circuit 102 detects the output signal Vo for each of the plurality of pixels Pix (sub-pixels 49) belonging to the pixel row PXA(n) (step ST14). The output signal Vo is, for example, the current value of the current flowing from the drive transistor DRT to the inspection jig 80(n) in response to the inspection signal VTG.

The inspection control circuit 100 determines whether or not there is a defect in the pixel circuit of each pixel Pix based on the output signal Vo (step ST15). The inspection control circuit 100 can, for example, compare the output signal Vo with a threshold value stored in the storage circuit 103 in advance to determine the operation of the pixel circuit. Further, when a defect occurs in the pixel circuit of the pixel Pix, the inspection control circuit 100 stores information regarding the position and defect mode of the pixel Pix where the defect has occurred in the storage circuit 103.

The inspection control circuit 100 determines whether inspection of all pixel rows PXA has been completed (step ST16). If the inspection of all pixel rows PXA has not been completed (step ST16, No), the next pixel row PXA is inspected (step ST17), and steps ST12 to ST15 are repeatedly executed. When the inspection of all pixel rows PXA is completed (step ST16, Yes), the inspection system 10 ends the inspection.

In this manner, in the inspection system 10, the inspection jig 80 is provided for each pixel row PXA, and the electrical characteristics of each pixel Pix can be detected for each pixel row PXA. Thereby, since the light emitting element 3 is not mounted, even if a defective pixel Pix occurs, there is no need to discard the light emitting element 3, and manufacturing costs can be suppressed. Further, a test jig 80 is provided for each pixel row PXA, and a plurality of test probes 82 provided on one support portion 81 respectively contact a plurality of anode test terminals 51 of the pixel row PXA. Therefore, the electrical characteristics of the pixel Pix can be detected more efficiently than when each pixel Pix is tested individually.

(Second embodiment)
FIG. 10 is an explanatory diagram for explaining a method for inspecting each pixel row of an array substrate according to the second embodiment. FIG. 11 is an explanatory diagram for explaining a method for inspecting each pixel column of an array substrate according to the second embodiment. FIG. 12 is a flowchart for explaining an array substrate inspection method according to the second embodiment.

In the second embodiment, a detection method for detecting the presence or absence of a short between the anode and cathode of each pixel Pix using the inspection system 10 will be described. Also in this embodiment, the inspection system 10A inspects the array substrate 2 on which the light emitting elements 3 are not mounted.

As shown in FIGS. 10 and 12, the inspection system 10A arranges the inspection jig 80 for each pixel row PXA, and connects the plurality of inspection probes 82 to the plurality of anode inspection terminals 51 arranged in the first direction Dx. They are brought into contact with each other (step ST21). Note that the connection relationship between each inspection jig 80 and the plurality of anode inspection terminals 51 is the same as that in the first embodiment described above, and redundant explanation will be omitted.

Note that in the second embodiment, unlike the first embodiment, the drive circuit 12 does not drive each gate line GL, and the test drive circuit 101 (not shown) does not supply the test signal VTG to the signal line SL. Therefore, the drive transistor DRT and write transistor SST of each pixel Pix are off (non-connected state), and the plurality of anode test terminals 51 are respectively non-connected to the anode power supply line LVDD and the signal line SL.

The detection circuit 102 detects the resistance value between the inspection jig 80 and the cathode power supply line LVSS for each pixel row PXA (step ST22). The plurality of cathode power lines LVSS are provided for each pixel row PXA, and each of the plurality of cathode power lines LVSS is provided across the plurality of pixels Pix belonging to the pixel row PXA. The detection circuit 102 may detect information regarding the resistance value, such as the voltage value and current value between the inspection jig 80 and the cathode power supply line LVSS. The inspection control circuit 100 may calculate the resistance value between the inspection jig 80 and the cathode power supply line LVSS based on information regarding resistance values such as voltage values and current values. The detection circuit 102 detects the resistance values of all pixel rows PXA for each pixel row PXA.

The inspection control circuit 100 determines whether the resistance values of all pixel rows PXA are equal to or greater than the reference value (step ST23).

If the resistance values of all pixel rows PXA are equal to or higher than the reference value (step ST23, Yes), the test control circuit 100 determines that no short circuit has occurred between the anodes and cathodes of all the pixels Pix, and performs the test. finish.

If the resistance value is smaller than the reference value in any pixel row PXA (step ST23, No), the inspection system 10 performs an inspection to identify the pixel Pix where a short circuit has occurred. In the following description, for example, a case where a short circuit occurs in pixel row PXA(n+1) will be described.

The inspection control circuit 100 causes the storage circuit 103 to store the pixel row PXA(n+1) in which the short circuit occurred in step ST22 (step ST24).

Next, as shown in FIGS. 11 and 12, the inspection system 10 arranges the inspection jig 80 for each pixel column PXB, and inserts the plurality of inspection probes 82 into the plurality of anodes arranged in the second direction Dy. It is brought into contact with each of the terminals 51 (step ST25). As shown in FIG. 11, the inspection system 10 rotates the inspection jigs 80 by 90 degrees so that they extend in the second direction Dy, and rotates the inspection jigs 80(n), 80(n+1), 80 (n+2) are arranged in pixel columns PXB(m), PXB(m+1), and PXB(m+2), respectively.

The plurality of test probes 82 of the test jig 80(n) each contact the anode test terminals 51 of each pixel Pix (sub-pixel 49) belonging to the pixel column PXB(m) arranged in the second direction Dy. . Similarly, each of the plurality of test probes 82 of the test jig 80 (n+1) is connected to the anode test terminal 51 of each pixel Pix (sub-pixel 49) belonging to the pixel column PXB (m+1) arranged in the second direction Dy. come into contact with. The plurality of test probes 82 of the test jig 80 (n+2) each contact the anode test terminal 51 of each pixel Pix (sub-pixel 49) belonging to the pixel column PXB (m+2) arranged in the second direction Dy. .

The detection circuit 102 detects the resistance value between the inspection jig 80 and the cathode power supply line LVSS for each pixel column PXB (step ST26). For example, if a short circuit occurs in the pixel row PXA (n+1) in steps ST21 to ST24 described above, the detection circuit 102 detects the short circuit between each inspection jig 80 and the cathode power line LVSS of the pixel row PXA (n+1). Detect resistance value.

The inspection control circuit 100 determines whether the resistance value of each pixel column PXB is equal to or greater than the reference value based on the information regarding the resistance value (output signal Vo), and identifies the pixel column PXB in which a short circuit has occurred (step ST27). ).

The inspection control circuit 100 identifies the pixel Pix where the short circuit occurred from the information about the pixel row PXA where the short circuit occurred and the information about the pixel column PXB where the short circuit occurred stored in step ST24 (step ST28).

As described above, in this embodiment, the continuity test between the anode and cathode of each pixel Pix can be performed. Since the inspection jig 80 can detect the resistance value for each pixel row PXA, if there is no defect, the detection can be completed by scanning the pixel row PXA once, and the inspection can be performed efficiently. In addition, since the pixel Pix where the light emitting element 3 is not mounted and a short circuit has occurred can be inspected, it is possible to repair the pixel circuit or not mount the light emitting element 3 on the pixel Pix where the short circuit has occurred. Compared to the case where a defect is discovered later, it is possible to suppress the discarding of the light emitting element 3.

(Third embodiment)
FIG. 13 is a flowchart for explaining an array substrate inspection method according to the third embodiment. In the third embodiment, a detection method for detecting the presence or absence of a short circuit between adjacent pixels Pix using the inspection system 10 will be described with reference to FIGS. 8, 11, and 13.

The inspection system 10 of this embodiment includes an inspection jig 80 having a configuration similar to that shown in FIG. That is, the inspection system 10 arranges the inspection jig 80 for each pixel row PXA, and brings the plurality of inspection probes 82 into contact with each of the plurality of anode inspection terminals 51 arranged in the first direction Dx (step ST31). . The inspection system 10 drives the gate line GL for each pixel row PXA (step ST32). Next, the test drive circuit 101 supplies the test signal VTG to the signal line SL for each pixel column PXB (step ST33). Steps ST31 to ST33 are the same as steps ST11 to ST13 of the first embodiment described above, and repeated explanation will be omitted.

The detection circuit 102 detects the output signal Vo from a pixel row PXA different from the pixel row PXA that drove the gate line GL (step ST34). In the following description, as an example, a case will be described in which the presence or absence of a short circuit between pixel row PXA(n) and pixel row PXA(n+1) adjacent in the second direction Dy is detected. Specifically, when the drive circuit 12 supplies a gate drive signal to the gate line GL belonging to the pixel row PXA(n), the detection circuit 102 supplies the gate drive signal to the gate line GL belonging to the pixel row PXA(n) and the pixel row PXA(n+1) adjacent to the pixel row PXA(n). An output signal Vo is detected from the inspection jig 80(n+1) connected to the test jig 80(n+1).

The inspection control circuit 100 determines whether a short circuit has occurred between the pixel rows PXA based on the output signal Vo detected by the detection circuit 102 (step ST35). When the output signal Vo (for example, current value) supplied from pixel row PXA(n+1) is smaller than the threshold value, the inspection control circuit 100 detects a short circuit between pixel row PXA(n) and pixel row PXA(n+1). It is determined that this has not occurred (step ST35, No). Then, the inspection control circuit 100 sequentially executes driving of the pixel rows PXA and detection of the output signal Vo from the first row to the last row.

When the output signal Vo (for example, current value) supplied from pixel row PXA(n+1) is equal to or greater than the threshold value, the inspection control circuit 100 determines that there is a short circuit between pixel row PXA(n) and pixel row PXA(n+1). It is determined that this has occurred (step ST35, Yes).

In this case, in the driven pixel row PXA(n), the test signal VTG is supplied to the signal line SL for each pixel column PXB in step ST33, so the adjacent pixel row PXA(n) and the pixel row PXA( It is possible to specify the pixel Pix in which a short circuit has occurred between the pixel Pix and the pixel Pix (n+1). On the other hand, in the pixel row PXA(n+1) which is not driven, the inspection jig 80(n+1) is in contact with the plurality of anode inspection terminals 51, so the pixel Pix where a short circuit has occurred cannot be identified.

The inspection system 10 detects the presence or absence of a short circuit by reversing the relationship between driving and detection between pixel row PXA(n) and pixel row PXA(n+1). That is, the inspection system 10 drives the gate line GL of the pixel row PXA(n+1) where the short circuit has occurred, and supplies the inspection signal VTG to the signal line SL for each pixel column PXB (step ST36). The detection circuit 102 detects the output signal Vo from the inspection jig 80(n) connected to the pixel row PXA(n+1) and the adjacent pixel row PXA(n). Thereby, the inspection control circuit 100 can identify the pixel Pix in which a short circuit has occurred in the pixel row PXA(n+1) based on the output signal Vo (step ST37).

In this embodiment, by driving each pixel row PXA using the inspection jig 80, it is possible to detect whether there is a short circuit between the pixel rows PXA. Therefore, the presence or absence of a short circuit between pixels Pix can be detected more efficiently than the method of inspecting each pixel Pix individually.

8 and 13, a method of detecting whether a short circuit has occurred between pixels Pix adjacent to each other in the second direction Dy has been described. However, the present invention is not limited to this, and the presence or absence of a short circuit between pixels Pix adjacent in the first direction Dx can also be detected.

That is, the inspection jig 80 is rotated by 90 degrees, and as shown in FIG. It is brought into contact with each of the anode test terminals 51 (step corresponding to step ST31). As in steps ST32 and ST33, the inspection system 10 drives the gate line GL for each pixel row PXA, and the inspection drive circuit 101 supplies the inspection signal VTG to the signal line SL for each pixel column PXB.

The detection circuit 102 detects the output signal Vo from a pixel column PXB different from the pixel column PXB to which the test signal VTG is supplied (step corresponding to step ST34). In the following description, as an example, a case will be described in which the presence or absence of a short circuit between pixel column PXB(m) and pixel column PXB(m+1) adjacent in the first direction Dx is detected. Specifically, when the test drive circuit 101 supplies the test signal VTG to the first signal line SL-1 belonging to the pixel column PXB(m), the detection circuit 102 detects a pixel adjacent to the pixel column PXB(m). Output signal Vo is detected from inspection jig 80 (n+1) connected to column PXB (m+1).

Thereby, the inspection control circuit 100 can determine whether a short circuit has occurred between the pixel columns PXB based on the output signal Vo supplied from the detection circuit 102. Further, when a short circuit occurs, by reversing the relationship between driving and detection between the pixel columns PXB, the inspection control circuit 100 can specify in which pixel row PXA the short circuit has occurred. In other words, the inspection control circuit 100 can specify the position in the second direction Dy of the pixel Pix where the short circuit has occurred.

Note that the above-described method for detecting the presence or absence of a short circuit between pixels Pix is merely an example, and can be changed as appropriate. For example, steps ST36 and ST37 may be omitted and only the presence or absence of a short circuit between pixels Pix may be detected. In this case, the inspection to identify the pixel Pix where the short circuit has occurred may be performed in a separate inspection process, or the position of the pixel Pix where the short circuit has occurred may not be specified. Furthermore, both the short-circuit test between pixel rows PXA and the short-circuit test between pixel columns PXB may be performed, or either one of them may be performed.

(Fourth embodiment)
FIG. 14 is an explanatory diagram for explaining an array substrate inspection method according to the fourth embodiment. In the fourth embodiment, a continuity test of wiring on the cathode side will be described. Also in this embodiment, the array substrate 2 on which the light emitting elements 3 are not mounted is inspected.

As shown in FIG. 14, the inspection system 10A of this embodiment includes an inspection jig 80A. The inspection jig 80A is provided along the arrangement direction (second direction Dy) of the plurality of pixels Pix included in the pixel column PXB. The inspection jig 80A is provided, for example, in the pixel column PXB(m+2). In FIG. 14, a case will be described in which a plurality of cathode test terminals 52 of pixel column PXB(m+2) are tested. When inspecting another pixel column PXB (for example, pixel column PXB(m+1)), the inspection control circuit 100 can inspect each column by moving the inspection jig 80A.

Each of the inspection jigs 80A includes a support portion 81, a plurality of inspection probes 82, and a connecting portion 83. The plurality of inspection probes 82 and the plurality of connecting parts 83 are arranged along the extending direction of the support part 81. The inspection jig 80A is provided in one pixel column PXB. As an example, each of the plurality of test probes 82 contacts the cathode test terminals 52 of each pixel Pix (sub-pixel 49) belonging to the pixel column PXB(m+2) arranged in the second direction Dy. Inspection probe 82(n) contacts cathode inspection terminal 52 belonging to pixel row PXA(n). Inspection probe 82 (n+1) contacts cathode inspection terminal 52 belonging to pixel row PXA (n+1). Inspection probe 82 (n+2) contacts cathode inspection terminal 52 belonging to pixel row PXA (n+2).

Inspection probes 82(n), 82(n+1), and 82(n+2) are connected to support portion 81 via connecting portions 83(n), 83(n+1), and 83(n+2), respectively. The support portion 81 is a rod-shaped member that extends across a plurality of pixels Pix belonging to the pixel column PXB. The support part 81 is formed of an insulating material, and the plurality of test probes 82(n), 82(n+1), and 82(n+2) are insulated from each other by the support part 81.

The detection circuit 102 can detect the output signal Vo from each of the test probes 82(n), 82(n+1), and 82(n+2). The output signal Vo is a signal corresponding to the resistance value between the cathode test terminal 52 and the cathode power supply line LVSS. The test control circuit 100 can perform a continuity test (presence or absence of disconnection) between the cathode test terminal 52 and the cathode power supply line LVSS based on the output signal Vo from the test probe 82. Alternatively, the test control circuit 100 can perform a continuity test (presence or absence of disconnection) of the cathode power supply line LVSS provided for each pixel row PXA based on the output signal Vo from the test probe 82.

In the inspection system 10B of the fourth embodiment, one inspection jig 80A is provided across a plurality of pixel rows PXA, and the electrical characteristics on the cathode side can be detected for each pixel row PXA (cathode power supply line LVSS). can. Thereby, the electrical characteristics on the cathode side can be detected more efficiently than when testing is performed by individually contacting each cathode power supply line LVSS with a probe.

Although preferred embodiments of the present invention have been described above, the present invention is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various changes can be made without departing from the spirit of the present invention. Appropriate changes made within the scope of the invention also fall within the technical scope of the invention. At least one of various omissions, substitutions, and modifications of the constituent elements can be made without departing from the gist of each of the embodiments and modifications described above.

1 Display device 2 Array substrate 3 Light emitting element 10, 10A, 10B Inspection system 12 Drive circuit 21 Substrate 22 Cathode electrode 23 Anode electrode 24 Mounting electrode 49 Sub-pixel 51 Anode inspection terminal 52 Cathode inspection terminal 60 Cathode wiring 80, 80(n) , 80(n+1), 80(n+2), 80A Inspection jig 81 Support part 82, 82(n), 82(n+1), 82(n+2) Inspection probe 83, 83(n), 83(n+1), 83( n+2) Connection part 100 Inspection control circuit 101 Inspection drive circuit 102 Detection circuit GL Gate line SL Signal line LVDD Anode power line LVSS Cathode power line Pix Pixel Vo Output signal VTG Inspection signal PXA, PXA(n), PXA(n+1), PXA (n+2) Pixel row PXB, PXB(m), PXB(m+1), PXB(m+2) Pixel column

Claims (8)

A method for inspecting an array substrate on which a plurality of light emitting elements are mounted, the method comprising:
The inspection system includes the array substrate to be inspected and an inspection jig,
The array substrate is
a plurality of transistors provided corresponding to a plurality of pixels;
a plurality of mounting electrodes that are electrically connected to the transistor and on which the plurality of light emitting elements are mounted;
a plurality of inspection terminals electrically connected to the plurality of mounting electrodes;
preparing the array substrate on which a plurality of the light emitting elements are not mounted;
A plurality of the inspection jigs each having a plurality of support parts extending over the plurality of pixels and a plurality of test probes arranged in the extending direction of the support part are connected to the plurality of test jigs arranged in the first direction. Arranging each pixel row consisting of pixels, and bringing a plurality of the test probes into contact with each of the plurality of test terminals arranged in the first direction;
A method for inspecting an array substrate, including the step of inspecting electrical characteristics of each of the pixel rows using a plurality of the inspection jigs. The inspection system includes a detection circuit that detects output signals from the plurality of inspection jigs,
The array substrate has a plurality of gate lines and a plurality of signal lines connected to the plurality of transistors,
The gate line is driven for each pixel row, and a test signal is supplied to the signal line for each column,
The method for inspecting an array substrate according to claim 1, wherein the detection circuit detects an output signal output from the inspection jig according to the inspection signal for each of a plurality of pixels belonging to the pixel row. The inspection system includes a detection circuit that detects output signals from the plurality of inspection jigs,
The array substrate has a cathode power line provided for each pixel row and supplying a reference potential to a plurality of the light emitting elements,
The method for inspecting an array substrate according to claim 1, wherein the detection circuit detects information regarding a resistance value between the inspection jig and the cathode power supply line for each pixel row. If the resistance value is smaller than the reference value in a predetermined pixel row,
A plurality of said inspection jigs are arranged for each pixel column consisting of a plurality of said pixels arranged in a second direction intersecting said first direction, and a plurality of said inspection probes are arranged in said plurality of said pixels arranged in said second direction. contacting each of the plurality of test terminals;
4. The detection circuit includes a step of detecting, for each pixel column, information regarding a resistance value between the inspection jig and the cathode power line provided in the predetermined pixel row. The method for inspecting the described array substrate. The inspection system includes a detection circuit that detects output signals from the plurality of inspection jigs,
The array substrate has a plurality of gate lines and a plurality of signal lines connected to the plurality of transistors,
The gate line is driven for each pixel row, and a test signal is supplied to the signal line for each column,
The method for inspecting an array substrate according to claim 1, wherein the detection circuit detects an output signal output from the inspection jig in a pixel row different from the pixel row in which the gate line is driven. A method for inspecting an array substrate on which a plurality of light emitting elements are mounted, the method comprising:
The array substrate is
a plurality of transistors provided corresponding to a plurality of pixels;
a plurality of mounting electrodes that are electrically connected to the transistor and on which the light emitting element is mounted;
a plurality of cathode power supply lines provided for each pixel row consisting of the plurality of pixels arranged in a first direction and supplying a reference potential to the plurality of light emitting elements;
a plurality of cathode test terminals each electrically connected to the plurality of cathode power supply lines and provided in each of the pixels ;
preparing the array substrate on which a plurality of the light emitting elements are not mounted;
preparing an inspection jig having a support portion extending across a plurality of pixels and a plurality of inspection probes provided on the support portion, and arranging the plurality of inspection probes for each pixel row; contacting each of the plurality of cathode test terminals arranged in a second direction intersecting the first direction;
A method for testing an array substrate, including the step of performing a continuity test between at least the cathode test terminal and the cathode power supply line for each pixel row using a plurality of the test probes. comprising an array substrate and a plurality of light emitting elements mounted on the array substrate,
The array substrate is
a plurality of transistors provided corresponding to a plurality of pixels;
a plurality of mounting electrodes that are electrically connected to the transistor and on which the light emitting element is mounted;
a plurality of inspection terminals electrically connected to the mounting electrode,
A display device in which a recess is formed in the plurality of test terminals by contact with a test probe. The array substrate is provided for each pixel row consisting of a plurality of pixels arranged in a first direction, and a cathode power line supplies a reference potential to a plurality of the light emitting elements;
a plurality of cathode test terminals electrically connected to the cathode power supply line and provided for each pixel ;
The display device according to claim 7, wherein a recess is formed in the plurality of cathode test terminals by contact with a test probe.

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