JP2001237429A - Method of manufacturing transistor array substrate and method of manufacturing optoelectric device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a TFT array substrate and an optoelectric device, in which cost can be reduced by performing an highly accurate inspection equivalent to a lighting inspection in a stage of TFT array substrate. SOLUTION: In a manufacturing method of a liquid crystal device, in the stage of completion of manufacturing the TFT array 200, the substrate is checked for a operation before a panel is assembled. That is, a data drive circuit 60 and a scanning line drive circuit 70 are supplied with power or signals from an input/output terminal 45 of the TFT array substrate 200 to actuate TFTs 10A, 10B and 10C, and it is inspected as to whether a very weak light with a wavelength between a visual region and a near-infrared region is generated on the TFT array substrate 200 by emission microscope.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a transistor array substrate (hereinafter, referred to as a TFT array substrate) on which a thin film transistor (hereinafter, referred to as a TFT) circuit is formed, and a method of manufacturing an electro-optical device using the TFT array substrate. It is about the method. More specifically, the present invention relates to an inspection technique for a TFT array substrate.

[0002]

2. Description of the Related Art A typical example of a TFT array substrate in which a TFT circuit and terminals are formed on a substrate is an active matrix substrate with a built-in driving circuit used in a liquid crystal device (electro-optical device). In this TFT array substrate, a plurality of pixels are arranged in a matrix at intersections between a plurality of scanning lines and a plurality of data lines arranged on an insulating substrate. Each pixel has a pixel switching TFT connected to a scanning line and a data line, and a TF.
A pixel electrode electrically connected to T is formed.
A data line driving circuit for supplying an image signal to each of the plurality of data lines and a scanning line driving circuit for supplying a scanning signal to each of the plurality of scanning lines are formed in a region outside the pixel portion on the insulating substrate. ing. These drive circuits
This is a TFT circuit including a plurality of TFTs.

In order to assemble a liquid crystal device using the TFT substrate configured as described above, a TFT array substrate must be
The opposing substrate on which the opposing electrode is formed is bonded through a predetermined gap, and thereafter, a liquid crystal as an electro-optical material is sealed between the TFT array substrate and the opposing substrate. After the liquid crystal is sealed in this way, power and various signals are supplied from the terminals to the drive circuit, and all the pixels are turned on at the same time to check whether a line defect has occurred.

[0004]

However, when the liquid crystal device is manufactured in the conventional process sequence, even if only the TFT array substrate has a defect, the inspection process determines that the entire liquid crystal device is defective. Thus, the entire liquid crystal device is disposed of. For this reason, in the conventional manufacturing method, there is a problem that the man-hours spent after manufacturing the liquid crystal and other materials or the TFT array substrate is wasted. On the other hand, it is impossible to perform a lighting test on the TFT array substrate alone.

An object of the present invention is to provide a TFT array substrate manufacturing method and an electro-optical device capable of reducing costs by performing a high-precision inspection corresponding to a lighting inspection at a TFT array substrate stage. It is to provide a manufacturing method of.

[0006]

According to the present invention, there is provided a method of manufacturing a transistor array substrate having a thin film transistor circuit and a terminal electrically connected to the thin film transistor circuit on a substrate. An element forming step of forming the thin film transistor circuit and the terminal on the substrate, and after performing the element forming step, a power supply or a signal is supplied to the thin film transistor circuit through the terminal on the transistor array substrate. A step of observing the light emission state of the transistor array with an emission microscope and examining whether or not there is a defect in the transistor array substrate based on the observation result.

According to the present invention, it is possible to effectively inspect the transistor array substrate for defects using an emission microscope without assembling the electro-optical device. That is, when a defect such as a leak or hot carrier occurs in a TFT array substrate, a very weak light emission having a wavelength in a visible region to a near-infrared region occurs. Such a weak light emission phenomenon is caused by emission. It can be detected using a microscope. In addition, the position where the cause of the lighting abnormality found when performing the lighting inspection in the electro-optical device or the like coincides with the position where light emission is observed by the emission microscope. Therefore, the quality of the electro-optical device can be inspected in the state of the transistor array substrate. Therefore, when a failure occurs in the TFT array substrate, only the TFT array substrate needs to be discarded, and there is no need to discard the entire electro-optical device. Therefore, the cost of the electro-optical device can be reduced.

The method for manufacturing a transistor array substrate thus configured can be applied to a method for manufacturing an electro-optical device. In this case, after performing the inspection step, an assembly step of assembling the electro-optical device using the transistor array substrate determined to be non-defective in the inspection step is performed.

For example, when an active matrix type liquid crystal device is manufactured as an electro-optical device, in the element forming step, the transistor circuit as a driving circuit and a signal supplied from the transistor circuit are provided on the substrate. A plurality of scanning lines and a plurality of data lines, and a pixel switching thin film transistor electrically connected to the scanning line and the data line, respectively, and a pixel electrode electrically connected to the pixel switching thin film transistor Are formed in a matrix, and in the assembling step, a counter substrate is bonded to the transistor array substrate determined to be non-defective in the inspection step via a predetermined gap, and then the counter substrate and the transistor array are bonded together. An electro-optical material is filled between the substrate and the substrate.

When inspecting such a TFT array substrate for an electro-optical device, it is preferable to set the magnification with an emission microscope in the range of 5 to 50 times. If a large area such as a TFT array substrate for an electro-optical device is to be inspected, it takes a long time to inspect if the magnification is too high. However, if the magnification is in the range of 5 to 50 times, the efficiency depends on the purpose. Can be inspected well. For example,
If the magnification is 5 times, the presence or absence of a defect can be inspected and the magnification is 5 times.
If the magnification is 0, the position of the defect can be specified.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to the drawings, an embodiment in which the present invention is applied to a liquid crystal device which is a typical electro-optical device will be described as an embodiment of the present invention.

(Overall Configuration of Electro-Optical Device) FIG. 1 is a plan view of a liquid crystal device according to the present embodiment as viewed from a counter substrate side. FIG. 2 is a cross-sectional view of the liquid crystal device taken along the line HH 'in FIG.

As shown in FIGS. 1 and 2, a liquid crystal device 300 used for a projection display device or the like has a TFT in which pixel electrodes 9 are formed in a matrix on the surface of an insulating substrate 10 such as quartz glass or heat-resistant glass. An array substrate 200 (active matrix substrate), a counter substrate 100 in which a counter electrode 32 is formed on the surface of an insulating substrate 41 also made of quartz glass or heat-resistant glass, and an electro-optical material sealed and sandwiched between these substrates And a liquid crystal 39.

TFT array substrate 200 and counter substrate 100
Are bonded together via a predetermined gap (cell gap) by a gap material-containing sealing material 59 formed along the outer peripheral edge of the counter substrate 100. Between the TFT array substrate 200 and the opposing substrate 100, a liquid crystal sealing region 40 is defined by a sealing material 59 containing a gap material, and a liquid crystal 39 is sealed in the liquid crystal sealing region 40.

The opposing substrate 100 is a TFT array substrate 200
Smaller, the peripheral portion of the TFT array substrate 200 is
It is in a state of protruding from the outer peripheral edge of the counter substrate 100. Accordingly, the driving circuits (the scanning line driving circuit 70 and the data line driving circuit 60) and the input / output terminals 45 of the TFT array substrate 200 are exposed from the counter substrate 100. Here, since the sealing material 59 is partially interrupted, the liquid crystal injection port 241 is formed by the interrupted portion. For this reason,
After the opposing substrate 100 and the TFT array substrate 200 are bonded to each other, if the inner region of the sealing material 59 is decompressed,
The liquid crystal 39 can be injected under reduced pressure from the liquid crystal
After sealing 9, the liquid crystal injection port 241 may be closed with a sealant 242.

A sealing material 5 is provided on the TFT array substrate 200.
A light-shielding film 55 for cutting off the image display area 11 is formed inside the formation area 9. Further, a light-shielding film 57 is formed on the counter substrate 100 in a region corresponding to a boundary region between the pixel electrodes 9 of the TFT array substrate 200.

A polarizing plate (not shown) or the like is provided on the light incident side or light exit side of the opposing substrate 100 and the TFT array substrate 200 according to the normally white mode / normally black mode. It is arranged in the direction of.

In the liquid crystal device 300 configured as described above, the TFT array substrate 200 uses the image signal applied to the pixel electrode 9 via a data line (not shown) and a pixel switching TFT (described later) to generate a pixel. The alignment state of the liquid crystal 39 between the electrode 9 and the counter electrode 32 is controlled for each pixel, and a predetermined image corresponding to an image signal is displayed. Therefore, in the TFT array substrate 200, it is necessary to supply an image signal to the pixel electrode 9 via the data line and the TFT 50, and also apply a predetermined potential to the counter electrode 32. Therefore, in the liquid crystal device 300, a portion of the surface of the TFT array substrate 200 facing each corner of the counter substrate 100 is formed of an aluminum film or the like for vertical conduction with the help of a process of forming a data line or the like. One electrode 47 is formed. On the other hand, the opposite substrate 10
A second electrode 48 for vertical conduction made of an ITO (Indium Tin Oxide) film or the like is formed at each of the corners 0 with the help of the formation process of the counter electrode 4. Further, the first electrode 47 and the second electrode 48 for vertical conduction are electrically connected by a conductive material 56 in which conductive particles such as silver powder and gold-plated fiber are mixed with an epoxy resin adhesive component. are doing. Therefore, in the liquid crystal device 300, the TFT array substrate 2 can be connected only to the TFT array substrate 200 without connecting a flexible wiring substrate or the like to each of the TFT array substrate 200 and the counter substrate 100.
A predetermined signal can be inputted to both the counter substrate 100 and the counter substrate 100.

(Overall Configuration of TFT Array Substrate 200) FIG. 3 shows the TFT array substrate 200 used in the liquid crystal device 300.
FIG. 3 is a block diagram schematically showing the configuration of FIG.

As shown in FIG. 3, the driving circuit built-in type TF
In the T-array substrate 200, pixel electrodes 9 that are connected to a plurality of scanning lines 7 and a plurality of data lines 6 that intersect with each other via a TFT for pixel switching described later are formed in a matrix on the insulating substrate 10. ing. The scanning lines 7 are made of a tantalum film, an aluminum film, an aluminum alloy film, or the like, and the data lines 6 are made of an aluminum film or an aluminum alloy film, each of which is a single layer or stacked. The region where the pixel electrode 9 and the TFT for pixel switching are formed functions as the pixel 22, and the region where the pixels 22 are arranged in a matrix is the image display region 11.

Image display area 11 on insulating substrate 10
A data line driving circuit 60 that supplies an image signal to each of the plurality of data lines 6 is formed in an outer region (peripheral portion) of the data line. In addition, each of both ends of the scanning line 7 includes
A scanning line driving circuit 70 that supplies a scanning signal for pixel selection to each scanning line 7 is configured. These drive circuits are configured using drive circuit TFTs formed at the same time as pixel switching TFTs.

The data line driving circuit 60 includes an X-side shift register circuit and a TFT as an analog switch that operates based on a signal output from the X-side shift register circuit.
, And six image signal lines 67 corresponding to each image signal developed in six phases. In this example, the data line driving circuit 60
The X-side shift register circuit has four phases, and a start signal, a clock signal, and its inverted clock signal are supplied from the outside via the input / output terminal 45 to the X-side shift register circuit. The data line driving circuit 60 is driven. Accordingly, in the sample hold circuit 66, each TFT operates based on the signal output from the X-side shift register circuit, and the image signal line 6
An image signal supplied via the gate 7 can be taken into the data line 6 at a predetermined timing and supplied to each pixel electrode 9.

On the other hand, a start signal, a clock signal, and its inverted clock signal are externally supplied to the scanning line driving circuit 70 via terminals, and the scanning line driving circuit 70 is driven by these signals.

In the TFT array substrate 200 of this embodiment, the data line driving circuit 6
In the side portion on the 0 side, a large number of conductive films such as a metal film such as an aluminum film, a metal silicide film, or an ITO film to which a constant power source, a modulated image signal (image signal), various drive signals and the like are input are provided. An output terminal 45 is configured.
A plurality of signal wirings 73 and 74 for driving the scanning line driving circuit 60 and the data line driving circuit 70 are routed from these input / output terminals 45, respectively. Made of a low-resistance metal film.

(Configuration of Pixel and Drive Circuit) FIG. 4
(A) and (B) are an equivalent circuit diagram of the pixel 22 of the TFT array substrate 200 shown in FIG.
FIG. 2 is a plan view of FIG.

In FIG. 4A, each pixel 22 has a pixel switching TFT 1C connected to the scanning line 7 and the data line 6, and a pixel electrode 9 electrically connected to the TFT 1C. Further, a capacitance line 75 is formed toward each pixel 22, and a storage capacitance 23 is formed in each pixel electrode 9 using the capacitance line 75.

Such a pixel 22 is, for example, shown in FIG.
The configuration is as shown in FIG. In FIG. 4B,
In each pixel 22, a plurality of transparent pixel electrodes 9 made of an ITO film or the like are formed in a matrix. Along the vertical and horizontal boundaries of the pixel electrode 9, the data lines 6,
In addition, the capacitance line 75 is formed together with the scanning line 7. The data line 6 is electrically connected to the source region of the TFT 1C in the semiconductor film 20C made of a polysilicon film or the like via a contact hole. Also, T
The scanning line 7 extends as a gate electrode so as to face the channel region of the FT1C. The storage capacity 23 is T
A semiconductor electrode corresponding to an extended portion of the semiconductor film 20C for forming the FT1C30, which is made conductive, is used as a lower electrode,
The lower electrode has a structure in which a capacitance line 75 overlaps as an upper electrode.

FIGS. 5A and 5B show two stages of Cs constituting the data line driving circuit 60 and the scanning line driving circuit 70, respectively.
It is an equivalent circuit diagram of a MOS inverter and an explanatory diagram showing an enlarged example of a planar structure of a CMOS inverter circuit.

As shown in FIG. 5A, in the data line driving circuit 60 and the scanning line driving circuit 70, an N-type TFT 1
The CMOS circuit 81 is constituted by the A and P-type TFTs 1B. Such a CMOS circuit 81 constitutes an inverter circuit with one stage or two or more stages. In this CMOS inverter circuit 80 (TFT circuit), as shown in FIG. 5B, in any P-type TFT 1B constituting the CMOS circuit 81 in each stage, one of the source / drain regions 12B has a voltage Vdd. Is electrically connected to a wiring layer 801 made of an aluminum layer through a contact hole 19, and in any N-type TFT 1A, one of the source / drain regions 12A has a voltage Vs
It is electrically connected via a contact hole 19 to a wiring layer 802 made of an aluminum layer to which s is supplied.

The N-type and P-type TFTs 1 of each stage
A gate electrode 15A made of aluminum layers B and 1B;
15B is electrically connected to the input / output wiring layer 803 via the contact hole 19, and the wiring layer 803 is formed of N-type and P-type TFTs constituting the CMOS circuit 81 in the preceding stage.
1B and 1B, the source region 12A of the N-type TFT 1A.
And a drain region 12B of the P-type TFT 1B via a contact hole 19.

(Cross-Sectional Structure of TFT Array Substrate) FIG.
TFTs 1A and 1B formed on the TFT array substrate 200,
It is sectional drawing of 1C and input / output terminal 45.

As described with reference to FIGS. 4 and 5, in the TTFT array substrate 200, a large number of TFTs are formed in the pixel 22 and the driving circuits 60 and 70 at high density. It can be built in the manufacturing process.

FIGS. 7 and 8 show these TFTs.
The detailed structure will be described while explaining the manufacturing method with reference to FIG. 9 and FIG. 9. As shown in FIG. 6, in the N-type TFT 1A for the drive circuit, the interlayer insulating film 5 made of a silicon oxide film is used.
1 has a structure in which a wiring layer 802 located on the upper layer side is electrically connected to the source / drain region 12A as a source / drain electrode via the contact hole 19 of the interlayer insulating film 51. In the P-type TFT 1B, the interlayer insulating film 5
1 has a structure in which a wiring layer 801 located on the upper layer side is electrically connected to the source / drain region 12B as a source / drain electrode via the contact hole 19 of the interlayer insulating film 51. An N-type TFT 1A and a P-type TF
Between T1B, the wiring layer 803 located on the upper layer side of the interlayer insulating film 51 serves as a source / drain electrode via the contact hole 19 of the interlayer insulating film 51 and the source region 12A of the N-type TFT 1A and the drain region of the P-type TFT 1B. 12B
Are electrically connected to both.

In the pixel TFT 1C, the data line 90 and the drain electrode 18 located on the upper layer side of the interlayer insulating film 51 are electrically connected to the source / drain regions 12C via the contact holes 19 of the interlayer insulating film 51, respectively. The pixel electrode 9 located on the upper layer side of the interlayer insulating film 52 is
It is electrically connected to the drain electrode 18 via the contact hole 96 of the interlayer insulating film 52. Note that a base protective film 11 made of a silicon oxide film is formed on the front side of the insulating substrate 10.

The input / output terminal 45 is connected to a lower electrode 451 formed simultaneously with the scanning line 7 on the lowermost layer side, and a data line 6.
And an ITO electrode 453 formed simultaneously with the pixel electrode 9.

As described above, the TFT array substrate 20 used as a drive circuit built-in type active matrix substrate
In the case of 0, a large number of TFTs 1A, 1B, 1C are formed, and various wirings are formed in multiple layers via interlayer insulating films 51, 52. Therefore, the TFT array substrate 2
In the case of 00, in addition to the problems caused by the TFTs 10A, 10B, and 10C, there is a possibility that a problem caused by a short circuit between the wirings may occur. Therefore, in the present embodiment, by configuring the manufacturing method as described below,
The inspection of the TFT array substrate 200 is performed efficiently.

(Liquid Crystal Device Manufacturing Method / Element Forming Step) T
An example of a method for forming the TFTs 1A, 1B, 1C and the input / output terminals 45 on the FT array substrate 200 will be described with reference to FIGS. 7, 8, and 9.

First, as shown in FIG. 7A, a silicon oxide film having a thickness of about 2000 Å is formed on a glass insulating substrate 10 by plasma CVD using TEOS (tetraethoxysilane), oxygen gas or the like as a source gas. A base protective film 11 made of a film is formed. Next, the substrate 10
Is set to 350 ° C., and a semiconductor film 20 made of an amorphous silicon film having a thickness of about 600 angstroms is formed on the surface of the base protective film 11 by a plasma CVD method. Next, a crystallization step such as laser annealing or a solid phase growth method is performed on the semiconductor film 20 made of an amorphous silicon film to crystallize the semiconductor film 20 to a polysilicon film.

Next, as shown in FIG. 7B, the semiconductor film 20 which has become a polysilicon film is patterned by using a photolithography technique, and the semiconductor films 20A, 20B, 20
Form C. The semiconductor films 20A, 20B, and 20C are an N-type TFT 1A for a drive circuit and a P
It is an island-shaped semiconductor film for forming a TFT 1B of a type and a TFT 1C for a pixel. During the previous steps, T
A low concentration impurity may be introduced in order to adjust the threshold value of FT.

Next, as shown in FIG.
On the surfaces of 0A, 20B, and 20C, a gate insulating film 13 made of a silicon oxide film having a thickness of about 1000 angstroms is formed by a plasma CVD method using TEOS (tetraethoxysilane), oxygen gas, or the like as a source gas.

Next, as shown in FIG. 7D, the entire area where the P-type TFT 1B for the driving circuit is to be formed is covered, and the N-type TFT 1A for the driving circuit and the TF for the pixel are formed.
A resist mask 91A is formed to slightly cover the T1C gate electrode formation region, and in this state, the semiconductor film 20A is formed.
Phosphorus ion (N-type impurity) about 2 × for A and 20C
It is introduced at a dose of 10 ¹⁵ cm ^-2 . As a result, regions of the semiconductor films 20A and 20C into which phosphorus ions have been implanted become high-concentration source / drain regions 122A and 122C.

Next, as shown in FIG. 7E, the N-type TFT 1A for the drive circuit and the entire area where the TFT 1C for the pixel is to be formed are covered, and the P-type TF for the drive circuit is covered.
A resist mask 91B is formed to slightly cover the gate electrode formation region of T1B, and in this state, the semiconductor film 20B is formed.
About 2 × 10 ¹⁵ c of boron ions (P-type impurity)
It is introduced at a dose of m- ² . As a result, the semiconductor film 20B
The region into which boron ions are implanted becomes the high concentration source / drain region 122B.

Next, as shown in FIG.
A rapid heating process using an arc lamp is performed on 0A, 20B, and 20C to activate the impurities introduced into the semiconductor films 20A, 20B, and 20C (rapid heating process step).

After the rapid heating process is completed, a conductive film 73 made of a metal film such as aluminum or tantalum is formed by a sputtering method as shown in FIG. ).

Next, as shown in FIG.
After a resist mask 92 is formed on the surface of FIG.
Then, the conductive film 73 is patterned to form the gate electrodes 15A and 15B of each TFT and the scanning line 7 as shown in FIG.
A base electrode 451 is formed in a region where the input / output terminal 45 is formed.

Next, as shown in FIG.
Covering the entire area where the P-type TFT 1B is to be formed
After forming the mask 93A, the temperature of the substrate 10 is set to 350 ° C.
Phosphine diluted with hydrogen gas (PH
_Three ) To reduce the concentration of phosphorus ions (N-type impurities)
About 1 × 10¹³cm^-2(Low concentration N-type)
Impurity introduction step). Hydrogen ions are applied to the semiconductor films 20A and 20C.
On is also about 2 × 10¹³cm ^-2Is introduced at a dose of. Unfortunate
The portion where the pure substance is not introduced is the channel region 17A, 1
7C. As a result, the drive circuit is mounted on the same insulating substrate 10.
N-type TFT 1A for road and N-type TFT for pixel
1C, and these TFTs have a source / drain
Gate regions 15A and 15C
Low-concentration source / drain regions 1
An LDD structure including 21A and 121C is obtained. like this
If the step of introducing a low concentration N-type impurity is omitted, the TFT 1
A and 1C have an offset gate structure.

Next, as shown in FIG. 8E, after forming an N-type TFT 1A for a driving circuit and a resist mask 93B covering the TFT 1C for a pixel, the temperature of the insulating substrate 10 is set to 350 ° C. And using diborane (B ₂ H ₆ ) diluted with hydrogen gas or the like to reduce the concentration of boron ions (P
Is introduced at a dose of about 1 × 10 ¹³ cm ⁻² . Hydrogen ions are also about 2 × 10 ¹³ cm in the semiconductor film 20B.
Introduced at a dose of ^-2 . The portion where the impurities are not introduced becomes the channel region 17B. As a result, a P-type TFT 1B for a drive circuit is formed on the insulating substrate 10. This TFT has a low-concentration source / drain region 121B in a portion of the source / drain region 12B facing the end of the gate electrode 15B. LDD structure provided. If the step of introducing such a low concentration P-type impurity is omitted, the TFT 1
B will have an offset gate structure.

Next, heat treatment is performed in a forming gas,
Low concentration source / drain regions 121A, 121B, 12
After activating the low-concentration impurities introduced into 1C, FIG.
As shown in (F), an interlayer insulating film 51 made of a silicon oxide film having a thickness of about 5000 Å is formed by a plasma CVD method using TEOS (tetraethoxysilane), oxygen gas or the like as a source gas.

Next, as shown in FIG.
A contact holes 19 are formed in the interlayer insulating film 51 in the formation regions of A, 1B, and 1C, and the input / output terminals 4
The contact hole 19 is also formed in the formation region of No. 5.

Next, as shown in FIG. 9B, after forming a metal film 600 such as an aluminum film,
0 is patterned to form wiring layers 801, 802, 803, data lines 6, and drain electrodes 18, as shown in FIG. 9C. Further, an aluminum electrode 452 is formed in a region where the input / output terminal 45 is formed.

Next, as shown in FIG.
An interlayer insulating film 52 made of a silicon oxide film having a thickness of about 5000 angstroms is formed by a plasma CVD method using (tetraethoxysilane), oxygen gas or the like as a source gas.

Next, as shown in FIG. 9E, a contact hole 96 reaching the drain electrode 18 is formed in the interlayer insulating film 52. Further, an opening 97 for exposing the aluminum electrode 452 to a large area is formed in a region where the input / output terminal 45 is formed.

Next, as shown in FIG.
After the 00 is formed, the ITO film 900 is patterned to form the pixel electrode 9 as shown in FIG. Also,
An ITO electrode 453 is formed in a region where the input / output terminal 45 is formed. As a result, the input / output terminal 45 is completed.

(Liquid Crystal Device Manufacturing Method / TFT Array Substrate Inspection Step) Thus, the TFT array substrate 200
After forming the TFTs 1A, 1B, 1C and the input / output terminals 45, an inspection process for the TFT array substrate 200 is performed. In this inspection step, in the present embodiment, the flexible wiring board 99 shown in FIG. 1 is connected to the input / output terminals 45 of the TFT array substrate 200 or an inspection probe is applied, and power is supplied from the input / output terminals 45 to the input / output terminals 45. Supplying a signal to the data line driving circuit 60 and the scanning line driving circuit 70;
A scanning signal for turning on all the pixel switching TFTs 10C is output to the scanning line 7 and a lighting level signal is output to all the data lines 6. Also,
In this state, the surface of the TFT array substrate 200 is imaged with a high sensitivity CCD of an emission microscope at a magnification of 5 to 50 times, and the data line driving circuit 6 of the TFT array substrate 200 is taken.
0, T in the scanning line driving circuit 70 and the image display area 11.
Observe whether the FTs 1A, 1B and 1C emit light. At this time, if the magnification is 5 times, the presence or absence of light emission (the presence or absence of a defect) can be confirmed, and if the magnification is 50 times, the position of the defect can be specified.

In such an inspection process, the TFTs 10A, 10B, 10C formed on the TFT array substrate 200
If a defect such as a leak or hot carrier occurs in the device, very weak light emission having a wavelength in the visible region to the near infrared region occurs, and even such a weak light emission phenomenon can be detected by an emission microscope. . Further, according to the emission microscope, it is possible to detect a short circuit caused by dielectric breakdown of the interlayer insulating films 51 and 52. In addition, the position where the cause of the lighting abnormality found when performing the lighting inspection in the liquid crystal device 300 is coincident with the position where light emission is observed by the emission microscope. For example, the T
When light emission is observed in the FTs 10A and 10B, the inspection result by the emission microscope and the defect in the liquid crystal device 300 correspond, for example, a line defect occurs when a lighting inspection is performed in the liquid crystal device 300. Therefore, according to this inspection method, the quality of the liquid crystal device 300 can be inspected in the state of the transistor array substrate 200. Therefore, in the method of performing the lighting inspection after the completion of the liquid crystal device 300, it is necessary to discard the entire liquid crystal device 300 even if the TFT array substrate 200 has a defect. If there is a defective TFT
Only the array substrate 200 needs to be discarded, and the liquid crystal device 30
There is no need to discard the whole 0. Therefore, it is possible to avoid a problem that the man-hour spent after manufacturing the liquid crystal and other materials or the TFT array substrate 200 is wasted.

If the inspection magnification is 5 times, the presence or absence of light emission (the presence or absence of a defect) can be confirmed. If the magnification is 50 times, the position of the defect can be specified. If so, the TFT array substrate 20 for the liquid crystal device
Even if a large object such as 0 is to be inspected, it can be inspected in 30 seconds to 1 minute, so that in-line conversion is easy.

In this embodiment, since the input / output terminal 45 has a laminated structure of the aluminum electrode 452 and the ITO electrode 453, the inspection process is performed after all the semiconductor processes are completed. An inspection step may be performed at the time of formation. The present invention can of course be applied to the case where the input / output terminal 45 is formed of an aluminum terminal.

(Manufacturing Method / Assembly Process of Liquid Crystal Device) For the TFT array substrate 200 determined to be non-defective in the inspection process, after forming an alignment film and performing a rubbing process,
As described with reference to FIGS. 1 and 2, a sealing material 59 is applied to one of the TFT array substrate 200 and the counter substrate 100, and the TFT array substrate 200 and the counter substrate 100 are bonded by the sealing material 59. Match. Thereafter, the liquid crystal injection port 24, which is a break in the sealing material 59, is provided between the TFT array substrate 200 and the opposing substrate 100.
After injecting the liquid crystal 39 from No. 1, the cut-off portion is
Close with 2. After the panel is completed in this manner, a liquid crystal device 300 is completed by attaching a polarizing plate or the like.

For such a liquid crystal device 300, lighting inspection or the like as a finished product is performed.
Since the T array substrate 200 has been inspected by the emission microscope, the defect rate of the liquid crystal device 300 can be significantly reduced.

(Other Embodiments) The present invention is not limited to the above embodiments, but can be implemented in variously modified forms within the scope of the present invention. For example, the present invention is not limited to the above-described liquid crystal device, but can also be applied to a TFT array substrate used for an electro-optical device such as an electroluminescence or a plasm display device.

[0061]

As described above, according to the present invention, it is possible to effectively inspect a transistor array substrate for defects using an emission microscope without assembling an electro-optical device. Therefore, when a failure occurs in the TFT array substrate, only the TFT array substrate needs to be discarded, and there is no need to discard the entire electro-optical device. Therefore, the cost of the electro-optical device can be reduced.

[Brief description of the drawings]

FIG. 1 is a plan view of a liquid crystal device to which the present invention is applied, as viewed from a counter substrate side.

FIG. 2 is a cross-sectional view of the liquid crystal device taken along the line HH ′ in FIG.

FIG. 3 is a block diagram of a TFT array substrate used in the liquid crystal device shown in FIG.

4A and 4B are TFTs shown in FIG. 3, respectively.
FIG. 2 is an equivalent circuit diagram of a pixel on an array substrate and a plan view thereof.

5A and 5B are TFTs shown in FIG. 3, respectively.
FIG. 3 is an equivalent circuit diagram of a two-stage CMOS inverter forming a data line driving circuit and a scanning line driving circuit on an array substrate, and an enlarged explanatory view showing an example of a planar structure of the CMOS inverter circuit.

FIG. 6 shows a TFT formed on the TFT array substrate shown in FIG.
And FIG.

FIG. 7 is a process sectional view illustrating the method of manufacturing the TFT array substrate illustrated in FIG.

8 is a process cross-sectional view of each process performed after the process illustrated in FIG. 7;

9 is a process cross-sectional view of each process performed after the process illustrated in FIG. 8;

[Explanation of symbols]

Reference Signs List 1A N-type TFT for drive circuit 1B P-type TFT for drive circuit 1C TFT for pixel switching 6 Data line 7 Scan line 9 Pixel electrode 10, 41 Insulating substrate 11 Image display area 22 Pixel 32 Counter electrode 39 Liquid crystal (electro-optical material) ) 40 liquid crystal sealing area 45 input / output terminal 60 data line driving circuit 70 scanning line driving circuit 75 capacitance line 99 flexible wiring substrate 100 counter substrate 200 TFT array substrate (active matrix substrate) 300 liquid crystal device (electro-optical device) 241 liquid crystal injection port 242 Sealant 451 Base electrode 452 Aluminum electrode 453 ITO electrode

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H088 FA11 FA30 HA06 HA08 MA20 2H092 GA29 GA50 JA05 JA24 JA37 JA41 JA46 JB22 JB31 JB67 KB25 MA05 MA07 MA13 MA30 NA29 NA30 PA06 5F110 AA24 BB02 CC02 DD02 DD03 DD13 EE03 02 FF04 GG02 GG13 GG25 GG32 GG45 HJ01 HJ02 HJ04 HJ12 HJ23 HL03 HM15 NN03 NN04 NN23 NN35 NN72 PP03 QQ11 QQ30

Claims (4)

[Claims] 1. A method for manufacturing a transistor array substrate having a thin film transistor circuit and a terminal electrically connected to the thin film transistor circuit on a substrate, comprising: forming an element forming the thin film transistor circuit and the terminal on the substrate; Step, after performing the element forming step, observing light emission on the transistor array substrate when power or a signal is supplied to the thin film transistor circuit through the terminal using an emission microscope, and based on the observation result. An inspection step of inspecting whether there is a defect in the transistor array substrate. 2. A method for manufacturing an electro-optical device using a transistor array substrate manufactured by the method according to claim 1, wherein the transistor is determined to be non-defective in the inspection step after performing the inspection step. A method of manufacturing an electro-optical device, comprising performing an assembling step of assembling the electro-optical device using an array substrate. 3. The element forming step according to claim 2, wherein the thin film transistor circuit as a driving circuit and a plurality of scanning lines and a plurality of data lines supplied with signals from the thin film transistor circuit are formed on the substrate. In addition, a pixel switching thin film transistor electrically connected to the scanning line and the data line, respectively, and a pixel electrode electrically connected to the pixel switching thin film transistor are formed in a matrix, and in the assembling step, Attaching an opposing substrate to the transistor array substrate determined to be non-defective in the inspection step via a predetermined gap, and then filling an electro-optical material between the opposing substrate and the transistor array substrate. A method for manufacturing an electro-optical device. 4. The method of manufacturing an electro-optical device according to claim 3, wherein a magnification when observing with an emission microscope in the inspection step is in a range of 5 to 50 times.