JP2022001911A - Display device - Google Patents

Abstract

To provide a display device that can suppress increasing of pixel size and easily perform repairing of a defective pixel.SOLUTION: A display device comprises: a substrate; a plurality of pixels that are provided on the substrate; and a plurality of light-emitting elements that are provided on each of the plurality of pixels. And, at least one pixel comprises: a plurality of first mounting electrodes electrically connected to an anode electrode; a face-up type plurality of first light-emitting elements mounted on each of the plurality of first mounting electrodes; a second mounting electrode that are provided by being adjacent to the plurality of first mounting electrodes and electrically connected to a cathode electrode; and a flip-chip type second light-emitting element mounted on the first mounting electrode and the second mounting electrode.SELECTED DRAWING: Figure 6

Description

The present invention relates to a display device.

A display device using a minute-sized light emitting diode (micro LED) as a display element is attracting attention (see, for example, Patent Documents 1 and 2). A display device using a light emitting diode is difficult to manufacture due to the small size of the light emitting diode, such as mounting the light emitting diode on a substrate, and tends to cause a defect of the light emitting diode. Patent Documents 1 to 3 describe a pixel structure having redundancy and a method of repairing defective pixels.

U.S. Patent Application Publication No. 2017/0061842 Japanese Unexamined Patent Publication No. 2018-010309 U.S. Patent Application Publication No. 2017/0346011

In such a display device, it is necessary to provide a large number of light emitting elements and circuits in order to ensure redundancy, and the pixel size may increase. Further, when a defective light emitting diode is detected and a light emitting diode for repair is mounted, a step of removing the defective light emitting diode is required, which makes it difficult to easily repair the defective pixel. In some cases.

An object of the present invention is to provide a display device capable of suppressing an increase in pixel size and easily repairing defective pixels.

The display device of one aspect of the present invention includes a substrate, a plurality of pixels provided on the substrate, and a plurality of light emitting elements provided in each of the plurality of the pixels, and at least one of the pixels is a display device. A plurality of first mounting electrodes electrically connected to the anode electrode, a plurality of face-up type first light emitting elements mounted on each of the plurality of first mounting electrodes, and a plurality of the first mounting electrodes. It has a second mounting electrode provided adjacent to each other and electrically connected to the cathode electrode, and a flip-tip type second light emitting element mounted on the first mounting electrode and the second mounting electrode.

FIG. 1 is a plan view schematically showing a display device according to an embodiment. FIG. 2 is a plan view showing a plurality of pixels. FIG. 3 is a circuit diagram showing a pixel circuit. FIG. 4 is a cross-sectional view taken along the line IV-IV'of FIG. FIG. 5 is a plan view showing a pixel on which a second light emitting element for repair is mounted. FIG. 6 is a sectional view taken along the line VI-VI'of FIG. FIG. 7 is an explanatory diagram for explaining a repair method of the display device according to the embodiment. FIG. 8 is a block diagram showing a configuration example of the repair system of the display device according to the embodiment. FIG. 9 is a plan view showing a plurality of pixels of the display device according to the first modification. FIG. 10 is a plan view showing a plurality of pixels of the display device according to the second modification. FIG. 11 is a plan view showing a plurality of pixels of the display device according to the third modification. FIG. 12 is a plan view showing a plurality of pixels of the display device according to the fourth modification. FIG. 13 is a plan view showing a plurality of pixels of the display device according to the fifth modification.

An embodiment (embodiment) for carrying out the present invention will be described in detail with reference to the drawings. The present invention is not limited to the contents described in the following embodiments. In addition, the components described below include those that can be easily assumed by those skilled in the art and those that are substantially the same. Furthermore, the components described below can be combined as appropriate. It should be noted that the disclosure is merely an example, and those skilled in the art can easily conceive of appropriate changes while maintaining the gist of the invention, which are naturally included in the scope of the present invention. Further, in order to clarify the explanation, the drawings may schematically represent the width, thickness, shape, etc. of each part as compared with the actual embodiment, but this is just an example, and the interpretation of the present invention is used. It is not limited. Further, in the present specification and each figure, the same elements as those described above with respect to the above-mentioned figures may be designated by the same reference numerals, and detailed description thereof may be omitted as appropriate.

In the present specification and the scope of patent claims, when expressing an aspect of arranging another structure on one structure, when the term "above" is simply used, the structure shall be used unless otherwise specified. It includes both the case where another structure is placed directly above the structure so as to be in contact with each other and the case where another structure is placed above one structure via another structure.

(Embodiment)
FIG. 1 is a plan view schematically showing a display device according to an embodiment. As shown in FIG. 1, the display device 1 includes an array substrate 2, a pixel Pix, a drive circuit 12, a drive IC (Integrated Circuit) 210, and a cathode wiring 60. The array board 2 is a drive circuit board for driving each pixel Pix, and is also called a backplane or an active matrix board. The array substrate 2 has a substrate 21, a plurality of transistors, a plurality of capacitances, various wirings, and the like.

As shown in FIG. 1, the display device 1 has a display area AA and a peripheral area GA. The display area AA is an area that is arranged so as to overlap with the plurality of pixels Pix and displays an image. The peripheral region GA is an region that does not overlap with the plurality of pixels Pix, and is arranged outside the display region AA.

The plurality of pixels Pix are arranged in the first direction Dx and the second direction Dy in the display area AA of the substrate 21. The first direction Dx and the second direction Dy are directions parallel to the surface of the substrate 21. The first direction Dx is orthogonal to the second direction Dy. However, the first direction Dx may intersect with the second direction Dy without being orthogonal to each other. The third direction Dz is a direction orthogonal to the first direction Dx and the second direction Dy. The third direction Dz corresponds to, for example, the normal direction of the substrate 21. In the following, the plan view indicates the positional relationship when viewed from the third direction Dz.

The drive circuit 12 has a plurality of gate lines (for example, a reset control signal line L5, an output control signal line L6, a pixel control signal line L7, and an initialization control signal line L8 (see FIG. 3) based on various control signals from the drive IC 210. )) Is a circuit that drives. The drive circuit 12 sequentially or simultaneously selects a plurality of gate lines and supplies a gate drive signal to the selected gate lines. As a result, the drive circuit 12 selects a plurality of pixels Pix connected to the gate line.

The drive IC 210 is a circuit that controls the display of the display device 1. The drive IC 210 is mounted as a COG (Chip On Glass) in the peripheral region GA of the substrate 21. Not limited to this, the drive IC 210 may be mounted as a COF (Chip On Film) on a flexible printed circuit board or a rigid board connected to the peripheral region GA of the board 21.

The cathode wiring 60 is provided in the peripheral region GA of the substrate 21. The cathode wiring 60 is provided so as to surround the plurality of pixels Pix in the display area AA and the drive circuit 12 in the peripheral area GA. The cathodes of the plurality of first light emitting elements 3 are connected to a common cathode wiring 60, and a fixed potential (for example, a ground potential) is supplied. More specifically, the cathode terminal 32 (see FIG. 4) of the first light emitting element 3 is connected to the cathode wiring 60 via the cathode electrode 22.

FIG. 2 is a plan view showing a plurality of pixels. As shown in FIG. 2, one pixel Pix includes a plurality of pixels 49. For example, the pixel Pix has a pixel 49R, a pixel 49G, and a pixel 49B. The pixel 49R displays the primary color red as the first color. The pixel 49G displays the primary color green as the second color. Pixel 49B displays the primary color blue as the third color. As shown in FIG. 2, in one pixel Pix, the pixels 49R and the pixels 49G are arranged in the second direction Dy. Further, the pixels 49R and the pixels 49B are arranged in the first direction Dx. The first color, the second color, and the third color are not limited to red, green, and blue, respectively, and any color such as a complementary color can be selected. In the following, when it is not necessary to distinguish between the pixel 49R, the pixel 49G, and the pixel 49B, it is simply referred to as the pixel 49.

The pixel 49 has a first light emitting element 3 and a first mounting electrode 24, respectively. The display device 1 displays an image by emitting different light for each of the first light emitting elements 3R, 3G, and 3B in the pixels 49R, the pixels 49G, and the pixels 49B. The first light emitting element 3 is an inorganic light emitting diode (LED) chip having a size of about 3 μm or more and about 300 μm or less in a plan view, and is called a micro LED. The display device 1 provided with a micro LED in each pixel is also referred to as a micro LED display device. The micro of the micro LED does not limit the size of the first light emitting element 3.

The plurality of first light emitting elements 3 may emit four or more different colors of light. Further, the arrangement of the plurality of pixels 49 is not limited to the configuration shown in FIG. For example, the pixel 49R may be adjacent to the pixel 49B in the second direction Dy. Further, the pixels 49R, the pixels 49G and the pixels 49B may be repeatedly arranged in the first direction Dx in this order.

The pixel Pix further has a second mounting electrode 24S. The second mounting electrode 24S is an electrode for mounting a second light emitting element 5 (see FIG. 5) for repair, and is provided adjacent to the plurality of first mounting electrodes 24. The second mounting electrode 24S is aligned with the first mounting electrode 24G of the pixel 49G in the first direction Dx. The second mounting electrode 24S is aligned with the first mounting electrode 24B of the pixel 49B in the second direction Dy. The second mounting electrode 24S is arranged in an oblique direction intersecting the first mounting electrode 24R of the pixel 49R with the first direction Dx and the second direction Dy. Further, the second mounting electrode 24S is electrically connected to the cathode electrode 22 (see FIG. 4). The first pixel Pix-1 shown in FIG. 2 is a pixel Pix in which a plurality of first light emitting elements 3 are not defective among the plurality of pixel Pix, and a plurality of first light emitting elements 3 are mounted. It is a pixel Pix to which the second light emitting element 5 is not mounted.

FIG. 3 is a circuit diagram showing a pixel circuit. FIG. 3 shows a pixel circuit PICA provided in one pixel 49, and the pixel circuit PICA is provided in each of a plurality of pixels 49. As shown in FIG. 3, the pixel circuit PICA includes a first light emitting element 3, five transistors, and two capacitances. Specifically, the pixel circuit PICA includes a drive transistor DRT, an output transistor BCT, an initialization transistor IST, a pixel selection transistor SST, and a reset transistor RST. The drive transistor DRT, output transistor BCT, initialization transistor IST, pixel selection transistor SST, and reset transistor RST are each composed of an n-type TFT (Thin Film Transistor). Further, the pixel circuit PICA includes a first capacitance Cs1 and a second capacitance Cs2.

The cathode (cathode terminal 32) of the first light emitting element 3 is connected to the cathode power supply line L10. Further, the anode (anode terminal 33) of the first light emitting element 3 is connected to the anode power supply line L1 via the drive transistor DRT and the output transistor BCT. The anode power supply potential P VDD is supplied to the anode power supply line L1. The cathode power supply potential PVSS is supplied to the cathode power supply line L10 via the cathode wiring 60 and the cathode electrode 22. The anode power supply potential Pldap has a higher potential than the cathode power supply potential PVSS.

The anode power supply line L1 supplies the pixel 49 with the anode power supply potential P VDD, which is a driving potential. Specifically, the first light emitting element 3 is ideally supplied with a forward current (driving current) by a potential difference (P VDD-PVSS) between the anode power supply potential P whether and the cathode power supply potential PVSS to emit light. That is, the anode power supply potential P VDD has a potential difference that causes the first light emitting element 3 to emit light with respect to the cathode power supply potential PVSS. The anode terminal 33 of the first light emitting element 3 is electrically connected to the anode electrode 23, and the second capacitance Cs2 is connected as an equivalent circuit between the anode electrode 23 and the anode power supply line L1.

The source electrode of the drive transistor DRT is connected to the anode terminal 33 of the first light emitting element 3 via the anode electrode 23, and the drain electrode is connected to the source electrode of the output transistor BCT. The gate electrode of the drive transistor DRT is connected to the first capacitance Cs1, the drain electrode of the pixel selection transistor SST, and the drain electrode of the initialization transistor IST.

The gate electrode of the output transistor BCT is connected to the output control signal line L6. The output control signal BG is supplied to the output control signal line L6. The drain electrode of the output transistor BCT is connected to the anode power supply line L1.

The source electrode of the initialization transistor IST is connected to the initialization power line L4. The initialization potential Vini is supplied to the initialization power line L4. The gate electrode of the initialization transistor IST is connected to the initialization control signal line L8. The initialization control signal IG is supplied to the initialization control signal line L8. That is, the initialization power line L4 is connected to the gate electrode of the drive transistor DRT via the initialization transistor IST.

The source electrode of the pixel selection transistor SST is connected to the video signal line L2. The video signal Vsig is supplied to the video signal line L2. A pixel control signal line L7 is connected to the gate electrode of the pixel selection transistor SST. The pixel control signal SG is supplied to the pixel control signal line L7.

The source electrode of the reset transistor RST is connected to the reset power line L3. The reset power supply potential Vrst is supplied to the reset power supply line L3. The gate electrode of the reset transistor RST is connected to the reset control signal line L5. A reset control signal RG is supplied to the reset control signal line L5. The drain electrode of the reset transistor RST is connected to the anode electrode 23 (anode terminal 33 of the first light emitting element 3) and the source electrode of the drive transistor DRT. By the reset operation of the reset transistor RST, the voltage held in the first capacitance Cs1 and the second capacitance Cs2 is reset.

A first capacitance Cs1 is provided as an equivalent circuit between the drain electrode of the reset transistor RST and the gate electrode of the drive transistor DRT. The pixel circuit PICA can suppress the fluctuation of the gate voltage due to the parasitic capacitance of the drive transistor DRT and the leakage current by the first capacitance Cs1 and the second capacitance Cs2.

In the following description, the anode power line L1 and the cathode power line L10 may be simply referred to as power lines. The video signal line L2, the reset power line L3, and the initialization power line L4 may be referred to as signal lines. The reset control signal line L5, the output control signal line L6, the pixel control signal line L7, and the initialization control signal line L8 may be referred to as a gate line.

A potential corresponding to the video signal Vsig (or gradation signal) is supplied to the gate electrode of the drive transistor DRT. That is, the drive transistor DRT supplies the current corresponding to the video signal Vsig to the first light emitting element 3 based on the anode power supply potential P VDD supplied via the output transistor BCT. In this way, the anode power supply potential P VDD supplied to the anode power supply line L1 is lowered by the drive transistor DRT and the output transistor BCT, so that the anode terminal 33 of the first light emitting element 3 has a potential lower than the anode power supply potential P VDD. Is supplied.

The anode power supply potential P VDD is supplied to one electrode of the second capacitance Cs2 via the anode power supply line L1, and a potential lower than the anode power supply potential P VDD is supplied to the other electrode of the second capacitance Cs2. That is, one electrode of the second capacitance Cs2 is supplied with a higher potential than the other electrode of the second capacitance Cs2. One electrode of the second capacitance Cs2 is, for example, the counter electrode 26 connected to the anode power supply line L1 shown in FIG. 4, and the other electrode of the second capacitance Cs2 is the source of the drive transistor DRT shown in FIG. The connected anode electrode 23.

In the display device 1, the drive circuit 12 (see FIG. 1) selects a plurality of pixel rows in order from the first row (for example, the pixel row located at the top in the display area AA in FIG. 1). The drive IC 210 writes a video signal Vsig (video writing potential) to the pixels 49 of the selected pixel row, and causes the first light emitting element 3 to emit light. The drive IC 210 supplies the video signal Vsig to the video signal line L2, supplies the reset power potential Vrst to the reset power line L3, and supplies the initialization potential Vini to the initialization power line L4 every one horizontal scanning period. The display device 1 repeats these operations for each frame of the image.

Next, the cross-sectional configuration of the display device 1 will be described. FIG. 4 is a cross-sectional view taken along the line IV-IV'of FIG. As shown in FIG. 4, the first light emitting element 3 is provided on the array substrate 2. The array substrate 2 has a substrate 21, various transistors, various wirings, and various insulating films. The substrate 21 is an insulating substrate, and for example, a glass substrate, a resin substrate, a resin film, or the like is used.

In the present specification, the direction from the substrate 21 toward the first light emitting element 3 in the direction perpendicular to the surface of the substrate 21 is referred to as “upper” or simply “upper”. Further, the direction from the first light emitting element 3 toward the substrate 21 is defined as "lower side" or simply "lower side".

The drive transistor DRT and the output transistor BCT are provided on one surface side of the substrate 21. The semiconductor layers 61 and 65 are provided on the substrate 21. An undercoat film may be provided between the semiconductor layers 61 and 65 and the substrate 21. The insulating film 91 is provided on the substrate 21 so as to cover the semiconductor layers 61 and 65. The insulating film 91 is, for example, a silicon oxide film.

The gate electrodes 64 and 66 are provided on the insulating film 91. In the example shown in FIG. 4, each transistor has a so-called top gate structure. However, each transistor may have a bottom gate structure in which a gate electrode is provided on the lower side of the semiconductor layer, or a dual gate structure in which gate electrodes are provided on both the upper side and the lower side of the semiconductor layer.

The insulating film 92 is provided on the insulating film 91 so as to cover the gate electrodes 64 and 66. The insulating film 92 has, for example, a laminated structure of a silicon nitride film and a silicon oxide film. The source electrode 62, the drain electrode 67, and the anode power supply line L1 are provided on the insulating film 92. The source electrode 62 is electrically connected to the semiconductor layer 61 via a contact hole penetrating the insulating films 91 and 92. Further, the drain electrode 67 is electrically connected to the semiconductor layer 65 via the contact holes provided in the insulating films 91 and 92.

A plurality of insulating films (first organic insulating film 93, insulating film 94, insulating film 95, and second organic insulating film 96) are provided so as to cover each transistor. As the first organic insulating film 93 and the second organic insulating film 96, an organic material such as photosensitive acrylic is used. Organic materials such as photosensitive acrylic are superior in coverage of wiring steps and surface flatness as compared with inorganic insulating materials formed by CVD or the like. The insulating film 94 and the insulating film 95 are inorganic insulating films, and the same materials as the above-mentioned insulating films 91 and 92, for example, a silicon nitride film or a silicon oxide film, can be used.

Specifically, the first organic insulating film 93 is provided on the insulating film 92 so as to cover the source electrode 62, the drain electrode 67, and the anode power supply line L1. The counter electrode 26, the insulating film 94, and the anode electrode 23 are laminated in this order on the first organic insulating film 93. The counter electrode 26 is made of a translucent conductive material such as ITO (Indium Tin Oxide). The counter electrode 26 is connected to the anode power line L1 at the bottom of the contact hole CH1 provided in the first organic insulating film 93.

The insulating film 94 is provided so as to cover the counter electrode 26. The anode electrode 23 faces the counter electrode 26 via the insulating film 94. The first organic insulating film 93 and the insulating film 94 are provided with contact holes CH2 and CH3 having a source electrode 62 as a bottom surface. The anode electrode 23 is electrically connected to the source electrode 62 via the contact holes CH2 and CH3. As a result, the anode electrode 23 is electrically connected to the drive transistor DRT.

The anode electrode 23 has, for example, a laminated structure of titanium (Ti) and aluminum (Al). However, the present invention is not limited to this, and the anode electrode 23 may be a material containing any one or more of molybdenum, titanium, and aluminum. Alternatively, the anode electrode 23 may be an alloy containing any one or more of molybdenum and titanium, or a translucent conductive material. Further, the second capacitance Cs2 is formed between the anode electrode 23 and the facing electrode 26 facing each other via the insulating film 94.

The insulating film 95 is provided on the insulating film 94 so as to cover the anode electrode 23. The second organic insulating film 96 is provided on the insulating film 95. That is, the first organic insulating film 93 is provided on the drive transistor DRT, and the second organic insulating film 96 is laminated on the upper side of the first organic insulating film 93. The insulating film 95 is provided between the first organic insulating film 93 and the second organic insulating film 96. The second organic insulating film 96 is provided with a contact hole CH4. The insulating film 95 is provided with the contact hole CH5 so as to overlap with the contact hole CH4. An anode electrode 23 is provided at the bottom of the contact holes CH4 and CH5. Further, the anode electrode 23 is provided so as to face at least a part of the first mounting electrode 24.

The first mounting electrode 24 is provided on the second organic insulating film 96 and is electrically connected to the anode electrode 23 via the contact holes CH4 and CH5. Like the anode electrode 23, the first mounting electrode 24 has a laminated structure of titanium and aluminum. However, the first mounting electrode 24 may use a conductive material different from that of the anode electrode 23. Further, as the second organic insulating film 96, an organic material different from that of the first organic insulating film 93 may be used.

The first light emitting elements 3R, 3G, and 3B are mounted on the corresponding first mounting electrodes 24R, 24G, and 24B, respectively. Each first light emitting element 3 is mounted so that the anode terminal 33 is in contact with the first mounting electrode 24. The bonding member 25 between the anode terminal 33 of each first light emitting element 3 and the first mounting electrode 24 is such that good conduction can be ensured between them and the formation on the array substrate 2 is not damaged. There is no particular limitation. The joining member 25 is, for example, solder or a conductive paste. As a bonding between the anode terminal 33 and the first mounting electrode 24, for example, a reflow process using a solder material melted at a low temperature, or a method of mounting the first light emitting element 3 on the array substrate 2 via a conductive paste and then firing and bonding. Can be mentioned.

Here, it is also possible to mount the first light emitting element 3 directly on the anode electrode 23 without providing the second organic insulating film 96 and the first mounting electrode 24 on the array substrate 2. However, by providing the second organic insulating film 96 and the first mounting electrode 24, it is possible to prevent the insulating film 94 from being damaged by the force applied when the first light emitting element 3 is mounted. That is, it is possible to suppress the occurrence of dielectric breakdown between the anode electrode 23 forming the second capacitance Cs2 and the counter electrode 26.

The first light emitting element 3 is a face-up type light emitting element, and the lower part of the first light emitting element 3 is connected to the anode electrode 23, and the upper part of the first light emitting element 3 is connected to the cathode electrode 22. The first light emitting device 3 has a semiconductor layer 31, a cathode terminal 32, and an anode terminal 33. As the semiconductor layer 31, a configuration in which an n-type clad layer 37, an active layer 36, and a p-type clad layer 35 (see FIG. 6) are laminated can be adopted. As the semiconductor layer 31, for example, a compound semiconductor such as gallium nitride (GaN), aluminum indium phosphide (AlInP), or indium gallium nitride (InGaN) is used. For the semiconductor layer 31, different materials may be used for each of the first light emitting elements 3R, 3G, and 3B. Further, as the active layer, a multiple quantum well structure (MQW structure) in which a well layer composed of several atomic layers and a barrier layer are periodically laminated may be adopted for high efficiency. Further, as the first light emitting element 3, the semiconductor layer 31 may be formed on the semiconductor substrate.

The element insulating film 97 is provided between the plurality of first light emitting elements 3. The element insulating film 97 is made of a resin material. The element insulating film 97 covers the side surface of the first light emitting element 3, and the cathode terminal 32 of the first light emitting element 3 is exposed from the element insulating film 97. The element insulating film 97 is formed flat so that the upper surface of the element insulating film 97 and the upper surface of the cathode terminal 32 form the same surface. However, the position of the upper surface of the element insulating film 97 may be different from the position of the upper surface of the cathode terminal 32. Further, the side wall of the first light emitting element 3 may be covered with a passivation film 98 (see FIG. 6) such as a silicon oxide film (SiO2) and aluminum oxide (Al2O3). In this case, for example, before covering the first light emitting element 3 with the element insulating film 97, the side wall of the light emitting element 3 and the cathode terminal 32 are covered with the passivation film 98, and then the passivation film 98 is patterned so as to expose the cathode terminal 32. This is the step of forming the element insulating film 97. Further, as will be described later, the passivation film 98 may be formed so as to cover only a specific first light emitting element 3, particularly the first light emitting element 3 in which a defect occurs and repair is required.

The cathode electrode 22 covers the plurality of first light emitting elements 3 and the element insulating film 97, and is electrically connected to the plurality of first light emitting elements 3. For the cathode electrode 22, a conductive material having translucency such as ITO is used. As a result, the light emitted from the first light emitting element 3 can be efficiently taken out to the outside. The cathode electrode 22 is electrically connected to the cathode terminals 32 of the plurality of first light emitting elements 3 mounted on the display region AA. The cathode electrode 22 is a contact portion provided outside the display area AA and is connected to the cathode wiring 60 provided on the array substrate 2 side.

As described above, the display device 1 using the first light emitting element 3 as the display element is configured. The display device 1 may have an overcoat layer or a cover substrate laminated on the cathode electrode 22 as needed. Further, the display device 1 may be provided with a circularly polarizing plate, a touch panel, or the like on the upper side of the cathode electrode 22.

Next, a repair method of the display device 1 will be described. FIG. 5 is a plan view showing a pixel on which a second light emitting element for repair is mounted. In the following description, as an example, a configuration of a pixel Pix (second pixel Pix-2) in which a defect has occurred in the first light emitting element 3R will be described.

As shown in FIG. 5, the second pixel Pix-2 has a second light emitting element 5R in addition to the plurality of first light emitting elements 3. In the second pixel Pix-2, the first light emitting element 3R in which the defect has occurred is subjected to the blinding process and does not emit red light. The second light emitting element 5R is a light emitting element for repair, and emits red light in place of the first light emitting element 3R in which a defect has occurred. That is, the pixel 49R has a second light emitting element 5R, a first mounting electrode 24R, and a second mounting electrode 24S. The second light emitting element 5R is a flip-chip type light emitting element, and is mounted on the first mounting electrode 24R and the second mounting electrode 24S. Specifically, the p-type electrode 54 (see FIG. 6) on one end side of the second light emitting element 5R is electrically connected to the first mounting electrode 24R, and the n-type electrode 51 on the other end side of the second light emitting element 5R. (See FIG. 6) is electrically connected to the second mounting electrode 24S.

The second light emitting element 5R is rectangular in a plan view, and the long side of the second light emitting element 5R is provided along an oblique direction inclined in the first direction Dx and the second direction Dy. The length of the long side of the second light emitting element 5R is longer than the length of one side of the first light emitting element 3.

Further, each of the first mounting electrodes 24 is provided with a connection portion 24a for repair. The connection portion 24a is provided at a position where it does not overlap with the first light emitting element 3, and is formed so as to project from one side of the first mounting electrode 24. Each of the plurality of connecting portions 24a is directed to a position close to the second mounting electrode 24S.

With such a configuration, in the second pixel Pix-2, the first light emitting element 3R in which the defect has occurred is mounted on the first mounting electrode 24R, and the spotting process is performed. It is mounted on the first mounting electrode 24R and the second mounting electrode 24S. In other words, the first light emitting element 3R and the second light emitting element 5R are mounted on the common first mounting electrode 24R.

FIG. 6 is a sectional view taken along the line VI-VI'of FIG. As shown in FIG. 6, the first light emitting element 3R is laminated on the first mounting electrode 24R and the bonding member 25 in the order of the p-type electrode 34, the p-type clad layer 35, the active layer 36, and the n-type clad layer 37. Will be done. Further, the first light emitting element 3R has a first high resistance layer 38 laminated on the n-type clad layer 37. The first high resistance layer 38 is formed of, for example, gallium nitride (GaN) which is not doped with impurities. The sheet resistance value of the first high resistance layer 38 is larger than the sheet resistance value of the n-type clad layer 37.

The first high resistance layer 38 has an area smaller than that of the n-type clad layer 37 in a plan view, and the first high resistance layer 38 is not laminated on the peripheral edge of the n-type clad layer 37. The cathode electrode 22 is provided so as to cover the first high resistance layer 38 and the n-type clad layer 37. The n-type clad layer 37 and the cathode electrode 22 are connected to each other at the peripheral edge of the upper surface of the n-type clad layer 37. In other words, the peripheral edge of the upper surface of the n-type clad layer 37 functions as the cathode terminal 32 (see FIG. 4). Further, the p-type clad layer 35, the active layer 36, and the n-type clad layer 37 correspond to the semiconductor layer 31 (see FIG. 4), and the p-type electrode 34 corresponds to the anode terminal 33 (see FIG. 4).

Note that FIG. 6 is a diagram schematically shown for explaining the connection configuration between the cathode electrode 22 and the first light emitting element 3R. As described above, the first light emitting element 3R of the second pixel Pix-2 is a light emitting element in which a defect has occurred, and is subjected to a spotting process in order to suppress unintended light emission. That is, even when the pixel circuit PICA shown in FIG. 3 is driven, no current flows through the first light emitting element 3R, and the light emitting element 3R is always in a non-lighting state. In the destructive treatment, any configuration may be adopted as long as the first light emitting element 3R is not connected to one of the anode electrode 23 and the cathode electrode 22.

Next, the defeating process will be described. As shown in FIG. 6, in the first light emitting element 3R in which a defect has occurred, the first light emitting element 3R and the cathode electrode 22 are insulated by the above-mentioned passivation film 98. That is, the passivation film 98 is patterned for the first light emitting element 3 that does not have any defects and functions normally, and an opening is formed so as to expose the cathode terminal 32 of the first light emitting element 3. Further, for the first light emitting element 3 in which a defect has occurred, an opening is not provided in the portion of the passivation film 98 that overlaps with the cathode terminal 32, and the cathode terminal 32 is covered so that the cathode terminal 32 is not connected to the cathode electrode 22. Patterning is performed such that the passivation film 98 is left.

Further, as the passivation treatment, in addition to the method of insulating the cathode electrode 22 by using the passivation film 98, it is also conceivable to destroy the first light emitting element 3 in which a defect has occurred in the laser. Even when the first light emitting element 3 in which a defect is generated by the laser is destroyed, it is preferable to cover the entire wall including the side wall of the first light emitting element 3 and the cathode terminal 32 with the passivation film 98. However, considering that debris generated by destroying the first light emitting element 3 remains on the substrate, the cathode electrode 22 and the first light emitting element 3 are used by using the passion film 98 without destroying the first light emitting element 3. It is better to insulate and to improve the yield and the production efficiency.

Further, the passivation film 98 forms openings 98a and 98b in the first mounting electrode 24 and the second mounting electrode 24S at the position where the second light emitting element 52R for repair is mounted, and the second light emitting element is formed in the openings 98a and 98b. 5R will be implemented.

Further, the passivation film 98 may be formed so as to cover only the first light emitting element 3R in which the defect has occurred. When the passivation film 98 is formed so as to cover only a specific light emitting element, particularly the first light emitting element 3R in which a defect has occurred, the passivation film 98 may be formed at a specific location by, for example, inkjet, in addition to patterning. It may be something to do.

The second light emitting element 5R has an n-type electrode 51 and a p-type electrode 54 that are electrically connected to the array substrate 2. The n-type electrode 51 and the p-type electrode 54 are arranged on the lower surface side of the second light emitting element 5R and are provided so as to face the array substrate 2. The n-type electrode 51 is electrically connected to the second mounting electrode 24S via the connecting portion 52 and the joining member 25S. The p-type electrode 54 is electrically connected to the first mounting electrode 24R via the joining member 25.

More specifically, the second light emitting element 5R is arranged so as to straddle the first mounting electrode 24R and the second mounting electrode 24S. The second light emitting element 5R is laminated on the first mounting electrode 24R and the bonding member 25 in the order of the p-type electrode 54, the p-type clad layer 55, the active layer 56, and the n-type clad layer 57. The n-type clad layer 57 extends to a position where it overlaps with the second mounting electrode 24S, and the n-type electrode 51 is provided on the surface of the n-type clad layer 57 facing the array substrate 2. The n-type electrode 51 is connected to the joining member 25S provided on the second mounting electrode 24S via the connecting portion 52.

Further, the second light emitting element 5R has a second high resistance layer 58 laminated on the n-type clad layer 57. The second high resistance layer 58 is provided so as to cover the entire upper surface of the n-type clad layer 57. The second high resistance layer 58 is formed of, for example, gallium nitride (GaN) which is not doped with impurities. The sheet resistance value of the second high resistance layer 58 is larger than the sheet resistance value of the n-type clad layer 57.

The element insulating film 97 is provided between the adjacent first light emitting element 3 and the second light emitting element 5R. Further, the element insulating film 97 is also provided between the n-type electrode 51 and the connection portion 52 of the second light emitting element 5R and the p-type electrode 54. Further, the element insulating film 97 is also provided between the first mounting electrode 24R and the second mounting electrode 24S. As a result, the insulation between the anode and the cathode of the second light emitting element 5R is ensured. An insulating material such as an air layer may be provided between the first mounting electrode 24R and the second mounting electrode 24S instead of the element insulating film 97.

The cathode electrode 22 is provided so as to cover the element insulating film 97, the first high resistance layer 38, and the second high resistance layer 58. The second high resistance layer 58 is provided so as to cover the entire upper surface of the n-type clad layer 57, and is laminated between the cathode electrode 22 and the n-type clad layer 57.

The element insulating film 97 is provided with a contact hole CH 6 in a region overlapping with the second mounting electrode 24S. The cathode electrode 22 is electrically connected to the second mounting electrode 24S at the bottom of the contact hole CH6 via the joining member 25S. When the passivation film 98 is provided so as to cover the joining member 25S and the second mounting electrode 24S, an opening 98c is formed in the passivation film 98 at a position where it overlaps with the contact hole CH 6 of the element insulating film 97.

With such a configuration, the flip-chip type second light emitting element 5R is electrically connected to the first mounting electrode 24R and the second mounting electrode 24S. In the present embodiment, the second pixel Pix-2 has a first light emitting element 3R, 3G, 3B and a second light emitting element 5R for repair. That is, the first light emitting element 3R in which the defect has occurred is also subjected to the blinding treatment and mounted on the first mounting electrode 24R. Therefore, the step of removing the first light emitting element 3R in which the defect has occurred can be omitted.

Further, the flip-chip type second light emitting element 5R is mounted on the first mounting electrode 24R common to the first light emitting element 3R. Therefore, the second light emitting element 5R for repair can be driven by the pixel circuit PICA of the first light emitting element 3R. Therefore, it is not necessary to separately provide the pixel circuit PICA for the second light emitting element 5R for repair, and the display device 1 can suppress the circuit scale.

FIG. 7 is an explanatory diagram for explaining a repair method of the display device according to the embodiment. In FIG. 7, for ease of understanding, the adjacent first pixel Pix-1 and the second pixel Pix-2 are schematically shown. Further, in order to facilitate understanding, the passivation film 98 including the passivation film 98 shown in FIG. 6 is omitted. However, in reality, each step of mounting, lighting inspection, and repair is executed for a large number of pixels Pix included in the display area AA.

As shown in FIG. 7, the semiconductor layer 31 is formed on the first surface 200a of the support substrate 200 (step ST1). Specifically, the manufacturing apparatus forms a film on the first surface 200a of the support substrate 200 in the order of the n-type clad layer 37, the active layer 36, and the p-type clad layer 35. The support substrate 200 is, for example, a sapphire substrate.

Next, the manufacturing apparatus arranges the first surface 200a of the support substrate 200 so as to face the array substrate 2. The first mounting electrode 24, the joining member 25, and the p-type electrode 34 are laminated in this order on the surface of the array substrate 2. In FIG. 7, the joining member 25 and the p-type electrode 34 are not shown. The manufacturing apparatus brings the p-type clad layer 35 of the semiconductor layer 31 into contact with the first mounting electrode 24. Then, the laser apparatus irradiates the semiconductor layer 31 with the laser beam LI1 (step ST2).

The laser beam LI1 is irradiated from the second surface 200b side of the support substrate 200 and reaches the semiconductor layer 31. When the semiconductor layer 31 is irradiated with the laser beam LI1, it absorbs the light, is separated (peeled) from the support substrate 200, and is laminated on the surface of the array substrate 2 (step ST3). That is, the manufacturing apparatus peels the semiconductor layer 31 from the support substrate 200 by laser lift-off.

The laser light LI1 is preferably set to a wavelength band in which the n-type clad layer 37 of the semiconductor layer 31 absorbs light while transmitting through the support substrate 200. For example, the laser beam LI1 preferably has an energy of 3.5 eV (electron volt) or more and 9.9 eV or less, which corresponds to a wavelength band that transmits sapphire but does not transmit gallium nitride. Further, it is preferable that the wavelength of the laser beam L is set to 310 nm or less.

After the semiconductor layer 31 is transferred to the array substrate 2 and before the cathode electrode 22 is formed, the lighting inspection of the first light emitting element 3 is performed (step ST4). The lighting inspection device 7 is connected to the plurality of first light emitting elements 3. The lighting inspection device 7 has an inspection substrate 71 and an inspection electrode 72. The inspection board 71 faces the array board 2. The inspection electrode 72 is provided on the surface of the inspection substrate 71 facing the array substrate 2. The inspection electrode 72 is in contact with the n-type clad layer 37 of the semiconductor layer 31.

Here, an example of a lighting inspection method for the first light emitting element 3 will be described. FIG. 8 is a block diagram showing a configuration example of the repair system of the display device according to the embodiment. The repair system 100 shown in FIG. 8 performs a lighting inspection of a display device 1 having an array substrate 2 and a plurality of first light emitting elements 3 arranged on the array substrate 2. The repair system 100 may also repair the first light emitting element 3 if necessary. As shown in FIG. 8, the repair system 100 includes a lighting inspection device 7, an inspection control circuit 101, a light detection device 102, an image processing circuit 103, an inspection drive circuit 104, a press device 220, and a laser. The device 230 and the heater power supply 240 are included.

The inspection control circuit 101 is a circuit that controls the lighting inspection of the plurality of first light emitting elements 3. Further, the inspection control circuit 101 is a circuit that controls the repair of the plurality of first light emitting elements 3 based on the information of the lighting state of the plurality of first light emitting elements 3.

The lighting inspection device 7 is an inspection board for performing a lighting inspection of a plurality of first light emitting elements 3. The inspection electrode 72 of the lighting inspection device 7 is connected to the cathodes (n-type clad layer 37) of the plurality of first light emitting elements 3. The inspection electrode 72 functions as the cathode electrode 22 of the first light emitting element 3 during the lighting inspection.

The inspection drive circuit 104 supplies the anode power supply potential P VDD to the array substrate 2 and supplies the cathode power supply potential PVSS to the lighting inspection device 7 based on the control signal from the inspection control circuit 101. A current corresponding to the potential difference between the anode power supply potential P whether and the cathode power supply potential PVSS flows through each first light emitting element 3 to emit light. The inspection drive circuit 104 may supply a potential for lighting the first light emitting element 3 as an inspection drive signal, and supplies a potential different from the anode power supply potential P whether and the cathode power supply potential PVSS in the display of the display device 1. You may.

The photodetector 102 detects the light emitted from each of the plurality of first light emitting elements 3. The photodetector 102 is an image sensor having an image pickup device such as a CCD. The image processing circuit 103 receives a detection signal (image data) from the light detection device 102 and performs image processing to analyze the lighting state (for example, brightness) of each of the plurality of first light emitting elements 3. The image processing circuit 103 outputs information regarding the lighting state of the plurality of first light emitting elements 3 to the inspection control circuit 101.

The inspection control circuit 101 determines the lighting state of each of the plurality of first light emitting elements 3 based on the information from the image processing circuit 103. For example, if the brightness of the light emitted from the first light emitting element 3 is within a predetermined range, the inspection control circuit 101 determines that the lighting state of the first light emitting element 3 is good. The inspection control circuit 101 determines that the first light emitting element 3 is in a non-lighting state when the brightness of the light emitted from the first light emitting element 3 is smaller than the reference value. Further, the inspection control circuit 101 calculates the ratio of the number of the first light emitting elements 3 in the non-lighting state to the number of all the first light emitting elements 3 as the connection failure rate. Further, the inspection control circuit 101 calculates the positions of the first light emitting element 3 in the lit state and the first light emitting element 3 in the non-lighted state.

The inspection control circuit 101 includes a press device 220, a laser device 230, and a heater power supply 240 when the connection failure rate is larger than a predetermined reference value, that is, when a predetermined number of first light emitting elements 3 in a non-lighting state are present. A control signal is output to at least one of the light emitting elements 3 to repair the first light emitting element 3. The press device 220 pressurizes the plurality of first light emitting elements 3 in which defects have occurred toward the array substrate 2, and connects the plurality of first light emitting elements 3 and the first mounting electrode 24. Further, the laser device 230 and the heater power supply 240 heat the plurality of first light emitting elements 3 and the array substrate 2 in a state where the plurality of first light emitting elements 3 are pressurized by the press device 220, whereby the plurality of first light emitting elements 3 are heated. The light emitting element 3 and the first mounting electrode 24 are connected to each other.

The repair system 100 may not have the press device 220, the laser device 230, and the heater power supply 240 shown in FIG. 8, and may only inspect the lighting of the plurality of first light emitting elements 3.

Returning to FIG. 7, the first light emitting element 3 determined to be defective in lighting in the lighting inspection in step ST4 is subjected to the destructive processing. In FIG. 7, the first light emitting element 3 which has been determined to be defective in lighting and has been subjected to the blinding treatment is shown with diagonal lines. Then, the repair system 100 transfers the second light emitting element 5 formed on the transfer substrate 201 to the array substrate 2 (step ST5). Here, the transfer substrate 201 is formed with the second light emitting element 5 at a position corresponding to the second pixel Pix-2 in which the defect has occurred, and the second light emitting element is formed in the first pixel Pix-1 in which the defect does not occur. 5 is not formed.

In the repair system 100, the p-type electrode 54 (see FIG. 6) of the second light emitting element 5 is brought into contact with the first mounting electrode 24 at the second pixel Pix-2, and the n-type electrode 51 and the connection portion 52 (see FIG. 6) are brought into contact with each other. ) Is brought into contact with the second mounting electrode 24S to pressurize and irradiate the laser beam LI2. An infrared laser is irradiated as the laser beam LI2, and the second light emitting element 5 is connected to the array substrate 2. Further, the repair system 100 irradiates a UV laser as a laser beam LI3. As a result, the second light emitting element 5 is separated from the transfer substrate 201. In this way, the repair system 100 performs transfer by laser beams LI2 and LI3 and transfer by pressurization (stamp transfer), and transfers the second light emitting element 5 from the transfer substrate 201 to the array substrate 2.

As a result, the first light emitting element 3 and the second light emitting element 5 are mounted on the second pixel Pix-2, the first light emitting element 3 is mounted on the first pixel Pix-1, and the second light emitting element 5 is mounted. Is not implemented. Note that FIG. 7 shows an example in which one second light emitting element 5 is transferred from the transfer substrate 201, but when a plurality of defective pixels Pix (second pixel Pix-2) are found, a step is taken. A plurality of second light emitting elements 5 may be transferred at the same time in ST5.

Further, the transfer substrate 201 is provided with a convex portion 201a, and the second light emitting element 5 is provided on the convex portion 201a. Further, the transfer substrate 201 is made of a flexible material that is more easily deformed than the first light emitting element 3 and the second light emitting element 5. As a result, when the second light emitting element 5 is pressurized, it is possible to suppress the occurrence of damage to the other first light emitting element 3 and the occurrence of poor connection in the other first light emitting element 3.

Next, the manufacturing apparatus forms an element insulating film 97 between the first light emitting element 3 and the second light emitting element 5, and covers the first light emitting element 3, the second light emitting element 5, and the element insulating film 97 to cover the cathode electrode. 22 is formed (step ST6). The display device 1 can be repaired by the above method.

As described above, the display device 1 of the present embodiment has the substrate 21, the plurality of pixel Pix provided on the substrate 21, and the plurality of light emitting elements (first light emitting element 3 and the plurality of light emitting elements) provided in each of the plurality of pixel Pix. It has a second light emitting element 5), and at least one pixel (second pixel Pix-2) among the plurality of pixel Pix has a plurality of first mounting electrodes 24 electrically connected to the anode electrode 23. , A plurality of face-up type first light emitting elements 3 mounted on each of the plurality of first mounted electrodes 24, and a plurality of first mounted electrodes 24 are provided adjacent to each other and electrically connected to the cathode electrode 22. It has a second mounting electrode 24S, and a flip-tip type second light emitting element 5 mounted on the first mounting electrode 24 and the second mounting electrode 24S.

As a result, the defective first light emitting element 3 is mounted on the second pixel Pix-2, and the flip-chip type second light emitting element 5R is the first mounted electrode common to the first light emitting element 3R. It is mounted on the 24R. Therefore, the second light emitting element 5R for repair can be driven by the pixel circuit PICA of the first light emitting element 3R. Therefore, it is not necessary to additionally provide a pixel circuit PICA for the second light emitting element 5R for repair, and the display device 1 can suppress the circuit scale. Further, in the present embodiment, the step of selecting and removing the defective first light emitting element 3 from the large number of first light emitting elements 3 can be omitted. Therefore, the display device 1 can simplify the repair process. As described above, in the present embodiment, it is possible to suppress an increase in pixel size and easily repair defective pixels (second pixel Pix-2).

Further, since the lighting inspection of the first light emitting element 3 and the mounting of the second light emitting element 5 are performed before the element insulating film 97 and the cathode electrode 22 are provided, repair is performed after the element insulating film 97 and the cathode electrode 22 are provided. Damage to the element insulating film 97 and the cathode electrode 22 can be suppressed, and repair can be easily performed.

(First modification)
FIG. 9 is a plan view showing a plurality of pixels of the display device according to the first modification. In the following description, the same components as those described in the above-described embodiment are designated by the same reference numerals, and duplicate description will be omitted.

In the above-described embodiment, the case where the defect-generated first light emitting element 3 is subjected to the destructive treatment before the element insulating film 97 and the cathode electrode 22 are formed has been described. However, the present invention is not limited to this, and the cathode electrode 22 may be subjected to the destructive treatment after forming a film.

In FIG. 9, the region where the cathode electrode 22 is provided is shown with diagonal lines. As shown in FIG. 9, in the first pixel Pix-1 in which defects do not occur, the cathode electrode 22 is provided so as to be superimposed on all the first light emitting elements 3 and the second mounting electrode 24S. On the other hand, in the second pixel Pix-2, an opening OP is provided in a region of the cathode electrode 22 that overlaps with the first light emitting element 3R in which a defect has occurred. As a result, the defective first light emitting element 3R is not connected to the cathode electrode 22. No current flows through the defective first light emitting element 3R, and the first light emitting element 3R is in a non-lighting state.

The opening OP can be formed, for example, by irradiating the cathode electrode 22 with a laser beam (UV laser) to remove the cathode electrode 22 at the portion overlapping with the first light emitting element 3. Further, the configuration is not limited to forming the opening OP, and any configuration may be used as long as the defective first light emitting element 3R is not connected to the cathode electrode 22. For example, in a plan view, a slit may be formed so as to surround the periphery of the first light emitting element 3R to separate the cathode electrode 22 and the first light emitting element 3R.

(Second modification)
FIG. 10 is a plan view showing a plurality of pixels of the display device according to the second modification. In the above-described embodiment, the configuration of the pixel Pix (second pixel Pix-2) in which the first light emitting element 3R has a defect has been described, but the present invention is not limited thereto. In the second modification, a case where a defect occurs in the first light emitting element 3G will be described.

As shown in FIG. 10, the second pixel Pix-2 has a second light emitting element 5G in addition to the plurality of first light emitting elements 3. The second light emitting element 5G is a light emitting element for repair, and emits green light in place of the first light emitting element 3G in which a defect has occurred. That is, the pixel 49G has a second light emitting element 5G, a first mounting electrode 24G, and a second mounting electrode 24S. The second light emitting element 5G is a flip-chip type similar to the above-mentioned second light emitting element 5R, and a detailed description of the configuration will be omitted.

The second light emitting element 5G extends along the first direction Dx and is mounted on the first mounting electrode 24G and the second mounting electrode 24S. Specifically, the p-type electrode 54 (see FIG. 6) on one end side of the second light emitting element 5G is electrically connected to the connection portion 24a of the first mounting electrode 24G, and is on the other end side of the second light emitting element 5G. The n-type electrode 51 (see FIG. 6) is electrically connected to the second mounting electrode 24S.

With such a configuration, in the second pixel Pix-2, the first light emitting element 3G in which a defect has occurred is mounted on the first mounting electrode 24G and subjected to a spotting process, and the second light emitting element 5G is subjected to a spotting process. It is mounted on the first mounting electrode 24G and the second mounting electrode 24S. In other words, the first light emitting element 3G and the second light emitting element 5G are mounted on the common first mounting electrode 24G.

(Third modification example)
FIG. 11 is a plan view showing a plurality of pixels of the display device according to the third modification. In the third modification, a case where a defect occurs in the first light emitting element 3B will be described.

As shown in FIG. 11, the second pixel Pix-2 has a second light emitting element 5B in addition to the plurality of first light emitting elements 3. The second light emitting element 5B is a light emitting element for repair, and emits blue light in place of the first light emitting element 3B in which a defect has occurred. That is, the pixel 49B has a second light emitting element 5B, a first mounting electrode 24B, and a second mounting electrode 24S. The second light emitting element 5B is a flip-chip type similar to the above-mentioned second light emitting elements 5R and 5G, and a detailed description of the configuration will be omitted.

The second light emitting element 5B extends along the second direction Dy and is mounted on the first mounting electrode 24B and the second mounting electrode 24S. Specifically, the p-type electrode 54 (see FIG. 6) on one end side of the second light emitting element 5G is electrically connected to the connection portion 24a of the first mounting electrode 24B, and is on the other end side of the second light emitting element 5B. The n-type electrode 51 (see FIG. 6) is electrically connected to the second mounting electrode 24S.

With such a configuration, in the second pixel Pix-2, the first light emitting element 3B in which the defect has occurred is mounted on the first mounting electrode 24B, and the spotting process is performed. It is mounted on the first mounting electrode 24B and the second mounting electrode 24S. In other words, the first light emitting element 3B and the second light emitting element 5B are mounted on the common first mounting electrode 24B.

As shown in the embodiment, the second modification, and the third modification, even if a defect occurs in any of the first light emitting elements 3R, 3G, and 3B, the second light emitting element 5 has a defect. Flip-chip mounting can be performed on the first mounting electrode 24 corresponding to one light emitting element 3 and the second mounting electrode 24S. That is, the display device 1 does not need to individually provide repair electrodes or circuits corresponding to the first light emitting elements 3R, 3G, and 3B. Therefore, the display device 1 can suppress the circuit scale and the electrode area of the pixel Pix, and can suppress the pixel size.

(Fourth modification)
FIG. 12 is a plan view showing a plurality of pixels of the display device according to the fourth modification. In the above-mentioned example, the configuration in which the first mounting electrode 24 and the second mounting electrode 24S are arranged in a matrix is shown, but the present invention is not limited to this.

As shown in FIG. 12, the plurality of pixels 49R, 49G, 49B are arranged in the first direction Dx. That is, in the pixel Pix, the first mounting electrodes 24AR, 24AG, and 24AB are arranged in the first direction, and the first light emitting elements 3R, 3G, and 3B are mounted on the first mounting electrodes 24AR, 24AG, and 24AB, respectively.

The second mounting electrode 24SA extends in the first direction Dx and is arranged adjacent to the first mounting electrodes 24AR, 24AG, 24AB and the second direction Dy. For example, when a defect occurs in the first light emitting element 3B, the first light emitting element 3B is subjected to a destructive treatment, and the second light emitting element 5B for repair is the first mounting electrode 24AB and the second mounting electrode. Connected to 24SA.

Also in this modification, the defective first light emitting element 3B and the second light emitting element 5B for repair are mounted on the same pixel Pix (second pixel Pix-2), and the second light emitting element 5B is the first. The pixel circuit PICA of the light emitting element 3B can be shared. Further, in the present embodiment, since the second mounting electrode 24SA is provided extending in the first direction Dx, a plurality of second light emitting elements 5 are mounted on one pixel Pix (second pixel Pix-2). Is also possible.

(Fifth modification)
FIG. 13 is a plan view showing a plurality of pixels of the display device according to the fifth modification. In the fifth modification, the configuration in which the pixel cathode wiring LVSS is provided on the array substrate 2 is different from that of the above-described embodiment and each modification.

As shown in FIG. 13, the pixel cathode wiring LVSS extends in the first direction Dx and is provided over a plurality of pixels Pix arranged in the first direction Dx. Here, a pixel group in one row including a plurality of pixel Pix arranged in the first direction Dx is referred to as a pixel row PixL. The plurality of pixel rows PixL are arranged in the second direction Dy. The pixel cathode wiring LVSS is provided for each pixel row PixL and is arranged in the second direction Dy.

Each of the plurality of pixel cathode wiring LVSSs is electrically connected to a plurality of second mounting electrodes 24S belonging to the pixel row PixL. Each of the plurality of pixel cathode wiring LVSS is connected to the cathode wiring 60 provided in the peripheral region GA, and the cathode power supply potential PVSS is supplied. Further, the plurality of pixel cathode wiring LVSSs are connected to the cathode electrode 22 via the contact hole CH6 provided for each pixel Pix. Alternatively, the present invention is not limited to this, and the plurality of pixel cathode wiring LVSS may be electrically connected to the cathode electrode 22 at any point.

In this modification, since the pixel cathode wiring LVSS is provided for each pixel Pix, the degree of freedom of connection between the plurality of second mounting electrodes 24S and the cathode electrode 22 can be increased. Further, since the pixel cathode wiring LVSS is provided for each pixel row PixL, it is possible to suppress variations in the cathode power supply potential PVSS supplied to each pixel Pix.

Although the preferred embodiments of the present invention have been described above, the present invention is not limited to such embodiments. The contents disclosed in the embodiments are merely examples, and various changes can be made without departing from the spirit of the present invention. Appropriate changes made without departing from the spirit of the present invention naturally belong to the technical scope of the present invention. At least one of the various omissions, substitutions and modifications of the components may be made without departing from the gist of each of the embodiments and modifications described above.

1 Display device 2 Array board 3, 3R, 3G, 3B 1st light emitting element 5, 5R, 5G, 5B 2nd light emitting element 12 Drive circuit 21 Board 22 Cathode electrode 23 Anodic electrode 24, 24R, 24G, 24B, 24AR, 24AG , 24AB 1st mounting electrode 24S, 24SA 2nd mounting electrode 25, 25S Joining member 26 Opposing electrode 34, 54 p-type electrode 35, 55 p-type clad layer 36, 56 Active layer 37, 57 n-type clad layer 38 First height Resistance layer 51 n-type electrode 58 Second high resistance layer 60 Cathode wiring 97 Element insulation film 100 Repair system 200 Support board 201 Transfer board 210 Drive IC
DRT drive transistor Pix, 49 pixels Pix-1 1st pixel Pix-2 2nd pixel PixL Pixel row LVSS Pixel cathode wiring

Claims (7)

With the board
With a plurality of pixels provided on the substrate,
It has a plurality of light emitting elements provided in each of the plurality of pixels, and has a plurality of light emitting elements.
At least one of the pixels
A plurality of first mounting electrodes electrically connected to the anode electrode,
A plurality of face-up type first light emitting elements mounted on each of the plurality of first mounting electrodes, and
A second mounting electrode provided adjacent to the plurality of first mounting electrodes and electrically connected to the cathode electrode,
A display device comprising the first mounting electrode and a flip-chip type second light emitting element mounted on the second mounting electrode. The display device according to claim 1, wherein the second light emitting element is rectangular in a plan view from a direction perpendicular to the substrate. The display device according to claim 1 or 2, wherein the length of the long side of the second light emitting element is longer than the length of one side of the first light emitting element in a plan view from a direction perpendicular to the substrate. The plurality of first light emitting elements are laminated in the order of a p-type clad layer, an active layer, and an n-type clad layer, and have a first high resistance layer laminated on the n-type clad layer.
The display device according to any one of claims 1 to 3, wherein the sheet resistance value of the first high resistance layer is larger than the sheet resistance value of the n-type clad layer. The second light emitting device has a second high resistance layer laminated in the order of a p-type clad layer, an active layer, and an n-type clad layer, and is laminated on the n-type clad layer.
A p-type electrode connected to the p-type clad layer and an n-type electrode connected to the n-type clad layer are provided so as to face the substrate.
The display device according to claim 4, wherein the sheet resistance value of the second high resistance layer is larger than the sheet resistance value of the n-type clad layer. The display according to claim 5, wherein the cathode electrode is provided so as to cover the first high resistance layer provided on the plurality of first light emitting elements and the second high resistance layer provided on the second light emitting element. Device. The display device according to any one of claims 1 to 6, wherein an insulator is provided between the adjacent first mounting electrode and the second mounting electrode.

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