JP2022017790A - Game machine - Google Patents

Abstract

To provide a game machine capable of reducing an amount of code of a program pertaining to processing for outputting a slotting signal and a putout signal.SOLUTION: Signal control means performs processing for updating a timer by a fixed value at a predetermined interval, processing for setting a putout signal to a first state until the timer reaches a threshold and for setting a putout signal to a second state after the timer reaches a threshold, processing for setting a slotting signal to a first state until the a timer reaches a threshold and for setting the slotting signal to a second state after the timer reaches a threshold, processing for setting a timer to a predetermined value when the timer reaches a specific value, a series of processing for updating a putout number counter by setting an address of the putout number counter to a register, and a series of processing for updating a slotting number counter by setting an address of the slotting number counter to a register, and repeats the first state and the second state of a slotting signal and a putout signal. The two series of processing are executed by looping one series of processing.SELECTED DRAWING: Figure 11

Description

The present invention relates to a gaming machine.

Conventionally, as a gaming machine, a slot machine (rotary drum type gaming machine) equipped with a plurality of reels in which a plurality of symbols are arranged on the outer peripheral surface is known. This type of gaming machine imparts a certain game value to a game medium such as a medal or a pachinko ball, and plays a game for acquiring such a game medium. As this type of gaming machine, a signal for notifying the outside of the number of gaming media used for the game (hereinafter referred to as “input signal”) and a signal for notifying the outside of the number of gaming media paid out as a result of the game (hereinafter referred to as “input signal”). Those capable of outputting a "payout signal") are known (see, for example, Patent Document 1). The process for outputting such an input signal and a payout signal is performed based on a program stored in the storage means (memory).

Japanese Unexamined Patent Publication No. 2009-66171

By the way, the capacity of the storage means is severely limited due to the rules regarding the gaming machine and the like. For this reason, if the amount of code of the program related to the process of outputting the input signal and the payout signal is large, the capacity of the storage means is consumed in large quantities for the program, and there is a problem that the capacity becomes tight. ..

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a gaming machine capable of reducing the amount of code of a program related to a process of outputting an input signal and a payout signal.

In order to solve the above problems, the gaming machine of the present invention
A signal control means for generating a payout signal for notifying the number of payouts of the game medium to be paid out as a result of the game and an input signal for notifying the number of payouts of the game medium used for the game.
A storage means including a timer, a payout number counter that stores a value corresponding to the payout number, and an input number counter that stores a value corresponding to the payout number.
The payout number counter and the register in which the address of the input number counter can be set are provided.
The signal control means is
The process of updating the stored value of the timer by a fixed value at predetermined intervals, and
The process of setting the payout signal to the first state until the stored value of the timer reaches the threshold value, and setting the payout signal to the second state after the stored value of the timer reaches the threshold value.
The process of setting the input signal to the first state until the stored value of the timer reaches the threshold value, and setting the input signal to the second state after the stored value of the timer reaches the threshold value.
A process of setting a predetermined value in the timer when the stored value of the timer reaches a specific value.
A series of processes for setting the address of the payout counter in the register and updating the payout counter, and
The address of the input number counter is set in the register, and a series of processes for updating the input number counter are performed.
The first state and the second state of the payout signal are repeated as many times as the number of payouts.
It is a gaming machine that repeats the first state and the second state of the input signal by the number of times corresponding to the input number.
A series of processes for setting the address of the payout number counter in the register and updating the payout number counter, and a series of processes for setting the address of the input number counter in the register and updating the input number counter. Is characterized in that it is executed by looping one series of processes.

According to the present invention, it is possible to reduce the amount of code of the program related to the process of outputting the input signal and the payout signal.

It is a perspective view which shows the gaming machine which concerns on embodiment of this invention. It is a block diagram which shows the schematic structure of the gaming machine. It is a figure for demonstrating the excitation pattern. It is a figure for demonstrating the connection state of a main CPU, a flip-flop, and a reel. It is a figure for demonstrating the signal passing through a flip-flop. The same is a flowchart for explaining the excitation pattern update process. It is a figure for demonstrating the excitation pattern table. It is a flowchart for demonstrating the excitation pattern update process in the conventional gaming machine. It is a figure for demonstrating the medal insertion signal and the medal payout signal output by the gaming machine which concerns on embodiment of this invention. The same is a flowchart for explaining the counter subtraction process. The same is a flowchart for explaining the terminal board output control process.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. Although the slot machine, which is one of the gaming machines, will be described below, the gaming machine according to the present invention is not limited to the slot machine, and may be a gaming machine such as a pachinko gaming machine.

As shown in FIG. 1, the slot machine (game machine) 10 of the present invention opens and closes a box-shaped housing 11 having an opening on the front side, which is a surface facing the player side, and an opening on the front side of the housing 11. It is provided with a front door 12 to be used. The housing 11 houses a reel unit in which a rotatable first reel 20a, a second reel 20b, and a third reel 20c are unitized, a hopper device for paying out medals, and the like. Further, the front door 12 is divided into an upper door 12a and a lower door 12b, and the upper door 12a and the lower door 12b can be opened and closed with respect to the housing 11, respectively.

The upper door 12a is provided with a liquid crystal display (display means) 13, a device for producing an effect such as a speaker 14, and a display window 16. The liquid crystal display 13 displays images (moving images, still images) for various effects. Further, the speaker 14 outputs sounds for various effects (music, sound effects, voice, etc.). In addition to the liquid crystal display and the speaker, a lighting device such as a lamp (LED), a movable accessory that can be operated by an actuator, or the like may be provided as the device for the effect.

At the back of the display window 16, a reel unit is arranged so that a part thereof can be visually recognized from the outside of the display window 16. A plurality of types of symbols are arranged in a row on the outer peripheral surface of each reel 20a to 20c, and when each reel 20a to 20c is stopped, three symbols per reel (upper symbol, middle symbol, lower row) are arranged through the display window 16. Design) is displayed. Further, the display window 16 is provided with an upper stage, a middle stage, and a lower stage as display positions for visually recognizing the symbols of the reels 20a to 20c, and an effective line is set by the combination of the display positions of the reels 20a to 20c. Has been done. In the gaming machine of the present embodiment, the effective line is composed of the middle stage of the first reel 20a, the middle stage of the second reel 20b, and the middle stage of the third reel 20c. Further, in the gaming machine of the present embodiment, the number of medals (specified number) required for one game is set to three, and when the specified number of medals are inserted, the effective line is activated. Will be done.

In the slot machine 10, each reel 20a to 20c starts to rotate with the start of the game, and the winning combination lottery is executed to determine the winning or losing (non-winning) of any of the winning combinations. Next, when the reels 20a to 20c are stopped, if the symbol combination corresponding to the winning combination won in the winning combination lottery is displayed on the valid line, this winning combination becomes a prize, and the process corresponding to the winning combination (the winning combination). Winning process) is executed. Specifically, a display determination process is performed in which the symbol combination displayed (stop display) on the effective line when the reels 20a to 20c are stopped is collated with the winning determination table stored in the ROM, and this display determination is performed. Winning processing is performed based on the processing result.

Specifically, for example, when a small winning combination is won, a payout process is performed, when a replay is won, a replay process (replay process) is performed, and when a bonus is won, a game state is performed. Is performed (game state transition control process).

Here, the payout process is a process of paying out the number of medals determined based on the dividend determined for each role when the small winning combination wins. Further, the replay process is a process of setting the same game start standby state as the previous game without requiring the player to insert a medal owned by the player for the next game when the replay wins a prize. That is, when the replay wins, the same number of medals as the number set in the inserted state in the previous game (the game in which the replay won) is added to the player's own medals (including credited medals). ) Is automatically inserted without using), and the game start operation for the next start lever 24 is waited for with the effective line corresponding to the number of medals inserted by the automatic insertion process set.
When the automatic insertion process is performed, the number of bets on the medal for the first game after the automatic insertion process cannot be added or subtracted. Specifically, when the automatic insertion process is performed, the number of bets does not increase even if a medal is inserted into the medal insertion slot 22. In addition, when the automatic insertion process is performed, even if the settlement button (payment switch: settlement operation means) is operated, the medals automatically inserted (bet) by the automatic insertion process will not be paid out. There is. On the other hand, even when the automatic insertion process is performed, it is possible to increase or decrease the number of medals to be credited (stored). That is, if the automatic insertion process is performed and a medal is inserted into the medal insertion slot 22 before the first game is started after the automatic insertion process is performed, the number of credits of the medal is increased. It has become. In addition, if the automatic insertion process is performed and the settlement button is operated before the first game is started after the automatic insertion process is performed, the credited medals are paid out. ..

The lower door 12b has a medal insertion slot 22 for inserting medals, a bet button (bet switch) 23 for betting credited medals, and a start lever (start switch: game start operation) operated when starting a game. Means) 24, stop buttons (stop switch: stop operating means) 26a, 26b, 26c for stopping the rotating reel, medals paid out from the payout port 27, and medals paid out from the payout port 27 by the hopper device. A medal tray 28 for receiving is provided. Further, at the back of the medal insertion slot 22, a medal sensor for detecting the passage of medals inserted from the medal insertion slot 22 is provided.

In the slot machine 10, the operation of the start lever 24 is enabled by inserting a medal into the medal insertion slot 22 or operating the bet button 23 to bet a predetermined number of medals. Further, when the activated start lever 24 is operated, the game is started. When the game is started, the reels 20a to 20c start to rotate, and when the rotation speed of the reels 20a to 20c reaches a constant speed and becomes a steady rotation, the operation of the stop buttons 26a to 26c is enabled. Further, when the activated stop buttons 26a to 26c are operated, the reels 20a to 20c corresponding to the operated stop buttons 26a to 26c are stopped.

As shown in FIG. 2, a main control board (main control device) 30 and a sub control board (sub control device) 98 are provided inside the slot machine 10. The main control board 30 receives input signals from input means such as a bet button 23, a start lever 24, stop buttons 26a to 26c, and a medal sensor, performs various calculations for executing a game, and is based on the calculation results. The reels 20a to 20c and output means such as a hopper device are controlled. Further, the sub control board 98 receives a signal sent from the main control board 30, performs various calculations for executing the effect, and based on the calculation results, the liquid crystal display 13, the speaker 14, the lighting device 15, and the like. Controls the device for the production of.

Further, the main control board 30 and the sub control board 98 are electrically connected to each other, and various information (signals) such as information indicating the game state can be transmitted from the main control board 30 to the sub control board 98. However, information cannot be transmitted from the sub control board 98 to the main control board 30.
Further, the functions of each board such as the main control board 30 and the sub control board 98 are preliminarily applied to various processors (CPU, DSP, etc.), ICs, hardware such as information storage media such as ROM and RWM, ROM and the like. It is realized by software consisting of a predetermined program stored.

The main control board 30 includes a game control means 100, a signal control means 102, a counter updating means 104, and a main storage means 106. Further, the main storage means 106 includes a ROM and an RWM. In the description of the present embodiment, the term ROM or RWM basically refers to the ROM or RWM of the main storage means 106.

The game control means 100 is a means for controlling the progress of the game, and when a medal is inserted and the start lever 24 is operated, the winning combination is determined by lottery and the reels 20a to 20c are rotated. When the stop operation is performed on the stop button 54, the rotating reel is stopped according to the result of the winning combination lottery, and it is determined whether or not the combination has won a prize based on the symbol combination displayed on the valid line. The main loop process for advancing the game is performed by executing the display determination process to be performed and performing the process according to the determination result.

Each reel 20a to 20c includes a four-phase stepping motor. Then, by controlling this stepping motor by a 1-2 phase excitation method, each reel 20a to 20c is rotated. Specifically, the stepping motor includes a rotor and a stator having four-phase coils of the first phase, the second phase, the third phase, and the fourth phase, and the coils of the first phase to the fourth phase are included. The rotor is rotated by being sequentially excited. Then, the rotors of the stepping motors corresponding to the reels 20a to 20c rotate, so that the reels 20a to 20c rotate.

In the following, the signals sent to the coils of the first phase of each of the first to third reels 20a to 20c are "first rotation stepping motor first phase signal" and "second rotation stepping motor first phase signal". , "Third rotation stepping motor first phase signal", and the signal sent to the second phase coil is "first rotation stepping motor second phase signal", "second rotation stepping motor second phase signal". , "Third rotation stepping motor second phase signal", and the signal sent to the third phase coil is "first rotation stepping motor third phase signal", "second rotation stepping motor third phase". Called "signal" and "third rotation stepping motor third phase signal", the signals sent to the fourth phase coil are "first rotation stepping motor fourth phase signal" and "second rotation stepping motor fourth". It will be referred to as "phase signal" and "third rotation stepping motor fourth phase signal". Each of these control signals is sent to each of the phase coils of the reels 20a to 20c to excite each phase coil.

When rotating the reels 20a to 20c, for example, the coils of the first phase to the fourth phase are excited in order in the pattern shown in FIG. The circles shown in FIG. 3 indicate that the corresponding coil is excited. By updating the excitation patterns in the order shown in FIG. 3, the reels 20a to 20c rotate in the normal direction. Further, when the reels 20a to 20c are stopped, all the coils of the first phase to the fourth phase are excited (all phases are excited). Then, after the reels 20a to 20c are stopped, the excitation of all the coils of the first phase to the fourth phase is stopped.
The excitation patterns may be updated in an order other than that shown in FIG. For example, the reels 20a to 20c can be inverted by updating the excitation pattern in the reverse order of the order shown in FIG. Further, the excitation method and the number of phases of the stepping motor are not limited to those of the present embodiment. The present invention can be applied by appropriately reading it according to the excitation method, the number of phases of the stepping motor, and the like.

The control signals for controlling the reels 20a to 20c are output from the main CPU (control circuit) 31 of the main control board 30 shown in FIG.
The main control board 30 includes a main CPU 31 and three flip-flops (ICs: integrated circuits) 32, 33, 34. Further, the flip-flop 32 constitutes a first output port, the flip-flop 33 constitutes a second output port, and the flip-flop 34 constitutes a third output port. Here, the output port is a circuit used by the main CPU 31 when transmitting a signal to peripheral devices such as reels 20a to 20c, and is a circuit capable of outputting a bit value "0" or "1". Means.

The main CPU 31 has output terminals D0 to D7. The main CPU 31 can output 8-bit data from the output terminals D0 to D7. Further, the flip-flop 32 has input terminals D1 to D8 and output terminals Q1 to Q8, and the input terminals and output terminals having the same numbers correspond to each other. Similarly, the flip-flops 33 and 34 also have input terminals D1 to D8 and output terminals Q1 to Q8, and the input terminals and output terminals having the same numbers correspond to each other.
The main CPU 31 and the flip-flops 32 to 34 also have a plurality of terminals.

The output terminal D0 of the main CPU 31 is connected to the input terminals D1 of the flip-flops 32 to 34 via the wiring MD0. Further, the output terminal D1 of the main CPU 31 is connected to the input terminals D2 of the flip-flops 32 to 34 via the wiring MD1. Further, the output terminal D2 of the main CPU 31 is connected to the input terminals D3 of the flip-flops 32 to 34 via the wiring MD2. Further, the output terminal D3 of the main CPU 31 is connected to the input terminals D4 of the flip-flops 32 to 34 via the wiring MD3. Further, the output terminal D4 of the main CPU 31 is connected to the input terminals D5 of the flip-flops 32 to 34 via the wiring MD4. Further, the output terminal D5 of the main CPU 31 is connected to the input terminals D6 of the flip-flops 32 to 34 via the wiring MD5. Further, the output terminal D6 of the main CPU 31 is connected to the input terminals D7 of the flip-flops 32 to 34 via the wiring MD6. Further, the output terminal D7 of the main CPU 31 is connected to the input terminals D8 of the flip-flops 32 to 34 via the wiring MD7. The wirings MD0 to MD7 are data buses capable of transmitting 8-bit data from the main CPU 31 to the flip-flops 32 to 34. Then, the main CPU 31 can transmit 8-bit data from the output terminals D0 to D7 to the flip-flops 32 to 34 by parallel communication.

Further, the output terminals Q5 to Q8 of the flip-flop 32 are connected to the first reel 20a. Specifically, the output terminal Q5 of the flip-flop 32 is connected to the coil of the first phase of the first reel 20a. Further, the output terminal Q6 of the flip-flop 32 is connected to the second phase coil of the first reel 20a. Further, the output terminal Q7 of the flip-flop 32 is connected to the coil of the third phase of the first reel 20a. Further, the output terminal Q8 of the flip-flop 32 is connected to the coil of the fourth phase of the first reel 20a.
Further, the output terminals Q5 to Q8 of the flip-flop 33 are connected to the second reel 20b. Specifically, the output terminal Q5 of the flip-flop 33 is connected to the coil of the first phase of the second reel 20b. Further, the output terminal Q6 of the flip-flop 33 is connected to the coil of the second phase of the second reel 20b. Further, the output terminal Q7 of the flip-flop 33 is connected to the coil of the third phase of the second reel 20b. Further, the output terminal Q8 of the flip-flop 33 is connected to the coil of the fourth phase of the first reel 20b.
Further, the output terminals Q5 to Q8 of the flip-flop 34 are connected to the third reel 20c. Specifically, the output terminal Q5 of the flip-flop 34 is connected to the coil of the first phase of the third reel 20c. Further, the output terminal Q6 of the flip-flop 34 is connected to the second phase coil of the third reel 20c. Further, the output terminal Q7 of the flip-flop 34 is connected to the coil of the third phase of the third reel 20c. Further, the output terminal Q8 of the flip-flop 34 is connected to the coil of the fourth phase of the third reel 20c.
More specifically, the output terminals Q5 to Q8 of the flip-flops 32 to 34 and the coils of the reels 20a to 20c are drive circuits for driving the reels 20a to 20c (for example, an amplifier circuit such as a Darlington transistor). ) (Not shown). Further, another IC or electronic component other than the flip-flops 32 to 34 may intervene in the signal path from the main CPU 31 to the reels 20a to 20c.

8-bit data is output from the output terminals D0 to D7 of the main CPU 31. Then, the data output from the output terminals D0 to D7 of the main CPU 31 is appropriately sent to the reels 20a to 20c via the flip-flops 32 to 34.

Here, the signals transmitted via the flip-flops 32 to 34 will be described with reference to FIG. FIG. 5 is a table summarizing the signals passing through the input terminals D1 to D8 and the output terminals Q1 to Q8 of the flip-flops 32 to 34. In other words, the signals shown in FIG. 5 are assigned to the input terminals D1 to D8 and the output terminals Q1 to Q8 (bits 0 to 7) of the flip-flops 32 to 34.

The "external signal 1" is sent from the input terminal D1 of the flip flop 32 to the output terminal Q1, the "external signal 2" is sent from the input terminal D2 to the output terminal Q2, and the "external signal 2" is sent from the input terminal D3 to the output terminal Q3. "External signal 3" is sent, "medal payout device signal" is sent from the input terminal D4 to the output terminal Q4, and "first rotation stepping motor first phase signal" is sent from the input terminal D5 to the output terminal Q5. Then, the "first rotation stepping motor second phase signal" is sent from the input terminal D6 to the output terminal Q6, and the "first rotation stepping motor third phase signal" is sent from the input terminal D7 to the output terminal Q7. Then, the "first rotation stepping motor phase 4 signal" is sent from the input terminal D8 to the output terminal Q8.

Further, a "medal insertion signal" is sent from the input terminal D1 of the flip flop 33 to the output terminal Q1, a "medal payout signal" is sent from the input terminal D2 to the output terminal Q2, and the input terminal D3 to the output terminal Q3. Is sent an "external signal 4", an "external signal 5" is sent from the input terminal D4 to the output terminal Q4, and a "second rotation stepping motor first phase signal" is sent from the input terminal D5 to the output terminal Q5. The "second rotation stepping motor second phase signal" is sent from the input terminal D6 to the output terminal Q6, and the "second rotation stepping motor third phase signal" is sent from the input terminal D7 to the output terminal Q7. It is sent, and the "second rotation stepping motor phase 4 signal" is sent from the input terminal D8 to the output terminal Q8.

Further, the "stop indicator 1 signal" is sent from the input terminal D1 of the flip flop 34 to the output terminal Q1, the "stop indicator 2 signal" is sent from the input terminal D2 to the output terminal Q2, and the "stop indicator 2 signal" is sent from the input terminal D3. A "stop indicator 3 signal" is sent to the output terminal Q3, a "blocker solenoid signal" is sent from the input terminal D4 to the output terminal Q4, and a "third rotation stepping motor" is sent from the input terminal D5 to the output terminal Q5. The "first phase signal" is sent, the "third rotation stepping motor second phase signal" is sent from the input terminal D6 to the output terminal Q6, and the "third rotation stepping motor" is sent from the input terminal D7 to the output terminal Q7. The "third phase signal" is sent, and the "third rotation stepping motor fourth phase signal" is sent from the input terminal D8 to the output terminal Q8.

That is, the "external signal 1", "medal insertion signal", and "stop indicator 1 signal" are appropriately output from the output terminal D0 of the main CPU 31, and the "external signal 2" and "medal" are output from the output terminal D1 of the main CPU 31. The "payout signal" and "stop indicator 2 signal" are appropriately output, and the "external signal 3", "external signal 4", and "stop indicator 3 signal" are appropriately output from the output terminal D2 of the main CPU 31, and the main CPU 31 "Medal payout device signal", "external signal 5", and "blocker solenoid signal" are appropriately output from the output terminal D3 of the main CPU 31, and "first rotation stepping motor first phase signal" is output from the output terminal D4 of the main CPU 31. , "Second rotation stepping motor first phase signal" and "third rotation stepping motor first phase signal" are appropriately output, and "first rotation stepping motor second phase signal" is output from the output terminal D5 of the main CPU 31. , "Second rotation stepping motor second phase signal", "third rotation stepping motor second phase signal" are appropriately output, and "first rotation stepping motor third phase" is output from the output terminal D6 of the main CPU 31. "Signal", "second rotation stepping motor third phase signal", "third rotation stepping motor third phase signal" are appropriately output, and "first rotation stepping motor fourth" is output from the output terminal D7 of the main CPU 31. "Phase signal", "second rotation stepping motor fourth phase signal", and "third rotation stepping motor fourth phase signal" are appropriately output. Further, the signals transmitted from the output terminals D0 to D7 of the main CPU 31 to the flip-flops 32 to 34 are output as 8-bit parallel signals.
The output terminals D0 to D7 of the main CPU 31 may output signals other than the above-mentioned signals, respectively. Further, the signals sent from the output terminals D0 to D7 of the main CPU 31 to each IC do not necessarily have to be output as 8-bit parallel signals.

Various data signals including the above-mentioned signals are sequentially output from the output terminals D0 to D7 of the main CPU 31, and the flip-flops 32 to 34 hold (latch) the corresponding signals to input terminals D1. A signal is sent from ~ D8 to the output terminals Q1 to Q8. That is, for example, from the output terminals D0 to D7 of the main CPU 31, "external signal 1", "external signal 2", "external signal 3", "medal payout device signal", "first rotation stepping motor first phase signal". , "1st rotary stepping motor 2nd phase signal", "1st rotary stepping motor 3rd phase signal" and "1st rotary stepping motor 4th phase signal" 8 bits corresponding to 8 data signals. When the parallel signal is output, a write signal is sent from the pulse output terminal PO0 of the main CPU 31 to the flip flop 32 via the wiring WR1 (see FIG. 4). Then, the flip-flop 32 holds these data signals according to the rising edge of the write signal sent via the wiring WR1, so that these data signals are output from the flip-flop 32 and peripherally via the flip-flop 32. Sent to the device. The same applies to the flip-flops 33 and 34, and when the data signal (parallel signal) corresponding to each of the flip-flops 33 and 34 is output from the main CPU 31, the wiring WRs 2 and 3 are connected from the pulse output terminals PO1 and PO2 of the main CPU 31. A write signal is sent to the flip-flops 33 and 34 via the flip-flops 33 and 34, and each data signal is sent to the peripheral device via the flip-flops 33 and 34.
As described above, in the gaming machine of the present embodiment, the flip-flops 32 to 34 are 8-input D flip-flops. Then, each of the flip-flops 32 to 34 holds the corresponding data signal according to the write signal sent from the main CPU 31 at the same time when the corresponding data signal is sent, so that various data signals pass through the flip-flops 32 to 34. It is designed to be sent. The ICs 32 to 34 do not have to be flip-flops, and among the data output from the output terminals D0 to D7 of the main CPU 31, the data sent to each of the reels 20a to 20c is the data sent to each of the reels 20a to 20a. Any circuit may be used as long as it can be transmitted individually to 20c. Further, another IC may be interposed between the main CPU 31 and the ICs 32 to 34.

The "medal insertion signal", "medal payout signal", "external signal 1", "external signal 2", "external signal 3", "external signal 4", and "external signal 5" are for notifying the state of the gaming machine. This is a signal sent to an external centralized terminal board provided above the inside of the housing 11. These signals are sent to a hall computer that monitors the state of the gaming machine via an external centralized terminal board as an electronic circuit board. Then, the hall computer monitors whether or not an abnormality has occurred based on these signals. Here, the "medal insertion signal" is a signal indicating the number of medals inserted in each game. The "medal payout signal" is a signal that informs the number of medals to be paid out. The "external signal 1", "external signal 2", and "external signal 3" are signals that can count the number of operations of so-called RB, BB, ART, and the like, respectively. The "external signal 4" is a signal for notifying when it is internally determined that there is a possibility of fraudulent activity. The "external signal 5" is a signal indicating that the front door 12 is open.
Further, the "stop indicator 1 signal", "stop indicator 2 signal", and "stop indicator 3 signal" are signals for controlling the lighting / extinguishing of the red LED and the blue LED built in the stop buttons 26a to 26c, respectively. Is. Then, by illuminating each of the stop buttons 26a to 26c in red or blue by these signals, the player is notified whether the operation of each of the stop buttons 26a to 26c is valid or invalid.
Further, the "blocker solenoid signal" is a signal for controlling ON / OFF of the blocker that prevents the insertion of medals. When the blocker is in the ON state, the medal inserted from the medal slot 22 is repelled by the blocker and ejected toward the medal tray 28. On the other hand, when the blocker is in the OFF state, the medals inserted from the medal insertion slot 22 are flown toward the hopper device, and the medals are bet or stored.
Further, the "medal payout device signal" is a signal for controlling the medal payout by the hopper device. The hopper device receives a "medal payout device signal" and pays out a predetermined number of medals.

Next, the generation of signals for controlling the reels 20a to 20c in the main CPU 31 will be described with reference to FIGS. 6 and 7. The main CPU 31 updates the excitation pattern by the excitation pattern update process shown in FIG. 6, outputs this excitation pattern from the output terminals D0 to D7 (more specifically, the output terminals D4 to D7), and reels 20a to 20c. To control.

The main CPU 31 acquires an excitation pattern from the excitation pattern table 60 shown in FIG. 7 (step S1). Here, the excitation pattern table 60 has the excitation pattern registered and is stored in the ROM (not shown) of the main control board 30. As shown in FIG. 7, each data registered in the excitation pattern table 60 is 8-bit data. Further, among the registered data, the upper 4 bits (4th to 7th bits) are the excitation pattern. Specifically, the data of "first rotation stepping motor first phase signal", "second rotation stepping motor first phase signal" and "third rotation stepping motor first phase signal" are stored in the 4th bit. The data of "1st rotation stepping motor 2nd phase signal", "2nd rotation stepping motor 2nd phase signal" and "3rd rotation stepping motor 2nd phase signal" are assigned to the 5th bit. The data of "1st rotation stepping motor 3rd phase signal", "2nd rotation stepping motor 3rd phase signal" and "3rd rotation stepping motor 3rd phase signal" are assigned to the 6th bit. The data of "1st rotation stepping motor 4th phase signal", "2nd rotation stepping motor 4th phase signal" and "3rd rotation stepping motor 4th phase signal" are assigned to the 7th bit. Assigned. Note that "0" is assigned to the lower 4 bits. Then, in the process of step S1, 8-bit data including the excitation pattern data is acquired from the excitation pattern table 60. In other words, the main CPU 31 acquires one excitation pattern from the excitation pattern table 60.

Next, the main CPU 31 is the current value (before synthesis) of the data to be sent to the output ports (flip-flops 32 to 34) corresponding to the reels whose excitation patterns are updated in the current excitation pattern update processing among the reels 20a to 20c. Value: pre-synthesis data) is acquired (step S2).

Next, the main CPU 31 masks the lower 4 bits of the pre-synthesis data acquired in step S2 (step S3). Next, the main CPU 31 synthesizes the pre-synthesis data masked in step S3 and the 8-bit data including the excitation pattern data acquired in step S1 (step S4). That is, the data output from the output terminals D0 to D7 of the main CPU 31 is 8-bit data, and the data acquired from the excitation pattern table 60 and the pre-synthesis data combined with this data are 8-bit data. However, since it is the upper 4 bits of the data acquired from the excitation pattern table 60 that has the information as the excitation pattern, by masking the lower 4 bits and synthesizing the data, the output terminal D0 is combined. The lower 4 bits of the data output from ~ D7 are not affected. Specifically, for example, in step S1, 8-bit data including the data of the excitation pattern of "00110000" is acquired, and in step S2, the pre-synthesis data of "00010001" (data in which the external signal 1 is ON) is acquired. Suppose you did. At this time, in the process of step S3, the AND (logical product) of the pre-synthesis data "00010001" acquired in step S2 and the mask data "00001111" is obtained, and the data "00000001" is obtained. Next, in the process of step S4, the OR (logical sum) of the data (masked pre-synthesis data) “00000001” acquired in step S3 and the data “00110000” acquired in step S1 is taken to obtain “00110001”. The composite data (data after synthesis) is obtained. By the above processing, the upper 4 bits (excitation pattern) can be updated while maintaining the values of the lower 4 bits.
The process of masking the lower 4 bits and synthesizing the two data is not limited to the above, and is a process that can update the excitation pattern without updating the value of the lower 4 bits, which is a value that is not desired to be updated. All you need is.

Next, the main CPU 31 saves the combined data (post-synthesized data) obtained in step S4 as data to be sent to the output port corresponding to the reels 20a to 20c for updating the excitation pattern (step S5). Then, the stored data is sent to the corresponding reels 20a to 20c via the corresponding output port at a predetermined timing. The combined data may be sent to the corresponding reels 20a to 20c at the time of creation.

As a result, the excitation pattern sent to the corresponding reels 20a to 20c is updated. Further, during the rotation of the reels 20a to 20c, the excitation pattern is repeatedly updated in the update order of 1 to 8 shown in FIG. 7 (a). Further, when the reels 20a to 20c are stopped, all the coils of the first phase to the fourth phase are excited by updating the excitation pattern in the update order of 1 to 2 shown in FIG. 7 (b). The reels 20a to 20c are stopped, and then the excitation of all the coils of the first phase to the fourth phase is stopped.

The pre-synthesis data and the post-combination data and the output terminals D0 to D7 of the main CPU 31 have the same numbered bits and the output terminals correspond to each other. That is, the 0th bit data of the combined data is output from the output terminal D0, the 1st bit data of the combined data is output from the output terminal D1, and the 2nd bit data of the combined data is output. The 3rd bit data of the post-synthesis data is output from the terminal D2, the 4th bit data of the post-synthesis data is output from the output terminal D4, and the 5th bit of the post-synthesis data is output from the output terminal D3. The data is output from the output terminal D5, the 6th bit data of the combined data is output from the output terminal D6, and the 7th bit data of the combined data is output from the output terminal D7. Since such 8-bit data is output, the output terminals D0 to D7 may be referred to as bits 0 to 7, respectively. Similarly, the input terminals D1 to D7 and the output terminals Q1 to Q7 of the flip-flops 32 to 34, respectively, may also be referred to as bits 0 to 7, respectively. Further, the wirings MD0 to MD7 may also be referred to as bit 0 to bit 7, respectively.
Further, the lower 4 bits of the pre-synthesis data or the post-synthesis data are set / reset bit by bit at predetermined timings. Then, each signal generated by this bit-by-bit set / reset and the excitation pattern updated by the excitation pattern update process are output from the output terminals D0 to D7 of the main CPU 31 at predetermined timings.

Here, problems in the conventional gaming machine will be described with reference to FIGS. 5 and 8. In the conventional gaming machine, for example, as shown in FIG. 5, the signal for the second reel 20b and the signal for the third reel 20c are transmitted via the same output port (flip-flop 33). Therefore, the number of processes in the excitation pattern update process has increased.

In this conventional gaming machine, as shown in FIG. 8, the main CPU 31 acquires an excitation pattern (step S11) and outputs an output port corresponding to the reels 20a to 20c for updating the excitation pattern, as in the gaming machine of the present invention. Acquires the current value (value before synthesis: data before synthesis) of the data to be sent to (step S12).
Next, the main CPU 31 determines whether or not to update the excitation pattern of the second reel 20b in the current excitation pattern update process (step S13).

When updating the excitation pattern of the second reel 20b (Yes in step S13), the main CPU 31 masks the upper 4 bits of the pre-synthesis data acquired in step S12 (step S14).
Next, the main CPU 31 inverts the upper 4 bits and the lower 4 bits of the masked pre-synthesis data (step S15). Next, the main CPU 31 synthesizes the inverted data and the excitation pattern acquired in step S11 (step S16). Next, the main CPU 31 inverts the upper 4 bits and the lower 4 bits of the data obtained by the synthesis (step S17). Next, the main CPU 31 stores the data (data after synthesis) obtained by synthesizing in step S16 and inverting in step S17 as data to be sent to the output ports corresponding to the second reel 20b and the third reel 20c. (Step S18).
Since the processing in the case of No in step S13 (steps S19, S20, S18) is the same as the processing in steps S3, S4, S5 described above, the description thereof will be omitted.

As described above, in this conventional gaming machine, since the flip-flop corresponding to the second reel 20b and the flip-flop corresponding to the third reel 20c are the same, the main CPU 31 has the same as the flip-flop 33. The data output from the output terminals D0 to D7 needs to include the data for the second reel 20b and the data for the third reel 20c. Therefore, among the output terminals D0 to D7 of the main CPU 31, the terminal on which the signal for controlling the second reel 20b is output and the terminal on which the signal for controlling the third reel 20c is output are different terminals. It ends up. In other words, in the data output from the output terminals D0 to D7 of the main CPU 31 to the flip-flop 33, the data for the second reel 20b and the data for the third reel 20c need to be assigned to different bits. There is. Therefore, as in steps S14 to S17, it is necessary to perform a calculation by inverting the high-order bit and the low-order bit, and the amount of code of the program related to the excitation pattern update process increases. Further, in the gaming machine of the present embodiment, if there is information about which output port the processing is for, the processing can be performed without determining which reel 20a to 20c the processing is for, whereas the conventional gaming machine can perform the processing. In step S13, it is necessary to perform a process of determining which reel 20a to 20c the process is for, and the amount of code of the program or the like increases. Further, it is possible to omit the inversion process by preparing the table data to which the excitation pattern is assigned to the lower 4 bits, but in this case, the data amount of the table data will increase.

On the other hand, according to the gaming machine of the present embodiment, the main CPU 31 outputs control signals from the same terminal groups D4 to D7 to the three reels 20a to 20c, so that the three reels 20a A control signal can be generated and output by the same excitation pattern update process for ~ 20c. Therefore, the process of controlling a plurality of reels can be facilitated and the program capacity can be reduced. In addition, according to the excitation pattern update process in the gaming machine of the present embodiment shown in FIG. 6, the capacity of the program can be suppressed to about half as compared with the excitation pattern update process in the conventional gaming machine shown in FIG.

Further, the control signals output from the same terminal groups D4 to D7 for the three reels 20a to 20c are passed through the three flip-flops 32 to 34 corresponding to the three reels 20a to 20c respectively. Since it is sent, it is possible to individually control the three reels 20a to 20c by the control signals output from the same terminal group D4 to D7.

Further, the three flip-flops 32 to 34 are the same IC. That is, not only the type of circuit (for example, D flip-flop, D latch, etc.) but also the number of terminals and the like are the same, and the model numbers are the same. Each of the output terminals D4 to D7 of the main CPU 31 is connected to the same input terminals D5 to D8 of the three flip-flops 32 to 34. Therefore, it is possible to facilitate the wiring work at the time of designing and assembling, and prevent wiring mistakes and the like. Further, since the flip-flops 32 to 34 have the same reaction speed and driving force, timing control in the main CPU 31 and design of the main control board 30 can be facilitated.

Of the signals output from the output terminals D0 to D7 of the main CPU 31 and sent to the flip-flops 32 to 34, the signals other than the signals controlling the reels 20a to 20c are different from the signals controlling the reels 20a to 20c, respectively. It may be generated by setting / resetting each bit, and it is not necessary to synthesize an excitation pattern consisting of data of a plurality of bits like a signal for controlling the reels 20a to 20c, so that the program capacity is not increased. It is possible to change the signal allocation from the conventional gaming machine as in the gaming machine of the present embodiment.

The slot machine 10 may include four or more reels. For example, when another reel is provided in addition to the reels 20a to 20c, the main control board 30 is provided with another flip-flop in addition to the flip-flops 32 to 34, and the control signal from the main CPU 31 is transmitted. It may be sent to an additional reel via an additional flip-flop. That is, it is provided with four or more reels and the same number of ICs (flip-flops) as the reels, and control signals from the main CPU 31 are transmitted to each reel via different ICs. May be good. In this case, the ICs may be the same IC or different ICs. Further, in the slot machine 10 of the second embodiment or the third embodiment described later, similarly, four or more reels and the same number of ICs as the reels are provided, and each reel is provided with the same number of ICs. The signal from the main CPU 31 may be transmitted via the IC of.

For example, when the slot machine 10 includes four reels, the input terminals D1 to D4 of the first output port (flip flop 32) are associated with the signal to the first reel 20a, and the input of the first output port is input. The signals to the second reel 20b are associated with the terminals D5 to D8, the signals to the third reel 20c are associated with the input terminals D1 to D4 of the second output port (flip flop 33), and the input terminal of the second output port. It is also conceivable to associate signals to the fourth reel (not shown) with D5 to D8, and to associate external signals 1 to 5 and the like with the input terminals D1 to D8 of the third output port (flip flop 34) and another IC. Be done.

Next, the generation of the above-mentioned "medal insertion signal (insertion signal)" and "medal payout signal (payout signal)" in the main CPU 31 will be described. As described above, the "medal insertion signal" is a signal that informs a device (external device) outside the gaming machine such as a hall computer of the number of medals inserted (bet). Further, the "medal payout signal" is a signal that informs a device outside the gaming machine such as a hall computer of the number of medals to be paid out.

The "medal insertion signal" and "medal payout signal" are generated by the signal control means 102. Specifically, the signal control means 102 generates pulses as a “medal insertion signal” for the number of times corresponding to the number of inserted (bet) medals (specified number). When the start lever 24 is operated as a game start operation, the signal control means 102 generates the pulse and outputs the pulse to the external device. Further, the signal control means 102 generates pulses as a “medal payout signal” for the number of times corresponding to the number of medals paid out as a result of the game. After the reels 20a to 20c are stopped, the signal control means 102 generates the pulse and outputs the pulse to the external device when the medal is paid out. The "medal payout signal" may be output to an external device before the medal is actually paid out (including the process of paying out from the hopper device and increasing the credit), and the medal is being paid out. It may be output to an external device, or it may be output to an external device after the medals have been paid out.
In the gaming machine of the present embodiment, when a replay wins a prize in a certain game, pulses corresponding to the number of medals inserted in the game are generated and output as a "medal payout signal". Will be done. Further, for the next game of the game, pulses corresponding to the number of times are generated and output as a "medal insertion signal". That is, if the replay wins a prize, there will be a payout according to the number of coins paid out in that game, and in the next game, there will be a payout according to the number of coins paid out. As a result, a "medal insertion signal" and a "medal payout signal" are generated. However, if the replay wins a prize without such a configuration, the number of payouts in that game and the number of inserts in the next game are regarded as "0", and a "medal insertion signal" and a "medal payout signal" are generated. Alternatively, it may be configured to output.

FIG. 9 shows an example of a “medal insertion signal” when three medals are inserted and a “medal payout signal” when three medals are paid out. The "medal insertion signal" and "medal payout signal" pulses are formed by an ON state (first state) that lasts 59.60 ms and an OFF state (second state) that lasts 59.60 ms. That is, the period of one pulse is 119.20 ms. Further, the "medal insertion signal" and the "medal payout signal" when the pulse is not output are in the OFF state. Therefore, when the "medal insertion signal" and the "medal payout signal" are considered by dividing them into 119.20 ms, the first half of each section is in the ON state or the OFF state depending on whether or not the medal is inserted or paid out (presence or absence of pulse). The latter half of each section is always in the OFF state. In other words, the first half of the specific period is in the ON state or the OFF state, and the latter half of the specific period is in the OFF state. Then, the switching from the ON state to the OFF state (OFF edge) occurs only when 1/2 of the specific period has elapsed, and the switching from the OFF state to the ON state (ON edge) has elapsed the specific period. It only happens when.

Next, the terminal board output control process (signal generation process) for generating such a “medal insertion signal” and / or a “medal payout signal” will be described with reference to the flowcharts shown in FIGS. 10 and 11.
The A register, B register, C register and HL register appearing in the following description are internal registers of the main CPU 31. Further, the zero flag and the carry flag appearing in the following description are flags set in the internal register of the main CPU 31.

First, the counter subtraction process, which is a general-purpose process called from the terminal board output control process, will be described with reference to FIG. The counter subtraction process is performed by the counter update means 104 that functions as a part of the signal control means 102. In the counter subtraction process, it is necessary to set the address (RWM area) of the RWM to be subtracted in the HL register.

In the counter subtraction process, first, the counter update means 104 reads the value (data) stored in the address set in the HL register (the RWM area indicated by the HL register) and sets it in the A register (step S31).

Next, the counter updating means 104 determines whether or not the value of the A register is “0” (step S32). When the value of the A register is "0" (YES in step S32), the counter updating means 104 sets the zero flag. On the other hand, when the value of the A register is not "0" (NO in step S32), the counter updating means 104 resets the zero flag. Further, the counter updating means 104 resets the carry flag regardless of the value of the A register. When the zero flag is set (YES in step S32), the counter subtraction process is terminated and the caller returns.

When the value of the A register is not "0" (NO in step S32), the counter updating means 104 compares the value of the A register with "2" and sets the carry flag according to the comparison result (step S33). Specifically, the counter updating means 104 sets the carry flag when the value of the A register is less than "2", and resets the carry flag when the value of the A register is "2" or more. Here, the value that the A register can take is any integer from 0 to 255. Therefore, the carry flag is set only when the value of the A register is "1" through the processes of steps S32 and S33, and when the value of the A register is other than "1", the carry flag is set. Is not set.

Next, the counter updating means 104 performs a decrement process for subtracting "1" from the value of the A register (step S34). The counter updating means 104 sets the zero flag when the value of the A register becomes "0" as a result of this subtraction, and resets the zero flag when the value does not become "0".

Next, the counter updating means 104 sets the value of the A register to the address indicated by the HL register (step S35).

As described above, in the counter subtraction process, when the value stored in the address indicated by the HL register is not "0", the processes of steps S33 to S35 are performed, and the value stored in the address indicated by the HL register is set to "1". reduce. Further, when the value stored in the address indicated by the HL register is "0", the value stored in the address indicated by the HL register is not changed as "0". If the value stored in the address indicated by the HL register is "0", the carry flag is reset and the zero flag is set. If the value stored in the address indicated by the HL register is "1", the carry flag is set and the zero flag is set. If the value stored in the address indicated by the HL register is "2" or more, the carry flag is reset and the zero flag is reset.

Next, the terminal board output control process will be described with reference to FIG. The terminal board output control process is executed once for every four timer interrupts. In the gaming machine of the present embodiment, the timer interrupt cycle is set to 1.49 ms, and the terminal board output control process is executed once every 5.96 ms.

First, the signal control means 102 sets the address of the pulse timer in the HL register (step S51). Here, the pulse timer makes it possible to measure and manage the pulse cycle (the specific period) of the "medal insertion signal" or the "medal payout signal". Specifically, the pulse timer is an area of RWM that stores data that enables measurement and management of the pulse cycle of the "medal insertion signal" or "medal payout signal". An integer value from "0" to "20" is stored in the pulse timer.

Next, the signal control means 102 (counter update means 104) performs counter subtraction processing (step S52). Specifically, the signal control means 102 performs a process of subtracting "1" from the value of the pulse timer. By this counter subtraction process, the value of the pulse timer is updated by a constant value at predetermined intervals (every 5.96 ms).

Next, the signal control means 102 sets "2" (twice) as the number of loops in the B register (step S53). Further, the signal control means 102 sets "0" as the initial value of the "medal insertion signal" in bit 0 (least significant bit) of the C register, and sets the initial value of the "medal payout signal" in bit 1 of the C register. Set to "0".
In the "medal insertion signal" and "medal payout signal", "0" corresponds to the OFF state and "1" corresponds to the ON state.

Next, the signal control means 102 determines whether or not the terminal board output signal (“medal insertion signal” and “medal payout signal”) is an OFF edge (step S54). Specifically, the signal control means 102 determines whether or not the value of the pulse timer after the subtraction in step S52 is the value “10” indicating the half cycle of the terminal board output signal, and determines “10”. If it is, it is determined that it is an OFF edge, and if it is not "10", it is determined that it is not an OFF edge. That is, in the process of step S54, it can be said that the signal control means 102 determines whether or not it is the timing at which the OFF edge of the "medal insertion signal" or the "medal payout signal" can occur. That is, in the gaming machine of the present embodiment, there is a possibility that the "medal insertion signal" or the "medal payout signal" is switched from the ON state to the OFF state (the possibility that an OFF edge occurs) is during a specific period. Since it is only the timing when 1/2 has elapsed (see FIG. 9), the signal control means 102 detects the timing based on the value of the pulse timer. When it is determined that the terminal board output signal is the OFF edge (timing at which the OFF edge can occur) (YES in step S54), the signal control means 102 shifts to the process of step S63. That is, the signal control means 102 determines the next process to be performed based on whether or not the value of the pulse timer reaches the threshold value “10”.
The terminal board output signal includes (combined) a "medal insertion signal" and a "medal payout signal". Further, in the terminal board output control process, the terminal board output signal can be said to be 8-bit data stored in the C register. The lower two bits (bit 0 and bit 1) of the data stored in the C register in the terminal board output control process correspond to the "medal insertion signal" and the "medal payout signal". Further, the upper 6 bits of the data stored in the C register in the terminal board output control process are all set to "0".

When it is determined that the terminal board output signal is not the OFF edge (timing at which the OFF edge can occur) (NO in step S54), the signal control means 102 determines whether or not the value of the pulse timer is "0" (step). S55). When it is determined that the value of the pulse timer is not "0" (NO in step S55), the terminal board output control process ends.

On the other hand, when the value of the pulse timer is determined to be "0" (YES in step S55), the signal control means 102 sets a predetermined value "20" in the pulse timer (step S56). In other words, the signal control means sets a predetermined value "20" in the pulse timer when the value of the pulse timer reaches the specific value "0".

Next, the signal control means 102 sets the address of the pulse counter in the HL register (step S57). Here, the pulse counter includes a pulse counter for the number of payouts for counting the number of payouts of medals and a pulse counter for the number of inserts for counting the number of inserts of medals. The payout number pulse counter is an area of RWM that stores a value corresponding to the payout number of medals. The pulse counter for the number of payouts stores a value corresponding to the number of medals to be paid out when the medals are paid out according to the determination result of the display determination process. Specifically, for example, when nine medals are paid out, the value "9" is stored in the payout number pulse counter. Further, the pulse counter for the number of inserted medals is an area of RWM for storing a value corresponding to the number of inserted medals. The pulse counter for the number of insertions stores a value corresponding to the number of medals inserted (bet) in the game when the game is performed triggered by the operation to start the game with respect to the start lever 24. Specifically, for example, when three medals are inserted, the value "3" is stored.

The processes of steps S57 to S62 are executed twice for each terminal board output control process, but in the first process of step S57, the address of the pulse counter for the number of payouts is set in the HL register for the number of payouts. The processing of steps S58 to S61 is performed on the pulse counter. Further, in the second process of step S57, the address of the input number pulse counter is set in the HL register, and the processes of steps S58 to S61 are performed for the input number pulse counter.

In the gaming machine of the present embodiment, the process of step S57 is a process of increasing the value of the HL register by "1". That is, in the gaming machine of the present embodiment, the pulse timer, the pulse counter for the number of payouts, and the pulse counter for the number of inputs are arranged at consecutive addresses on the RWM (storage means) in this order, and the first step S57. In the process of step S51, the address of the pulse counter for the number of payouts is set in the HL register by adding "1" to the value indicating the address of the pulse timer (value of the HL register) set in the process of step S51. .. Further, in the processing of the second step S57, "1" is added to the value indicating the address (value of the HL register) of the pulse counter for the number of payouts set in the processing of the first step S57, so that the HL register is registered. The address of the pulse counter for the number of inputs is set in.
The pulse timer, the payout number counter, and the input number pulse counter may be arranged at consecutive addresses on the RWM in the order of the pulse timer, the payout number pulse counter, and the payout number counter. That is, in the first process of step S57, the address of the input count pulse counter is set in the HL register, the input count pulse counters are processed in steps S58 to S61, and in the second step S57 process, they are dispensed. The address of the number pulse counter may be set in the HL register, and the processing of steps S58 to S61 may be performed on the payout number pulse counter.

Next, the signal control means 102 performs counter subtraction processing on the pulse counter set in the HL register in step S57 (step S58).

Next, the signal control means 102 determines whether or not the value of the pulse counter is “0” (step S59).

When the value of the pulse counter is not "0" (NO in step S59), the signal control means 102 sets the carry flag (step S60). On the other hand, when the value of the pulse counter is "0" (YES in step S59), the signal control means 102 proceeds to the process of step S61 without setting the carry flag.

In the processing of steps S58 to S60, if the value of the pulse counter before being subtracted by the counter subtraction processing is "0", the carry flag is reset in step S58 and the carry flag is not set thereafter, so that the content of the carry flag is It becomes "0". Further, when the value of the pulse counter before being subtracted by the counter subtraction process is "1", the carry flag is set in step S58, so that the content of the carry flag is "1". If the value of the pulse counter before being subtracted by the counter subtraction process is "2" or more, the carry flag is reset in step S58, but the carry flag is set in step S60, so that the content of the carry flag is It becomes "1". That is, in the processing of steps S58 to S60, when the value of the pulse counter before being subtracted by the counter subtraction processing is "0", the content of the carry flag becomes "0" and the pulse before being subtracted by the counter subtraction processing. When the value of the counter is "1" or more, the content of the carry flag is "1". Further, when the value of the pulse counter before being subtracted by the counter subtraction process is "1" or more, "1" is subtracted from the value of the pulse counter by the counter subtraction process.

Next, the signal control means 102 generates a terminal board output signal (step S61). Specifically, the signal control means 102 rotates the C register to the left. Therefore, in the first process of step S61, the content of the carry flag for the number of payouts is moved to bit 0 of the C register. Further, in the second process of step S61, the content of the carry flag for the number of payouts moved to bit 0 of the C register in the first process of step S61 is moved to bit 1 of the C register, and the number of input sheets is changed. The contents of the carry flag move to bit 0 of the C register. That is, as a result of the processing of the two steps S61, the information of the "medal payout signal" corresponding to the latest payout is stored in the bit 1 of the C register, and the latest insertion (bet) is made in the bit 0 of the C register. Information on the "medal insertion signal" is stored.

Next, the signal control means 102 determines whether or not the processing of steps S57 to S61 has been completed for both the number of payouts and the number of inputs (step S62), and if not, returns to the processing of step S57. If it is completed, the process proceeds to step S63. Specifically, the signal control means 102 subtracts "1" from the value of the B register in which "2" is set as the number of loops in step S53, and if the subtracted result is larger than "0", step S57. It is determined that the processing of to S61 has not been completed, and if the subtraction result is "0", it is determined that the processing of steps S57 to S61 has been completed. That is, when the signal control means 102 performs the processes of steps S57 to S61 twice, the signal control means 102 shifts to the process of step S63.

By the process of step S63, the information of the "medal insertion signal" is stored in the bit 0 of the C register, and the information of the "medal payout signal" is stored in the bit 1 of the C register by the processing up to this point. It will be. Further, at the start of the first half of the specific period, when the process of step S63 is executed, "0" or "1" is set in bit 0 and bit 1 of the C register, and the latter half of the specific period. At the start, when the process of step S63 is executed, "0" is set in bit 0 and bit 1 of the C register.

Next, the signal control means 102 sets the address of the second output port image in the HL register (step S63). Here, the second output port image is an area of RWM that stores information of an output signal transmitted from the main CPU 31 via the second output port 33, or information stored therein.

Next, the signal control means 102 reads the contents of the second output port image into the A register (step S64).

Next, the signal control means 102 masks the portion corresponding to the “medal insertion signal” and the “medal payout signal” with respect to the content of the second output port image read out to the A register (step S65). That is, as described above, since the signal transmitted from the main CPU 31 via the second output port 33 includes signals other than the "medal insertion signal" and the "medal payout signal", the terminal plate output control process is ". Process so that signals other than the "medal insertion signal" and "medal payout signal" do not fluctuate. Specifically, the signal control means 102 has data of bit 0 corresponding to the “medal insertion signal” and bit 1 corresponding to the “medal payout signal” for the A register from which the contents of the second output port image have been read. Is set to "0", and the data is maintained as it is for the other bits. More specifically, the signal control means 102 takes a logical product of the data of the A register and "11111100B", and stores the result in the A register.

Next, the signal control means 102 includes a signal other than the “medal insertion signal” and the “medal payout signal” included in the second output port image, and a terminal board output signal (“medal insertion signal” generated in the terminal board output control process. "And" medal payout signal ") are combined (step S66). Specifically, the signal control means 102 takes the logical sum of the data of the A register and the data of the C register, and stores the result in the A register.

Next, the signal control means 102 sets the data in the A register in the second output port image (step S67). This completes the terminal board output control process.

As described above, in the terminal board output control process, the pulse timer is updated once every 5.96 ms, and makes one round with 20 updates. That is, the pulse timer loops with a period of 119.20 ms. Then, one lap of the pulse timer is in the specific period, that is, a specific period having a first half portion that is in the ON state or the OFF state and a second half portion that is always in the OFF state depending on the presence or absence of the insertion or withdrawal (pulse) of the medal. It is designed to correspond. Therefore, the pulse timer makes it possible to determine the start point and end point of the specific period and the 1/2 elapsed point of the specific period.

When 1/2 of the specific period measured by the pulse timer elapses, the signal control means 102 turns off the "medal insertion signal" and the "medal payout signal" regardless of the signal states up to that point. Further, when the specific period measured by the pulse timer ends and the next specific period starts, the signal control means pays for the value of the pulse counter for the number of inserted medals indicating the number of medals inserted in the game or in the game. It is determined whether or not to turn on the "medal insertion signal" or "medal payout signal" based on the value of the payout pulse counter indicating the number of issued medals.

According to the gaming machine of the present embodiment, the signal control means 102 that generates a "medal insertion signal" that informs the number of insertions of the game medium used for the game is provided, and the signal control means 102 has a predetermined interval (5.96 ms interval). ) To update the stored value of the pulse timer by a fixed value "1", and to set the "medal insertion signal" to the ON state (first state) until the stored value of the pulse timer reaches the threshold value "10". After the stored value of the pulse timer reaches the threshold value "10", the process of turning the "medal insertion signal" into the OFF state (second state) and the case where the stored value of the pulse timer reaches the specific value "0". The pulse timer is set to a predetermined value "20", and the "medal insertion signal" is turned on (first state) and OFF (second state) for the number of times according to the number of times the game medium is inserted. ) And can be repeated.

Further, according to the gaming machine of the present embodiment, the signal control means 102 for generating a "medal payout signal" notifying the number of payouts of the game medium to be paid out as a result of the game is provided, and the signal control means 102 is provided with a predetermined interval (5). The process of updating the stored value of the pulse timer by a constant value "1" at intervals of .96 ms) and the "medal payout signal" being turned on (first state) until the stored value of the pulse timer reaches the threshold value "10". ), And after the stored value of the pulse timer reaches the threshold value "10", the process of turning the "medal payout signal" to the OFF state (second state) and the stored value of the pulse timer to the specific value "0". When it reaches, the process of setting the predetermined value "20" to the pulse timer is performed, and the "medal payout signal" is turned on (first state) and turned off (first state) for the number of times according to the number of input of the game medium. The second state) can be repeated.

As mentioned above, the edges of the "medal insertion signal" and "medal payout signal" always occur at the switching point between the first half and the second half of the specific period, and in the latter half of the specific period, the "medal insertion signal" and "medal" The payout signal is always in the OFF state. In the gaming machine of the present embodiment, when the stored value of the pulse timer reaches the specific value "0", the process of setting the predetermined value "20" in the pulse timer and the pulse timer are updated by a constant value at predetermined intervals. The processing makes it possible to measure the specific period, and determines the switching point from the first half to the second half of the specific period based on whether or not the stored value of the pulse timer reaches the threshold value "10". It is possible. Therefore, it is determined whether or not it is a switching point between the first half and the second half of the specific period, and only at this switching point, the process of switching between the ON state and the OFF state of the "medal insertion signal" or "medal payout signal" is performed. It becomes possible to do. In addition, the "medal insertion signal" and "medal payout signal" are always turned off in the latter half of the specific period, and turned on when the medal is inserted or paid out in the first half of the specific period. It is possible to determine the signal state according to whether the current corresponds to the first half or the second half of a specific period, such as turning it off. Therefore, a "medal insertion signal" or a "medal payout signal" can be generated by a simple process (program) and output to an external device.

The threshold value of the pulse timer does not necessarily have to be able to determine the lapse of 1/2 of the specific period, and may be any value as long as it can determine the lapse of a predetermined period of the specific period. In other words, the threshold value may be any as long as it can determine the timing at which the ON edge or OFF edge of the "medal insertion signal" or "medal payout signal" can occur.

The flow shown in the flowchart described in the present specification is merely an example, and the order and configuration of each process may be different.

10 slot machine (game machine)
30 Main control board 102 Signal control means

Claims (1)

A signal control means for generating a payout signal for notifying the number of payouts of the game medium to be paid out as a result of the game and an input signal for notifying the number of payouts of the game medium used for the game.
A storage means including a timer, a payout number counter that stores a value corresponding to the payout number, and an input number counter that stores a value corresponding to the payout number.
The payout number counter and the register in which the address of the input number counter can be set are provided.
The signal control means is
The process of updating the stored value of the timer by a fixed value at predetermined intervals, and
The process of setting the payout signal to the first state until the stored value of the timer reaches the threshold value, and setting the payout signal to the second state after the stored value of the timer reaches the threshold value.
The process of setting the input signal to the first state until the stored value of the timer reaches the threshold value, and setting the input signal to the second state after the stored value of the timer reaches the threshold value.
A process of setting a predetermined value in the timer when the stored value of the timer reaches a specific value.
A series of processes for setting the address of the payout counter in the register and updating the payout counter, and
The address of the input number counter is set in the register, and a series of processes for updating the input number counter are performed.
The first state and the second state of the payout signal are repeated as many times as the number of payouts.
It is a gaming machine that repeats the first state and the second state of the input signal by the number of times corresponding to the input number.
A series of processes for setting the address of the payout number counter in the register and updating the payout number counter, and a series of processes for setting the address of the input number counter in the register and updating the input number counter. Is a gaming machine characterized in that it is executed by looping one series of processes.

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