JP2022010853A - Wiring board and manufacturing method thereof - Google Patents

Abstract

To provide a build-up wiring board with a stack via structure with fewer dents in a portion where only an insulating resin layer is laminated at the periphery of a region where a plurality of stack vias are in close contact with one another and a manufacturing method thereof.SOLUTION: A wiring board includes at least a plurality of core substrates each having a wiring layer and an insulating layer, a plurality of build-up layers in each of which the insulating layer and the wiring layer are sequentially laminated on the core substrate, and a plurality of stack vias formed by overlapping and connecting via conductors penetrating the build-up layer, and in the wiring layer of each of the core substrate and the build-up layer, a distance between a wiring layer pattern around the region where the stack vias are in close contact with one another (hereinafter referred to as a stack via region) and the end of the land of the stack via (hereinafter referred to as a gap) varies depending on the core substrate and each layer of the build-up layer.SELECTED DRAWING: Figure 1

Description

The present invention relates to a wiring board having a stack via structure and a manufacturing method thereof.

A build-up wiring board having a stacked via (also referred to as stacked via) structure (see Patent Document 1) has been put into practical use in order to meet the demands for higher functionality, smaller size, and lighter weight of electronic devices.

In the conventional build-up wiring board, a printed wiring board in which a plurality of wiring layers are conducted by conducting through holes is used as a core board, and a build-up layer composed of an insulating layer and a wiring layer is laminated one after another on both sides or one side of the core board. Further, in this process, a via conductor for inter-layer conduction between wiring layers of different build-up layers is also formed, and a multi-layered build-up layer is arranged.

FIG. 4 is a schematic cross-sectional view of a conventional wiring board, and assumes a case where three build-up layers 52, 53, and 54 are laminated on the core layer 40.

An insulating layer 12 made of an insulating resin layer is formed by hot pressing on a core layer 40 having an insulating layer 11 and a wiring layer 21, and then a wiring layer 22 and a via conductor 30 are formed to form a build-up layer 52. Form. The via conductor 30 is intended to conduct interlayer conduction between the land 35 in the wiring layer 22 and the land 35 in the wiring layer 21 of the core layer 40 in the stack vias SV1, SV2, and SV3. Further, there is a wiring pattern P21 of the wiring layer 21 in the wiring pattern formation position range H1 around the stack via SV1. Further, there is a wiring pattern of the wiring layer 21 in the wiring pattern portion H2 around the stack via SV3.

Similarly, an insulating layer 13 made of an insulating resin layer is formed by hot pressing on a build-up layer 52 having an insulating layer 12, a wiring layer 22, and a via conductor 30, and then the wiring layer 23 and the via conductor 30 are formed. Form. In the stack via portions S1, S2, and S3, the via conductor 30 establishes an interlayer conduction between the land 35 in the wiring layer 23 and the land 35 in the wiring layer 22 of the build-up layer 52. Further, there is a wiring pattern of the wiring layer 22 in the wiring pattern portion H1 around the stack via SV1. Further, there is a wiring pattern of the wiring layer 22 in the wiring pattern portion H2 around the stack via portion SV3.

Similarly, an insulating layer 14 made of an insulating resin layer is formed by hot pressing on a build-up layer 53 having an insulating layer 13, a wiring layer 23, and a via conductor 30, and then the wiring layer 24 and the via conductor 30 are formed. Form. The via conductor 30 is intended to conduct interlayer conduction between the land 35 in the wiring layer 24 and the land 35 in the wiring layer 23 of the build-up layer 53 in the stack vias SV1, SV2, and SV3. Further, there is a wiring pattern of the wiring layer 23 in the wiring pattern formation position range H1 around the stack via SV1. Further, there is a wiring pattern of the wiring layer 23 in the wiring pattern formation position range H2 around the stack via portion SV3.

In the stack vias SV1, SV2, and SV3, the land 35 in the wiring layer 24 exposed is joined to the terminal of the semiconductor chip 60.

As described above, in the formation of the build-up layer, the insulating resin to be the insulating layer is first laminated by a hot press, and then the via conductor and the wiring layer are formed. There is either an insulating resin layer or a wiring layer which is a metal pattern in the base portion where the insulating resin is laminated. When the base was an insulating resin layer, the thickness of the insulating resin was thinner than that when the metal pattern was on the base due to the flow during hot pressing in the step of laminating the insulating resin.

Further, the stack via structure is often arranged in a grid pattern in a plan view according to the connection pattern of the semiconductor chip mounting portion to the substrate, whereas the semiconductor chip mounting portion is arranged. In many cases, no wiring pattern is placed in the peripheral part of. Therefore, since the density of wiring patterns is extremely different between the mounting portion of the semiconductor chip and its peripheral portion, when the build-up layer is multi-layered, the dent is increased around the mounting portion of the semiconductor chip. It will be. That is, in the build-up wiring board having the stack via structure, the amount of dent on the surface of the insulating resin layer tends to be large in the peripheral portion where the stack via is arranged. FIG. 5 is a schematic cross-sectional view of the conventional wiring board shown in FIG. 4, and shows an explanatory diagram of a state when a dent is generated around the stack via. As shown in the range K1 and K2 in FIG. 5, a dent is formed.

In the recessed part of the surface of the insulating resin layer, the conductor of the electroless plating layer part used when wiring is formed by the semi-additive method (see Patent Document 2) cannot be completely removed, and a short circuit due to unnecessary conduction between wirings cannot be completely removed. There was a risk of (short circuit) and a defect that caused the wiring width of the wiring layer to increase.

In the process of forming wiring on the layer having a recessed portion on the surface of the insulating resin layer by the semi-additive method (see Patent Document 2), the dry film resist is patterned and plated on the planned installation portion of the wiring layer without the dry film resist. When the wiring layer is formed, the plating will enter the non-electrolytic plating layer part under the dry film resist that is not planned to be installed. Therefore, after the wiring layer is formed, the dry film resist By etching, it is not possible to completely remove the plating in which the plating has entered the electroless plating layer portion with the electroless plating layer, and there is a possibility that a short circuit (short circuit) may occur due to conduction between unnecessary wirings.

The problems of this prior art will be described with reference to the accompanying drawings. 6 to 8 are schematic cross-sectional views illustrating a conventional manufacturing process of a wiring board having a stack via region.

It is assumed that the build-up layer 52 is laminated on the core substrate 40 and there are two stack vias in the cross section. The horizontal range in which the stack vias are formed is defined as the stack via formation ranges S1 and S2.

The pattern of the wiring layer 21 is formed on the insulating layer 11 on the core substrate 40. In the wiring layer 21, the wiring patterns P21 of the wiring pattern formation position ranges H1 and H2 and the lands 35 (L21S1 and L21S2) are formed (FIG. 6A).

An insulating layer material sheet is placed on the insulating layer 12 as the insulating layer 12. For example, a prepreg is used as the insulating layer material sheet (FIG. 6 (b)).

The insulating layer material sheet is softened by heating in an oven or the like, and the insulating layer material sheet is adhered to the pattern of the wiring layer 21, laminated, and cured to form the insulating layer 12 (FIG. 6 (c)). .. Where there is no wiring pattern of the wiring layer 21, the insulating layer material sheet falls into the lower insulating layer 11 (core substrate 40) due to its fluidity, and a recess is formed in the upper part of the insulating layer 12.

The recess of the insulating layer 12 above the wiring between the wiring pattern P21 and the land 35 (L21S1) (range location K1) and the recess of the insulating layer 12 between the wiring of the land 35 (L21S2) and the wiring pattern P21 (range location). The volume of K2) is relatively large, and the volume of the recess (range portion i) of the insulating layer 12 between the land 35 (L21S1) and the land 35 (L21S2) is smaller than this.

A via hole 31 is formed on the land 35 (L21S1, L21S2) in the wiring layer 21. It is done by laser irradiation or a drill or the like (FIG. 6 (d)).

The surface of the product manufactured above is electroless plated, and an electroless plating layer 80 capable of electrically conducting is formed on the upper surface. (Fig. 7 (e)).

The dry film resist 85 is laminated on the surface of the product manufactured above. The lower surface of the dry film resist has adhesiveness, and the dry film resist 85 and the insulating layer 12 (consisting of an insulating layer material sheet) can be adhered to each other, but the fine recesses on the insulating layer 12 follow the dry film resist 85. However, the relatively large recesses on the insulating layer 12 do not follow the dry film resist 85 sufficiently, and cavities may occur (FIG. 7 (f)).

The recess (range location K1) of the insulating layer 12 above the wiring between the wiring pattern P21 and the land 35 (L21S1), and the recess (range location) of the insulating layer 12 above the wiring between the land 35 (L21S2) and the wiring pattern P21. Since the volume of K2) is large, it is assumed that a cavity is formed between the dry film resist 85 and the insulating layer 12.

Since the volume of the recess (range point i) of the insulating layer 12 between the land 35 (L21S1) and the land 35 (L21S2) is small, no cavity is formed between the dry film resist 60 and the insulating layer 12, and the insulating layer 12 is in close contact with each other. ing.

A positive film 90 is placed on the film manufactured above, and exposure light U such as UV light is irradiated from above as shown in the figure (FIG. 7 (g)). The high transparency of the positive film 90 is the exposure light. U permeates and irradiates the dry film resist 85 to cure the dry film resist 85. Where the positive film 90 is not transparent, the exposure light U does not pass through, the dry film resist 85 is not irradiated, and the dry film resist 85 does not cure.

After the exposure light U irradiation is completed, the positive film 90 is removed and developed. The portion photo-cured by the dry film resist 85 remains, and the uncured portion disappears by melting, and the dry film resist 85 selectively remains (FIG. 8 (h)). At the range points K1 and K2, the cavity between the insulating layer 12 and the dry film resist 85 remains.

Electroplat the surface of the above. The electroless plating layer 80 exposed between the dry film resists 85 is electroplated to form the wiring layer 22 (FIG. 8 (i)).

Wiring patterns P22 are formed in the wiring pattern forming position ranges H1 and H2, lands 35 (L22S1 and L22S2) are formed in the stack via forming ranges S1 and S2, and the entire inside of the via hole 1 is also electroplated. The lands 35 (L22S1, L22S2) are electrically connected to the lands 35 (L21S1, L21S2) in the wiring layer 21 by vias 30 (V52S1, V52S2) (FIG. 8 (i)).

Land 35 (L22S1), via 30 (V52S1) and land 35 (L21S1) form a stack via SV1, land 35 (L22S2), via 30 (V52S2) and land 35 (L21S2) form a stack via SV2. The stack via SV1 and the stack via SV2 are in close contact with each other and form a stack via region.

At the time of electroplating, the plating solution infiltrates the cavity between the insulating layer 12 and the dry film resist 85 at the range points K1 and K2, and the electroless plating layer 80 on the insulating layer 12 in the cavity is electroplated. A plating layer may be formed. It is assumed that a certain amount of electroplating layer is formed in the cavities of K1 and K2 in the range.

The surface of the above is entirely etched, the dry film resist 85 is melted, and the surface of the plating layer on the wiring pattern P22 and the land 35 (L22S1, L22S2) is also surface-polished (FIG. 8 (j)).

If the plating layer formed in the cavities of the range points K1 and K2 is thick, it cannot be removed by etching and remains, and remains between the wiring pattern P21 and the land 35 (L22S1) or the wiring pattern land 35 (L22S1). It causes problems such as an electrical short circuit between the wiring pattern P21 and a thickening of the line width on the wiring pattern P22 and the land 35 (L22S1, L22S2).

In the case of one build-up layer on the core substrate, in reality, the build-up layer may be further laminated. Further, when the build-up layer is laminated on the upper layer, there is a possibility that the wiring layer of the laminated build-up layer may cause the same problem. When the lands and via conductors are stacked vertically, the recesses in the resin laminated part between the wiring pattern in the wiring pattern formation position range around the stack via area and the periphery of the stack via area form a build-up layer. It is accumulated every time it is stacked.

In a build-up wiring board with a stack via structure, where only the insulating resin layer around the area where the stack vias are placed is laminated, if the wiring board has few dents, the wiring pattern and the electrical between the lands are electrical. It has been desired not to cause a short circuit or a problem such as a thick line width on the wiring pattern P22 and the land 35 (L22S1, L22S2).

Japanese Unexamined Patent Publication No. 2008-112987 Japanese Unexamined Patent Publication No. 2001-24324

It is an object of the present invention to provide a wiring board having a stack via structure and a wiring board having few dents in a portion where only an insulating resin layer is laminated in a peripheral portion of a region where a plurality of stack vias are in close contact with each other and a method for manufacturing the wiring board. ..

The present invention has been made to solve the above problems, and in the invention according to claim 1 of the present invention, a core substrate having a wiring layer and an insulating layer, and an insulating layer and a wiring layer on the core substrate are sequentially arranged. A wiring board having at least a plurality of stacked vias formed by stacking and connecting a build-up layer and a via conductor penetrating the build-up layer, in the wiring layer of the core board and each layer of the build-up layer. , The distance between the wiring layer pattern around the region where the stack vias are in close contact (hereinafter referred to as the stack via region) and the end of the land of the stack via (hereinafter referred to as the gap) is the difference between the core board and the build-up layer. It is a wiring board characterized by being different for each layer.

The invention according to claim 2 of the present invention is characterized in that the gap between the core substrate and the wiring layer of each of the build-up layers gradually increases from the core substrate toward the upper layer. It is a wiring board of.

The invention according to claim 3 of the present invention is characterized in that the gap between the core substrate and each layer of the build-up layer increases equally from the core substrate toward the upper layer. It is a wiring board.

The invention according to claim 4 of the present invention penetrates the core substrate having the wiring layer and the insulating layer, the build-up layer in which the insulating layer and the wiring layer are sequentially laminated on the core substrate, and the build-up layer. This is a method of manufacturing a wiring board having at least a plurality of stack vias in which via conductors are overlapped and connected, and is a step of forming a wiring layer on the surface of the core substrate and stack vias are formed on the surface of the core substrate. It has a multi-layered build-up layer forming step, and has a wiring layer pattern around the stack via region and an end portion of a land of the stack via in the wiring layer of the core substrate and each layer of the build-up layer. This is a method for manufacturing a wiring board, characterized in that the spacing (gap) differs depending on the core board and each layer of the build-up layer.

The invention according to claim 5 of the present invention is the wiring board according to claim 4, wherein the gap between the core substrate and each of the build-up layers gradually increases from the core substrate toward the upper layer. It is a manufacturing method.

The wiring according to claim 5 of the present invention is characterized in that the gap between the core substrate and each of the build-up layers increases equally from the core substrate to the upper layer. This is a method for manufacturing a substrate.

In a build-up wiring board having a stack via structure, it becomes possible to provide a wiring board having few dents and a manufacturing method thereof in a portion where only the insulating resin layer in the peripheral portion of the portion where the stack via is arranged is laminated. We can provide a wiring board and its manufacturing method that do not have a wiring pattern around the part where the stack vias are placed and an electrical short circuit (short circuit) defect of the vias, and also arrange the wiring around the area where multiple stack vias are in close contact. Therefore, it is possible to provide a wiring board having a high wiring density and a method for manufacturing the wiring board.

It is a schematic cross-sectional view of the wiring board in embodiment of this invention. It is a schematic cross-sectional view of the wiring board in Embodiment of this invention, and is the figure which included the explanation of the gap. It is a schematic cross-sectional view of the wiring board which explains embodiment of this invention. It is a schematic cross-sectional view of the conventional wiring board. It is a schematic cross-sectional view of a conventional wiring board, and is explanatory drawing of the state when a dent occurs around a stack via. It is a schematic cross-sectional view explaining the manufacturing process of the conventional wiring board. It is a schematic cross-sectional view explaining the manufacturing process of the conventional wiring board. It is a schematic cross-sectional view explaining the manufacturing process of the conventional wiring board.

The wiring board according to the embodiment of the present invention penetrates the core substrate having the wiring layer and the insulating layer, the build-up layer in which the insulating layer and the wiring layer are sequentially laminated on the core substrate, and the build-up layer. A wiring board having at least a plurality of stacked vias formed by overlapping and connecting via conductors, and in a wiring layer of the core substrate and each of the build-up layers, a region in which the stack vias are in close contact with each other (hereinafter, a stack via region). The distance between the wiring layer pattern around (referred to as) and the end of the land of the stack via (hereinafter referred to as a gap) differs depending on the core substrate and each layer of the build-up layer.

An embodiment of the wiring board of the present invention will be described with reference to the accompanying drawings. FIG. 1 is a schematic cross-sectional view of a wiring board according to an embodiment of the present invention.

The wiring board 100 according to the embodiment of the present invention is a build-up layer formed by laminating a core substrate 40 having a wiring layer 21 on the surface and an insulating layer 11 on the core, and an insulating layer and a wiring layer on the core substrate 40. The stack vias SV1, SV2, and SV3 are adjacent to each other in the three layers 52, 53, and 54, and the three layers of the build-up layer to form a stack via region.

In the wiring layer of the core board 40 and each layer 52, 53, 54 of the build-up layer, the distance between the wiring layer pattern around the region where a plurality of stack vias are in close contact (hereinafter referred to as the stack via region) and the end of the land of the stack via. (Hereinafter referred to as a gap) is characterized in that it differs depending on the core substrate 40 and each of the build-up layers 52, 53, 54.

FIG. 2 is a schematic cross-sectional view of a wiring board according to an embodiment of the present invention, and is a diagram including an explanation of a gap.

In the wiring layer 21 of the core substrate 40, the dimension of the gap between the wiring layer pattern P21 around the stack via region and the end of the land 35 of the stack via is the gap D1.

In the wiring layer 22 of the build-up layer 52, the dimension of the gap between the wiring layer pattern P21 around the stack via region and the end of the land 35 of the stack via is the gap D2.

In the wiring layer 23 of the build-up layer 53, the dimension of the gap between the wiring layer pattern P21 around the stack via region and the end of the land 35 of the stack via is the gap D3.

In the wiring layer 24 of the build-up layer 54, the dimension of the gap between the wiring layer pattern P21 around the stack via region and the end of the land 35 of the stack via is the gap D4.

The wiring boards 100 according to the embodiment of the present invention have different sizes of gaps D1, D2, D3, and D4.

From the core substrate 40 toward the surface, the gaps D1, D2, D3, and D4 in the wiring layers of the core substrate 40 and the build-up layers 52, 53, and 54 are gradually increased, that is,
D1 <D2 <D3 <D4
Is desirable.

Further, from the core substrate 40 toward the surface, the gaps D1, D2, D3, and D4 in the wiring layer between the core substrate 40 and the build-up layer are equidistantly increased, that is, D1 <D2 <D3. <D4
And
D2-D1 = D3-D2 = D4-D3
Is desirable.

<Manufacturing method of wiring board>
The method of manufacturing the wiring board will be described with reference to the example of FIG.

A core substrate 40 having a wiring layer 21 and an insulating layer 11, and build-up layers 52, 53, 54 in which insulating layers 12, 13, 14 and wiring layers 22, 23, 24 are sequentially laminated on the core substrate 40. A method for manufacturing a wiring board having at least a plurality of stack vias in which via conductors 30 penetrating the build-up layers 52, 53, 54 are overlapped and connected is described.
It has a pattern forming step of the wiring layer 21 on the surface of the core substrate 40, and a forming step of build-up layers 52, 53, 54 having stack vias on the surface of the core substrate 40.
In the wiring layers of the core board 40 and the build-up layers 52, 53, 54, the gap between the wiring layer patterns P21, P22, P23, P24 around the stack via region and the end of the land 35 of the stack via is large. , The core substrate 40 and the build-up layer 52, 53, 54, respectively.

The details of the manufacturing method will be described below.

(Step of forming the wiring layer 21 on the surface of the core substrate 40)
The core substrate 40 composed of the insulating layer 11 and the wiring layer 21 forms a pattern of the wiring layer 21. The wiring layer 21 is composed of a wiring pattern P21 and lands 35 (L21S1, L21S2, L21S3) of stack via formation ranges S1, S2, and S3.

Further, there is a wiring pattern P21 of the wiring layer 21 in the wiring pattern portion H1 around the stack via formation range S1. Further, there is a wiring pattern P21 of the wiring layer 21 in the wiring pattern portion H2 around the stack via formation range S3.

In the wiring layer 21 of the core substrate 40, the dimension of the distance between the wiring layer pattern P21 around the stack via forming range S1 on the outer periphery of the stack region and the end of the land 35 (L21S1) of the stack via forming range S1 is a gap. It is D1.

(Step of forming build-up layers 52, 53, 54 having stack vias S1, S2, S3 on the surface of the core substrate 40)
Build-up layers 52, 53, and 54 are formed on the core substrate 40 by sequentially stacking them. In the step of forming the build-up layer 52 composed of the insulating layer 12 and the wiring layer 22 on the core substrate 40, the build-up layer 53 composed of the insulating layer 13 and the wiring layer 23 is formed on the build-up layer 52. It is the same process as the process. This is the same process as the process of forming the build-up layer 54 composed of the insulating layer 14 and the wiring layer 24 on the build-up layer 53.

An insulating layer 12 made of an insulating resin layer is formed by hot pressing on a core substrate 40 having an insulating layer 11 and a wiring layer 21, and then a wiring pattern P22 and a land 35, which are wiring layers 22, and a via conductor 30 are formed. It forms and forms the build-up layer 52. In the insulating layer 12, for example, a prepreg as an insulating material is laminated on a core substrate 40 having an insulating layer 11 and a wiring layer 21 by a hot press and cured to form a wiring layer 22. A via hole is formed on the pattern of the land 35 of the stack via S1 in the wiring layer 21 by laser irradiation or a drill or the like. Electroless plating is applied to this surface, and an electroless plating layer capable of electrical conduction is formed on the upper surface. Further, a dry film resist is laminated on this surface. Further, a positive film having a light and dark pattern is placed on this surface, and exposure light such as UV light is irradiated from above. The dry film resist cures where it corresponds to the bright part of the positive film and cures where it corresponds to the dark part of the positive film. After developing this, when electroplating of a conductor such as copper is performed, the conductor is plated on the exposed portion of the electroless plating layer other than the cured dry film resist, and the wiring pattern P22 and the wiring layer 22 composed of the land 35 are formed. , The via conductor 30 is formed inside the via hole.

The via conductors 30 (V52S1, V52S2, V52S3) are the lands 35 (L22S1, L22S2, L22S3) in the wiring layer 22 and the lands 35 (L22S3) in the wiring layer 21 of the core layer 40 in the stack via formation ranges S1, S2, S3. L21S1, L21S2, L21S3) are intended for interlayer conduction.

Further, there is a wiring pattern P22 of the wiring layer 22 in the wiring pattern portion H1 around the stack via portion S1. Further, there is a wiring pattern P22 of the wiring layer 22 in the wiring pattern formation position range H2 around the stack via S3.

In the wiring layer 22 of the build-up layer 52, the dimension of the distance between the wiring layer pattern P22 around the stack via S1 on the outer periphery of the stack area and the end of the land 35 (L22S1) of the stack via S1 is the gap D2. ..

Similarly, an insulating layer 13 made of an insulating resin layer is formed by hot pressing on the insulating layer 12, the wiring layer pattern P22 and the land 35 which are the wiring layers 22, and the build-up layer 52 having the via conductor 30. After that, the via conductor 30, the wiring layer pattern P23 which is the wiring layer 23, and the land 35 are formed.

The via conductors 30 (V53S1, V53S2, V53S3) are the land 35 (L23S1, L23S2, L23S3) in the wiring layer 23 and the land 35 in the wiring layer 22 of the build-up layer 52 in the stack via formation ranges S1, S2, S3. (L22S1, L22S2, L22S3) are intended for interlayer conduction.

Further, there is a wiring pattern P23 of the wiring layer 23 in the wiring pattern formation position range H1 around the stack via S1. Further, there is a wiring pattern P23 of the wiring layer 23 in the wiring pattern formation position range H2 around the stack via S3.

In the wiring layer 23 of the build-up layer 53, the dimension of the distance between the wiring layer pattern P23 around the stack via forming range S1 on the outer periphery of the stack area and the end of the land 35 (L23S1) of the stack via S1 is the gap D3. Is.

Similarly, an insulating layer 14 made of an insulating resin layer is formed by hot pressing on the insulating layer 13, the wiring layer pattern P23 and the land 35 which are the wiring layers 23, and the build-up layer 53 having the via conductor 30. After that, the via conductor 30 (V54S1, V54S2, V54S3) forming the via conductor 30, the wiring pattern P24 which is the wiring layer 24, and the land 35 is the land 35 in the wiring layer 24 in the stack via forming ranges S1, S2, S3. L24S1, L24S2, L24S3) and the land 35 (L23S1, L23S2, L23S3) of the wiring layer 23 of the build-up layer 53 are interconnected.

Further, there is a wiring pattern P24 of the wiring layer 24 in the wiring pattern formation position range H1 around the stack via formation range S1. Further, there is a wiring pattern P24 of the wiring layer 24 in the wiring pattern formation position range H2 around the stack via portion S3.

In the wiring layer 24 of the build-up layer 54, the dimension of the distance between the wiring layer pattern P24 around the stack via portion S1 on the outer periphery of the stack area and the end portion of the land 35 (L24S1) of the stack via S1 is the gap D4. The wiring board 100 according to the embodiment of the present invention has different sizes of gaps D1, D2, D3, and D4.

From the core substrate 40 toward the surface, the gaps D1, D2, D3, and D4 in the wiring layers of the core substrate 40 and the build-up layers 52, 53, and 54 are gradually increased, that is,
D1 <D2 <D3 <D4
Is desirable.

Further, from the core substrate 40 toward the surface, the gaps D1, D2, D3, and D4 in the wiring layer between the core substrate 40 and the build-up layer are equidistantly increased, that is, D1 <D2 <D3. <D4
And
D2-D1 = D3-D2 = D4-D3
Is desirable.

Conventionally, as shown in FIG. 5, in each layer of the core substrate and the build-up layer, the dimension (gap) of the distance between the wiring layer pattern around the stack via on the outer periphery of the stack area and the end of the land 35 of the stack via. ) Is the same and D, the size of the dent on the surface of the insulating resin layer generated in the overlapped portion of the insulating resin is large, and the electroless plating layer portion used when wiring is formed by the semi-additive method. There was a possibility that the conductor could not be completely removed, resulting in an electrical short circuit (short circuit) due to unnecessary conduction between the wirings.

According to the embodiment of the present invention, in each layer of the core substrate and the build-up layer, the dimension of the distance between the wiring layer pattern around the stack via on the outer periphery of the stack area and the end of the land 35 of the stack via around the stack area. Since the (gap) is different for each layer and D1 <D2 <D3 <D4, the size of the dent on the surface of the insulating resin layer generated in the portion where the insulating layers overlap is reduced.

In the process of forming wiring by the semi-additive method, the dry film resist is patterned, plating is applied to the planned wiring layer installation part, and when the wiring layer is formed, under the dry film resist located in a place other than the wiring layer installation planned. Since the plating does not penetrate into the electroless plating layer part in, the electroless plating layer can be completely removed by etching the dry film resist after the wiring layer is formed, and an electrical short circuit due to conduction between unnecessary wirings can be performed. There is no longer any fear of becoming a defect that causes (short circuit).

Further, since it is possible to arrange the wiring around the area where a plurality of stack vias are in close contact with each other, it is possible to provide a wiring board having a high wiring density.

Hereinafter, the effect of the present invention will be verified using examples. Further, the present invention is not limited to the following examples.

FIG. 3 is a schematic cross-sectional view illustrating an embodiment of the present invention.

<Formation of core substrate>
Prepared FR-4 substrate (glass epoxy resin impregnated copper-clad laminate, trade name: MCL-E-67 (manufactured by Hitachi Kasei Co., Ltd.), size: 340 x 510 x 0.8 mm, 35 μm thick copper foil on the surface) Then, a dry film type photosensitive copper etching resist layer was formed on the copper foil, and a wiring pattern was exposed on the copper etching resist layer by an exposure apparatus. After developing the exposed resist layer, the copper in the non-wiring portion was removed by a copper etching apparatus. After etching the copper, the remaining resist for copper etching was peeled off to produce a core substrate 40 on which the wiring pattern P21 and the land 35 were formed. A stack via is formed in the land 35 in a later step, and a region adjacent to the stack via is referred to as a stack via region. The distance between the wiring layer pattern P21 around the stack via region on the core board and the end of the land 35 around the stack via region is D1.

<Formation of build-up layer>
A thermosetting epoxy resin film in a semi-cured state as an insulating layer on the wiring pattern P21 and land 35 of the wiring layer (copper) of the core substrate 40 with a wiring layer obtained above (trade name: ABF-GX13). , Film thickness: 30 μm, manufactured by Ajinomoto Fine-Techno Co., Ltd.), and then heat-cured with a hot press device.

A hole for a via hole 31 was made in the insulating layer on the surface of the above-mentioned product by a UV-YAG laser processing device, and after desmear treatment, a copper layer was formed on the entire surface by an electroless plating method.

A photosensitive resist layer is formed on the copper layer formed by the electrolytic plating method, exposed using a photomask on which a wiring pattern is formed, and a development process is performed to remove unnecessary photosensitive resist from the exposed substrate. rice field. After that, copper plating was performed in an electrolytic copper plating bath while passing a current through the electroless plating layer. After the electroplating treatment is performed for a predetermined time, the resist layer is removed from the copper plating bath, the resist layer is peeled off by a peeling device, and the electroless plating of the portion that does not become the wiring portion is removed by the etching treatment to remove the wiring pattern P22, the land 35, and the like. The via conductor 30 was formed.

The formation of the above wiring pattern, land and via conductor was repeated for the number of layers of the build-up layer to form the wiring board 100 having the stack via region. The formed build-up layers are build-up layers 52, 53, and 54, and the total number of build-up layers is three.

By laminating the core substrate 40 and the build-up layers 52, 53, and 54 on the core substrate 40, the core substrate 40 having the insulating layer 11 and the wiring layer 21, and the build-up layer 52 having the insulating layer 12 and the wiring layer 22 are formed. The wiring board 100 includes a build-up layer 53 having an insulating layer 13 and a wiring layer 23, and a build-up layer 54 having an insulating layer 14 and a wiring layer 24.

<Stack via>
Stack vias in which lands 35 and via conductors 30 are vertically stacked are arranged in a grid array of 5 × 5, which forms a stack via region. In the cross-sectional view of FIG. 3, there are five stack vias SV1, SV2, SV3, SV4, and SV5. The hole diameter of the via hole is 60 μmφ. The land diameter of the land is 110 μmφ, and the distance between adjacent lands is 30 μm.

<Wiring pattern>
The thickness of the wiring layer (copper) is 15 μm common to all build-up layers.

A non-wiring portion was set on the outside of the land around the stack via region of 5 × 5, and a wiring pattern having a width of 300 μm was formed by electroplating so as to be adjacent to the non-wiring portion.

The width of the non-wiring portion in each of the build-up layers is called a gap, and the numerical values of the gaps in the build-up layers 52, 53, and 54 are D2, D3, and D4, respectively.

Build-up layer The area of the non-wiring part in each layer is called the gap part.

In each build-up layer, wiring patterns P22, P23, and P24 are formed with a width gap of the non-wiring portion from the periphery of the stack via region.

That is, the dimension of the distance between the wiring layer pattern around the stack via area and the end of the land around the stack via area is the gap, and in each of the build-up layer layers 52, 53, 54, the gap values are D2 and D3, respectively. , D4.

<Insulation evaluation pattern>
In the process of forming the wiring layer 24 of the build-up layer 54, when forming the wiring pattern P24, the land 35, and the via conductor, in the gap portion between the land around the stack via region and the wiring pattern P24 around the stack via region. , L / S = 30/30 μm, and three parallel wirings 70 were formed.

In the wiring layer 24 of the build-up layer 54, three parallel wirings formed at intervals of L / S = 30/30 μm were arranged between the stack via region and the wiring pattern around the stack via region, and the insulation property was evaluated. ..

(Example 1)
In each layer of the core board and the build-up layer, the distance between the wiring layer pattern P21 around the stack via region and the end of the land 35 around the stack via region is D1, D2, D3, and D4.
It is assumed that D1 = 100 μm, D2 = 1000 μm, D3 = 1500 μm, and D4 = 2000 μm.

The gap values are different between the core substrate and each build-up layer, and D1 <D2 <D3 <D4.

(Example 2)
In each layer of the core board and the build-up layer, the distance between the wiring layer pattern P21 around the stack via region and the end of the land 35 around the stack via region is D1, D2, D3, and D4.
It is assumed that D1 = 100 μm, D2 = 600 μm, D3 = 1300 μm, and D4 = 2000 μm.

The gap value in each layer of the core substrate and the build-up layer is different, and it is a condition that D1 <D2 <D3 <D4, and it is a condition that the gap value is arithmetically increased from D1 to D4.

(Comparative example)
In each layer of the core board and the build-up layer, the distance between the wiring layer pattern P21 around the stack via region and the end of the land 35 around the stack via region is D1, D2, D3, and D4.
It is assumed that D1 = 2000 μm, D2 = 2000 μm, D3 = 2000 μm, and D4 = 2000 μm.

The gap values in each layer of the core board and the build-up layer are equal conditions.

<Evaluation>
The insulation of the wiring board manufactured in Example 1, Example 2, and Comparative Example 1 was evaluated. The insulation evaluation results are shown in Table 1.

<Insulation evaluation>
Insulation was tested using three parallel wirings formed at intervals of L / S = 30/30 μm in the gap portion of the build-up layer 54. Check the insulation between the three inner wires and the outer right wire, and the insulation between the three inner wires and the outer left wire, and if there is no electrical short circuit, 〇 , If there is a short circuit in either or both, it is marked as x.

〇: There is no electrical short circuit. It is insulated.

X: There is an electrical short circuit. There is continuity between the wiring

From the results shown in Table 1, in Examples 1 and 2, the dimension (gap) of the distance between the wiring layer pattern around the stack via region in each layer of the core substrate and the build-up layer and the end of the land around the stack via region. However, it is different in each layer,
D1 <D2 <D3 <D4
It was confirmed that there was no electrical short circuit and that there was insulation.

On the other hand, as in the comparative example,
D1 = D2 = D3 = D4
It was confirmed that there was an electrical short circuit, there was continuity between the wiring, and there was no insulation.

11 ... Insulation layer 12 ... Insulation layer 13 ... Insulation layer 14 ... Insulation layer 21 ... Wiring layer 22 ... Wiring layer 23 ... Wiring layer 24 ... Wiring layer 30 ...・ ・ Via conductor 31 ・ ・ ・ Via hole 35 ・ ・ ・ Land 40 ・ ・ ・ Core substrate 52 ・ ・ ・ Build-up layer 53 ・ ・ ・ Build-up layer 54 ・ ・ ・ Build-up layer 60 ・ ・ ・ Semiconductor chip 70 ・ ・・ Wiring pattern (for insulation test)
80 ... Electroless plating layer 85 ... Dry film resist 90 ... Positive film 100 ... Wiring board 200 ... Wiring board D1 ... Gap (in wiring layer 21)
D2 ... Gap (in wiring layer 22)
D3 ... Gap (in wiring layer 23)
D4 ... Gap (in wiring layer 24)
D ... Gap H1, H2 ... Wiring pattern formation position range i ... Range location K1, K2 ... Range location P21 ... Wiring layer pattern (in wiring layer 21)
P22 ... Wiring layer pattern (in wiring layer 22)
P23 ... Wiring layer pattern (in wiring layer 23)
P24 ... Wiring layer pattern (in wiring layer 24)
L21S1, L21S2, L21S3 ... Land (in the wiring layer 21)
L22S1, L22S2, L22S3 ... Land (in the wiring layer 22)
L23S1, L23S2, L23S3 ... Land (in the wiring layer 23)
L24S1, L24S2, L24S3 ... Land (in the wiring layer 24)
SV1, SV2, SV3 ... Stack via SV4, SV5 ... Stack via S1, S2, S3 ... Stack via formation range S4, S5 ... Stack via formation position range V52S1, V52S2, V52S3 ... Via Conductor (in build-up layer 52)
V53S1, V53S2, V53S3 ... Via conductor (in build-up layer 53)
V54S1, V54S2, V54S3 ... Via conductor (in the build-up layer 54)

Claims (6)

A stack formed by stacking a core substrate having a wiring layer and an insulating layer, a build-up layer in which an insulating layer and a wiring layer are sequentially laminated on the core substrate, and a via conductor penetrating the build-up layer. A wiring board with at least multiple vias
In the wiring layer of each of the core board and the build-up layer, the distance between the wiring layer pattern around the region where the stack vias are in close contact with each other (hereinafter referred to as the stack via region) and the end of the land of the stack via (hereinafter referred to as the stack via region). A wiring board characterized in that the gap) differs depending on the core board and each layer of the build-up layer. The wiring board according to claim 1, wherein the gap between the core board and the wiring layer of each of the build-up layers gradually increases from the core board to the upper layer. The wiring board according to claim 2, wherein the gap between the core board and each layer of the build-up layer increases arithmetically from the core board to the upper layer. A stack formed by stacking a core substrate having a wiring layer and an insulating layer, a build-up layer in which an insulating layer and a wiring layer are sequentially laminated on the core substrate, and a via conductor penetrating the build-up layer. It is a manufacturing method using a wiring board having at least a plurality of vias.
The pattern formation process of the wiring layer on the surface of the core substrate and
On the upper layer of the core substrate, a step of forming a plurality of build-up layers having stack vias is provided.
In the wiring layer of the core board and each layer of the build-up layer, the gap between the wiring layer pattern around the stack via region and the end of the land of the stack via is determined by the core board and each layer of the build-up layer. A method of manufacturing a wiring board characterized by being different. The method for manufacturing a wiring board according to claim 4, wherein the gap between the core board and each of the build-up layers gradually increases from the core board toward the upper layer. The method for manufacturing a wiring board according to claim 5, wherein the gap between the core board and each of the build-up layers increases in an arithmetic progression from the core board toward the upper layer.

Images