JP2021525420A5 - - Google Patents

Info

Publication number
JP2021525420A5
JP2021525420A5 JP2020565488A JP2020565488A JP2021525420A5 JP 2021525420 A5 JP2021525420 A5 JP 2021525420A5 JP 2020565488 A JP2020565488 A JP 2020565488A JP 2020565488 A JP2020565488 A JP 2020565488A JP 2021525420 A5 JP2021525420 A5 JP 2021525420A5
Authority
JP
Japan
Prior art keywords
command
integrated circuit
controller
execution
compute
Prior art date
Application number
JP2020565488A
Other languages
English (en)
Japanese (ja)
Other versions
JP2021525420A (ja
JPWO2019226355A5 (https=
JP7313381B2 (ja
Filing date
Publication date
Priority claimed from US15/988,900 external-priority patent/US10877766B2/en
Application filed filed Critical
Publication of JP2021525420A publication Critical patent/JP2021525420A/ja
Publication of JPWO2019226355A5 publication Critical patent/JPWO2019226355A5/ja
Publication of JP2021525420A5 publication Critical patent/JP2021525420A5/ja
Application granted granted Critical
Publication of JP7313381B2 publication Critical patent/JP7313381B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2020565488A 2018-05-24 2019-05-09 ハードウェアアクセラレーションのためのハードウェアリソースの埋込みスケジューリング Active JP7313381B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/988,900 US10877766B2 (en) 2018-05-24 2018-05-24 Embedded scheduling of hardware resources for hardware acceleration
US15/988,900 2018-05-24
PCT/US2019/031443 WO2019226355A1 (en) 2018-05-24 2019-05-09 Embedded scheduling of hardware resources for hardware acceleration

Publications (4)

Publication Number Publication Date
JP2021525420A JP2021525420A (ja) 2021-09-24
JPWO2019226355A5 JPWO2019226355A5 (https=) 2022-05-17
JP2021525420A5 true JP2021525420A5 (https=) 2022-05-17
JP7313381B2 JP7313381B2 (ja) 2023-07-24

Family

ID=66641498

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020565488A Active JP7313381B2 (ja) 2018-05-24 2019-05-09 ハードウェアアクセラレーションのためのハードウェアリソースの埋込みスケジューリング

Country Status (6)

Country Link
US (1) US10877766B2 (https=)
EP (1) EP3803588A1 (https=)
JP (1) JP7313381B2 (https=)
KR (1) KR102668599B1 (https=)
CN (1) CN112204524B (https=)
WO (1) WO2019226355A1 (https=)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10761992B2 (en) * 2018-10-31 2020-09-01 Advanced Micro Devices, Inc. Shared loads at compute units of a processor
US10705993B2 (en) 2018-11-19 2020-07-07 Xilinx, Inc. Programming and controlling compute units in an integrated circuit
KR102737418B1 (ko) * 2018-12-13 2024-12-04 에스케이하이닉스 주식회사 데이터 처리 시스템 및 그것의 동작방법
US11294992B2 (en) * 2019-03-12 2022-04-05 Xilinx, Inc. Locking execution of cores to licensed programmable devices in a data center
US11443018B2 (en) * 2019-03-12 2022-09-13 Xilinx, Inc. Locking execution of cores to licensed programmable devices in a data center
US11500901B2 (en) 2019-06-28 2022-11-15 Nxp B.V. Apparatuses and methods involving synchronization using data in the data/address field of a communications protocol
US10996950B2 (en) * 2019-06-28 2021-05-04 Nxp B.V. Apparatuses and methods involving selective disablement of side effects caused by accessing register sets
US11010323B2 (en) 2019-06-28 2021-05-18 Nxp B.V. Apparatuses and methods involving disabling address pointers
US10985759B2 (en) 2019-06-28 2021-04-20 Nxp B.V. Apparatuses and methods involving a segmented source-series terminated line driver
US10999097B2 (en) 2019-06-28 2021-05-04 Nxp B.V. Apparatuses and methods involving first type of transaction registers mapped to second type of transaction addresses
KR102787374B1 (ko) 2019-12-20 2025-03-27 삼성전자주식회사 가속기, 가속기의 동작 방법 및 가속기를 포함한 디바이스
US11175957B1 (en) * 2020-09-22 2021-11-16 International Business Machines Corporation Hardware accelerator for executing a computation task
CN112783506B (zh) * 2021-01-29 2022-09-30 展讯通信(上海)有限公司 一种模型运行方法及相关装置
US11561733B2 (en) * 2021-02-05 2023-01-24 Micron Technology, Inc. Interrupt mode or polling mode for memory devices
CN113032010B (zh) * 2021-03-12 2022-09-20 歌尔科技有限公司 命令的传输控制方法、终端及计算机可读存储介质
CN114548389B (zh) * 2022-01-27 2025-10-10 苏州登临科技有限公司 异构计算中计算单元的管理方法及相应处理器
US11861010B2 (en) 2022-02-14 2024-01-02 Xilinx, Inc. Extensible device hosted root of trust architecture for integrated circuits
CN114637536B (zh) * 2022-03-25 2025-11-07 苏州登临科技有限公司 任务处理方法、计算协处理器、芯片及计算机设备
CN115168081B (zh) * 2022-09-08 2022-11-15 井芯微电子技术(天津)有限公司 转换电路和报文转换方法
CN115292053B (zh) * 2022-09-30 2023-01-06 苏州速显微电子科技有限公司 移动端cnn的cpu、gpu、npu统一调度方法

Family Cites Families (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4245306A (en) 1978-12-21 1981-01-13 Burroughs Corporation Selection of addressed processor in a multi-processor network
US6360243B1 (en) * 1998-03-10 2002-03-19 Motorola, Inc. Method, device and article of manufacture for implementing a real-time task scheduling accelerator
US6243736B1 (en) * 1998-12-17 2001-06-05 Agere Systems Guardian Corp. Context controller having status-based background functional task resource allocation capability and processor employing the same
US8913667B2 (en) * 1999-11-09 2014-12-16 Broadcom Corporation Video decoding system having a programmable variable-length decoder
US20100146256A1 (en) 2000-01-06 2010-06-10 Super Talent Electronics Inc. Mixed-Mode ROM/RAM Booting Using an Integrated Flash Controller with NAND-Flash, RAM, and SD Interfaces
CA2402018A1 (en) 2000-03-03 2001-09-13 Tenor Networks, Inc. High-speed data processing using internal processor memory space
US6477598B1 (en) 2000-07-20 2002-11-05 Lsi Logic Corporation Memory controller arbitrating RAS, CAS and bank precharge signals
US6829697B1 (en) * 2000-09-06 2004-12-07 International Business Machines Corporation Multiple logical interfaces to a shared coprocessor resource
US7346898B2 (en) * 2002-01-29 2008-03-18 Texas Instruments Incorporated Method for scheduling processors and coprocessors with bit-masking
WO2004051450A2 (en) * 2002-12-04 2004-06-17 Koninklijke Philips Electronics N.V. Software-based control of microprocessor power dissipation
WO2006031157A1 (en) 2004-09-16 2006-03-23 Telefonaktiebolaget Lm Ericsson (Publ) Routing based on transmission utilization
US7743176B1 (en) * 2005-03-10 2010-06-22 Xilinx, Inc. Method and apparatus for communication between a processor and hardware blocks in a programmable logic device
US7669037B1 (en) * 2005-03-10 2010-02-23 Xilinx, Inc. Method and apparatus for communication between a processor and hardware blocks in a programmable logic device
US7428603B2 (en) 2005-06-30 2008-09-23 Sigmatel, Inc. System and method for communicating with memory devices via plurality of state machines and a DMA controller
JP4936517B2 (ja) * 2006-06-06 2012-05-23 学校法人早稲田大学 ヘテロジニアス・マルチプロセッサシステムの制御方法及びマルチグレイン並列化コンパイラ
US7934113B2 (en) 2007-05-21 2011-04-26 Texas Instruments Incorporated Self-clearing asynchronous interrupt edge detect latching register
US8250578B2 (en) * 2008-02-22 2012-08-21 International Business Machines Corporation Pipelining hardware accelerators to computer systems
US7673087B1 (en) * 2008-03-27 2010-03-02 Xilinx, Inc. Arbitration for an embedded processor block core in an integrated circuit
US7737725B1 (en) * 2008-04-04 2010-06-15 Xilinx, Inc. Device control register for a processor block
US9547535B1 (en) 2009-04-30 2017-01-17 Nvidia Corporation Method and system for providing shared memory access to graphics processing unit processes
JP5521403B2 (ja) 2009-06-23 2014-06-11 ソニー株式会社 情報処理装置とリソース管理方法およびプログラム
US8056080B2 (en) * 2009-08-31 2011-11-08 International Business Machines Corporation Multi-core/thread work-group computation scheduler
US8423799B2 (en) * 2009-11-30 2013-04-16 International Business Machines Corporation Managing accelerators of a computing environment
DE102010028227A1 (de) * 2010-04-27 2011-10-27 Robert Bosch Gmbh Coprozessor mit Ablaufsteuerung
US8914805B2 (en) * 2010-08-31 2014-12-16 International Business Machines Corporation Rescheduling workload in a hybrid computing environment
US9405550B2 (en) 2011-03-31 2016-08-02 International Business Machines Corporation Methods for the transmission of accelerator commands and corresponding command structure to remote hardware accelerator engines over an interconnect link
CN102902581B (zh) * 2011-07-29 2016-05-11 国际商业机器公司 硬件加速器及方法、中央处理单元、计算设备
WO2013147887A1 (en) * 2012-03-30 2013-10-03 Intel Corporation Context switching mechanism for a processing core having a general purpose cpu core and a tightly coupled accelerator
US9378182B2 (en) * 2012-09-28 2016-06-28 Intel Corporation Vector move instruction controlled by read and write masks
US9582321B2 (en) * 2013-11-08 2017-02-28 Swarm64 As System and method of data processing
US10031773B2 (en) 2014-02-20 2018-07-24 Nxp Usa, Inc. Method to communicate task context information and device therefor
GB2525002B (en) * 2014-04-09 2021-06-09 Advanced Risc Mach Ltd Data processing systems
US9785473B2 (en) * 2014-07-14 2017-10-10 Nxp Usa, Inc. Configurable per-task state counters for processing cores in multi-tasking processing systems
US9022291B1 (en) 2014-07-24 2015-05-05 Apple Inc. Invisible optical label for transmitting information between computing devices
US9665509B2 (en) * 2014-08-20 2017-05-30 Xilinx, Inc. Mechanism for inter-processor interrupts in a heterogeneous multiprocessor system
SG11201702584UA (en) * 2014-10-05 2017-04-27 Amazon Tech Inc Emulated endpoint configuration
US9846660B2 (en) * 2014-11-12 2017-12-19 Xilinx, Inc. Heterogeneous multiprocessor platform targeting programmable integrated circuits
EP3218827B1 (en) * 2014-11-12 2020-05-27 Xilinx, Inc. Heterogeneous multiprocessor program compilation targeting programmable integrated circuits
JP6897574B2 (ja) * 2016-01-29 2021-06-30 日本電気株式会社 アクセラレータ制御装置、アクセラレータ制御方法およびプログラム
CN108713190B (zh) * 2016-03-31 2024-03-01 英特尔公司 用于加速安全存储能力的技术
GB2549722B (en) * 2016-04-25 2018-09-26 Imagination Tech Ltd Communications interface circuit architecture
EP4089531B1 (en) * 2016-12-31 2024-06-26 Intel Corporation Systems, methods, and apparatuses for heterogeneous computing
US10235736B2 (en) 2017-04-21 2019-03-19 Intel Corporation Intelligent graphics dispatching mechanism

Similar Documents

Publication Publication Date Title
JP2021525420A5 (https=)
CN108463808B (zh) 事件触发的可编程预取器
US10521375B2 (en) Controller for a memory system
JPWO2019226355A5 (https=)
US10782915B2 (en) Device controller that schedules memory access to a host memory, and storage device including the same
US9436470B2 (en) Restoring a register renaming map
CN107193761B (zh) 队列优先级仲裁的方法与装置
JP5548037B2 (ja) 命令発行制御装置及び方法
US9058217B2 (en) Preferential CPU utilization for tasks
US10019283B2 (en) Predicting a context portion to move between a context buffer and registers based on context portions previously used by at least one other thread
CN112384894B (zh) 存储偶然的分支预测以减少错误预测恢复的时延
GB2581836A (en) Handling ring buffer updates
US20150123980A1 (en) Method and apparatus for supporting programmable software context state execution during hardware context restore flow
CN108694078B (zh) 计算资源和用于处理中断的系统和方法
JP2013200692A (ja) メモリシステム
CN113128531B (zh) 一种数据处理方法及装置
CN101324839A (zh) 信息处理装置
CN118051265A (zh) 用于前端聚集/分散存储器合并的方法和装置
JP2004295195A (ja) 命令発行方法及び装置、中央演算装置、命令発行プログラム及びそれを記憶したコンピュータ読み取り可能な記憶媒体
US20260003505A1 (en) Data writing method and memory controller
EP2159701A1 (en) Cash control device and cash control method
CN101341471B (zh) 动态高速缓存管理的设备和方法
JP2011081564A (ja) 制御装置、記憶装置、演算処理装置および制御方法
JP2006031710A (ja) データ処理システム、方法およびキャッシュシステム
JP2008015668A (ja) タスク管理装置