JP2021506027A5 - - Google Patents

Download PDF

Info

Publication number
JP2021506027A5
JP2021506027A5 JP2020531647A JP2020531647A JP2021506027A5 JP 2021506027 A5 JP2021506027 A5 JP 2021506027A5 JP 2020531647 A JP2020531647 A JP 2020531647A JP 2020531647 A JP2020531647 A JP 2020531647A JP 2021506027 A5 JP2021506027 A5 JP 2021506027A5
Authority
JP
Japan
Prior art keywords
offset value
adjusted
frequency
pointer
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2020531647A
Other languages
English (en)
Japanese (ja)
Other versions
JP7299890B2 (ja
JP2021506027A (ja
Filing date
Publication date
Priority claimed from US15/837,951 external-priority patent/US10592442B2/en
Application filed filed Critical
Publication of JP2021506027A publication Critical patent/JP2021506027A/ja
Publication of JP2021506027A5 publication Critical patent/JP2021506027A5/ja
Application granted granted Critical
Publication of JP7299890B2 publication Critical patent/JP7299890B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2020531647A 2017-12-11 2018-09-24 ポインタオフセットを用いた非同期バッファ Active JP7299890B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US15/837,951 2017-12-11
US15/837,951 US10592442B2 (en) 2017-12-11 2017-12-11 Asynchronous buffer with pointer offsets
PCT/US2018/052378 WO2019118040A1 (en) 2017-12-11 2018-09-24 Asynchronous buffer with pointer offsets

Publications (3)

Publication Number Publication Date
JP2021506027A JP2021506027A (ja) 2021-02-18
JP2021506027A5 true JP2021506027A5 (enExample) 2021-11-04
JP7299890B2 JP7299890B2 (ja) 2023-06-28

Family

ID=66696195

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020531647A Active JP7299890B2 (ja) 2017-12-11 2018-09-24 ポインタオフセットを用いた非同期バッファ

Country Status (6)

Country Link
US (1) US10592442B2 (enExample)
EP (1) EP3724741B1 (enExample)
JP (1) JP7299890B2 (enExample)
KR (1) KR102427775B1 (enExample)
CN (1) CN111512261A (enExample)
WO (1) WO2019118040A1 (enExample)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7419944B2 (ja) * 2020-04-13 2024-01-23 富士通株式会社 半導体装置及び同期化方法
CN111949582B (zh) * 2020-08-25 2022-01-18 海光信息技术股份有限公司 指针同步装置及方法、异步fifo电路、处理器系统
US11967960B2 (en) * 2021-07-30 2024-04-23 Advanced Micro Devices, Inc. Methods and apparatus for synchronizing data transfers across clock domains using heads-up indications
CN116561027A (zh) 2022-01-27 2023-08-08 瑞昱半导体股份有限公司 异步先进先出内存的控制方法及对应的数据传输系统
US20250173090A1 (en) * 2023-11-26 2025-05-29 Qualcomm Incorporated Universal Flash Storage Device With Partial Buffer Flush and Flush Resume Functions

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9024084D0 (en) * 1990-11-06 1990-12-19 Int Computers Ltd First-in-first-out buffer
US6233629B1 (en) * 1999-02-05 2001-05-15 Broadcom Corporation Self-adjusting elasticity data buffer with preload value
US6738917B2 (en) * 2001-01-03 2004-05-18 Alliance Semiconductor Corporation Low latency synchronization of asynchronous data
US6801143B2 (en) 2002-06-28 2004-10-05 Intel Corporation Method and apparatus for generating gray code for any even count value to enable efficient pointer exchange mechanisms in asynchronous FIFO'S
US7107393B1 (en) * 2003-03-28 2006-09-12 Xilinx, Inc. Systems and method for transferring data asynchronously between clock domains
US6956776B1 (en) * 2004-05-04 2005-10-18 Xilinx, Inc. Almost full, almost empty memory system
US7519788B2 (en) 2004-06-04 2009-04-14 Micron Technology, Inc. System and method for an asynchronous data buffer having buffer write and read pointers
US7287105B1 (en) * 2005-01-12 2007-10-23 Advanced Micro Devices, Inc. Asynchronous-mode sync FIFO having automatic lookahead and deterministic tester operation
US8001409B2 (en) * 2007-05-18 2011-08-16 Globalfoundries Inc. Synchronization device and methods thereof
NO327377B1 (no) 2007-12-18 2009-06-22 Tandberg Telecom As Fremgangsmate og system for klokkedriftskompensering
US8270552B1 (en) 2009-02-26 2012-09-18 Maxim Integrated Products, Inc. System and method for transferring data from non-spread clock domain to spread clock domain
JP5331902B2 (ja) 2009-12-25 2013-10-30 富士通株式会社 信号復元回路、レイテンシ調整回路、メモリコントローラ、プロセッサ、コンピュータ、信号復元方法及びレイテンシ調整方法
GB2482303A (en) 2010-07-28 2012-02-01 Gnodal Ltd Modifying read patterns for a FIFO between clock domains
US8995207B2 (en) 2011-08-12 2015-03-31 Qualcomm Incorporated Data storage for voltage domain crossings
US8806118B2 (en) * 2012-11-05 2014-08-12 Sandisk Technologies Inc. Adaptive FIFO
US9429981B2 (en) 2013-03-05 2016-08-30 St-Ericsson Sa CPU current ripple and OCV effect mitigation

Similar Documents

Publication Publication Date Title
JP2021506027A5 (enExample)
KR101554294B1 (ko) 추론적 프리챠지의 검출
US20150212941A1 (en) Managing out-of-order memory command execution from multiple queues while maintaining data coherency
CN202453864U (zh) 基于fpga和ddr2 sdram的大容量异步fifo缓存
EP2808801B1 (en) Multiple data rate memory with read timing information
EP2539824A1 (en) Critical word forwarding with adaptive prediction
TW201137613A (en) Multi-modal data prefetcher
WO2007115004A1 (en) Dynamic update adaptive idle timer
US9214952B2 (en) Sensor time
US8010726B2 (en) Data processing apparatus and method for handling interrupts
US20160196231A1 (en) System and method for bus bandwidth management in a system on a chip
JP2019522858A5 (enExample)
WO2015176475A1 (zh) Fifo数据缓存器及其进行时延控制的方法、计算机存储介质
TWI433163B (zh) 記憶體控制器及其控制方法
US20070226382A1 (en) Method for improving direct memory access performance
US8332568B2 (en) Memory access determination circuit, memory access determination method and electronic device
US9411362B2 (en) Storage circuitry and method for propagating data values across a clock boundary
KR102570454B1 (ko) 반도체 메모리 장치 및 그의 동작 방법
CN104753500B (zh) 一种任意波形发生器
CN102403008B (zh) 音频播放中数据流断点续接的方法和系统、fifo控制器
CN112882659B (zh) 一种信息获得方法、装置、电子设备及存储介质
CN109446111A (zh) 存储器集成电路及其预取地址决定方法
CN114827076A (zh) 一种基于地址翻译单元的地址返回方法及系统
CN104658594B (zh) 下降沿触发延迟计数器及方法
JP5218225B2 (ja) メモリアクセス装置、メモリアクセスシステム及びメモリアクセス装置の処理方法