JP2021192072A - Display system, and video signal transmission error determination method - Google Patents

Abstract

To provide a data abnormality detection method with a small time delay in an irregular display system.SOLUTION: The display system includes: an irregular display panel 8 including an image display area 4 and a dummy display area 13 arranged outside this area; a transmission line 7 for transmitting the image data of the test pattern image corresponding to a test pattern area 14 in the dummy display area as first image data; a first memory 202 for holding the first image data; a calculation unit 401 in which the first image data becomes second image data after the transmission of the transmission line, and the CRC calculation is performed from the second image data to obtain the calculated value; a second memory 103 that holds an expected value obtained by performing the CRC calculation from the first image data; a comparator 402 that compares the calculated value with the expected value; and a video processing unit 201 that sends the first image data together with the video signal to the transmission line.SELECTED DRAWING: Figure 1

Description

This disclosure relates to a display system and a method for determining a transmission error of a video signal thereof, and is particularly suitable for a display device having a function of detecting a display abnormality in displaying a deformed shape.

Nowadays, display devices are used not only in applications such as TVs, PC displays, and mobile phones, but also in in-vehicle devices and industrial devices. In addition to conventional navigation devices for in-vehicle devices, display devices include speedometers installed on dashboards, instrument panels that are instrument panels such as warning lamps, and back monitors that display images of the rear of the vehicle. It has spread to applications such as.

Further, especially for in-vehicle applications and mobile information devices, there is a demand for a display device that emphasizes design. For this reason, the display area may be manufactured by punching a shape having rounded corners, a shape having a complicated curved surface, a shape having a hole in the center, or the like instead of the conventional rectangular shape (Patent Document 1 and). 2). Such a free-form display is called a deformed display or a free-form display (FFD). Such a display device is considered to be used for an instrument panel of an automobile or the like.

Generally, the display device includes a display panel, a circuit board, and a flexible printed circuit board (hereinafter abbreviated as "FPC") for connecting the display panel and the circuit board. The display panel includes a pixel region, a gate driver IC on the vertical axis of the outer peripheral region of the pixel region, and a source driver IC on the horizontal axis of the outer peripheral region of the pixel region. The gate driver IC controls ON / OFF of a thin film transistor (TFT, hereinafter referred to as “pixel TFT”) of a pixel.

The circuit board includes a timing controller (hereinafter abbreviated as T-CON), a ROM (read-only memory) for storing T-CON setting values, an interface connector for connecting to a video processing device, a power supply circuit, and a gradation reference. It is equipped with a voltage generation circuit. In the T-CON, the received image data may be corrected for the image such as contrast adjustment, brightness adjustment, and gamma adjustment, and the corrected image data may be output to the source driver.

Safety standards such as ISO 26262 and IEC 61508 have been established for in-vehicle devices and industrial devices that are well known as external devices for display devices, and when a display device is adopted for these products, the display device also requires safety. Occurs. For example, in instrument panel applications such as speedometers and warning lamps built into instrument panels of in-vehicle devices, it is necessary to avoid afterimages and display disturbances due to obstruction of display signal transmission, and display between external devices and display devices. Signal transmission needs to be constantly monitored.

The display device confirms that there is no abnormality in the received image data by a cyclic redundancy check (hereinafter referred to as CRC; CRC: Cyclic Redundancy Check) or the like. When CRC is used, CRC is performed on the video processing device side and the display device side, respectively, and the results are compared on the video processing device side or the display device side. If the comparison results are different, a data transmission abnormality can be detected.

However, in order to compare the results calculated by CRC, it is necessary to send the calculation result (expected value) to the video processing device side or the display device side separately from the video signal, for example, by serial communication, and from the occurrence of data abnormality. There is a time lag before the abnormality is detected. Alternatively, if the expected value is transmitted at the same time as the video signal, it is necessary to prepare a dedicated wiring different from the wiring for the video signal. (Patent Document 3)

Further, the video signal has a data valid period defined by a data enable signal or a horizontal / vertical synchronization signal, and normally, the video signal of the data valid period is output to the display area. There is also a method of detecting an error of this pattern by providing a process of adding a fixed pattern to the data validity period in the processing portion. (Patent Document 4)

Japanese Unexamined Patent Publication No. 2019-075229 International Publication No. 2007/105700 Japanese Unexamined Patent Publication No. 2018-136371 Japanese Unexamined Patent Publication No. 2012-147140

When the additional pattern is arranged in the data effective area as in Patent Document 4, the data effective area is included in the display area in a normal liquid crystal display device having a rectangular display area, which hinders the display area. Further, in a normal video processing device, pattern data cannot be arranged outside the data effective area.

For these reasons, it is difficult for a liquid crystal display device having a rectangular display area to add pattern data without disturbing the display.

It is an object of the present disclosure to provide a data abnormality detection method with a small time delay in an irregular display system in which a display area is not rectangular.

The display system according to this disclosure includes a deformed display panel composed of an image display area, a dummy display area arranged outside the area and not used for display, and a test pattern image corresponding to the test pattern area in the dummy display area. The transmission line for transmitting the image data of the above as the first image data, the first memory for holding the first image data, and the first image data become the second image data after the transmission of the transmission line. , A calculation unit that performs a predetermined operation from the second image data to obtain an operation value, a second memory that holds an expected value obtained by performing the operation from the first image data, and the operation. It is provided with a comparator that compares the value with the expected value and detects a discrepancy between the two, and a video processing unit that sends the first image data to the transmission line together with the display image data in the image display area. It is characterized by.

The display system in another aspect according to this disclosure corresponds to a deformed display panel composed of an image display area, a dummy display area arranged outside the area and not used for display, and a test pattern area in the dummy display area. The image data of the test pattern image to be performed is set as the first image data, and the result obtained by performing a predetermined operation from the first image data is set as the first expected value, and the first image data and the first image data are used. The transmission path for transmitting the expected value of the above, the memory holding the first expected value, and the received data after the first image data is transmitted through the transmission path are set as the second image data, and the second image data thereof is used. The calculation unit that performs the calculation from the image data of 2 to obtain the calculated value, and the received data after the first expected value is transmitted through the transmission path are set as the second expected value, and the second expected value is used. An image in which a comparator that compares the calculated values and detects a discrepancy between the two, and the first image data and the first expected value are transmitted to the transmission path together with the display image data in the image display area. It is characterized by having a processing unit.

The method for determining a transmission error of a video signal according to this disclosure is a method for determining a transmission error of a video signal of a deformed display device including an image display area and a dummy display area arranged outside the area and not used for display. The video signal input to the variant display device includes a section for transmitting a packet of display image data in the image display area and a non-display section corresponding to the dummy display area during the period of the horizontal cycle. The hidden section includes a section for transmitting a packet of image data of the test pattern image, a step of preparing the image data of the test pattern image, and a predetermined calculation from the image data of the test pattern image. A step of preparing an expected value, a step of inputting image data of the test pattern image to the variant display device through a transmission path, and a step of performing the calculation from the image data of the test pattern image input to the variant display device. It includes a step of obtaining a calculated value and a step of comparing the expected value and the calculated value to determine a discrepancy between the two.

In the display system in this disclosure, in the irregular display display system, a fixed value pattern for detecting a data abnormality is embedded in a portion of the video processing apparatus that is a data effective area but not a display area. This pattern does not interfere with the display of the normal display area.

Since the added pattern is a fixed value, the information of the pattern data added on the liquid crystal display device side can be stored in advance and collated with the test pattern portion in the input signal. This makes it possible to detect data transmission errors with little time delay.

It is a schematic diagram which shows the structure of the image processing apparatus and the liquid crystal display apparatus which concerns on Embodiment 1 of this disclosure. It is a schematic diagram which shows the circuit structure of the image processing apparatus and the liquid crystal display apparatus shown in FIG. It is a schematic diagram which shows the shape of the pixel area, the image non-output area, and the test pattern area of the liquid crystal panel shown in FIG. It is a timing diagram of the video signal transmitted from the video processing device shown in FIG. 1 to the liquid crystal display device. It is a schematic diagram which shows the data collation of the video signal in the video processing apparatus and the liquid crystal display apparatus shown in FIGS. 1 and 2. It is a schematic diagram which shows the structure of the image processing apparatus and the liquid crystal display apparatus which concerns on modification 1 of Embodiment 1. FIG. It is a schematic diagram which shows the structure of the image processing apparatus and the liquid crystal display apparatus which concerns on modification 2 of Embodiment 1. FIG. It is a schematic diagram which shows the shape of the pixel region, the video non-output region, the test pattern region, and the CRC expected value transmission region of the liquid crystal panel which concerns on Embodiment 2 of this disclosure.

Hereinafter, embodiments in the present disclosure will be described with reference to the drawings. It should be noted that the drawings are shown schematically, and for convenience of explanation, the configuration is omitted or the configuration is simplified as appropriate. Further, the interrelationship between the sizes and positions of the configurations and the like shown in different drawings is not always accurately described and can be changed as appropriate.

Further, in the description shown below, similar components are illustrated with the same reference numerals, and their names and functions are the same. Therefore, detailed description of them may be omitted to avoid duplication.

Embodiment 1.
Hereinafter, the display system according to the present embodiment will be described. FIG. 1 is a schematic diagram showing a configuration of a video processing device 12 and a liquid crystal display device 1 which are display systems according to the present embodiment. As shown in FIG. 1, the video processing device 12 communicates a video signal and other control signals with the liquid crystal display device 1 via the interface connector 7 and the transmission cable 16 to supply power to the liquid crystal display device 1.

As shown in FIG. 1, the liquid crystal display device 1 includes an FPC 3 that connects the liquid crystal panel 8, the circuit board 2, the liquid crystal panel 8, and the circuit board 2. In some cases, the circuit board 2 is composed of FPCs, that is, the circuit boards 2 and the FPC 3 are integrated into one FPC.

The liquid crystal panel 8 includes a pixel region 4, a gate driver IC (hereinafter abbreviated as G-IC) 5 arranged in an outer peripheral region of the pixel region 4, and a source driver IC (hereinafter abbreviated as S-IC) 6. To prepare for. The G-IC5 and S-IC6 are mounted in the peripheral region of the liquid crystal panel 8 by adopting COG (Chip ON Glass) technology. Further, as shown in FIG. 1, the pixel region 4 has an irregular shape that combines a rectangular shape and a trapezoidal shape, and has n gate wirings (corresponding to scanning signal lines) GL1 to GLn and m source wirings (image). SL1 to SLm intersect in a matrix (corresponding to a signal line), and a pixel electrode 10 and a pixel portion 11 consisting of a pixel TFT 9 whose drain electrode is connected to the pixel electrode 10 to drive the pixel electrode 10 are vertically aligned at the intersection. The main pixel TFTs and pixel electrodes connected to the gate wirings GL1, GLx3, GLn and the source wirings SL1, SLy1, SLy2, and SLm are illustrated. The reference numerals n and m are natural numbers representing the number of rows and columns of the pixel area 4).

On the other hand, the image non-output region 13 is a fictitious display region (dummy display region) in which the pixel electrodes 10 and the pixel TFT 9 are not arranged and the pixel portion 11 does not exist.

Further, the n gate wires GL1 to GLn connected to the gate electrode of the pixel TFT 9 are connected to the G-IC5, respectively, and the m source wires SL1 to SLm connected to the source electrode of the pixel TFT 9 are connected to the S-IC6. They are connected to each other. Further, as shown in FIG. 1, the G-IC 5 is arranged in the outer peripheral region of the pixel region 4 in the vertical direction, and the S-IC 6 is arranged in the outer peripheral region of the pixel region 4 in the horizontal direction. Further, the S-IC is generally referred to as an image signal line drive circuit, and the G-IC is generally referred to as a scanning signal line drive circuit.

Further, the S-IC6 is an IC that integrates the function of the source drive and the function of the T-CON. The S-IC6 also has a built-in power supply circuit (not shown) and a memory (not shown). The G-IC5 controls ON / OFF of the pixel TFT 9.

Further, as shown in FIG. 1, the FPC 3 is mounted on the end of the liquid crystal panel 8 using ACF technology (Anisotropic Conductive Film), and is in the vicinity of the S-IC 6 for easy wiring. Located in. Further, the FPC 3 mounted on the liquid crystal panel 8 is electrically connected to the circuit board 2 via a connector (not shown).

The circuit board 2 includes an interface connector 7, and although not specified in the drawing, electronic components such as a capacitor are mounted for driving the S-IC in addition to the interface connector 7. The circuit board 2 receives various signals including video signals from the video processing device 12 from the connected transmission cable 16 (FPC or the like is also possible) via the interface connector 7, and via the FPC 3, the circuit board 2 receives various signals. Connect those signals to S-IC6. That is, for various signals, the transmission cable 16, the interface connector 7, the FPC 3, the connection wiring in the circuit board 2, and the like are transmission paths from the video processing device 12 to the S-IC 6. On the contrary, it also serves as a transmission line for outputting the signal from the S-IC 6 to the transmission cable 16 connected to the interface connector 7.

FIG. 2 is a schematic configuration diagram of a video processing device 12 and a liquid crystal display device 1 corresponding to the display system exemplified in FIG. The circuit diagram shown in FIG. 2 is just an example, and the numbers of S-IC, FPC, and G-IC may be different. Further, as shown in FIG. 2, a power supply circuit 100 is built in the S-IC6, and the power supply voltage used in the G-IC5 and the S-IC6 is an analog reference power supply, a common power supply, and a gradation reference. It generates voltage, power supply for gate drive, etc. Further, in FIG. 3, the illustration of the pixel region 4 driven by the source drive unit 101 of the S-IC 6 and the gate drive unit 104 of the G-IC 5 in the liquid crystal panel 8 is omitted.

Further, in FIG. 2, the power supply circuit 100 is shown only in the S-IC6, but passive components such as coils and capacitors, power supply transistors, and the like necessary for power generation are mounted on the circuit board 2 (non-). Illustrated).

Further, in the figure, the power supply for the gate drive is supplied to the G-IC 5 via the circuit board 2, but may be supplied to the G-IC 5 via a dedicated FPC different from the circuit board 2. ..

A video signal is input to the T-CON 102 from the video processing device 12. The T-CON 102 outputs a video signal / timing control signal (image data, STH, LP / LR / POL) necessary for video output to the source drive unit 101. Further, the scanning timing control signal (STV, CLKV / OE / UD) is output to the G-IC 5 via the wiring arranged in the peripheral region of the liquid crystal panel 8.

The test pattern information memory 103 built in the S-IC 6 is connected to the T-CON 102 and is used for collation of input data described later.

The video processing device 12 has a built-in video processing unit 201, and outputs a video signal to the T-CON 102 inside the liquid crystal display device 1. The video signal is image data or a timing control signal (for example, a dot clock signal, a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, etc.). The test pattern memory 202 holds the video pattern data to be inserted into the test pattern area 14 described later, and the video processing unit 201 reads the video pattern data from the test pattern memory 202.

FIG. 3 is a diagram illustrating the shapes of the pixel region (image display region) 4, the video non-output region (dummy display region) 13, and the test pattern region 14 of the liquid crystal panel 8. As shown in FIG. 1, the pixel area 4 of the liquid crystal panel 8 has a deformed shape that combines a rectangular shape and a trapezoidal shape, and as shown in FIG. 3, the liquid crystal panel 8 has a range defined as the pixel area 4 and an image. There is a range set as the non-output area 13. The range defined as the pixel area 4 is the pixel (1, y1) in the first L1 row, the pixel (1, y2), the pixel (x3, 1), (x3, m) in the third Lx3 row, and the Lnth row. It is a deformed display area exhibiting a hexagon having the pixels (n, 1) and (n, m) of. The numbers in parentheses indicating the coordinates of the pixels are the row numbers on the left side and the column numbers on the right side. For example, (x, y) indicates the intersection of the vertical x-th row and the horizontal y-th column (x, y). The same applies below). As described above, in the display area, except for the video non-output area 13, the pixel portions 11 are arranged in a matrix of n rows vertically and m columns horizontally. Here, the codes n, m, x3, y1, y2 and the like are natural numbers representing the number of rows and columns. Further, the video non-output area 13 occupies two triangular areas on the left and right hatched in FIG. Further, the character "L" followed by one or two characters represents the line number of the array of the pixel unit 11, where the L1 line is the first display line and the Ln line is the final display line.

As is clear from FIG. 1, in the pixel region 4, the pixel portion 11 is arranged at the intersection of the source wiring output from the S-IC 6 and the gate wiring output destination from the G-IC 5, and the video non-output region 13 Is not arranged with the pixel portion 11.

The test pattern area 14 is virtually arranged in the video non-output area 13 of the triangle on the right side hatched in FIG. 3, and is set to the upper left coordinates (x1, y3) and the lower right coordinates (x2, y4). It is a rectangular area to be used. This test pattern area 14 is a range that does not contribute to the display, and in order to secure the timing of transmitting the image data of the test pattern image (hereinafter abbreviated as test pattern data) from the video processing device 12 to the liquid crystal display device 1. It is virtually arranged.

The test pattern image transmitted from the image processing device 12 to the liquid crystal display device 1 may be a general color bar image or a monoscope pattern, but in order to detect a transmission error with high probability, the number of data is large. Complex image data is better.

As shown in FIG. 3, when the pixel area 4, the video non-output area 13, and the test pattern area 14 of the liquid crystal panel 8 are combined, the pixels (including fictitious pixels) are a matrix of n rows vertically and m columns horizontally. It is a rectangular pixel area arranged in a shape. Therefore, the video signal transmitted from the video processing unit 201 of the video processing device 12 to the S-IC 6 in the liquid crystal display device 1 is transmitted at the timing corresponding to the rectangular pixel region arranged in n rows × m columns. To. The number of rows n and the number of columns m may be the same natural number. In this case, the pixel area 4, the video non-output area 13, and the test pattern area 14 of the liquid crystal panel 8 are combined to form a square.

<Transmission timing of test pattern data>
FIG. 4 shows a timing diagram of a video signal transmitted from the video processing unit 201 of the video processing device 12 to the S-IC 6 in the liquid crystal display device 1. The transmission timing of the video signal from the video processing device 12 to the liquid crystal display device 1 in the present embodiment is a well-known method of being transmitted in synchronization with a dot clock, a vertical synchronization signal, and a horizontal synchronization signal (HD) (not shown). No particular explanation will be given. Even if the pixel region 4 has a deformed shape, the number of dot clocks during one horizontal synchronization period and the number of dot clocks during the data enable DENA period are constant regardless of the number of the pixel row to be transmitted. Therefore, the configuration of the source drive unit 101 in the S-IC6, the scanning timing control (STV, CLKV / OE / UD) of the G-IC5 in the T-CON 102, and the timing control of the source drive unit 101 (STH, LP / LR). / POL) may be a general control.

Next, the allocation of the valid transmission packet section, the invalid section, and the test pattern transmission packet section of the image data during the data enable DENA period, which is a feature of the present disclosure, will be described in detail below. (Here, "packet" is a block of transmitted / received data.)

In FIG. 4, a horizontal synchronization signal (HD) for representing a horizontal period occupied in a video signal is shown, and a data enable DENA is also shown for showing the valid / invalid timing of data transmitted during that period. (H period is valid, L period is invalid. The same applies to other data below). Further, the video data for the L1 line (V-Data_L1), the video data for the Lx1 line (V-Data_Lx1), the video data for the Lx2 line (V-Data_Lx2), the video data for the Lx3 line (V-Data_Lx3), and the Ln line in the figure. The video data (V-Data_Ln) is a data transmission packet corresponding to the image data written in the pixel unit 11 arranged in the L1 line, Lx1 line, Lx2 line, Lx3 line, and Ln line shown by the broken lines in FIG. It is a section. Here, the character "L" followed by one or two characters represents the line number of the array of the pixel unit 11, the L1 line is the first display line, the Ln line is the final display line, and the Lx3 line is. This is the first display line in which the video non-output area 13 is not arranged.

In FIG. 3, since the video non-output region 13 is not arranged in the rectangular shape region from the Lx3 row to the Ln row, in FIG. 4, the Lx3 row video data (V-Data_Lx3) section and the Ln row video data (V) are arranged. -Data_Ln) section occupies between time t1 and time t9, which is the same time as the H section of the data enable DENA. Further, in the area from the L1 row to the Lx3-1 row (not shown, the row above the Lx3 row), the video non-output regions 13 are arranged on the left and right of the pixel region 4, and are arranged in those rows. The image data written in the pixel unit 11 is, for example, H of the L1 line video data (V-Data_L1), the Lx1 line video data (V-Data_Lx1), and the Lx2 line video data (V-Data_Lx2) shown in FIG. It is transmitted from the video processing device 12 to the liquid crystal display device 1 during the data transmission packet section corresponding to the period.

On the other hand, the L period of the L1 line video data (V-Data_L1), the Lx1 line video data (V-Data_Lx1), and the Lx2 line video data (V-Data_Lx2) shown in FIG. 4 is a fictitious display area. It is a section corresponding to the non-output area 13, and the data transmitted from the image processing device 12 to the liquid crystal display device 1 during this period does not contribute to the display on the liquid crystal display device 1. For example, the time t1-t4 and t5-t9 of the video data for the L1 line (V-Data_L1), the time t1-t3, t6-t7 and t8-t9 of the video data for the Lx1 line (V-Data_Lx1), and the video for the Lx2 line. The time t1-t2 and t8-t9 of the data (V-Data_Lx1) are invalid periods, and the data during this period is not displayed on the liquid crystal display device 1.

Further, the video data for the Lx1 line (V-Data_Lx1) and the video data for the Lx2 line (V-Data_Lx2) shown in FIG. 4 include a period for transmitting the test pattern data. For example, test pattern data is transmitted from the video processing device 12 to the liquid crystal display device 1 during the time t7-t8 of the Lx1 line video data (V-Data_Lx1) and during the time t7-t8 of the Lx2 line video data (V-Data_Lx2). Will be done. However, the test pattern data transmitted during this period is the transmission timing of the video pattern data corresponding to the area shown in the test pattern area 14 in FIG. 3, and is displayed on the liquid crystal display device 1 as described above. There is no.

Here, the test pattern area 14 can be freely placed inside the video non-output area 13. Further, the outer shape of the test pattern area 14 does not have to be the rectangular shape illustrated in FIG. 3, and may be a square shape, and if the area can be specified, it may be a circular shape, an elliptical shape, a trapezoidal shape, or the like. May be good. Furthermore, the entire video non-output area 13 may be used as the test pattern area 14.

<Occurrence of transmission error>
FIG. 5 is a schematic diagram showing a configuration related to data matching of video signals in the video processing device 12 and the liquid crystal display device 1 exemplified in FIGS. 1 and 2. In FIG. 5, the video signal is input from the video processing unit 201 to the receiving unit 301 of the T-CON 102. When the video signal is an unintended video signal due to noise, disconnection of the wiring of the FPC 3, or the like, the liquid crystal display device 1 displays the unintended video.

<Preparation for transmission error detection>
In this embodiment, CRC is used for data collation of video signals in the video processing device 12 and the liquid crystal display device 1. With CRC, the transmitting side adds the remainder divided by the specified generation polynomial as inspection data and sends it, and the receiving side divides the data using the same generation polynomial and receives by comparing and collating the remainder. This is a data error detection method that detects data errors and corruption. Therefore, one type of test pattern data virtually allocated to the test pattern area 14 of the liquid crystal display device 1 is determined in advance, and the expected value of CRC is calculated from the image data.

That is, the test pattern data (first image data) prepared in advance in accordance with the test pattern area 14 is stored in the test pattern memory 202 (first memory) in the video processing device 12. Next, the expected value of CRC is calculated from the test pattern data based on a predetermined calculation formula. The expected value of the CRC is stored in the test pattern information memory 103 (second memory) in the T-CON 102. Further, the position information of the test pattern area 14 is also stored in the test pattern information memory 103. The data stored in the test pattern memory 202 and the test pattern information memory 103 are fixed data prepared in advance as described above, and these memories do not need to frequently rewrite the stored data, and are read-only memory (ROM) or electric. It is also possible to adopt a non-volatile memory such as an erasable programmable ROM (EEPROM).

<Transmission error detection operation>
Next, as illustrated in the video data for Lx1 line (V-Data_Lx1) and the video data for Lx2 line (V-Data_Lx2) in FIG. 4, the video data from the video processing device 12 shown in FIG. 5 to the liquid crystal display device 1 The test pattern data (first image data) read from the test pattern memory 202 by the video processing unit 201 and the image data to be displayed in the pixel area 4 are embedded in the input video signal when the video is periodically transmitted. Output. As described above, since the test pattern area 14 is inside the video non-output area 13, even if the test pattern data is added to the video signal input to the liquid crystal display device 1, the display in the pixel area 4 of the liquid crystal panel 8 is impaired. No.

The T-CON 102 in the S-IC 6 in the liquid crystal display device 1 shown in FIG. 5 has an error detection unit 302 and a test pattern register unit 303 built-in. The error detection unit 302 includes a calculation unit 401, a comparison unit 402, an error signal output unit 403, and an error detection register 404 unit. Further, the test pattern register unit 303 includes a test pattern position information register 405 and a test pattern expected value register 406.

The position information of the test pattern is written from the test pattern information memory 103 to the test pattern position information register 405. In the present embodiment, as shown in FIG. 3, the upper left coordinates (x1, y3) and the lower right coordinates (x2, y4) are written as the position information of the rectangular region. The calculation unit 401 reads the coordinates of the position information from the test pattern position information register 405, extracts the test pattern data (second image data) of the test pattern area 14 from the video signal, and calculates the CRC value (CRC) of the data. Value) is calculated. As the CRC value, one value (data) is calculated for the image data (test pattern data) of the test pattern area 14.

The expected value of CRC in the test pattern area 14 is written from the test pattern information memory 103 to the test pattern expected value register 406. As described above, the CRC value (expected value) transmitted from the test pattern information memory 103 is obtained from the test pattern data transmitted from the image processing unit 201 to the receiving unit 301 in the T-CON 102 according to the test pattern area 14. It is a CRC value calculated in advance on the assumption that a transmission error does not occur.

On the other hand, the CRC value calculated by the calculation unit 401 from the image data (test pattern data) input from the reception unit 301 based on the position information from the test pattern position information register 405 was calculated by the same calculation formula as the above calculation. , With the same number of bits.

Next, the comparison unit 402 compares the expected value of the CRC from the test pattern expected value register 406 with the CRC value calculated from the image data corresponding to the test pattern region 14 from the calculation unit 401. When the expected value and the CRC value match in the comparison unit 402, the error code becomes inactive (logical value 0), and when the expected value and the CRC value do not match, the error code becomes active (logical value 1). Here, the comparison circuit used in the comparison unit 402 does not need to compare the magnitude of the expected value and the CRC value or obtain the difference, and it is only necessary to be able to determine the match / mismatch for each bit, and it is a simple logic circuit (for example). It can be configured by a combination of an XOR circuit and an OR circuit).

<Sending error detection result>
The error signal output unit 403 receives the error detection result in the comparison unit 402 and outputs the H level when the error code is active and the L level when the error code is inactive to the video processing unit 201. The video processing unit 201 receives the H level, performs error processing such as re-sending of the video signal, and sends an error signal to the outside of the display system as needed. If safety control is performed based on this error occurrence signal, it is possible to execute from the occurrence of a data error to the safety control in a short period of time.

Further, in the error detection register 404, when the error code is active, 1 (H level) is written to the detection bit of the error detection register 404 in response to the error detection result in the comparison unit 402, and the error code is inactive. 0 (L level) is written. The error detection register 404 can be accessed from the outside by SPI (Serial Peripheral Interface) communication, and the presence or absence of an error can be determined by the value (0 or 1) of the error detection register 404. Access to the error detection register 404 may be performed by a communication means other than SPI communication. Further, the value of the image data at the time of error detection and the number of error detections may be stored in a register accessible from the outside.

In this way, the error state can be detected by the output from the error signal output unit 403 and the access to the error detection register 404, but either one may be provided or both may be provided.

Further, in this example, the data are compared by the CRC value, but the data is not limited to the CRC, and a method such as checksum or addition of parity information may be adopted.

Further, in the error signal output unit 403 of this example, if there is even one difference in data, it is determined as an error (due to one CRC mismatch), but if the error detection exceeds a predetermined number of times, it is determined as an error. And output an error signal.

Further, if an error is detected a plurality of times within a predetermined time, for example, during the output from the first line to the last line in the vertical direction, it may be determined as an error and an error signal may be output.

<Modification 1>
Further, as shown in FIG. 6, the S-IC6 and the G-IC5 may be arranged on the FPC by adopting the COF (Chip On Film) technology. The S-IC6 is arranged on the FPC3a, and the G-IC5 is arranged on the FPC3b. The FPC 3b is connected to the circuit board 2b. On the circuit board 2b, there is a connection connector 7b with the FPC 16b arranged for connection with the video processing device 12. The circuit board 2a receives various signals including video signals from the connected transmission cable 16a via the interface connector 7a from the video processing device 12, and receives them to the S-IC 6 via the FPC 3. Connect the signal of. The power supply for the gate drive and the scanning timing control signal (STV, CLKV / OE / UD) of the G-IC5 pass through the FPC3a, the circuit board 2a, the transmission cable 16a, the video processing device 12, the FPC16b, the circuit board 2b, and the FPC3b. It is supplied from S-IC6.

When it is necessary to arrange the FPC 16b inside the liquid crystal display device 1, the circuit board 2a and the circuit board 2b may be arranged so as to be directly connected to each other without going through the image processing device 12.

<Modification 2>
Further, as shown in FIG. 7, the power supply circuit 100 may be provided on the circuit board 2 and various generated power supplies may be supplied to the G-IC 5 and the S-IC 6.

Further, as shown in FIG. 7, the T-CON 102 may be an independent IC (integrated circuit), mounted on the circuit board 2, and the signal generated by this IC may be supplied to the G-IC 5 and the S-IC 6.

Further, as shown in FIG. 7, the test pattern information memory 103 may be an independent memory IC and may be provided on the circuit board 2. Further, it may be built in the T-CON 102.

Embodiment 2.
In the first embodiment described above, the expected CRC value is stored in advance in the test pattern information memory 103 in the T-CON 102, but in the second embodiment of the present disclosure, the image processing in the image processing device 12 is performed. The unit 201 calculates the expected value of CRC based on the test pattern image, and embeds the calculated result, that is, the expected value of CRC (first expected value) in the video signal and transmits the result. Therefore, the video signal transmitted from the video processing device 12 to the liquid crystal display device 1 includes three types of data: display image data in the pixel region 4, test pattern data, and CRC expected value.

Further, FIG. 8 illustrates a virtual area of the CRC expected value transmission area 15 in the second embodiment of the present disclosure. Not only the test pattern area 14 in the video non-output area 13 on the right half surface, but also the virtual CRC expected value transmission area 15 is provided in the video non-output area 13 on the left half surface.

In the second embodiment of the present disclosure, the CRC is expected from the receiving unit 301 in the T-CON 102 that has received the video data based on the coordinate information of the CRC expected value transmission area 15 stored in advance in the test pattern information memory 103. The value (second expected value) is transmitted to and stored in the test pattern expected value register 406 (path shown by the broken line in FIG. 5). On the other hand, as in the first embodiment described above, the calculation unit 401 reads the coordinates of the position information from the test pattern position information register 405, and obtains the test pattern data (second image data) of the test pattern area 14 from the video signal. Extract and calculate the CRC value (calculated value of CRC) of the data.

Next, the comparison unit 402 uses the CRC value (second expected value) calculated from the CRC expected value (second expected value) from the test pattern expected value register 406 and the image data corresponding to the test pattern area 14 from the calculation unit 401 (second expected value). Compare with the expected value of 1).

Since the subsequent transmission error detection operation and transmission of the error detection result are the same as those in the first embodiment described above, detailed description thereof will be omitted.

With such a configuration, it is not necessary to store the CRC expected value in the test pattern information memory 103 in the T-CON 102 in advance, and the coordinate information of the test pattern area 14 and the CRC expected value transmission area 15 is stored in the memory. You only have to memorize it, and you can reduce the capacity.

In the second embodiment, as an example, the virtual area of the CRC expected value transmission area 15 is provided in the video non-output area 13 on the left side of the pixel area 4, but the test pattern area 14 on the right side of the pixel area 4 is provided. It may be in the video non-output area 13 other than the above, and can be freely placed inside the video non-output area 13. Further, the outer shape of the virtual area of the CRC expected value transmission area 15 does not have to be the rectangular shape illustrated in FIG. 8, but may be a square shape, and if the area can be further specified, a circular shape, an elliptical shape, or the like. It may be trapezoidal or the like. Furthermore, the entire video non-output area 13 excluding the test pattern area 14 may be used as the CRC expected value transmission area 15.

In the disclosure in the above-described first and second embodiments, the number of S-ICs, the number of FPCs, and the number of G-ICs are not limited to those exemplified in FIG. For example, there may be a configuration in which there are four S-ICs, the circuit board and the S-ICs are connected by one FPC, and there are two G-ICs.

In the above-mentioned disclosures in the first and second embodiments, a hexagonal irregular display area having six vertices as the pixel area of the display panel is used as an example of the display panel, but the area does not have to be a hexagon. If the video non-output area can be secured, there are various application examples such as a semicircular pixel area, a combined semicircular and rectangular shape, and a deformed shape along the display portion of an automobile instrument panel.

Further, the outer shape of the liquid crystal panel 8 is a rectangle or a square, and the pixel electrodes 10 and the pixel TFT 9 are also arranged in the video non-output region 13 to form the pixel portion 11, and the general liquid crystal panel 8 can be displayed once. After that, a light-shielding member may be arranged in a region corresponding to the video non-output region 13 to form a dummy display region to form a deformed display panel.

Further, although the outer shape of the liquid crystal panel 8 shown in FIGS. 1, 3, 6 and the like has a rectangular shape, as shown by the alternate long and short dash line in FIG. 8, the video non-output area 13 is used for miniaturization of the device. A portion may be cut off to form a hexagonal outer shape having the pixel area 4, the wiring, the IC mounting area, the seal area, and the like with the minimum necessary peripheral area. Further, even if the pixel area has a shape other than the hexagonal shape or the display panel has a deformed shape along the shape, the present embodiment can be set as a virtual area of the test pattern area and the CRC expected value transmission area. 1 and 2 can be applied.

On the other hand, in the above-mentioned disclosures in the first and second embodiments, as an example of the electroluminescent device, a liquid crystal display device in which a liquid crystal element is used for pixels as an electroluminescent layer is described as an example. It can also be applied to a matrix variant display device that employs electroluminescence (EL), organic EL, plasma display, electronic paper, or the like as an electroluminescence layer that converts into brightness. Further, although the color display of the electro-optic device is not mentioned, it is needless to say that the present disclosure can be adopted for a color electro-optic device in which pixels are classified into R, G, and B and controlled for each. stomach.

1 Liquid crystal display 2 Circuit board 3 Flexible printed circuit board (FPC)
4 Pixel area 5 Gate driver IC (G-IC)
6 Source driver IC (S-IC)
7 Interface connector 8 Liquid crystal panel 12 Video processing device 13 Video non-output area 14 Test pattern area 15 CRC expected value Transmission area 16 Transmission cable 102 Timing controller (T-CON)
103 Test pattern information memory 201 Video processing unit 202 Test pattern memory 301 Reception unit 302 Error detection unit 303 Test pattern register unit 401 Calculation unit 402 Comparison unit 403 Error signal output unit 405 Test pattern position information register 406 Test pattern expected value register

<Modification 1>
Further, as shown in FIG. 6, the S-IC6 and the G-IC5 may be arranged on the FPC by adopting the COF (Chip On Film) technology. The S-IC6 is arranged on the FPC3a, and the G-IC5 is arranged on the FPC3b. The FPC 3b is connected to the circuit board 2b. On the circuit board 2b, there is a connection connector 7b with a transmission cable 16b arranged for connection with the video processing device 12. The circuit board 2a receives various signals including video signals from the connected transmission cable 16a via the interface connector 7a from the video processing device 12, and then to the S-IC 6 via the FPC 3a. Connect those signals. The power supply for the gate drive and the scanning timing control signal (STV, CLKV / OE / UD) of the G-IC5 pass through the FPC 3a, the circuit board 2a, the transmission cable 16a, the video processing device 12, the transmission cable 16b, the circuit board 2b, and the FPC 3b. Then, it is supplied from S-IC6.

When it is necessary to arrange the transmission cable 16b inside the liquid crystal display device 1, the transmission cable 16b may be arranged so as to directly connect between the circuit board 2a and the circuit board 2b without going through the image processing device 12.

Claims (8)

An irregular display panel consisting of an image display area and a dummy display area that is not used for display and is arranged outside the area.
A transmission line for transmitting the image data of the test pattern image corresponding to the test pattern area in the dummy display area as the first image data, and
A first memory for holding the first image data, and
A calculation unit that obtains a calculated value by performing a predetermined calculation from the second image data after the first image data becomes the second image data after transmission on the transmission line.
A second memory that holds the expected value obtained by performing the above calculation from the first image data, and
A comparator that compares the calculated value with the expected value and detects a discrepancy between the two.
A video system including a video processing unit that sends the first image data to the transmission line together with the display image data in the image display area. An irregular display panel consisting of an image display area and a dummy display area that is not used for display and is arranged outside the area.
The image data of the test pattern image corresponding to the test pattern area in the dummy display area is set as the first image data, and the result obtained by performing a predetermined calculation from the first image data is set as the first expected value. , A transmission path for transmitting the first image data and the first expected value,
The memory that holds the first expected value and
The receiving data after the first image data is transmitted through the transmission line is used as the second image data, and the calculation unit that performs the calculation from the second image data to obtain the calculation value, and the calculation unit.
The received data after the first expected value is transmitted through the transmission line is set as the second expected value.
A comparator that compares the second expected value with the calculated value and detects a discrepancy between the two.
A video system including a video processing unit that sends the first image data and the first expected value to the transmission line together with the display image data of the image display area. The video system according to claim 1 or 2, wherein when the comparator detects a mismatch, an error signal is output to the video processing unit. The image display area has a deformed shape having n rows of pixels and m columns of pixels, and when the dummy area is added, the outer shape becomes a rectangle or square of n rows × m columns. The video system according to any one of claims 1 to 3, wherein the video system is characterized by. The video system according to any one of claims 1 to 4, wherein the outer shape of the deformed display panel is a deformed shape along the outer shape of the image display area. It is a method of determining a transmission error of a video signal of a deformed display device including an image display area and a dummy display area not used for display arranged outside the area.
The video signal input to the variant display device includes a section for transmitting a packet of display image data in the image display area and a non-display section corresponding to the dummy display area during the period of the horizontal cycle.
The hidden section includes a section for transmitting a packet of image data of a test pattern image.
The process of preparing the image data of the test pattern image and
A process of preparing an expected value by performing a predetermined calculation from the image data of the test pattern image, and
The process of inputting the image data of the test pattern image to the variant display device through the transmission line, and
A step of performing the calculation from the image data of the test pattern image input to the variant display device to obtain a calculation value, and a step of obtaining the calculation value.
A step of comparing the expected value and the calculated value to determine a discrepancy between the two,
Transmission error determination method for video signals including. The step of adding the expected value to the image data of the test pattern image and
A step of separating the expected value from the image data of the test pattern image input to the variant display device, and
The method for determining a transmission error of a video signal according to claim 6. The method for determining a transmission error of a video signal according to claim 6 or 7, wherein a transmission error is determined when the mismatch exceeds a predetermined number of times.

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