JP2021190646A - Semiconductor device - Google Patents

Abstract

To reduce the size of a semiconductor device in which a semiconductor element is mounted on a conductive member including a concave part.SOLUTION: A relay member 4 with conductivity including a concave part 41 includes a notch 42 at a bottom part 4c of the concave part 41. A semiconductor element 2 includes a first electrode 21 and a second electrode 22 on a front surface 2a side and includes a third electrode 23 on a back surface 2b side. The third electrode 23 is bonded to the bottom part 4c of the concave part 41 through a bonding material 3. The semiconductor element 2 is disposed so as to cover the notch 42. When the semiconductor element 2 is mounted on the relay member 4, an excess part of the bonding material 3 flows into the notch 42. Thus, even if the concave part 41 has the size similar to the external dimension of the semiconductor element 2, the flow of the bonding material 3 to the front surface 2a of the semiconductor element 2 can be suppressed and the size reduction of the relay member 4 and moreover the size reduction of the semiconductor device become possible.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device in which a semiconductor element is mounted on a conductive member.

In recent years, in the field of semiconductor devices including power semiconductor devices such as IGBTs (abbreviations for Insulated Gate Bipolar Transistors), wire bondingless structures have been studied from the viewpoint of improving connection reliability and reducing wiring resistance. Examples of this type of semiconductor device include those described in Patent Document 1.

The semiconductor device described in Patent Document 1 includes a semiconductor element, a frame-shaped conductive member surrounding the semiconductor element, an insulating side portion that fills a gap between the semiconductor element and the conductive member, an upper surface of the semiconductor element and the conductive member, and the surface of the conductive member. A rewiring layer provided on each of the lower surfaces is provided. This semiconductor device includes a source electrode and a gate electrode on the front surface side of the semiconductor element, and a drain electrode on the back surface side of the semiconductor element. The source electrode and the gate electrode of the semiconductor element are each connected with rewiring formed by electrolytic plating. The drain electrode of the semiconductor element is connected to the rewiring formed by electrolytic plating and is electrically connected to the lower surface of the conductive member via the rewiring, and is electrically connected to the lower surface of the conductive member through the rewiring. It is a configuration that can be electrically connected to other members.

According to this, each electrode of the semiconductor element and another member are connected via rewiring instead of the wire, so that the connection area at each electrode is increased, the connection reliability is improved, and the connection reliability is improved. By increasing the thickness of the wiring, the wiring resistance also decreases.

Japanese Unexamined Patent Publication No. 2013-219324

In this semiconductor device, in order to enable further increase in current, it is particularly necessary to increase the thickness of the rewiring connecting the drain electrode and the conductive member. However, if the rewiring, which is the plating layer, is thickened, the rewiring forming process becomes long and the manufacturing cost increases.

Therefore, the conductive member has a shape having a recess that can accommodate the semiconductor element, the semiconductor element and the conductive member are directly bonded using a bonding material such as solder, and the structure has a rewiring layer that covers the semiconductor element and the conductive member. Is conceivable.

In this case, if a step is generated between the electrode surface on the surface side of the semiconductor element and the upper surface of the conductive member, cracks may occur in the rewiring. Therefore, these surfaces are positioned so as to be located on substantially the same plane. It is necessary to make adjustments. Hereinafter, for convenience of explanation, the alignment between the surfaces of the semiconductor element and the conductive member may be simply referred to as "surface alignment". When aligning the surfaces, it is necessary to adjust the height position of the semiconductor element with respect to the conductive member when the semiconductor element is mounted on the conductive member via the bonding material (hereinafter, simply referred to as “height adjustment”).

Further, from the viewpoint of miniaturization of the semiconductor device, the concave portion of the conductive member is preferably made as small as possible according to the size of the semiconductor element.

However, the closer the external dimension of the concave portion is to the external dimension of the semiconductor element, the more there is no escape place for the excess portion of the bonding material, the height adjustment becomes difficult, and the surface alignment becomes difficult. On the other hand, if the external dimensions of the recesses are made too large for the semiconductor element, the size of the semiconductor device will increase.

In view of the above points, the present invention is a semiconductor device in which a semiconductor element is mounted on a conductive member having a recess and has a rewiring layer covering the semiconductor element and the conductive member, while suppressing an increase in size of the conductive member. It is an object of the present invention to have a structure that can be easily aligned with the surface of the semiconductor element and the conductive member.

In order to achieve the above object, the semiconductor device according to claim 1 has a first electrode (21) and a second electrode (22) on the front surface (2a), and a third electrode (23) on the back surface (2b). It has a semiconductor element (2) having an upper surface (4a) and a lower surface (4b) which are in a front-to-back relationship, and has a recess (41) recessed toward the lower surface and a bottom portion (4c) of the recess on the upper surface side. A conductive relay member (4) having a notch (42) which is a through hole to be formed, a sealing material (5) that covers the semiconductor element and a part of the relay member, a surface of the semiconductor element, and a relay. It comprises an insulating film (61) that covers the upper surface of the member and a part of the sealing material, and a rewiring layer (6) having a rewiring (62), and the semiconductor element is arranged inside the recess. At the same time, the third electrode is electrically connected to the bottom of the recess via the bonding material (3), and the normal direction with respect to the bottom of the recess is defined as the bottom normal direction, and the third electrode is viewed from the bottom normal direction. The notch is located inside the outer shell of the semiconductor element, and the rewiring is the first rewiring (621) connected to the first electrode and the second rewiring (622) connected to the second electrode. ) And a third rewiring (623) connected to a part of the upper surface of the relay member electrically connected to the third electrode.

According to this, since the semiconductor element is bonded to the bottom of the recess having the notch via the bonding material, even if the recess is close to the external dimensions of the semiconductor element, the surplus portion of the bonding material is notched. It flows into the part. Therefore, the semiconductor device has a structure in which the surface of the semiconductor element and the conductive member can be easily aligned while suppressing the increase in size of the conductive member.

The reference numerals in parentheses attached to each component or the like indicate an example of the correspondence between the component or the like and the specific component or the like described in the embodiment described later.

It is sectional drawing which shows the semiconductor device of 1st Embodiment. It is a top view seen from the direction II of FIG. It is sectional drawing which shows the process of preparation of a relay member and application of a bonding material in the manufacturing process of the semiconductor device of 1st Embodiment. It is sectional drawing which shows the manufacturing process following FIG. 3A. It is sectional drawing which shows the manufacturing process following FIG. 3B. It is sectional drawing which shows the manufacturing process following FIG. 3C. It is sectional drawing which shows the manufacturing process following FIG. 3D. It is sectional drawing which shows the manufacturing process following FIG. 3E. It is sectional drawing which shows the manufacturing process following FIG. 3F. It is sectional drawing which shows the manufacturing process following FIG. 3G. It is a figure which shows the semiconductor device of 2nd Embodiment, and is the top view which corresponds to FIG. It is sectional drawing which shows the cross section between VV in FIG. It is sectional drawing which shows the cross section between VI and VI in FIG. It is sectional drawing which shows the cross section between VII and VII in FIG. It is a figure which shows the semiconductor device of 3rd Embodiment, and is the top view which corresponds to FIG. It is sectional drawing which shows the cross section between IX and IX in FIG. It is sectional drawing which shows the cross section between XX in FIG.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each of the following embodiments, the parts that are the same or equal to each other will be described with the same reference numerals.

(First Embodiment)
The semiconductor device 1 of the first embodiment will be described with reference to FIGS. 1 and 2. FIG. 1 is a cross-sectional view taken along the line II shown in FIG.

〔composition〕
As shown in FIG. 1, for example, the semiconductor device 1 of the present embodiment includes a semiconductor element 2, a bonding material 3, a relay member 4, a sealing material 5, and a rewiring layer 6. In the semiconductor device 1, the semiconductor element 2 is bonded to the recess 41 of the relay member 4 via the bonding material 3, and the periphery of the semiconductor element 2 and the relay member 4 is covered with the sealing material 5. The semiconductor device 1 has, for example, a rewiring layer 6 formed so as to cover the surface 2a of the semiconductor element 2 together with a part of the relay member 4 and the sealing material 5. The semiconductor device 1 is, for example, a fan-out type in which a second rewiring 622 connected to an electrode 22 formed on the surface 2a of the semiconductor element 2 of the rewiring layer 6 extends to the outside of the outer shell of the semiconductor element 2. It has a package structure of. Hereinafter, for the sake of simplicity of description, the fan-out type package structure may be referred to as a “FOP structure”.

The semiconductor element 2 is, for example, a power element such as an IGBT, and is formed by a known semiconductor process. As shown in FIG. 1, for example, the semiconductor element 2 includes a first electrode 21 and a second electrode 22 on the front surface 2a, and a third electrode 23 on the back surface 2b. In the semiconductor element 2, for example, the first electrode 21 and the third electrode 23 are paired, and are used as an emitter electrode and a collector electrode, respectively. The semiconductor element 2 includes, for example, a plurality of second electrodes 22 which are gate electrodes and electrodes for signal transmission. That is, the semiconductor element 2 is, for example, a vertical power element in which a current is generated in the direction connecting the first electrode 21 and the third electrode 23, and current control between these electrodes is performed by applying a voltage to the second electrode 22. Is a possible configuration.

In the semiconductor element 2, for example, as shown in FIG. 1, the first rewiring 621 of the rewiring layer 6 is connected to the first electrode 21, and the second rewiring 622 is connected to the second electrode 22. In the semiconductor element 2, the third electrode 23 on the back surface 2b is electrically connected to the conductive relay member 4 via the bonding material 3, and the upper surface 4a of the relay member 4 on the front surface 2a side of the semiconductor element 2 Electrical exchange is possible through the third rewiring 623 connected to. That is, as shown in FIG. 2, for example, the semiconductor element 2 electrically connects the external power supply and the electrodes 21 to 23 via the rewiring 621 to 623 in which a part of the insulating film 61 of the rewiring layer 6 is exposed. It is configured to be connectable. That is, the semiconductor element 2 can be electrically connected to the electrodes 21 to 23 from the one side through the rewiring 621 to 623 with the outer surface of the semiconductor device 1 on the rewiring layer 6 side as one surface.

The joining material 3 is a conductive joining material such as solder, and is composed of any joining material.

The relay member 4 is, for example, a conductive member made of a metal material having good conductivity such as Cu (copper) or Al (aluminum), and includes a recess 41 on which the semiconductor element 2 is mounted. The relay member 4 includes an upper surface 4a and a lower surface 4b that are in a front-to-back relationship, and a recess 41 that is recessed toward the lower surface 4b is formed on the upper surface 4a side.

The recess 41 has an external dimension that can accommodate the semiconductor element 2, and the external dimension can be appropriately changed according to the size and thickness of the semiconductor element 2.

The notch 42 is a through hole provided so that a surplus portion of the bonding material 3 can flow in when adjusting the height when the semiconductor element 2 is mounted. The cutout portion 42 is formed, for example, in the bottom portion 4c of the recess 41 to which the back surface 2b of the semiconductor element 2 is joined, as shown in FIG. The cutout portion 42 has an outer shape that fits inside the outer shell of the semiconductor element 2 when viewed from the normal direction with respect to the bottom portion 4c (hereinafter referred to as “bottom normal direction”). The cutout portion 42 can be formed by any processing method such as cutting, etching, or punching. The cutout portion 42 is a joining material when the concave portion 41 has a dimension close to the external dimension of the semiconductor element 2 and the surface of the surface 2a side of the semiconductor element 2 and the upper surface 4a of the relay member 4 are aligned. It functions as a space for letting out the surplus part of 3.

If the relay member 4 is not provided with the notch 42 and the external dimensions of the recess 41 are close to those of the semiconductor element 2, the surplus portion of the bonding material 3 is the side surface 2c of the semiconductor element 2 and the wall portion of the recess 41. There is a possibility that it will flow in between the semiconductor element 2 and protrude from the surface 2a side of the semiconductor element 2. In this case, a short circuit occurs between the front surface 2a and the back surface 2b of the semiconductor element 2.

Therefore, in the case where the relay member 4 is not provided with the notch 42, in order to prevent the above situation, it is conceivable that the external dimension of the recess 41 is made larger than the predetermined size as compared with the semiconductor element 2. However, this requires the relay member 4 to be larger than necessary, which makes it difficult to reduce the size of the semiconductor device 1.

In the relay member 4 having the notch 42, even when the external dimension of the recess 41 is close to the semiconductor element 2, the surplus portion of the joining material 3 flows into the notch 42 and the surface 2a side of the semiconductor element 2 side. Will not wrap around. That is, the cutout portion 42 is a portion that facilitates the alignment of the surfaces of the semiconductor element 2 and the relay member 4 while reducing the size of the relay member 4, and thus contributes to the miniaturization of the semiconductor device 1.

As shown in FIG. 1, for example, the relay member 4 has a portion different from the upper surface 4a and the lower surface 4b, that is, the inner and outer side surfaces of the recess 41 are covered with the sealing material 5. Conversely, the upper surface 4a and the lower surface 4b of the relay member 4 are exposed from the sealing material 5. The relay member 4 has a third rewiring 623 connected to the upper surface 4a, and is a part of the current path of the semiconductor element 2 together with the third rewiring 623.

The sealing material 5 is made of, for example, an arbitrary insulating resin material such as an epoxy resin, and covers the periphery of the semiconductor element 2, the bonding material 3, and the relay member 4. The encapsulant 5 is formed by an arbitrary resin molding step such as compression molding. As shown in FIG. 2, for example, the sealing material 5 has an outer shape larger than that of the relay member 4, and forms a part of the outer shell of the semiconductor device 1.

The rewiring layer 6 is formed by a known rewiring forming technique so as to cover the upper surface 4a of the relay member and a part of the sealing material 5 together with the surface 2a of the semiconductor element 2. The rewiring layer 6 includes, for example, an insulating film 61 and rewiring 621-623, as shown in FIG.

The insulating film 61 is made of an arbitrary insulating resin material such as polyimide, and is formed by a wet film forming method such as spin coating.

The rewiring 621-623 is made of a conductive material such as Cu, and is formed by electrolytic plating or the like. As shown in FIGS. 1 and 2, for example, the rewiring 621 to 623 are partially exposed from the insulating film 61 on one side of the semiconductor device 1.

The first rewiring 621 is connected to, for example, the first electrode 21 of the semiconductor element 2. The second rewiring 622 is connected to, for example, the second electrode 22 of the semiconductor element 2, extends to the outside of the outer shell of the semiconductor element 2, and extends from the insulating film 61 in a region located outside the outer shell of the semiconductor element 2. The part is exposed. The third rewiring 623 is connected to the upper surface 4a of the relay member 4.

The portion of the rewiring 621 to 623 exposed from the insulating film 61 is subjected to a surface treatment (not shown) having conductivity such as Au (gold) or Pd (palladium) to ensure the adhesion of the bonding material. do.

The above is the basic configuration of the semiconductor device 1 of the present embodiment.

〔Production method〕
Next, an example of the manufacturing method of the semiconductor device 1 of the present embodiment will be described with reference to FIGS. 3A to 3H.

First, for example, as shown in FIG. 3A, a relay member 4 having a recess 41 and a notch 42 is prepared, and a joining material 3 is applied to the bottom 4c of the recess 41 so as to straddle the notch 42.

Subsequently, for example, as shown in FIG. 3B, the semiconductor element 2 on which the electrodes 21 to 23 are formed is prepared, and the semiconductor element 2 is mounted on the bonding material 3 so that the third electrode 23 abuts.

Next, for example, as shown in FIG. 3C, a height adjusting jig 100 having a flat surface 101 is prepared, and in the joining process of the joining material, the flat surface 101 is brought into contact with the surface 2a side of the semiconductor element 2 and pushed. , Adjust the height of the semiconductor element 2 with respect to the relay member 4. As a result, the surface of the surface 2a of the semiconductor element 2 and the upper surface 4a of the relay member 4 are aligned, and the back surface 2b of the semiconductor element 2 and the relay member 4 are bonded at the bottom 4c via the bonding material 3. Will be done. Further, since the notch 42 is formed in the recess 41, the excess portion of the joining material 3 flows into the notch 42, so that even if the external dimension of the recess 41 is close to that of the semiconductor element 2, the semiconductor element 2 It is possible to prevent the excess portion of the bonding material 3 from heading toward the surface 2a side.

Then, for example, as shown in FIG. 3D, a support substrate 200 having an arbitrary adhesive sheet (not shown) having high adhesion to a metal material, Si (silicon), or the like is prepared on the surface, and the surface 2a of the semiconductor element 2 is prepared. The side and the upper surface 4a of the relay member 4 are temporarily fixed to the support substrate 200.

After that, for example, as shown in FIG. 3E, a mold (not shown) having a cavity along the outer shape of the sealing material 5 is prepared, an epoxy resin or the like is put into the cavity, and the sealing material 5 is formed by compression molding or the like. .. As a result, the sealing material 5 that covers the periphery of the semiconductor element 2, the bonding material 3, and the relay member 4 is formed.

After forming the sealing material 5 that covers the lower surface 4b of the relay member 4, the sealing material 5 is sealed as shown in FIG. 3E through an arbitrary step of removing a part of the sealing material 5 such as grinding, cutting, and etching. The lower surface 4b of the relay member 4 may be exposed from the material 5.

Subsequently, as shown in FIG. 3F, for example, the work on which the sealing material 5 is formed is peeled off from the support substrate 200 by an arbitrary method such as heating, and the surface 2a of the semiconductor element 2, the upper surface 4a of the relay member 4, and the seal are sealed. The first layer 611, which is a part of the insulating film 61 that covers a part of the stop material 5, is formed. Specifically, for example, an insulating material such as polyimide is formed into a film by a wet film forming method such as spin coating, and then the first electrode 21 and the second electrode 22 are formed among the insulating materials formed by the photolithography etching method. And the portion covering a part of the upper surface 4a of the relay member 4 is removed. As a result, it is possible to form the first layer 611 having a predetermined pattern shape that exposes a part of the upper surface 4a of the first electrode 21, the second electrode 22, and the relay member 4 to the outside.

When the work is peeled off from the support substrate 200, if the surface of the work temporarily fixed to the support substrate 200 (the surface on the side where the rewiring layer 6 is formed) is dirty, the first layer is formed. Prior to the formation of 611, a cleaning step such as irradiation with a chemical solution or plasma gas may be performed.

Then, as shown in FIG. 3G, for example, the rewiring 621-623 is formed by electrolytic plating or the like. Specifically, for example, a seed layer (not shown) made of Cu or the like is formed by sputtering or the like. Then, by the same process as that of the first layer 611, an insulating resist (not shown) having a predetermined pattern shape covering a portion of the seed layer (not shown) other than the portion forming the rewiring 621-623 is formed. Subsequently, after rewiring 621 to 623 is formed by electrolytic plating, a resist (not shown) is removed with a stripping solution or the like, and then a portion of the seed layer (not shown) exposed by removing the resist is removed with an etching solution or the like. For example, by such a step, the rewiring 621-623 shown in FIG. 3G can be formed.

Finally, by the same method as the first layer 611, an insulating second layer 612 having a predetermined pattern shape, which is the remainder of the insulating film 61 and exposes a part of the rewiring 621 to 623, is formed. .. If necessary, the exposed portion of the rewiring 621-623 is subjected to surface treatment such as a conductive plating layer or a bump by an arbitrary method such as electroless plating. An externally exposed layer may be formed on the surface.

The rewiring layer 6 is not limited to the example shown in FIG. 1, and may have a structure in which more layers are laminated. In this case, for example, by repeating the steps described with reference to FIGS. 3F to 3H, the rewiring layer 6 having a more multi-layered structure can be formed.

According to the present embodiment, since the semiconductor element 2 is bonded to the bottom 4c of the recess 41 having the notch 42 via the bonding material 3, even when the recess 41 is close to the external dimensions of the semiconductor element 2. , The surplus portion of the joining material 3 flows into the notch portion 42. Therefore, the semiconductor device 1 has a structure in which the surfaces of the semiconductor element 2 and the relay member 4 can be easily aligned while suppressing the increase in size of the relay member 4.

Further, in the semiconductor device 1, the third electrode 23 on the back surface 2b side of the semiconductor element 2 is connected to the outside through the lower surface 4b of the relay member 4 or the third rewiring 623 of the upper surface 4a without using a metal clip or a wire separately. Since it can be electrically connected, it has a simplified and miniaturized structure.

(Second Embodiment)
The semiconductor device 1 of the second embodiment will be described with reference to FIGS. 4 to 7. The semiconductor device 1 of the present embodiment can be applied to, for example, a power card or the like.

In FIG. 4, the outer shells of the mold resin 8 and the encapsulant 5, which will be described later, are shown by a two-dot chain line in order to make the structure easy to see and understand. Further, in FIG. 4, the outer shell of the portion of the second rewiring 622 and the third rewiring 623 exposed from the insulating film 61 and the outer shell of the lead frames 71 to 73 described later are shown by solid lines. Further, in FIG. 4, the outer shell of the portion of the first rewiring 621 connected to the first lead frame 71, which will be described later, exposed from the insulating film 61 is shown by a broken line.

The semiconductor device 1 of the present embodiment further includes a lead frame 71 to 73 connected to the electrodes 21 to 23 of the semiconductor element 2, and a mold resin 8 covering a part of the encapsulant 5 and the lead frames 71 to 73. It differs from the first embodiment in that it is different from the first embodiment. In this embodiment, this difference will be mainly described.

The lead frames 71 to 73 are made of, for example, a conductive metal material such as Cu, and are connected to the rewiring 621 to 623, respectively, as shown in FIG. The lead frames 71 to 73 are connected by, for example, a tie bar or the like (not shown) from the joining to the rewiring 621 to 623 to the molding process of the mold resin 8, and the tie bar or the like (not shown) is removed after the mold resin 8 is molded. It is finally separated.

As shown in FIG. 5, for example, the first lead frame 71 is from the connection surface side between the base portion 711 connected to the first rewiring 621 via the joining material 3 and the first rewiring 621 of the base 711. A plurality of lead portions 712 extending toward the outside are provided.

One surface of the base portion 711 on the side opposite to the joint surface with the first rewiring 621 is exposed from the mold resin 8. The base portion 711 is thicker than the plurality of lead portions 712 and also functions as, for example, a heat sink. The base 711 covers the first rewiring 621, while being displaced from the second rewiring 622 and the third rewiring 623.

As shown in FIG. 4, for example, the plurality of lead portions 712 have a comb-teeth shape that extends outward from the base 711 in the same direction and is arranged in parallel at a predetermined distance from each other. ing. The lead portion 712 is arranged between the lead portion 712 and the other adjacent lead portions 712 at a distance from each other so that the third lead frame 73 connected to the third rewiring 623 can be arranged. The spacing between the plurality of lead portions 712 can be appropriately changed depending on the size of the portion of the third rewiring 623 exposed from the insulating film 61. Each of the plurality of lead portions 712 is an outer lead that partially protrudes from the mold resin 8.

The second lead frame 72 is connected to the second rewiring 622 via the joining material 3, for example, as shown in FIGS. 4 and 5. The number of the second lead frames 72 is the same as that of the second electrodes 22, and the second lead frames 72 are connected to different second rewiring 622s. Each of the plurality of second lead frames 72 is an outer portion of the side surface of the mold resin 8 that protrudes from the surface opposite to the surface on which the lead portion 712 of the first lead frame 71 and the third lead frame 73 protrude. It is the lead.

The number of the third lead frames 73 is the same as that of the third rewiring 623, and when a plurality of the third rewiring 623s are formed, the number is the same. As shown in FIG. 6, for example, the third lead frame 73 is connected to the third rewiring 623 via the bonding material 3 and electrically connected to the third electrode 23 through the relay member 4. When a plurality of third lead frames 73 are provided, for example, as shown in FIG. 4, the third lead frames 73 are arranged between adjacent lead portions 712 of the first lead frames 71. In other words, when a plurality of third lead frames 73 are provided, for example, as shown in FIG. 7, the third lead frames 73 are alternately arranged with the lead portions 712 of the first lead frame 71, and are in a state of being staggered with the lead portions 712. The third lead frame 73 is an outer lead that partially protrudes from the same surface as the surface on which the lead portion 712 protrudes from the side surface of the mold resin 8.

The mold resin 8 is made of an arbitrary insulating resin material such as an epoxy resin, and is formed by an arbitrary resin molding method such as transfer molding. As shown in FIGS. 4 to 6, the mold resin 8 covers a part of the sealing material 5, the rewiring layer 6, and a part of the lead frames 71 to 73.

Also in this embodiment, the semiconductor element 2 is mounted on the relay member 4 provided with the recess 41 and the notch 42 in a state where the surfaces are aligned with each other, and the semiconductor device 1 is miniaturized and the structure is simplified. Become. Further, the plurality of lead portions 712 connected to the first electrode 21 and the third lead frame 73 electrically connected to the third electrode 23 are alternately arranged so that the current of each terminal is diverted. Therefore, the effect of lowering the inductance can also be obtained.

(Third Embodiment)
The semiconductor device 1 of the third embodiment will be described with reference to FIGS. 8 to 10.

Hereinafter, for convenience of explanation, the unit including the semiconductor element 2, the relay member 4, a part of the sealing material 5, and a part of the rewiring layer 6 corresponding to the semiconductor device of the first embodiment is referred to as “element unit 1a”. It is referred to as "element unit 1b".

In FIG. 8, in order to make the structure easy to see and understand, the outer shells of the element portions 1a and 1b are represented by a two-dot chain line, and the outer shells of the semiconductor element 2 of the element portions 1a and 1b and the outer shell of the control element 9 described later are represented by broken lines. Shows. Further, in FIG. 8, the second rewiring 622 functioning as an internal wiring described later for connecting the semiconductor element 2 and the control element 9 of the element portions 1a and 1b inside the rewiring layer 6 is shown by a broken line and the second rewiring is shown. Wiring 622 other than the typical one is omitted.

In the semiconductor device 1 of the present embodiment, for example, as shown in FIG. 8, in addition to the element unit 1a, the element unit 1b and the control element 9 used for driving control of the semiconductor element 2 of the element units 1a and 1b are further added. It differs from the first embodiment in that it is provided. In this embodiment, this difference will be mainly described.

As shown in FIG. 9, for example, the element units 1a and 1b have substantially the same basic configuration as the semiconductor device 1 of the first embodiment, but the first electrode 21 and the element unit 1a of the element unit 1b The third electrode 23 is electrically connected to the third electrode 23 via the first rewiring 621 of the element portion 1b. That is, the element portions 1a and 1b are connected in series. As shown in FIG. 9, the element portions 1a and 1b are covered with a common sealing material 5 and a rewiring layer 6.

In the present embodiment, the rewiring layer 6 is connected to the electrode pad 91 of the control element 9 in addition to the rewiring 621 to 623, and a part of the rewiring layer 6 is exposed from the insulating film 61, for example, as shown in FIG. A rewiring 624 is provided. Further, in the present embodiment, the rewiring layer 6 includes a plurality of second rewiring 622s, for example, as shown in FIG. 8, and at least a part of the second rewiring 622 is the semiconductor element 2 or the element of the element unit 1a. It is an internal wiring that electrically connects the semiconductor element 2 and the control element 9 of the unit 1b. The second rewiring 622, which is the internal wiring, is connected to, for example, the second electrode 22 of the different semiconductor element 2 and the electrode pad 91 of the control element 9, and enables electrical exchange between them. The rewiring layer 6 is formed, for example, by the same process as in the first embodiment.

As shown in FIGS. 8 and 9, for example, the first rewiring 621 may have a plane size larger than that of the outer shell of the semiconductor element 2 in the present embodiment. Further, as shown in FIG. 9, for example, the first rewiring 621 of the element portion 1b extends toward the element portion 1a side and is connected to the third rewiring 623 of the element portion 1a.

In the present embodiment, the second rewiring 622 is arranged in the insulating film 61 at a portion of the first rewiring 621 different from the portion extending along the film plane direction of the insulating film 61. It is electrically independent of the rewiring 621. A plurality of second rewiring 622s are formed, and a part or all of them are connected to the element unit 1a or the element unit 1b and the control element 9, and the entire area thereof is an internal wiring covered with an insulating film 61.

As shown in FIG. 9, for example, the third rewiring 623 is formed on at least the upper surface 4a of the relay member 4 of the element portion 1a and the first rewiring of the element portion 1b inside the insulating film 61. It is connected to the wiring 621.

The control element 9 includes, for example, a control IC (integrated circuit) connected to each semiconductor element 2 of the element portions 1a and 1b and used for current control of each semiconductor element 2. The control element 9 may be, for example, an arbitrary power supply control element corresponding to a power element such as an IGBT. As shown in FIG. 10, for example, the control element 9 includes a plurality of electrode pads 91 on one surface 9a, and a fourth rewiring 624 is connected to at least a part of the plurality of electrode pads 91. The control element 9 can be electrically connected to an external power source or the like via the fourth rewiring 624, and the drive control of the element portions 1a and 1b is possible via the second rewiring 622 which is the internal wiring. ing.

That is, the semiconductor device 1 of the present embodiment has a configuration capable of controlling the current of the element portions 1a and 1b by driving the control element 9 via the fourth rewiring 624.

The semiconductor device 1 of this embodiment is basically manufactured by the same manufacturing process as that of the first embodiment. First, the semiconductor element 2 constituting the element portions 1a and 1b and the relay member 4 having the recess 41 and the notch portion 42 are prepared, and the surfaces are aligned while joining these members via the joining material 3. Then, a control element 9 having an electrode pad 91 is prepared, and one side 9a side of the control element 9 is temporarily fixed to the support substrate 200 together with the relay member 4 to which the semiconductor element 2 is bonded. Subsequently, a mold (not shown) is used to form a sealing material 5 that covers the semiconductor element 2, the bonding material 3, the relay member 4, and the control element 9. Next, after the encapsulant 5 is formed, the work is peeled off from the support substrate 200, and the rewiring layer 6 is formed by a known rewiring forming technique. The semiconductor device 1 of the present embodiment can be manufactured, for example, through the above-mentioned steps.

According to the present embodiment, in addition to obtaining the same effect as that of the first embodiment, the individual element portions 1a and 1b are miniaturized and simplified even in the configuration having a plurality of semiconductor elements 2. Because of this configuration, the effect of reducing the size and simplification of the entire package can be obtained. Further, by connecting the element unit 1a and the element unit 1b, the element unit 1a or the element unit 1b and the control element 9 by rewiring 621 to 623, it is not necessary to separately use a metal clip or a wire, and the height is reduced. The structure will be miniaturized.

In the above example, the configuration in which one semiconductor element 2 and the relay member 4 are provided by two element portions has been described, but the present invention is not limited to this, and there are three or more element portions. This may be the case, or the number of control elements 9 may be plurality.

(Other embodiments)
Although the present invention has been described in accordance with the examples, the present invention is not limited to the examples and the structure, and can be appropriately modified within the scope of the claims.

1a, 1b ... Element part, 2 ... Semiconductor element, 21 to 23 ... (1st to 3rd) electrodes,
3 ... Joining material, 4 ... Relay member, 4a ... Top surface, 4b ... Bottom surface,
4c ... bottom, 41 ... recess, 42 ... notch, 5 ... encapsulant,
6 ... Rewiring layer, 61 ... Insulating film, 621-624 ... (1st to 4th) rewiring,
71-73 ... (1st to 3rd) lead frames, 711 ... base,
712 ... Lead part, 8 ... Mold resin, 9 ... Control element, 9a ... One side,
91 ... Electrode pad

Claims (6)

A semiconductor device (2) having a first electrode (21) and a second electrode (22) on the front surface (2a) and a third electrode (23) on the back surface (2b).
It has an upper surface (4a) and a lower surface (4b) that are in a front-to-back relationship, and is a recess (41) recessed toward the lower surface on the upper surface side and a through hole formed in the bottom portion (4c) of the recess. A conductive relay member (4) having a notch (42) and
A sealing material (5) that covers a part of the semiconductor element and the relay member, and
A rewiring layer (6) having an insulating film (61) covering the surface of the semiconductor element, the upper surface of the relay member, and a part of the encapsulant, and rewiring is provided.
The semiconductor element is arranged inside the recess, and the third electrode is electrically connected to the bottom of the recess via a bonding material (3).
The notch is located inside the outer shell of the semiconductor element when viewed from the bottom normal direction with the normal direction of the recess with respect to the bottom as the bottom normal direction.
The rewiring is electrically connected to the first rewiring (621) connected to the first electrode, the second rewiring (622) connected to the second electrode, and the third electrode. A semiconductor device comprising a third rewiring (623) connected to a part of the upper surface of the relay member. The semiconductor element is a power element that generates a current in a direction connecting the first electrode and the third electrode, and has a plurality of the second electrodes.
The semiconductor device according to claim 1, wherein the rewiring layer has a plurality of the second rewiring connected to each of the second electrodes. A first lead frame (71) having a base portion (711) electrically connected to the first rewiring and a plurality of lead portions (712) extending from the base portion to the outside.
A plurality of second lead frames (72) electrically connected to the plurality of the second rewiring, and a plurality of second lead frames (72).
A plurality of third lead frames (73) electrically connected to the third rewiring, and
With the mold resin (8) covering the side surface of the sealing material, the rewiring layer, a part of the first lead frame, a part of the plurality of second lead frames, and a part of the plurality of third lead frames. The semiconductor device according to claim 2, further comprising. The semiconductor device according to claim 3, wherein the plurality of lead portions and the third lead frame are arranged so as to be alternately adjacent to each other when viewed from the bottom normal direction. A plurality of the element portions and a portion formed by the semiconductor element, the relay member, and the rewiring layer are used as element portions (1a, 1b).
Further, it has a control element (9) electrically connected to each of the semiconductor elements of the plurality of element portions and used for drive control of the plurality of semiconductor elements.
The sealing material is a member common to the plurality of element portions, and covers a portion of the control element different from the one surface (9a) provided with the plurality of electrode pads (91).
The rewiring layer is a common member that covers a plurality of the element portions, the control element, and a part of the sealing material, and is connected to the plurality of electrode pads, and a part of the rewiring layer is exposed from the insulating film. Further having a fourth rewiring (624),
2. The second rewiring is an internal wiring that is provided in plurality, is at least partially covered with the insulating film, and electrically connects the second electrode and the electrode pad. Semiconductor device. The third rewiring of the element portion extends to the outside of the outer shell of the semiconductor element of the element portion when viewed from the bottom normal direction, and the first of the other element portions. The semiconductor device according to claim 5, which is connected to the rewiring.

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