JP2021174947A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

To provide a semiconductor device capable of improving reliability, and to provide a method of manufacturing the same.SOLUTION: A temperature sensing part 13 is configured by horizontal-type polysilicon diodes 80a and 80b laminated on an interlayer insulating film 40 on the front face of a semiconductor substrate 10. The polysilicon diodes 80a and 80b are connected in parallel to each other by being laminated so that anode regions are adjacent to each other in a depth direction and cathode regions are adjacent to each other in the depth direction. A crystal grain size, as well as a planar grain size and a cross-sectional grain size, of polysilicon crystal grain of the upper polysilicon diode 80b is larger than a crystal grain size of polysilicon crystal grain of the lower polysilicon diode 80a, and thereby crystal grain boundaries 84b of the polysilicon crystal grain are less.SELECTED DRAWING: Figure 4

Description

The present invention relates to semiconductor devices and methods for manufacturing semiconductor devices.

Conventionally, power semiconductor devices that control high voltage and large current include, for example, bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), MOSFETs (Metal Oxide Semiconductor Field Effect Transistors: Metal-Oxide Transistors). There are a plurality of types (MOS type field effect transistors) equipped with an insulating gate (MOS gate) having a three-layer structure, and these are used properly according to the application.

For example, bipolar transistors and IGBTs have a higher current density than MOSFETs and can increase the current, but they cannot be switched at high speed. Specifically, the bipolar transistor is limited to use at a switching frequency of about several kHz, and the IGBT is limited to use at a switching frequency of about several tens of kHz. On the other hand, MOSFETs have a lower current density than bipolar transistors and IGBTs, making it difficult to increase the current, but they can perform high-speed switching operations up to about several MHz.

Further, unlike the IGBT, the MOSFET has a built-in parasitic diode formed by a pn junction between a ^{p-type base region and an n-type drift region inside a semiconductor substrate (semiconductor chip) to protect itself.} This parasitic diode can be used as a freewheeling diode. Therefore, when the MOSFET is used as an inverter device, it can be used without adding an external freewheeling diode to the MOSFET and connecting it, which is attracting attention in terms of economy.

Silicon (Si) is used as a constituent material of a power semiconductor device. There is a strong demand in the market for power semiconductor devices that have both large current and high speed, and efforts have been made to improve IGBTs and MOSFETs, and development is now progressing to near the material limit. For this reason, semiconductor materials that can replace silicon are being studied from the perspective of power semiconductor devices, and silicon carbide is a semiconductor material that can manufacture (manufacture) next-generation power semiconductor devices with excellent low-on-voltage, high-speed characteristics, and high-temperature characteristics. (SiC) is attracting attention.

Silicon carbide is a chemically stable semiconductor material, has a wide bandgap of 3 eV, and can be used extremely stably as a semiconductor even at high temperatures. Further, since silicon carbide has a maximum electric field strength that is an order of magnitude higher than that of silicon, it is expected as a semiconductor material capable of sufficiently reducing the on-resistance. Such features of silicon carbide include not only silicon carbide but also all semiconductors having a bandgap wider than that of silicon (hereinafter referred to as wide bandgap semiconductors).

Further, in the MOSFET, as compared with the case of having a planar gate structure in which a channel (inversion layer) is formed along the front surface of the semiconductor chip as the current increases, the semiconductor chip is formed along the side wall of the gate trench. It is advantageous in terms of cost to have a trench gate structure in which channels are formed in a direction orthogonal to the front surface. The reason is that the trench gate structure can increase the unit cell (constituent unit of the element) density per unit area, so that the current density per unit area can be increased.

As the current density per unit area is increased, the temperature rise rate according to the occupied volume of the unit cell increases, so a double-sided cooling structure is required to improve discharge efficiency and stabilize reliability. .. Further, on the same semiconductor substrate as the main semiconductor element that performs the main operation of the power semiconductor device, high-performance parts such as a current sense part, a temperature sense part, and an overvoltage protection part are used as circuit parts for protecting and controlling the main semiconductor element. A power semiconductor device with improved reliability has been proposed by having a high-performance structure in which the above are arranged.

The structure of a conventional semiconductor device will be described. FIG. 21 is a cross-sectional view showing the structure of a conventional semiconductor device. In the conventional semiconductor device 220 shown in FIG. 21, the main semiconductor element 211 and one or more circuit units for protecting and controlling the main semiconductor element 211 and the main semiconductor element 211 on the same semiconductor substrate (semiconductor chip) 210 made of silicon carbide are used. Has. Examples of the circuit unit for protecting and controlling the main semiconductor element 211 include high-performance units such as a current sense unit 212, a temperature sense unit 213, an overvoltage protection unit (not shown), and an arithmetic circuit unit (not shown). Be done.

The main semiconductor element 211 and the current sense unit 212 are vertical MOSFETs having a general trench gate structure on the front surface side of the semiconductor substrate 210. The temperature sense unit 213 is a polysilicon diode formed by a pn junction of a p-type polysilicon layer 221 which is a p-type anode region and an n-type polysilicon layer 222 which is an n-type cathode region. The p-type polysilicon layer 221 and the n-type polysilicon layer 222 are provided on the interlayer insulating film 240 on the front surface of the semiconductor substrate 210.

On the anode pad 223a and the cathode pad 223b of the temperature sense unit 213, a wiring structure is provided by plating films 241a and 241b, terminal pins 242a and 242b, and protective films 243 and 244. A double-sided cooling structure is configured by this wiring structure and cooling fins (not shown) on the back surface side of the semiconductor substrate 210. Reference numeral 230 is an interlayer insulating film covering the temperature sense portion 213, and reference numerals 230a and 230b are contact holes for exposing the p-type polysilicon layer 221 and the n-type polysilicon layer 222, respectively.

As a conventional semiconductor device, the upper layer portion of the polysilicon layer is recrystallized, and the resistance value formed by the upper layer portion of the polysilicon layer and the remaining portion (lower layer portion) excluding the upper layer portion is different. A temperature sense unit having a structure in which two diodes are connected in parallel has been proposed (see, for example, Patent Document 1 below). In Patent Document 1 below, the temperature sense portion is configured by connecting a plurality of polysilicon diodes in parallel to suppress adverse effects on the characteristics due to variations in the finished dimensions of the polysilicon layer.

Further, it is disclosed that the particle size of polysilicon crystal grains when a polysilicon layer is used as an electrode is usually about 0.1 μm to 0.2 μm for a gate electrode, for example (see, for example, Patent Document 2 below). .). In Patent Document 2 below, when a non-crystalline silicon layer is used as a gate electrode, the non-crystalline silicon layer is polypolized by the growth of crystal grains by heat treatment for activating p-type impurities ion-injected into the non-crystalline silicon layer. It is disclosed that silicon (polycrystalline silicon layer) is formed, and the grain size of the crystal grains is usually about 0.6.

International Publication No. 2015/004774 Japanese Unexamined Patent Publication No. 2004-071653

However, semiconductor devices using silicon carbide as a semiconductor material are used as high-frequency devices and devices for high-current operation, and the temperature rises momentarily during operation, so that the internal temperature distribution tends to vary. In particular, with respect to the temperature sense unit 213 composed of the polysilicon layer, the p-type polysilicon layer 221 and the n-type polysilicon due to a momentary temperature rise may occur due to the large variation in the forward voltage characteristics of the current polysilicon diode. The variation in the internal temperature distribution of the polysilicon layer 222 cannot be reflected in the forward voltage characteristics.

Further, in the conventional semiconductor device 220, the step coverage (surface coverage) of the front surface of the semiconductor substrate 210 is poor due to the integration of a plurality of semiconductor elements, and the polysilicon on the front surface of the semiconductor substrate 210 Although thinning of the layer is required, when the p-type polysilicon layer 221 and the n-type polysilicon layer 222 are thinned, the variation in the forward voltage characteristics of the temperature sense unit 213 becomes large. Therefore, the temperature range for detecting the temperature abnormality of the main semiconductor element 211 by the temperature sense unit 213 becomes wider than the design value, and the reliability of the semiconductor device 220 becomes low.

An object of the present invention is to provide a highly reliable semiconductor device and a method for manufacturing the semiconductor device in order to solve the above-mentioned problems caused by the prior art.

In order to solve the above-mentioned problems and achieve the object of the present invention, the semiconductor device according to the present invention includes a main semiconductor element and a temperature sense unit, and has the following features. The main semiconductor element has a pn junction on the first main surface side of a semiconductor substrate made of a semiconductor having a bandgap wider than that of silicon, and a current passing through the pn junction flows. The temperature sense unit detects the temperature of the main semiconductor element. The temperature sense unit is laminated on the first main surface of the semiconductor substrate via an insulating film, and has a plurality of transverse polysilicon diodes made of polysilicon with the same conductive region adjacent to each other in the depth direction. The structure is such that the polysilicon diode in the upper layer has a larger crystal grain size of the polysilicon crystal grains.

Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the polysilicon diode has a uniform impurity concentration in the in-plane of the polysilicon crystal grains and across the crystal grain boundaries.

Further, the semiconductor device according to the present invention is characterized in that, in the above-described invention, the impurity concentration is higher than that of the polysilicon diode in the upper layer.

Further, in order to solve the above-mentioned problems and achieve the object of the present invention, the method for manufacturing a semiconductor device according to the present invention is a method for manufacturing a semiconductor device provided with a main semiconductor element and a temperature sense unit, and is as follows. It has characteristics. The main semiconductor element has a pn junction on the first surface side of a semiconductor substrate made of a semiconductor having a bandgap wider than that of silicon, and a current passing through the pn junction flows. The temperature sense unit detects the temperature of the main semiconductor element.

The temperature sense portion is formed by performing the laminating step and the injection step. In the laminating step, a plurality of polysilicon layers are laminated on the first main surface of the semiconductor substrate via an insulating film. In the laminating step, the upper layer of the polysilicon layer is deposited in a higher temperature environment. In the injection step, each time the polysilicon layer is laminated in the lamination step, a p-type impurity and / or an n-type impurity is ionically injected into the polysilicon layer to form a region having the same conductivity in the depth direction. It forms an adjacent transverse polysilicon diode.

Further, according to the method for manufacturing a semiconductor device according to the present invention, in the above-described invention, in the lamination step, the lower layer is in the depth direction in a temperature environment higher than the temperature at the time of deposition of the polysilicon layer of the lower layer by 100 ° C. or more. It is characterized in that the polysilicon layer adjacent to the polysilicon layer is deposited.

Further, in the above-described invention, the method for manufacturing a semiconductor device according to the present invention is characterized in that, in the injection step, the dose amount of the ion implantation increases as the polysilicon layer in the upper layer increases.

According to the above-mentioned invention, since the crystal grain boundary of the polysilicon crystal grains can be reduced as much as the polysilicon diode in the upper layer, the bending of the band due to homojunction occurs at the crystal grain boundaries of the polysilicon crystal grains, which causes an energy barrier. There are few depleted layers, low resistance, and forward current easily flows. A forward current flows mainly through the polysilicon diode in the upper layer, which has few energy barriers, in the temperature sense portion, and it is possible to suppress variations in the forward voltage characteristics. As a result, the temperature detection accuracy of the temperature sense unit can be improved.

According to the semiconductor device and the method for manufacturing the semiconductor device according to the present invention, there is an effect that the reliability can be improved.

FIG. 5 is a plan view showing a layout of the semiconductor device according to the embodiment as viewed from the front surface side of the semiconductor substrate. It is sectional drawing which shows the cross-sectional structure of the active region of FIG. It is sectional drawing which shows the cross-sectional structure of the active region of FIG. FIG. 5 is a plan view schematically showing a state in which the polysilicon crystal grains of the temperature sense portion of FIG. 3 are viewed from the front surface side of the semiconductor substrate. FIG. 5 is a cross-sectional view schematically showing a state in which the polysilicon crystal grains of the temperature sense portion of FIG. 3 are viewed from the side surface side of the semiconductor substrate. It is a band diagram which shows the energy level of the grain boundary of the polysilicon crystal grain of the temperature sense part of FIG. It is a band diagram which shows the energy level of the grain boundary of the polysilicon crystal grain of the temperature sense part of FIG. It is a band diagram which shows the energy level of the grain boundary of the polysilicon crystal grain of the temperature sense part of FIG. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on embodiment. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on embodiment. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on embodiment. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on embodiment. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on embodiment. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on embodiment. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on embodiment. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on embodiment. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on embodiment. It is sectional drawing which shows the state in the manufacturing process of the semiconductor device which concerns on embodiment. It is a frequency distribution diagram of the forward voltage characteristic of an Example. It is a frequency distribution map of the forward voltage characteristic of the conventional example. It is sectional drawing which shows the structure of the conventional semiconductor device.

Hereinafter, preferred embodiments of the semiconductor device and the method for manufacturing the semiconductor device according to the present invention will be described in detail with reference to the accompanying drawings. In the present specification and the accompanying drawings, it means that the electrons or holes are a large number of carriers in the layers and regions marked with n or p, respectively. Further, + and-attached to n and p mean that the impurity concentration is higher and the impurity concentration is lower than that of the layer or region to which it is not attached, respectively. In the following description of the embodiment and the accompanying drawings, the same reference numerals are given to the same configurations, and duplicate description will be omitted.

(Embodiment)
The semiconductor device according to the embodiment is configured by using a semiconductor (wide bandgap semiconductor) having a bandgap wider than that of silicon (Si) as a semiconductor material. Here, the structure of the semiconductor device according to the embodiment will be described by taking as an example the case where silicon carbide (SiC) is used as the wide bandgap semiconductor material constituting the semiconductor device according to the embodiment. FIG. 1 is a plan view showing a layout of the semiconductor device according to the embodiment as viewed from the front surface side of the semiconductor substrate.

The semiconductor device 20 according to the embodiment shown in FIG. 1 protects and controls the main semiconductor element 11 and the main semiconductor element 11 in the active region 1 of the same semiconductor substrate (semiconductor chip) 10 made of silicon carbide. It has one or more circuit units of the above. The active region 1 is provided in the substantially center (center of the chip) of the semiconductor substrate 10. The main semiconductor element 11 is a vertical MOSFET that performs the main operation of the semiconductor device 20, and is composed of a plurality of unit cells (functional units of the element) connected in parallel to each other by a source pad 21a described later.

The main semiconductor element 11 is arranged in the effective region (hereinafter referred to as the main effective region) 1a of the active region 1. The main effective region 1a is the main current (drift current) of the main semiconductor element 11 in the direction from the back surface to the front surface of the semiconductor substrate 10 (opposite to the depth direction Z) when the main semiconductor element 11 is turned on. Is the area where the current flows. The main effective region 1a has, for example, a substantially rectangular planar shape and occupies most of the surface area of the active region 1. The three sides of the main effective region 1a having a substantially rectangular planar shape are adjacent to the edge termination region 2 described later.

The circuit unit for protecting and controlling the main semiconductor element 11 is, for example, a high-performance unit such as a current sense unit 12, a temperature sense unit 13, an overvoltage protection unit (not shown), and an arithmetic circuit unit (not shown). It is arranged in the main invalid region 1b of the active region 1. The main invalid region 1b is an region in which the unit cell of the main semiconductor element 11 is not arranged, and does not function as the main semiconductor element 11. The main invalid region 1b has, for example, a substantially rectangular planar shape, and is arranged between the remaining one side of the substantially rectangular planar shape main effective region 1a and the edge termination region 2.

The edge termination region 2 is a region between the active region 1 and the end portion (chip end portion) of the semiconductor substrate 10, and is adjacent to the active region 1 and surrounds the active region 1 so as to surround the semiconductor substrate 10. It has the function of relaxing the electric field on the front surface side and maintaining the withstand voltage. In the edge termination region 2, for example, a general pressure resistant structure (not shown) such as a field limiting ring (FLR: Field Limiting Ring) or a junction termination (JTE: Junction Termination Extension) structure is arranged. The withstand voltage is the limit voltage at which the semiconductor device does not malfunction or break.

The source pad (electrode pad) 21a of the main semiconductor element 11 is arranged on the front surface of the semiconductor substrate 10 in the main effective region 1a. The source pad 21a of the main semiconductor element 11 is arranged apart from the electrode pads other than the source pad 21a. The main semiconductor element 11 has a larger current capacity than other circuit units. Therefore, the source pad 21a of the main semiconductor element 11 has substantially the same planar shape as the main effective region 1a, and covers almost the entire surface of the main effective region 1a.

The electrode pads other than the source pad 21a are arranged apart from each other on the front surface of the semiconductor substrate 10 in the main invalid region 1b. The electrode pads other than the source pad 21a include the gate pad 21b of the main semiconductor element 11, the electrode pad (OC pad) 22 of the current sense unit 12, and the electrode pads (anode pad and cathode pad) 23a and 23b of the temperature sense unit 13. These include an electrode pad of the overvoltage protection unit (hereinafter referred to as an OV pad: not shown), an electrode pad of the arithmetic circuit unit (not shown), and the like.

The electrode pads other than the source pad 21a have, for example, a substantially rectangular planar shape, and have a surface area required for joining terminal pins 48b to 48d (see FIGS. 3 and 4) and wires (not shown), which will be described later. FIG. 1 shows a case where electrode pads other than the source pad 21a are arranged in a row in one direction X along the boundary between the main invalid region 1b and the edge termination region 2. In FIG. 1, the source pad 21a, the gate pad 21b, the OC pad 22, the anode pad 23a, and the cathode pad 23b are illustrated in a rectangular shape with S, G, OC, A, and K, respectively.

The current sense unit 12 is connected in parallel to the main semiconductor element 11 and operates under the same conditions as the main semiconductor element 11 to have a function of detecting an overcurrent (OC: Overcurent) flowing through the main semiconductor element 11. The current sense unit 12 is arranged apart from the main semiconductor element 11. The current sense unit 12 is a vertical type in which the number of unit cells having the same configuration as that of the main semiconductor element 11 is smaller (for example, about 10) than the number of unit cells of the main semiconductor element 11 (for example, about 1,000 or more). It is a MOSFET and has a smaller surface area than the main semiconductor element 11.

The unit cell of the current sense unit 12 is arranged in a part of a region (hereinafter referred to as a sense effective region) 12a of the region covered with the OC pad 22 of the semiconductor substrate 10. The unit cells of the current sense unit 12 are arranged adjacent to each other in the direction parallel to the front surface of the semiconductor substrate 10. The direction in which the unit cells of the current sense unit 12 are adjacent to each other is the same as the direction in which the unit cells of the main semiconductor element 11 are adjacent to each other, for example. The unit cells of the current sense unit 12 are connected in parallel to each other by the OC pad 22.

Further, in the region of the semiconductor substrate 10 covered with the OC pad 22, the region excluding the sense effective region 12a is the sense invalid region 12b that does not function as the current sense unit 12. The unit cell of the current sense unit 12 is not arranged in the sense invalid region 12b. In almost the entire region of the main invalid region 1b excluding the sense effective region 12a, the p-type base region 34b (see FIGS. 2 and 3) described later from the sense effective region 12a is formed on the surface region of the front surface of the semiconductor substrate 10. Is postponed.

The temperature sense unit 13 has a function of detecting the temperature of the main semiconductor element 11 (semiconductor substrate 10) by utilizing the temperature characteristics of the diode. The temperature sense unit 13 is arranged directly below the anode pad 23a and the cathode pad 23b. The temperature sense unit 13 has a multilayer structure in which a plurality of horizontal polysilicon diodes composed of a polysilicon (poly-Si) layer are laminated (see FIG. 3), and the higher the polysilicon diode, the more polysilicon crystal grains (silicon crystals). The grain size of the aggregate of silicon) is large (see FIGS. 4 and 5).

The overvoltage protection unit (not shown) is a diode that protects the main semiconductor element 11 from overvoltage (OV: Over Voltage) such as a surge. The current sense unit 12, the temperature sense unit 13, and the overvoltage protection unit are controlled by the arithmetic circuit unit. The arithmetic circuit unit controls the main semiconductor element 11 based on the output signals of the current sense unit 12, the temperature sense unit 13, and the overvoltage protection unit. The arithmetic circuit unit is composed of a plurality of semiconductor elements such as a CMOS (Complementary MOS) circuit.

Next, the cross-sectional structure of the semiconductor device 20 according to the embodiment will be described. 2 and 3 are cross-sectional views showing a cross-sectional structure of the active region of FIG. FIG. 4 is a plan view schematically showing a state in which the polysilicon crystal grains of the temperature sense portion of FIG. 3 are viewed from the front surface side of the semiconductor substrate. FIG. 5 is a cross-sectional view schematically showing a state in which the polysilicon crystal grains of the temperature sense portion of FIG. 3 are viewed from the side surface (chip end portion) side of the semiconductor substrate. 6 to 8 are band diagrams showing the energy levels of the grain boundaries of the polysilicon crystal grains in the temperature sense portion of FIG.

FIG. 2 shows the cross-sectional structure of the main effective region 1a and the current sense unit 12 (cross-sectional structure at the cutting line X1-X2-X3-X4 in FIG. 1). FIG. 3 shows the cross-sectional structures of the main effective region 1a, the sense effective region 12a, and the temperature sense unit 13 (cross-sectional structures at the cutting lines X1-X2, cutting lines X3-X4, and cutting lines Y1-Y2 in FIG. 1). Some unit cells are shown in the main effective region 1a and the sense effective region 12a in FIGS. 2 and 3, respectively. In FIGS. 4 and 5, the pn junction interface of the polysilicon diodes 80a and 80b is not shown.

In FIG. 4, the planar size of the polysilicon diode 80b in the upper layer and the planar surface of the p-type polysilicon layer 81a in the lower layer are vertically arranged so that the planar particle diameters of the polysilicon crystal grains of the polysilicon diodes 80a and 80b can be easily compared. Shown side by side. 6 and 7 show the energy levels of the grain boundaries of the polysilicon crystal grains of the polysilicon diode 80a in the lower layer (energy levels at the cutting lines AA'in FIG. 4). FIG. 8 shows the energy levels of the grain boundaries of the polysilicon crystal grains of the polysilicon diode 80b in the upper layer (energy levels at the cutting lines BB'in FIG. 4).

^{The main semiconductor element 11 has a p-type base region 34a, an n +} -type source region 35a, a p ^++- type contact region 36a, a trench 37a, and a gate insulating film 38a on the front surface side of the semiconductor substrate 10 in the main effective region 1a. It also has a MOS gate (insulated gate having a three-layer structure of metal-oxide film-semiconductor) having a trench gate structure composed of a gate electrode 39a. The semiconductor substrate 10 is formed by epitaxially growing silicon carbide layers 72 and 73, which form an ^n- type drift region 32 and a p-type base region 34a, on the front surface of an ^{n + type starting substrate 71 made of silicon carbide.}

The n ^{+ type starting substrate 71 serves as an n +} type drain region 31 of the main semiconductor element 11 and the current sense unit 12. The main surface of the semiconductor substrate 10 on the p-type silicon carbide layer 73 side is the front surface, and the main surface on the n ⁺ type departure substrate 71 side ( ^{the back surface of the n +} type departure substrate 71) is the back surface. Here, an example is taken in the case where the main semiconductor element 11 and the circuit unit that protects and controls the main semiconductor element 11 have a wiring structure having the same configuration using pin-shaped wiring members (terminal pins 48a to 48d described later). As will be described, a wiring structure using a wire may be used instead of the pin-shaped wiring member.

The trench 37a penetrates the p-type silicon carbide layer 73 in the depth direction Z from the front surface (surface of the p-type silicon carbide layer 73) of the semiconductor substrate 10 ^{and reaches the n-} type silicon carbide layer 72. A gate electrode 39a is provided inside the trench 37a via a gate insulating film 38a. ^{A p-type base region 34a, an n +} -type source region 35a, and a p ^++- type contact region 36a are selectively provided on the surface region of the front surface of the semiconductor substrate 10 between the trenches 37a adjacent to each other. ..

The n ⁺ type source region 35a and the p ⁺⁺ type contact region 36a are selectively provided between the front surface of the semiconductor substrate 10 and the p-type base region 34a in contact with the p-type base region 34a. There is. The n ⁺ type source region 35a and the p ⁺⁺ type contact region 36a are exposed on the front surface of the semiconductor substrate 10. The exposure on the front surface of the semiconductor substrate 10 means that the n ⁺ type source region 35a and the p ⁺⁺ type contact region 36a are formed inside the first contact hole 40a of the interlayer insulating film 40 described later to the NiSi film 41a described later. To touch.

The n ⁺ type source region 35a is in contact with the gate insulating film 38a on the side wall of the trench 37a. The p ⁺⁺ type contact region 36a is provided in contact with the n ⁺ type source region 35a at a position farther from the trench 37a than the n ⁺ type source region 35a. The p ⁺⁺ type contact region 36a may not be provided. In this case, ^{instead of the p ++} type contact region 36a, the p-type base region 34a reaches the front surface of the semiconductor substrate 10 and is exposed on the front surface of the semiconductor substrate 10.

Inside the semiconductor substrate 10, between the p-type base region 34a and the n ⁺ type drain region 31 (n ⁺ type starting substrate 71), the p-type base region 34a and the n ⁺ type drain region 31 are in contact with each other, and n ⁻ A mold drift region 32 is provided. An n-type current diffusion region 33a may be provided between the p-type base region 34a and the n ^{-type drift region 32 in contact with these regions.} The n-type current diffusion region 33a is a so-called current diffusion layer (Curent Spreading Layer: CSL) that reduces the spread resistance of carriers.

Further, inside the semiconductor substrate 10, first and second p ⁺ type regions 61a and 62a for relaxing the electric field applied to the bottom surface of the trench 37a ^{are provided at positions closer to the n + type drain region 31 than the p type base region 34a.} May be. The 1p ⁺ -type region 61a is provided apart from the p-type base region 34a, it faces the bottom surface of the trench 37a in the depth direction Z. The second p ⁺ type region 62a is provided between the trenches 37a adjacent to each other ^{, apart from the first p +} type region 61a and the trench 37a, and is in contact with the p type base region 34a.

The interlayer insulating film 40 is provided on substantially the entire surface of the front surface of the semiconductor substrate 10 and covers the gate electrode 39a in the main effective region 1a. The gate electrodes 39a of all unit cells are electrically connected to the gate pad 21b (see FIG. 1). In the main effective region 1a, a first contact hole 40a penetrating the interlayer insulating film 40 is provided in the depth direction Z. ^{The n +} type source region 35a and the p ⁺⁺ type contact region 36a are exposed in the first contact hole 40a.

Nickel silicide (NiSi, Ni ₂ Si or thermally stable NiSi _2: hereinafter, collectively and NiSi in) film 41a is in ohmic contact with the semiconductor substrate 10 inside the first contact hole 40a, n ⁺ -type source region It is electrically connected to 35a and the p ⁺⁺ type contact area 36a. When the p ⁺⁺ type contact region 36a is not provided, the p type base region 34a is exposed to the first contact hole 40a instead of the ^{p ++ type contact region 36a and is electrically connected to the NiSi film 41a.} ..

A barrier metal 46a is provided along the surfaces of the interlayer insulating film 40 and the NiSi film 41a on the entire surface of the interlayer insulating film 40 and the NiSi film 41a in the main effective region 1a. The barrier metal 46a has a function of preventing mutual reaction between each metal film of the barrier metal 46a or between regions facing each other across the barrier metal 46a. The barrier metal 46a may have, for example, a laminated structure in which a first titanium nitride (TiN) film 42a, a first titanium (Ti) film 43a, a second TiN film 44a, and a second Ti film 45a are laminated in this order.

The first TiN film 42a covers the entire surface of the interlayer insulating film 40. The first TiN film 42a is not provided on the front surface of the semiconductor substrate 10 at the portion where the NiSi film 41a is formed. The first Ti film 43a is provided on the surfaces of the first TiN film 42a and the NiSi film 41a. The second TiN film 44a is provided on the surface of the first Ti film 43a. The second Ti film 45a is provided on the surface of the second TiN film 44a. A source pad 21a is provided on the entire surface of the second Ti film 45a.

^{The source pad 21a is electrically connected to the n +} type source region 35a and the p ⁺⁺ type contact region 36a via the barrier metal 46a and the NiSi film 41a. The source pad 21a may be, for example, an aluminum (Al) film, an aluminum-silicon (Al-Si) film, or an aluminum-silicon-copper (Al-Si-Cu) film having a thickness of about 5 μm. The source pad 21a, the barrier metal 46a and the NiSi film 41a function as source electrodes of the main semiconductor element 11.

One end of the terminal pin 48a is joined onto the source pad 21a via a plating film 47a and a solder layer (not shown). The other end of the terminal pin 48a is joined to a metal bar (not shown) arranged so as to face the front surface of the semiconductor substrate 10. Further, the other end of the terminal pin 48a is exposed to the outside of a case (not shown) on which the semiconductor substrate 10 is mounted, and is electrically connected to an external device (not shown). The terminal pins 48a are solder-bonded to the plating film 47a in a state of standing substantially perpendicular to the front surface of the semiconductor substrate 10.

The terminal pin 48a is a round bar-shaped (cylindrical) wiring member having a predetermined diameter, and is connected to an external ground potential (minimum potential). The terminal pin 48a is an external connection terminal that takes out the potential of the source pad 21a to the outside. The first and second protective films 49a and 50a are, for example, polyimide films. The first protective film 49a covers a portion of the surface of the source pad 21a other than the plating film 47a. The second protective film 50a covers the boundary between the plating film 47a and the first protective film 49a.

The drain electrode 51 is in ohmic contact with the entire back surface of the semiconductor substrate 10 (the back surface of the n ^{+ type starting substrate 71).} On the drain electrode 51, for example, a drain pad (electrode pad: not shown) is provided in a laminated structure in which a Ti film, a nickel (Ni) film, and a gold (Au) film are laminated in this order. The drain pad is solder-bonded to a metal base plate (not shown) formed of, for example, copper (Cu) foil of an insulating substrate, and at least a part of the drain pad is connected to a base portion of a cooling fin (not shown) via the metal base plate. Are in contact.

By joining the terminal pin 48a to the source pad 21a on the front surface of the semiconductor substrate 10 and the drain pad on the back surface to the metal base plate of the insulating substrate in this way, the semiconductor substrate 10 can be attached to both main surfaces. It has a double-sided cooling structure with a cooling structure. The heat generated in the semiconductor substrate 10 is dissipated from the fin portion of the cooling fin via the metal base plate bonded to the drain pad on the back surface of the semiconductor substrate 10, and the terminal pin 48a on the front surface of the semiconductor substrate 10 is radiated. Heat is dissipated from the joined metal bar.

The current sense unit 12 has a p-type base region 34b, an n ⁺ type source region 35b, a p ⁺⁺ type contact region 36b, a trench 37b, a gate insulating film 38b, and a gate electrode 39b having the same configuration as the corresponding parts of the main semiconductor element 11. And an interlayer insulating film 40 is provided. Each portion of the MOS gate of the current sense portion 12 is provided in the sense effective region 12a of the main invalid region 1b. The p-type base region 34b is separated from the p-type base region 34a of the main semiconductor element 11 by ^{the n-} type region 32a of the surface region of the front surface of the semiconductor substrate 10.

The p-type base region 34b extends from, for example, the sense effective region 12a to almost the entire area of the main invalid region 1b. The current sense unit 12 may have an n-type current diffusion region 33b and first and second p ⁺ type regions 61b and 62b, similarly to the main semiconductor element 11. The p ⁺⁺ type contact region 36b may not be provided as in the main semiconductor element 11. The gate electrodes 39b of all unit cells are electrically connected to the gate pad 21b (see FIG. 1). The gate electrode 39b is covered with an interlayer insulating film 40.

In the sense effective region 12a, the interlayer insulating film 40 is provided with a second contact hole 40b that penetrates in the depth direction Z and reaches the semiconductor substrate 10, and the n ⁺ type source region 35b and the p ⁺⁺ type contact region 36b are exposed. Has been done. Similar to the main semiconductor element 11, a NiSi film 41b and a barrier metal 46b are provided on the front surface of the semiconductor substrate 10 in the sense effective region 12a. Reference numerals 42b to 45b are a first TiN film, a first Ti film, a second TiN film, and a second Ti film, respectively, which constitute the barrier metal 46b.

The NiSi film 41b is in ohmic contact with the semiconductor substrate 10 inside the second contact hole 40b ^{and is electrically connected to the n +} type source region 35b and the p ⁺⁺ type contact region 36b. When the p ⁺⁺ type contact region 36b is not provided, the p type base region 34b is exposed to the second contact hole 40b instead of the ^{p ++ type contact region 36b and is electrically connected to the NiSi film 41b.} .. The barrier metal 46b extends on the interlayer insulating film 40 in the sense invalid region 12b.

An OC pad 22 is provided on the entire surface of the barrier metal 46b apart from the source pad 21a. ^{The OC pad 22 is electrically connected to the n +} type source region 35b and the p type base region 34b via the barrier metal 46b and the NiSi film 41b. The OC pad 22 is made of the same material as the source pad 21a, and is formed at the same time as the source pad 21a. The OC pad 22, the barrier metal 46b, and the NiSi film 41b function as source electrodes for the current sense unit 12.

The terminal pin 48b is joined to the OC pad 22 with the same wiring structure as that on the source pad 21a. The terminal pin 48b is a round bar-shaped (cylindrical) wiring member having a diameter smaller than that of the terminal pin 48a. The terminal pin 48b is, for example, an external connection terminal that takes out the potential of the OC pad 22 to the outside, and connects the OC pad 22 to the ground potential via an external resistor (not shown). Reference numerals 47b, 49b, and 50b are plating films and first and second protective films that form a wiring structure on the OC pad 22, respectively.

P-type base region 34b of the p-type base region 34a and the sense effective area 12a of the main effective area 1a is shown omitted n of the surface region of the semiconductor substrate 10 ^- by type region, p-type region (not shown for element isolation ) Is separated. The p-type region for element isolation is provided in a substantially rectangular shape surrounding the periphery of the active region 1 in the edge termination region 2, the parasitic diode to electrically isolate the active region 1 and the edge termination region 2 n ^- It is a floating p-type region formed by a pn junction with the type drift region 32.

The temperature sense unit 13 is composed of two or more transverse polysilicon diodes sequentially laminated on the interlayer insulating film 40 on the front surface of the semiconductor substrate 10 in the main invalid region 1b. All the polysilicon diodes constituting the temperature sense unit 13 are connected in parallel by being laminated so that the anode regions are adjacent to each other in the depth direction Z and the cathode regions are adjacent to each other in the depth direction Z. .. Here, a case where the temperature sense unit 13 has a two-layer structure in which two transverse polysilicon diodes 80a and 80b are laminated will be described as an example (FIG. 3).

The underlying polysilicon diode 80a is formed by a pn junction between a p-type polysilicon layer 81a, which is an anode region, and an n-type polysilicon layer 82a, which is a cathode region. The p-type polysilicon layer 81a and the n-type polysilicon layer 82a are provided on the interlayer insulating film 40 on the front surface of the semiconductor substrate 10. The polysilicon diode 80b in the upper layer may have the same impurity concentration as the polysilicon diode 80a in the lower layer, or preferably have a higher impurity concentration than the polysilicon diode 80a in the lower layer.

Here, a case where the polysilicon diode 80b in the upper layer has a higher impurity concentration than the polysilicon diode 80a in the lower layer will be described as an example. The upper-layer polysilicon diode 80b is formed by a pn junction between ^{a p + -type polysilicon layer 81b, which is an anode region, and an n +} -type polysilicon layer 82b, which is a cathode region. The p ⁺ type polysilicon layer 81b is laminated on the p-type polysilicon layer 81a and electrically connected to the p-type polysilicon layer 81a.

The crystal grain size of the polysilicon crystal grains of the upper layer p ⁺ type polysilicon layer 81b is the crystal grain size seen from the front surface side of the semiconductor substrate 10 (maximum width of crystal grains: hereinafter, plane grain size. FIG. 4) and the crystal grain size (maximum height of crystal grains: hereinafter referred to as cross-sectional grain size) as seen from the direction parallel to the front surface of the semiconductor substrate 10 (side surface side of the semiconductor substrate 10). Both are larger than the crystal grain size of the polysilicon crystal grains of the underlying p-type polysilicon layer 81a.

The n ⁺ type polysilicon layer 82b is laminated on the n-type polysilicon layer 82a and electrically connected to the n-type polysilicon layer 82a. The crystal grain size of the polysilicon crystal grains of the upper n ⁺ type polysilicon layer 82b is larger than the crystal grain size of the polysilicon crystal grains of the lower n-type polysilicon layer 82a in both the planar particle size and the cross-sectional particle size. When the polysilicon diode is further laminated on the polysilicon diode 80b, the planar particle size and the cross-sectional particle size of the polysilicon crystal grains may be increased as the polysilicon diode in the upper layer increases.

By setting the planar particle size and the cross-sectional particle size of the polysilicon crystal grains of the polysilicon layer constituting the temperature sense unit 13 in this way, the polysilicon diode 80b in the upper layer has more crystal grains than the polysilicon diode 80a in the lower layer. Since the surface area of the polysilicon crystal grains per grain is large and the resistance is low, the variation in the forward voltage characteristics is smaller than that of the polysilicon diode 80a in the lower layer. Therefore, when the forward voltage of the temperature sense unit 13 is applied, the current flowing through the temperature sense unit 13 mainly flows through the polysilicon diode 80b in the upper layer.

The higher the polysilicon diode, the lower the resistance. The reason is as follows. The polysilicon layer has a plurality of polysilicon crystal grains oriented in different crystal orientations. FIGS. 4 and 5 show one polysilicon crystal grain in one rectangle. Ion species injected at the grain boundaries (boundaries of polysilicon crystal grains adjacent to each other) 84a and 84b of polysilicon crystal grains to make the polysilicon layer a predetermined conductive type (p-type or n-type) By introducing the same conductive type, a bond (homogeneous bond) between the same materials (polysilicon) is formed.

Specifically, in the p-type polysilicon layer 81a and the p ⁺ -type polysilicon layer 81b, pp-type and p ⁺ p ⁺ -type homojunctions are formed at the grain boundaries of the polysilicon crystal grains, respectively. In the n-type polysilicon layer 82a and the n ⁺ -type polysilicon layer 82b, nn-type and n ⁺ n ⁺ -type homojunctions are formed at the grain boundaries of the polysilicon crystal grains, respectively. When this homojunction is formed, the region including the crystal grain boundaries of the polysilicon crystal grains adjacent to each other is depleted with a predetermined width, and band bending occurs.

In the p-type polysilicon layer 81a and the p ⁺ -type polysilicon layer 81b, the band bending means that the energy level Ev at the top of the valence band decreases with a predetermined gradient, and the minimum value is set at the grain boundary of the polysilicon crystal grains. This is the state shown. In the n-type polysilicon layer 82a and the n ⁺ -type polysilicon layer 82b, the band bending 85a and 85b increase the energy level Ec at the bottom of the conduction band with a predetermined gradient, and are the largest at the grain boundaries of the polysilicon crystal grains. It is a state showing a value.

6 and 7 and 8 show band diagrams at the grain boundaries 84a and 84b of the polysilicon crystal grains of the n-type polysilicon layer 82a and the n ^{+ -type polysilicon layer 82b, respectively.} Although not shown, the band diagrams of the polysilicon crystal grains of the p-type polysilicon layer 81a and the p ⁺ -type polysilicon layer 81b at the grain boundaries show the energy level Ev at the top of the valence band in FIGS. 6 to 8, respectively. , The energy level Ec at the bottom of the conduction band is inverted. The symbol Ef is Fermi energy.

In all the polysilicon crystal grains, the bending of this band is caused by the polysilicon adjacent to the depth direction Z at the grain boundaries with the polysilicon crystal grains adjacent to each other in the direction parallel to the front surface of the semiconductor substrate 10. It also occurs at the grain boundaries with the crystal grains. The depletion layer formed at the grain boundaries of polysilicon crystal grains by bending the band serves as an energy barrier for carriers (holes, electrons) moving in the polysilicon layer. Therefore, the smaller the grain boundaries of the polysilicon crystal grains in the polysilicon layer, the lower the resistance of the polysilicon diode can be.

Further, as the carrier concentration of the polysilicon layer is increased, the bending of the band becomes steeper and the width of the depletion layer formed at the grain boundary of the polysilicon crystal grains becomes narrower (reference numerals wa and wb in FIGS. 6 to 8). .. As a result, a tunnel current path through which the depletion layer penetrates is formed with a relatively small amount of energy, carriers can move between polysilicon crystal grains adjacent to each other, and the carrier is not easily affected by the energy barrier. As a result, the resistance of the polysilicon diode can be further reduced, so that the higher the polysilicon diode, the higher the carrier concentration.

^{Specifically, the p +} -type polysilicon layer 81b and the n ⁺ -type polysilicon layer 82b of the upper polysilicon diode 80b are the p-type polysilicon layer 81a and the n-type polysilicon layer of the lower polysilicon diode 80a, respectively. The crystal grain size of the polysilicon crystal grains is larger than that of 82a. Therefore, the polysilicon diode 80b in the upper layer has a smaller number of polysilicon crystal grains and a smaller grain boundary 84b of the polysilicon crystal grains than the polysilicon diode 80a in the lower layer.

In addition, the upper layer of the p ⁺ -type polysilicon layer 81b, as compared with the lower layer of p-type polysilicon layer 81a, that high p-type impurity concentration, the grain boundaries 84b of polysilicon crystal grains by band bending The width of the poverty layer formed should be narrow. Layer of n ⁺ -type polysilicon layer 82b, as compared with the lower layer of n-type polysilicon layer 82a, the n-type impurity concentration that is higher, the depletion formed in the crystal grain boundary 84b of the polysilicon grains by band bending The width wb of the layer is preferably narrow (wa> wb).

As described above, the polysilicon diode 80b in the upper layer has a lower resistance than the polysilicon diode 80a in the lower layer because there are few locations where band bending occurs. Further, since the polysilicon diode 80b in the upper layer has a high carrier concentration (impurity concentration), it is not easily affected by the energy barrier and has a lower resistance than the polysilicon diode 80a in the lower layer. In the portion of the polysilicon diode 80b in the upper layer where the forward current does not flow, there may be a portion in which the width of the depletion layer caused by the bending of the band is widened.

Further, the difference in the magnitude of the energy level at the bending of the band for each grain boundary with the polysilicon crystal grains is one of the factors that can disperse the forward voltage characteristics of the polysilicon diode. Therefore, as described above, the polysilicon diode 80b in the upper layer has less band bending points than the polysilicon diode 80a in the lower layer, and thus has forward voltage characteristics as compared with the polysilicon diode 80a in the lower layer. Variation can be suppressed.

Further, each polysilicon layer constituting the polysilicon diode has a uniform impurity concentration. The polysilicon layers are a p-type polysilicon layer 81a, an n-type polysilicon layer 82a, a p ⁺ -type polysilicon layer 81b, and an n ⁺ -type polysilicon layer 82b. The uniform impurity concentration means that the impurity concentration is the same over the entire polysilicon layer (the portion where the forward current does not flow may be excluded) within the range including the tolerance of process variation. The impurity concentration of each polysilicon layer can be made uniform for the following reasons.

As will be described later, a predetermined ion species is ion-implanted into each polysilicon layer constituting the polysilicon diode so as to satisfy a predetermined impurity concentration in a predetermined conductive type (p type or n type). The ion-injected ion species are introduced into the in-plane (parts other than the grain boundaries) of the polysilicon crystal grains, but the crystals of the polysilicon crystal grains are crystallized by the bending of the band generated at the crystal grain boundaries of the polysilicon crystal grains. A potential gradient (potential change) is generated at the grain boundaries, and the ionic species are sucked into the grain boundaries of the polysilicon crystal grains due to this potential gradient.

When the ion species are sucked into the grain boundaries of the polysilicon crystal grains, the ion species in the in-plane of the polysilicon crystal grains are reduced, and a difference in impurity concentration occurs between the in-plane of the polysilicon crystal grains and the crystal grain boundaries. In addition, the in-plane impurity concentration of the polysilicon crystal grains cannot be set to the originally required predetermined impurity concentration. As a result, the variation in the forward voltage characteristics of the temperature sense unit 13 that depends on the in-plane impurity concentration of the polysilicon crystal grains becomes large. The larger the grain boundaries of the polysilicon crystal grains and the thinner the polysilicon layer, the more likely this problem will occur.

For example, the polysilicon diode 80b in the upper layer has a large planar grain size of the polysilicon crystal grains, and it is easy to stably hold the ion-injected ion species in the plane of the polysilicon crystal grains. The diameter also increases in the depth direction Z. For example, the size of the cross-sectional particle size of one polysilicon crystal grain may be about the thickness of the polysilicon layer (see FIG. 5), and the ion-injected ion species is along the grain boundaries of the polysilicon crystal grains. It penetrates the polysilicon layer and cannot retain all ion species in the polysilicon layer.

Therefore, in the present embodiment, the upper-layer polysilicon diode 80b is formed on the lower-layer polysilicon diode 80a whose crystal grain size of the polysilicon crystal grains is smaller than that of the upper-layer polysilicon diode 80b. Therefore, the ion species injected into the grain boundaries of the polysilicon crystal grains of the polysilicon diode 80b in the upper layer stops between the polysilicon diode 80b in the upper layer and the polysilicon diode 80a in the lower layer, so that the polysilicon in the upper layer is poly. It tends to stay at the grain boundaries of the polysilicon crystal grains of the polysilicon diode 80b.

In this way, the ion-implanted ion species does not penetrate the polysilicon diode 80b along the grain boundaries of the polysilicon crystal grains of the polysilicon diode 80b. Therefore, the ion species can be retained at the grain boundaries of the polysilicon crystal grains of the polysilicon diode 80b in the upper layer to stably maintain a predetermined impurity concentration. In addition, by implanting a high dose of ions, a predetermined impurity concentration is stably maintained even in the plane of the polysilicon crystal grains of the polysilicon diode 80b in the upper layer.

Further, when the polysilicon diode 80b in the upper layer is formed, some conductive impurities are diffused outward from the polysilicon diode 80a in the lower layer, but these conductive impurities are diffused to the polysilicon diode 80b in the upper layer, and the polysilicon diode is formed. It is difficult to diffuse to the outside of 80a and 80b. By implanting the ion species into the polysilicon diode 80b in the upper layer at a high dose amount, the outward diffusion of conductive impurities from the polysilicon diode 80a in the lower layer to the polysilicon diode 80b in the upper layer can be reduced. can.

Therefore, a predetermined impurity concentration of the polysilicon diode 80a in the lower layer is also stably secured. By ensuring a predetermined impurity concentration of the polysilicon diode 80a in the lower layer, when the polysilicon diode 80b in the upper layer is formed, the polysilicon diode 80b in the upper layer also secures conductive impurities from the polysilicon diode 80a in the lower layer. be able to. Thereby, the impurity concentration can be made uniform in the in-plane of the polysilicon crystal grains of the polysilicon diode 80b in the upper layer and across the crystal grain boundaries.

In this way, each polysilicon layer constituting the polysilicon diode can have a stable and uniform impurity concentration, so that the impurity concentration is uniform in the in-plane of the polysilicon crystal grains and across the crystal grain boundaries. become. Therefore, the bending of the band due to homozygote becomes small, and the energy barrier becomes small regardless of the magnitude of the forward current, so that the variation in the forward voltage characteristic is further suppressed. Therefore, the variation in the forward voltage characteristics of the entire temperature sense unit 13 is also suppressed.

It has been confirmed by the inventor that the effect of suppressing the variation in the forward voltage characteristics of the temperature sense unit 13 is remarkable, for example, when the total thickness of the polysilicon diodes 80a and 80b is about 0.5 μm or less. .. The lower-layer polysilicon diode 80a can retain the ion species ion-injected into the upper-layer polysilicon diode 80b in the upper-layer polysilicon diode 80b as described above when the upper-layer polysilicon diode 80b is formed. It suffices to be as thick as possible, preferably as thin as possible.

The thickness of the polysilicon diode 80b in the upper layer is equal to or greater than the thickness of the polysilicon diode 80a in the lower layer. The crystal grain size of the polysilicon crystal grains of the polysilicon diode 80a in the lower layer is, for example, about 0.01 μm or more, and is smaller than the crystal grain size of the polysilicon crystal grains of the polysilicon diode 80b in the upper layer. The crystal grain size of the polysilicon crystal grains of the polysilicon diode 80b in the upper layer is, for example, about 0.2 μm or more and less than 0.5 μm, preferably about 0.3 μm or less.

When the crystal grain size of the polysilicon crystal grains of the underlying polysilicon diode 80a is less than the above lower limit, the cross-sectional resistance of the polysilicon diode 80a becomes high, and as a result, the p-type polysilicon layer 81a of the polysilicon diode 80a ( The carrier injection amount from the anode region) and the carrier injection amount from the n-type polysilicon layer 82a (cathode region) vary, and the forward voltage variation becomes large. By setting the crystal grain size of the polysilicon crystal grains of the polysilicon diode 80a in the lower layer to less than the above upper limit value, the polysilicon in the upper layer is poly at the time of ion injection of a predetermined conductive impurity into the polysilicon diode 80b in the upper layer as described above. Ion species that have penetrated the silicon diode 80b can be stopped.

By setting the crystal grain size of the polysilicon crystal grains of the polysilicon diode 80b in the upper layer to the above lower limit value or more, the effect of suppressing the variation in the forward voltage characteristics of the temperature sense unit 13 can be obtained. Further, since the step coverage of the front surface of the semiconductor substrate 10 is deteriorated due to the integration of a plurality of semiconductor elements, the thickness of the polysilicon diode 80b in the upper layer should be as thin as possible. Therefore, the smaller the crystal grain size of the polysilicon crystal grains of the polysilicon diode 80b in the upper layer, the better.

The interlayer insulating film 83 is laminated on the interlayer insulating film 40 and covers the polysilicon diodes 80a and 80b. The polysilicon diodes 80a and 80b, the semiconductor substrate 10, the main semiconductor element 11, and the current sense unit 12 are electrically insulated by the interlayer insulating films 40 and 83. ^{The anode pad 23a is in contact with the p +} -type polysilicon layer 81b at the third contact hole 83a of the interlayer insulating film 83, ^{and is electrically connected to the p +} -type polysilicon layer 81b and the p-type polysilicon layer 81a.

^{The cathode pad 23b is in contact with the n +} type polysilicon layer 82b at the fourth contact hole 83b of the interlayer insulating film 83, ^{and is electrically connected to the n +} type polysilicon layer 82b and the n-type polysilicon layer 82a. The anode pad 23a and the cathode pad 23b are made of the same material as the source pad 21a, and are formed at the same time as the source pad 21a, for example. Terminal pins 48c and 48d are joined to the anode pad 23a and the cathode pad 23b, respectively, with the same wiring structure as that on the source pad 21a.

The terminal pins 48c and 48d are external connection terminals that take out the potentials of the anode pad 23a and the cathode pad 23b to the outside, respectively, and are round bar-shaped wiring members having a predetermined diameter according to the current capacity of the temperature sense unit 13. .. Reference numerals 47c and 47d are plating films constituting the wiring structure on the anode pad 23a and the wiring structure on the cathode pad 23b, respectively. Reference numerals 49c and 50c are first and second protective films constituting the wiring structure on the temperature sense unit 13, respectively. No barrier metal is provided on the temperature sense unit 13.

Further, in the main invalid region 1b, a gate pad portion 14 in which the gate pad 21b of the main semiconductor element 11 is arranged is provided (see FIG. 1). The gate pad 21b is provided on the interlayer insulating film 40 in the main invalid region 1b, apart from the other electrode pads. The gate pad 21b is made of the same material as the source pad 21a, and is formed at the same time as the source pad 21a. Terminal pins (not shown) are joined on the gate pad 21b with the same wiring structure as that on the source pad 21a.

The operation of the semiconductor device 20 according to the embodiment will be described. In a state where a positive voltage (forward voltage) is applied to the drain electrode 51 with respect to the source electrode (source pad 21a) of the main semiconductor element 11, a voltage equal to or higher than the gate threshold voltage is applied to the gate electrode 39a of the main semiconductor element 11. When applied, a channel (n-type inversion layer) is formed in a portion of the main semiconductor element 11 along the trench 37a of the p-type base region 34a. As a result, ^{a current flows from the n +} type drain region 31 of ^{the main semiconductor element 11 toward the n +} type source region 35a, and the main semiconductor element 11 is turned on.

Under the same conditions as the main semiconductor element 11, the gate electrode of the current sense unit 12 is in a state where a positive voltage (forward voltage) is applied to the drain electrode 51 with respect to the source electrode (OC pad 22) of the current sense unit 12. When a voltage equal to or higher than the gate threshold voltage is applied to 39b, a channel (n-type inversion layer) is formed in a portion of the current sense unit 12 along the trench 37b of the p-type base region 34b. ^{As a result, a current (hereinafter referred to as a sense current) flows from the n +} type drain region 31 of the current sense unit 12 ^{toward the n +} type source region 35b, and the current sense unit 12 is turned on.

When the main semiconductor element 11 is turned on, the current sense unit 12 is turned on. When the sense current flows through the current sense unit 12, a voltage drop occurs in a resistor (not shown) connected between ^{the n + type source region 35b of the current sense unit 12 and the ground point.} Since the sense current of the current sense unit 12 increases according to the magnitude of the current flowing through the main semiconductor element 11, the voltage drop in the resistor also increases. Therefore, by monitoring the magnitude of the voltage drop in this resistor, the overcurrent in the main semiconductor element 11 can be detected.

On the other hand, when a voltage lower than the gate threshold voltage is applied to the gate electrode 39a, the main semiconductor element 11 includes the first and second p ⁺ type regions 61a and 62a, the n-type current diffusion region 33a, and the n ^- type drift region 32. By reverse biasing the pn junction of, the off state is maintained. A voltage lower than the gate threshold voltage is also applied to the gate electrode 39b of the current sense unit 12, and the current sense unit 12 has the first and second p ⁺ type regions 61b and 62b, the n-type current diffusion region 33b, and the n ^- type drift region 32. The pn junction with and is reverse biased to maintain the off state.

Further, during the operation of the semiconductor device 20 according to the embodiment, the temperature sense unit 13 is constantly connected to the anode region (p-type polysilicon layer 81a and p ⁺ -type polysilicon layer 81b) and the cathode region (from the anode pad 23a). A forward current continues to flow toward the cathode pad 23b through the pn junction with the n-type polysilicon layer 82a and the n ^{+ -type polysilicon layer 82b).} The curve (forward voltage characteristic) showing the relationship between the forward current If and the forward voltage Vf of the temperature sense unit 13 depends on the temperature, and the higher the temperature, the smaller the forward voltage Vf.

Therefore, the forward voltage characteristic of the temperature sense unit 13 is acquired in advance and stored in, for example, a storage unit (not shown). During the operation of the semiconductor device 20 according to the embodiment, for example, the forward voltage Vf (1) generated between the anode pad 23a and the cathode pad 23b of the temperature sense unit 13 at room temperature (for example, about 25 ° C.) by the arithmetic circuit unit. The voltage drop in the temperature sense unit 13) is continuously monitored. The change in the temperature of the main semiconductor element 11 (the temperature of the semiconductor substrate 10) can be detected by the change in the forward voltage Vf of the temperature sense unit 13.

The temperature of the main semiconductor element 11 can be confirmed based on the forward voltage characteristic of the temperature sense unit 13 acquired in advance and the forward current If (for example, about 200 μA) that is constantly flowing through the temperature sense unit 13. can. When the voltage value of the forward voltage Vf of the temperature sense unit 13 decreases from normal temperature (for example, about 1 V) to, for example, about 0.5 V, the semiconductor substrate 10 has a high temperature (for example, about 160 ° C.) portion. Therefore, the arithmetic circuit unit stops the supply of the gate voltage to the main semiconductor element 11 and stops the operation of the main semiconductor element 11.

Next, a method of manufacturing the semiconductor device 20 according to the embodiment will be described. 9 to 18 are cross-sectional views showing a state in the middle of manufacturing the semiconductor device according to the embodiment. Although FIGS. 9 to 14 show only the state in which the main semiconductor element 11 is in the process of being manufactured, each part of the semiconductor element (see FIGS. 1 to 3) manufactured on the same semiconductor substrate 10 is the same as each part of the main semiconductor element 11. It is formed at the same time as each part with the same impurity concentration and depth. FIGS. 15 to 18 show a state in which the temperature sense unit 13 is in the process of being manufactured.

First, as shown in FIG. 9, as an n ⁺ type starting substrate (semiconductor wafer) 71 made of silicon carbide, for example, a nitrogen (N) -doped silicon carbide single crystal substrate is prepared. Then, the front surface of the n ⁺ -type starting substrate 71, n nitrogen is lightly doped than n ⁺ -type starting substrate 71 ^- -type silicon carbide layer 72 is epitaxially grown. When the main semiconductor element 11 has a withstand voltage of 3300 V class, ^{the thickness t1 of the n-} type silicon carbide layer 72 may be, for example, about 30 μm.

Next, as shown in FIG. 10, by photolithography and ion implantation of a p-type impurity such as Al ^{, the first p +} type region 61a and p in ^{the surface region of the n-} type silicon carbide layer 72 in the main effective region 1a. ^{Each +} type region 91 is selectively formed. The first p ⁺ type region 61a and the p ⁺ type region 91 are alternately and repeatedly arranged in one direction Y (horizontal direction: see FIGS. 2 and 3) parallel to the semiconductor substrate 10, for example.

Next, by ion implantation of n-type impurities such as photolithography and example nitrogen, n over the entire main effective area 1a ^- forming the n-type region 92 in the surface region of the -type silicon carbide layer 72. The n-type region 92 is formed between the first p ⁺ type region 61a and the p ⁺ type region 91 in contact with the p ⁺ type regions 61a and 91. The formation order of the n-type region 92 and the p ⁺ -type regions 61a and 91 may be interchanged.

^{The distance d2 between the p +} type regions 61a and 91 adjacent to each other is, for example, about 1.5 μm. The p ⁺ type regions 61a and 91 have, for example, a depth d1 and an impurity concentration of about 0.5 μm and 5.0 × 10 ¹⁸ / cm ³ , respectively. The depth d3 and the impurity concentration of the n-type region 92 are, for example, about 0.4 μm and about 1.0 × 10 ¹⁷ / cm ³ , respectively. The portion of the n ^- type silicon carbide layer 72 that has not been ion-implanted becomes the n ^- type drift region 32.

Next, as shown in FIG. 11, n ^- -type n doped with n-type impurities further on the silicon carbide layer 72 such as nitrogen or the like ^- in the form of a silicon carbide layer for example about 0.5μm thickness t2 is epitaxially grown , The thickness of the n ^- type silicon carbide layer 72 is increased. As a result, ^{the thickness of the n-} type silicon carbide layer 72 becomes a predetermined thickness. The impurity concentration of the thickened portion 72a of the n ^- type silicon carbide layer 72 may be, for example, 3 × 10 ¹⁵ / cm ³ .

Next, by ion implantation of p-type impurities such as photolithography and Al, n ^- the part 72a with an increased thickness of -type silicon carbide layer 72, selectively the p ⁺ -type region 93 to reach the p ⁺ -type region 91 Form. Next, by ion implantation of n-type impurities such as photolithography and example nitrogen, n ^- the part 72a with an increased thickness of -type silicon carbide layer 72, selectively forming an n-type region 94 reaching the n-type region 92 do.

As a result, the p ⁺ type regions 91 and 93 adjacent to each other in the depth direction Z are connected to each other to form the second p ⁺ type region 62a. The n-type regions 92 and 94 adjacent to each other in the depth direction Z are connected to each other to form the n-type current diffusion region 33a. Conditions such as the impurity concentration of the p ⁺ type region 93 and the n-type region 94 are the same as those of the p ⁺ type region 91 and the n-type region 92, respectively. The formation order of the p ⁺ type region 93 and the n-type region 94 may be exchanged.

Next, as shown in FIG. 12, a p-type silicon carbide layer 73 doped with a p-type impurity such as Al is epitaxially grown on ^{the n-type silicon carbide layer 72.} The thickness t3 and the impurity concentration of the p-type silicon carbide layer 73 are, for example, about 1.3 μm and about 4.0 × 10 ¹⁷ / cm ³ , respectively. Through the steps up to this point, ^{a semiconductor substrate 10 (semiconductor wafer) in which an n-} type silicon carbide layer 72 and a p-type silicon carbide layer 73 are sequentially laminated on an ^{n +} type starting substrate 71 is produced.

Next, the steps of photolithography and ion implantation as a set are repeated under different conditions, and in the main effective region 1a, the surface region of the p-type silicon carbide layer 73 is covered with the n ⁺ type source region 35a and the p ⁺⁺ type contact region. Each of 36a is selectively formed. The portion of the p-type silicon carbide layer 73 of the main effective region 1a between the n ⁺ type source region 35a and the p ⁺⁺ type contact region 36a and the n ^- type silicon carbide layer 72 is the p-type base region 34a. ..

Next, regarding the diffusion regions (first and second p ⁺ type regions 61a and 62a, n-type current diffusion region 33a, n ⁺ type source region 35a and p ⁺⁺ type contact region 36a) formed by ion implantation, for example, about 1700 ° C. Impurities are activated by heat treatment (activation annealing) for about 2 minutes at the same temperature. The activation annealing may be performed once after the formation of all the diffusion regions, or may be performed after each diffusion region is formed by ion implantation.

Next, as shown in FIG. 13, the n-type current diffusion region 33a is reached from the front surface of the semiconductor substrate 10 through the n ⁺ type source region 35a and the p-type base region 34a by photolithography and etching. ^{A trench 37a facing the first p +} type region 61a is formed in the depth direction Z (longitudinal direction: see FIGS. 3 and 4). The trench 37a may reach, for example, the first p ⁺ type region 61a and ^{terminate inside the first p +} type region 61a.

Next, as shown in FIG. 14, a gate insulating film 38a is formed along the front surface of the semiconductor substrate 10 and the inner wall of the trench 37a. The gate insulating film 38a may be, for example, a thermal oxide film formed by thermally oxidizing the semiconductor surface at a temperature of about 1000 ° C. in _{an oxygen (O 2) atmosphere, or may be a high temperature oxidation (HTO: High Temperature Oxide).} ) May be a deposited film.

Next, for example, a phosphorus (P) -doped polysilicon layer is deposited (formed) on the front surface of the semiconductor substrate 10 so as to be embedded in the trench 37a. Next, the polysilicon layer is selectively removed by photolithography and etching, leaving only the portion of the polysilicon layer that becomes the gate electrode 39a inside the trench 37a.

Further, as described above, when each part of the MOS gate of the main semiconductor element 11 is formed, the semiconductor element (current sense unit 12, overvoltage protection unit (not shown), and arithmetic circuit unit (current sense unit 12, overvoltage protection unit (not shown)) manufactured on the same semiconductor substrate 10 are formed. High-performance parts (not shown) and the like: (see FIGS. 3 and 4) may be formed at the same time as each part having the same impurity concentration and depth as each part of the main semiconductor element 11.

By arranging the main semiconductor element 11 in the island-shaped p-type base region 34a formed in the surface region of the front surface of the semiconductor substrate 10, the p-type base region 34a and the n ^- type drift region 32 can be arranged. By pn junction separation, it is separated from other semiconductor elements manufactured on the same semiconductor substrate 10. The current sense unit 12 has the same structure as the main semiconductor element 11, and may be arranged in the island-shaped p-type base region 34b formed in the surface region of the front surface of the semiconductor substrate 10.

Next, an interlayer insulating film 40 such as BPSG (Boro Phospho Silicate Glass) or PSG (Phospho Silicate Glass) is applied to the entire front surface of the semiconductor substrate 10 so as to cover the gate electrode 39a to a thickness of, for example, 1 μm. Formed with.

Next, as shown in FIG. 15, the polysilicon layer 101 is deposited (formed) on the interlayer insulating film 40 in the main invalid region 1b under a temperature environment of, for example, about 500 ° C. or higher and 630 ° C. or lower. The polysilicon layer 101 may be doped with n-type impurities at an impurity concentration or less of the n-type polysilicon layer 82a formed in a later step, or may be non-doped.

Next, the polysilicon layer 101 is selectively removed by photolithography and etching to leave a portion of the polysilicon layer 101 that becomes the polysilicon diode 80a. Next, an ion implantation mask 102 having a portion corresponding to the formation region of the p-type polysilicon layer 81a, which is the anode region of the polysilicon diode 80a, is formed on the polysilicon layer 101.

Next, a p-type impurity (ion species) such as boron (B) is ion-implanted using the ion implantation mask 102 to selectively form the p-type polysilicon layer 81a inside the polysilicon layer 101. do. The dose amount of the ion implantation 103 may be, for example, about 1 × 10 ¹⁵ / cm ² . Then, the ion implantation mask 102 is removed.

Next, as shown in FIG. 16, an ion implantation mask 104 having a portion corresponding to the formation region of the n-type polysilicon layer 82a, which is the cathode region of the polysilicon diode 80a, is formed on the polysilicon layer 101. do. Next, an n-type impurity (ion species) such as arsenic (As) is ion-implanted 105 using the ion implantation mask 104, and the n-type polysilicon layer 82a is selectively placed inside the polysilicon layer 101. Form.

By the steps up to this point, a polysilicon diode 80a is formed on the polysilicon layer 101 by a pn junction between the p-type polysilicon layer 81a and the n-type polysilicon layer 82a. The dose amount of the ion implantation 105 may be, for example, about 5 × 10 ¹⁵ / cm ² . When the polysilicon layer 101 has the same impurity concentration as the n-type polysilicon layer 82a, the formation of the ion implantation mask 104 and the ion implantation 105 are omitted. Then, the ion implantation mask 104 is removed.

Next, as shown in FIG. 17, the polysilicon layer 106 is deposited (formed) on the polysilicon layer 101 (that is, the polysilicon diode 80a) and laminated. The polysilicon layer 106 may be doped with n-type impurities at an impurity concentration or less of the n ⁺ -type polysilicon layer 82b formed in a later step, or may be non-doped.

The polysilicon layer 106 is deposited at a temperature higher than the temperature at which the underlying polysilicon layer 101 is deposited, and in a temperature environment of, for example, 520 ° C. or higher and 650 ° C. or lower. Specifically, the temperature at the time of deposition of the polysilicon layer 106 may be higher than the temperature at the time of deposition of the polysilicon layer 101, for example, by about 100 ° C.

By making the temperature at the time of deposition of the polysilicon layer 106 higher than the temperature at the time of deposition of the polysilicon layer 101, the crystal grain size of the polysilicon crystal grains of the polysilicon layer 106 can be changed in both the planar particle size and the cross-sectional particle size. It can be made larger than the crystal grain size of the polysilicon crystal grains of the polysilicon layer 101.

Further, the polysilicon layer 106 may be deposited on the polysilicon layer 101 as soon as possible. The reason is that the surface of the polysilicon layer 101 is naturally oxidized before the polysilicon layer 106 is deposited, and there is a possibility that the polysilicon layer 101 and the polysilicon layer 106 are electrically insulated by this natural oxide film. Because there is.

Next, the polysilicon layer 106 is selectively removed by photolithography and etching to leave a portion of the polysilicon layer 106 that becomes the polysilicon diode 80b. Next, an ion implantation mask 107 having a portion corresponding to the formation region of the ^{p +} type polysilicon layer 81b, which is the anode region of the polysilicon diode 80b, is formed on the polysilicon layer 106.

Next, the p-type impurity (ion species) such as boron is ion-implanted using the ion implantation mask 107, and the p-type impurity (ion species) is ion-implanted 108 to reach the p-type polysilicon layer 81a through the polysilicon layer 106 in the depth direction. ^{A +} -type polysilicon layer 81b is formed. The dose amount of the ion implantation 108 is preferably the same as the dose amount of the ion implantation 103 for forming the p-type polysilicon layer 81a, or preferably larger than the dose amount of the ion implantation 103. Then, the ion implantation mask 107 is removed.

Next, as shown in FIG. 18, an ion implantation mask 109 having a portion corresponding to the formation region of the ^{n + type polysilicon layer 82b, which is the cathode region of the polysilicon diode 80b, opened on the polysilicon layer 106.} Form. Next, the ion implantation mask 109 is used to implant an n-type impurity (ion species) such as arsenic into the ion implantation 110, and the n-type polysilicon layer 82a is reached through the polysilicon layer 106 in the depth direction. ^{The +} -type polysilicon layer 82b is selectively formed. When the polysilicon layer 106 has the ^{same impurity concentration as the n +} type polysilicon layer 82b, the formation of the ion implantation mask 109 and the ion implantation 110 may be omitted.

By the steps up to this point, a polysilicon diode 80b is formed on the ^{polysilicon layer 106 by a pn junction between the p +} type polysilicon layer 81b and the n ^{+ type polysilicon layer 82b.} The dose amount of the ion implantation 110 is preferably the same as the dose amount of the ion implantation 105 for forming the n-type polysilicon layer 82a, or preferably larger than the dose amount of the ion implantation 105.

When the polysilicon layer 106 has the ^{same impurity concentration as the n +} type polysilicon layer 82b, the formation of the ion implantation mask 109 and the ion implantation 110 are omitted. Then, the ion implantation mask 109 is removed. As a result, the temperature sense portion 13 is formed by the polysilicon diodes 80a and 80b. Next, the interlayer insulating film 83 that covers the temperature sense portion 13 is formed.

Next, the first and second contact holes 40a and 40b penetrating the interlayer insulating film 40 and the gate insulating film 38a are formed in the depth direction Z by photolithography and etching. The third and fourth contact holes 83a and 83b penetrating the interlayer insulating film 83 are formed in the depth direction Z. ^{The n +} type source region 35a and the p ⁺⁺ type contact region 36a of the main semiconductor element 11 are exposed in the first contact hole 40a.

^{The n +} type source region 35b and the p ⁺⁺ type contact region 36b of the current sense unit 12 are exposed in the second contact hole 40b. ^{The p +} type polysilicon layer 81b and the n ⁺ type polysilicon layer 82b of the temperature sense unit 13 are exposed in the third and fourth contact holes 83a and 83b, respectively. Next, the interlayer insulating films 40 and 83 are flattened (reflowed) by heat treatment.

Next, the first TiN film 42a that covers only the interlayer insulating film 40 is formed. Next, a NiSi film 41a is formed on the front surface of the semiconductor substrate 10 so as to be exposed to the first contact hole 40a. Next, the first Ti film 43a, the second TiN film 44a, and the second Ti film 45a are laminated in this order so as to cover the NiSi film 41a and the first TiN film 42a to form the barrier metal 46a. Next, the source pad 21a is deposited on the second Ti film 45a.

Further, in the second contact hole 40b, at the same time as the NiSi film 41a and the barrier metal 46a, the NiSi film 41b and the barrier metal 46b are formed in the same configuration as these metal films, respectively. The OC pad 22, the anode pad 23a, and the cathode pad 23b are formed in the second to fourth contact holes 40b, 83a, and 83b at the same time as the source pad 21a in the same configuration as the source pad 21a, respectively.

Further, a drain electrode 51 that makes ohmic contact is formed on the back surface of the semiconductor substrate 10, and for example, a Ti film, a Ni film, and a gold (Au) film are laminated in this order on the surface of the drain electrode 51 to form a drain pad (not shown). ..

Next, first protective films 49a to 49c made of polyimide are selectively formed on the front surface of the semiconductor substrate 10, and different electrode pads 21a, 22 and are formed in the openings of the first protective films 49a to 49c, respectively. The 23a and 23b are exposed. Next, after the general pre-plating treatment, the plating films 47a to 47d are exposed on the openings of the first protective films 49a to 49c of the electrode pads 21a, 22, 23a, and 23b by the general plating treatment. To form.

Next, the plating films 47a to 47d are dried by heat treatment (baking). Next, the second protective films 50a to 50c made of polyimide are formed to cover the boundaries between the plating films 47a to 47d and the first protective films 49a to 49c. Next, the strength of the polyimide film (first protective film 49a to 49c and second protective film 50a to 50c) is improved by heat treatment (cure). Next, the terminal pins 48a to 48d are joined onto the plating films 47a to 47d by solder layers, respectively.

Although not shown, a first protective film, a plating film, and a second protective film are sequentially formed on the gate pad 21b at the same time as the wiring structure on the electrode pads 21a, 22, 23a, and 23b, and the terminals are formed by the solder layer. A wiring structure in which pins are joined is formed. After that, the semiconductor apparatus 20 shown in FIGS. 1 to 8 is completed by dicing (cutting) the semiconductor substrate 10 (semiconductor wafer) into individual chips.

As described above, according to the embodiment, the temperature sense portion has a multilayer structure in which a plurality of horizontal polysilicon diodes are laminated, and the upper layer of polysilicon diodes have a larger crystal grain size of the polysilicon crystal grains. The polysilicon diode in the upper layer has a larger crystal grain size of the polysilicon crystal grains than the polysilicon diode in the lower layer, so that the grain boundaries of the polysilicon crystal grains are smaller. Therefore, compared to the polysilicon diode in the lower layer, the polysilicon diode in the upper layer has less depletion layer that is generated at the grain boundary of the polysilicon crystal grains due to the bending of the band due to homojunction and becomes an energy barrier, and has low resistance and forward direction. Current easily flows.

Since the forward current mainly flows through the polysilicon diode in the upper layer in the temperature sense part, the forward voltage characteristics vary as compared with the conventional structure (see FIG. 21) in which the polysilicon diode having a single layer structure is used as the temperature sense part. It is suppressed. As a result, the temperature detection accuracy of the temperature sense unit can be improved, so that the reliability of the semiconductor device can be improved. Further, in the polysilicon diode in the upper layer, the higher the impurity concentration, the narrower the width of the depletion layer formed at the grain boundary of the polysilicon crystal grains due to the bending of the band due to homojunction, and the carrier becomes an energy barrier due to the depletion layer. Can be less affected by.

Further, according to the embodiment, the temperature sense is set to a multilayer structure of a polysilicon diode in which the crystal grain size of the polysilicon crystal grains is larger in the upper layer, so that the ion species ion-injected into the polysilicon diode in the upper layer can be obtained. , It can be stopped between the polysilicon diode in the upper layer and the polysilicon diode in the lower layer and fastened to the polysilicon diode in the upper layer. Further, when the polysilicon diode in the upper layer is formed, the conductive impurities diffused outward from the polysilicon diode in the lower layer are diffused to the polysilicon diode side in the upper layer, and it is difficult to diffuse to the outside of the temperature sense portion.

Thereby, the impurity concentration of each polysilicon layer of the polysilicon diode constituting the temperature sense unit can be made uniform. As a result, each polysilicon diode constituting the temperature sense portion has a uniform impurity concentration in the in-plane of the polysilicon crystal grains and over the crystal grain boundaries, and is formed by homojunction at the crystal grain boundaries of the polysilicon crystal grains. The bending of the band becomes smaller. Each polysilicon diode that constitutes the temperature sense portion has a small bending of the band formed by homojunction at the grain boundaries of the polysilicon crystal grains, and thus is affected by the energy barrier of the carrier regardless of the magnitude of the forward current. It becomes difficult to receive.

Further, in the conventional structure, when the semiconductor material of the semiconductor substrate is silicon, if a portion having a temperature of about 180 ° C. is generated in the semiconductor substrate, a large leakage current (about several hundred mA) flows through the main semiconductor element. .. Therefore, when the temperature sense unit is a polysilicon diode, if the main semiconductor element is used at a high temperature close to the upper limit of use temperature (for example, about 170 ° C) or higher, the temperature will vary due to the variation in the forward voltage characteristics of the polysilicon diode. If the detection temperature by the sense unit deviates by only a few degrees Celsius, a large leak current will flow through the main semiconductor element, and the main semiconductor element will be damaged only by the leak current.

By using silicon carbide, which has excellent high-temperature characteristics, as the semiconductor material of the semiconductor substrate, the main semiconductor element will not be damaged even if a large leak current flows, but when it is used as a high-frequency device or a device for high-current operation, When the main semiconductor element operates, the temperature of the semiconductor substrate rises momentarily, and a portion of the semiconductor substrate having a temperature of, for example, 300 ° C. or higher is generated. For this reason, the variation in the internal temperature distribution of the semiconductor substrate further increases the variation in the forward voltage characteristics of the polysilicon diode, and the temperature detection accuracy is further lowered as compared with the diffusion diode formed in the diffusion region inside the semiconductor substrate. ..

On the other hand, according to the embodiment, even if the semiconductor material of the semiconductor substrate is silicon carbide and the temperature-sense portion is a polysilicon diode, the upper-layer polysilicon diode constituting the temperature-sense portion is the surface of the polysilicon crystal grains. Since the impurity concentration is uniform throughout the inside and the crystal grain boundary, a constant amount of forward current can be continuously applied to the polysilicon diode in the upper layer even if the internal temperature distribution of the semiconductor substrate varies. Therefore, the forward voltage characteristic of the temperature sense unit is less likely to vary, and the temperature detection accuracy can be improved as compared with the conventional structure.

Further, when the temperature sense unit is a diffusion diode, the temperature sense unit malfunctions due to the adverse effect of the parasitic operation inside the semiconductor substrate. Therefore, in order to avoid the malfunction due to the parasitic operation inside the semiconductor substrate, the temperature sense unit malfunctions. Need to be formed in a large area (surface area) area. On the other hand, according to the embodiment, by using a polysilicon diode for the temperature sense portion, the temperature sense portion and the semiconductor substrate are electrically insulated by a thick oxide film (interlayer insulating film), so that the inside of the semiconductor substrate is internally insulated. Malfunction does not occur due to parasitic operation of. Therefore, the temperature sense unit can be reduced.

(Example)
The forward voltage characteristics of the temperature sense unit 13 (see FIGS. 3 to 8) of the semiconductor device 20 according to the above-described embodiment were verified. FIG. 19 is a frequency distribution diagram showing the forward voltage characteristics of the embodiment. FIG. 20 is a frequency distribution diagram showing the forward voltage characteristics of the conventional example. Frequency distribution of the forward voltage Vf of the temperature sense unit 13 in a state where a predetermined forward current If is continuously applied to the temperature sense unit 13 (hereinafter referred to as an embodiment) of the semiconductor device 20 according to the above-described embodiment. Is shown in FIG.

For comparison, the order of the temperature sense unit 213 in a state where the same predetermined forward current If as in the embodiment is continuously applied to the temperature sense unit 213 of the conventional semiconductor device 220 (hereinafter referred to as a conventional example: see FIG. 21). The frequency distribution of the directional voltage Vf is shown in FIG. The difference between the conventional example and the embodiment is that the polysilicon diode 80b in the upper layer is not provided. The thickness of the temperature sense unit 213 of the conventional example is the same as the total thickness of the polysilicon diodes 80a and 80b of the embodiment.

From the results shown in FIGS. 19 and 20, it was confirmed that in the examples, the range of the measured forward voltage Vf was narrowly limited as compared with the conventional example, and the variation in the forward voltage characteristics could be suppressed.

As described above, the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, a polysilicon diode may be formed by depositing a p-type polysilicon layer and then ion-injecting n-type impurities, or depositing an n-type polysilicon layer and then ion-injecting p-type impurities. May form a polysilicon diode. Further, the present invention can be applied even when a wide bandgap semiconductor or silicon other than silicon carbide is used instead of using silicon carbide as a semiconductor material. Further, the present invention holds the same even if the conductive type (n type, p type) is inverted.

As described above, the semiconductor device and the method for manufacturing the semiconductor device according to the present invention are useful for a power semiconductor device that controls a high voltage or a large current.

1 Active area 1a Main effective area 1b Main invalid area 2 Edge termination area 10 Semiconductor substrate 11 Main semiconductor element 12 Current sense part 12a Sense effective area 12b Sense invalid area 13 Temperature sense part 14 Gate pad part 20 Semiconductor device 21a Source pad (electrode) pad)
21b Gate pad (electrode pad)
22 OC pad (electrode pad)
23a Anode pad (electrode pad)
23b Cathode pad (electrode pad)
31 n ⁺ -type drain region 32 n ^- -type drift region 32a n ^- -type regions 33a, 33b n-type current diffusion regions 34a, 34b p-type base region 35a, 35b n ⁺ -type source region 36a, 36b p ⁺⁺ type contact region 37a , 37b Trench 38a, 38b Gate insulating film 39a, 39b Gate electrode 40,83 Interlayer insulating film 40a, 40b, 83a, 83b Contact hole 41a, 41b NiSi film 42a, 42b 1st TiN film 43a, 43b 1st Ti film 44a, 44b 2TiN film 45a, 45b Second Ti film 46a, 46b Barrier metal 47a to 47d Plating film 48a to 48d Terminal pin 49a to 49c First protective film 50a to 50c Second protective film 51 Drain electrode 61a, 61b, 62a, 62b, 91, 93 p ⁺ -type region 71 n ⁺ -type starting substrate 72 n ^- type silicon carbide layer 72a n ^- type silicon carbide layer having a thickness of the increased portion 73 p-type silicon carbide layer 80a, 80b polysilicon diodes 81a p-type polysilicon layer 81b p ⁺ type polysilicon layer 82an type polysilicon layer 82b n ⁺ type polysilicon layer 92,94 n type region d1 p ⁺ type region depth d2 ^{Distance between p +} type regions adjacent to each other d3 n type region Depth Thickness of the t1 n ^- type silicon carbide layer ^{first laminated on the n +} type starting substrate Thickness of the thickened portion of the t2 n ^- type silicon carbide layer t3 p-type silicon carbide layer thickness X, Y One direction parallel to the front surface of the semiconductor substrate Z Depth direction

Claims (6)

A semiconductor substrate made of a semiconductor with a wider bandgap than silicon,
A main semiconductor element having a pn junction on the first main surface side of the semiconductor substrate and through which a current passes through the pn junction flows.
A temperature sense unit that detects the temperature of the main semiconductor element,
With
The temperature sense unit
It is a multilayer structure having a plurality of transverse polysilicon diodes made of polysilicon, which are laminated on the first main surface of the semiconductor substrate via an insulating film and the conductive type regions are adjacent to each other in the depth direction.
A semiconductor device characterized in that the crystal grain size of the polysilicon crystal grains is larger than that of the polysilicon diode in the upper layer. The semiconductor device according to claim 1, wherein the polysilicon diode has a uniform impurity concentration in the in-plane of the polysilicon crystal grains and across the crystal grain boundaries. The semiconductor device according to claim 1 or 2, wherein the polysilicon diode in the upper layer has a higher impurity concentration. The temperature of a semiconductor substrate made of a semiconductor having a band gap wider than that of silicon, a main semiconductor element having a pn junction on the first surface side of the semiconductor substrate, and a current flowing through the pn junction, and the temperature of the main semiconductor element. A method for manufacturing a semiconductor device including a temperature sense unit for detecting.
A laminating step of laminating a plurality of polysilicon layers on the first main surface of the semiconductor substrate via an insulating film, and
Each time the polysilicon layer is laminated in the lamination step, a p-type impurity and / or an n-type impurity is ionically injected into the polysilicon layer, and a horizontal poly having the same conductive region adjacent to each other in the depth direction. The injection process that forms the silicon diode and
To form the temperature sense part,
A method for manufacturing a semiconductor device, characterized in that, in the laminating step, the polysilicon layer, which is the upper layer, is deposited in a higher temperature environment. The laminating step is characterized in that the polysilicon layer adjacent to the underlying polysilicon layer is deposited in the depth direction in a temperature environment that is 100 ° C. or more higher than the temperature at which the underlying polysilicon layer is deposited. The method for manufacturing a semiconductor device according to claim 4. The method for manufacturing a semiconductor device according to claim 4 or 5, wherein in the injection step, the dose amount of the ion implantation increases as the polysilicon layer in the upper layer increases.

Images