JP2020074495A - SiC semiconductor device - Google Patents

Abstract

To provide an SiC semiconductor device capable of reducing an influence of a modified layer on an SiC semiconductor chip.SOLUTION: An SiC semiconductor device 1 includes an SiC semiconductor layer 2 (SiC semiconductor chip) having a laminate structure including a SiC semiconductor substrate 6 and an SiC epitaxial layer 7 and including a first principal surface 3 (element formation surface) formed by the SiC epitaxial layer 7 and side surfaces 5A to 5D formed by the SiC semiconductor substrate 6 and the SiC epitaxial layer 7, and modified layers 22A to 22D (modified layers) formed in a portion composed of the SiC semiconductor substrate 6 at intervals from the SiC epitaxial layer 7 in the side surfaces 5A to 5D and modified into properties different from the SiC semiconductor substrate 6.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a SiC semiconductor device.

  In recent years, a method of processing a SiC semiconductor wafer, which is called a stealth dicing method, has attracted attention. In the stealth dicing method, the SiC semiconductor wafer is selectively irradiated with the laser light, and then the SiC semiconductor wafer is cut along the portion irradiated with the laser light. According to this method, an SiC semiconductor wafer having a relatively high hardness can be cut without using a cutting member such as a dicing blade, so that the manufacturing time can be shortened.

  Patent Document 1 discloses a method for manufacturing an SiC semiconductor device using a stealth dicing method. In the manufacturing method of Patent Document 1, a plurality of rows of modified regions (modified layers) are formed over the entire area of each side surface of the SiC semiconductor chip (SiC semiconductor layer) cut out from the SiC semiconductor wafer. The plurality of rows of modified regions (modified layers) extend along the tangential direction of the main surface of the SiC semiconductor chip and are formed at intervals in the normal direction of the main surface of the SiC semiconductor chip.

JP2012-146878A

  The modified layer is formed by modifying the SiC single crystal to have other properties. Therefore, considering the influence of the modified layer on the SiC semiconductor chip (SiC semiconductor layer), it is not desirable to form a plurality of modified layers on the entire side surface of the SiC semiconductor chip. Examples of the influence of the modified layer on the SiC semiconductor chip include changes in the electrical characteristics of the SiC semiconductor chip caused by the modified layer, occurrence of cracks in the SiC semiconductor chip originating from the modified layer, and the like. It

  One embodiment of the present invention provides a SiC semiconductor device capable of reducing the influence of a modified layer on a SiC semiconductor chip.

  One embodiment of the present invention has a laminated structure including a SiC semiconductor substrate and a SiC epitaxial layer, and has an element formation surface formed by the SiC epitaxial layer, and formed by the SiC semiconductor substrate and the SiC epitaxial layer. A SiC semiconductor chip having a side surface, and a modified layer formed on a portion of the side surface of the SiC semiconductor substrate spaced apart from the SiC epitaxial layer and modified to have a property different from that of the SiC semiconductor substrate. An SiC semiconductor device including the same is provided. According to this structure, it is possible to reduce the influence of the modified layer on the SiC semiconductor chip, particularly, the influence on the SiC epitaxial layer forming the element formation surface.

  According to one embodiment of the present invention, a SiC semiconductor chip having a first main surface as an element formation surface, a second main surface opposite to the first main surface, and a side surface, and the first main surface and the side surface. A first conductivity type first impurity region formed in the surface layer portion of the first main surface so as to be exposed from the first main surface, and a first conductivity type impurity concentration exceeding the first conductivity type impurity concentration of the first impurity region. And is formed in a region on the second main surface side with respect to the first impurity region so as to be exposed from the second main surface and the side surface and electrically connected to the first impurity region. The second impurity region of the first conductivity type is formed in a portion of the side surface where the second impurity region is exposed at a distance from the first impurity region, and is modified to have a property different from that of the SiC semiconductor chip. Provided is a SiC semiconductor device including a modified layer. . According to this structure, it is possible to reduce the influence of the modified layer on the SiC semiconductor chip, particularly, the influence on the element formation surface where the first impurity region is exposed.

FIG. 1 is a diagram showing a unit cell of a 4H—SiC single crystal applied to an embodiment of the present invention. FIG. 2 is a plan view showing the silicon surface of the unit cell of the 4H—SiC single crystal shown in FIG. FIG. 3 is a perspective view of the SiC semiconductor device according to the first embodiment of the present invention viewed from one angle, and is a perspective view showing a first example of the reforming line. FIG. 4 is a perspective view of the SiC semiconductor device shown in FIG. 3 viewed from another angle. FIG. 5 is an enlarged view of the area V shown in FIG. FIG. 6 is an enlarged view of the area VI shown in FIG. FIG. 7 is a plan view of the SiC semiconductor device shown in FIG. FIG. 8 is a sectional view taken along the line VIII-VIII shown in FIG. 7. FIG. 9 is a perspective view showing an SiC semiconductor wafer used for manufacturing the SiC semiconductor device shown in FIG. FIG. 10A is a cross-sectional view showing an example of a method for manufacturing the SiC semiconductor device shown in FIG. 10B is a diagram showing a step subsequent to FIG. 10A. FIG. 10C is a diagram showing a step subsequent to FIG. 10B. FIG. 10D is a diagram showing a step subsequent to FIG. 10C. FIG. 10E is a diagram showing a step subsequent to FIG. 10D. 10F is a diagram showing a step subsequent to FIG. 10E. FIG. 10G is a diagram showing a step subsequent to FIG. 10F. FIG. 10H is a diagram showing a step subsequent to FIG. 10G. 10I is a diagram showing a step subsequent to FIG. 10H. 10J is a diagram showing a step subsequent to FIG. 10I. FIG. 10K is a diagram showing a step subsequent to FIG. 10J. 10L is a diagram showing a step subsequent to FIG. 10K. 10M is a diagram showing a step subsequent to FIG. 10L. FIG. 11 is a perspective view showing a semiconductor package incorporating the SiC semiconductor device shown in FIG. FIG. 12A is a perspective view showing the SiC semiconductor device shown in FIG. 3, and is a perspective view showing a second form example of the reforming line. FIG. 12B is a perspective view showing the SiC semiconductor device shown in FIG. 3, and is a perspective view showing a third form example of the reforming line. 12C is a perspective view showing the SiC semiconductor device shown in FIG. 3, and is a perspective view showing a fourth form example of the reforming line. FIG. 12D is a perspective view showing the SiC semiconductor device shown in FIG. 3, and is a perspective view showing a fifth form example of the reforming line. FIG. 12E is a perspective view showing the SiC semiconductor device shown in FIG. 3, and is a perspective view showing a sixth form example of the reforming line. FIG. 12F is a perspective view showing the SiC semiconductor device shown in FIG. 3, and is a perspective view showing a seventh form example of the reforming line. FIG. 12G is a perspective view showing the SiC semiconductor device shown in FIG. 3, and is a perspective view showing an eighth example of the reforming line. FIG. 13 is a perspective view showing the SiC semiconductor device according to the second embodiment of the present invention, and is a perspective view showing the structure to which the reforming line according to the first embodiment is applied. FIG. 14 is a perspective view of the SiC semiconductor device according to the third embodiment of the present invention seen from one angle, and is a perspective view showing a structure to which the reforming line according to the first embodiment is applied. FIG. 15 is a perspective view of the SiC semiconductor device shown in FIG. 14 seen from another angle. FIG. 16 is a plan view showing the SiC semiconductor device shown in FIG. FIG. 17 is a plan view with the resin layer removed from FIG. FIG. 18 is an enlarged view of region XVIII shown in FIG. 17, and is a view for explaining the structure of the first main surface of the SiC semiconductor layer. 19 is a sectional view taken along line XIX-XIX shown in FIG. 20 is a sectional view taken along line XX-XX shown in FIG. FIG. 21 is an enlarged view of the area XXI shown in FIG. 22 is a sectional view taken along line XXII-XXII shown in FIG. FIG. 23 is an enlarged view of the area XXIII shown in FIG. FIG. 24 is a graph for explaining the sheet resistance. FIG. 25 is an enlarged view of a region corresponding to FIG. 18, showing an SiC semiconductor device according to the fourth embodiment of the present invention. FIG. 26 is a sectional view taken along line XXVI-XXVI shown in FIG. FIG. 27 is an enlarged view of a region corresponding to FIG. 21, showing an SiC semiconductor device according to the fifth embodiment of the present invention. FIG. 28 is an enlarged view of a region corresponding to FIG. 18, showing an SiC semiconductor device according to the sixth embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
In the embodiment of the present invention, a hexagonal SiC (silicon carbide) single crystal is applied. The hexagonal SiC single crystal has a plurality of polytypes including 2H (Hexagonal) -SiC single crystal, 4H-SiC single crystal, and 6H-SiC single crystal, depending on the period of atomic arrangement. Although the embodiment of the present invention describes an example in which a 4H-SiC single crystal is applied, other polytypes are not excluded from the present invention.

The crystal structure of 4H-SiC single crystal will be described below. FIG. 1 is a diagram showing a unit cell of 4H—SiC single crystal (hereinafter, simply referred to as “unit cell”) applied to an embodiment of the present invention. FIG. 2 is a plan view showing a silicon surface of the unit cell shown in FIG.
Referring to FIGS. 1 and 2, the unit cell includes a tetrahedral structure in which four C atoms are bonded to one Si atom in a tetrahedral arrangement (regular tetrahedral arrangement). The unit cell has an atomic arrangement in which tetrahedral structures are stacked for four periods. The unit cell has a hexagonal prism structure having a regular hexagonal silicon surface, a regular hexagonal carbon surface, and six side surfaces connecting the silicon surface and the carbon surface.

The silicon surface is a termination surface terminated by Si atoms. On the silicon surface, one Si atom is located at each of the six vertices of the regular hexagon, and one Si atom is located at the center of the regular hexagon.
The carbon surface is a terminal surface terminated by C atoms. On the carbon surface, one C atom is located at each of the six vertices of the regular hexagon, and one C atom is located at the center of the regular hexagon.

The crystal plane of the unit cell is defined by four coordinate axes (a1, a2, a3, c) including an a1, an a2 axis, an a3 axis and a c axis. The value of a3 of the four coordinate axes is a value of − (a1 + a2). Hereinafter, the crystal plane of the 4H—SiC single crystal will be described with reference to the silicon plane as an example of the hexagonal termination surface.
The a1 axis, the a2 axis, and the a3 axis are the arrangement directions of the Si atoms closest to each other (hereinafter simply referred to as “nearest neighbor atomic directions”) with reference to the Si atom located at the center in a plan view of the silicon surface viewed from the c-axis direction. That is) each is set. The a1 axis, the a2 axis, and the a3 axis are set to be offset by 120 ° in accordance with the arrangement of Si atoms.

The c-axis is set in the direction normal to the silicon surface with reference to the Si atom located at the center. The silicon surface is the (0001) surface. The carbon face is the (000-1) face.
The side surface of the hexagonal column includes six crystal planes along the closest atomic direction in a plan view of the silicon surface viewed from the c-axis direction. More specifically, the side surface of the hexagonal column includes six crystal planes each including the two closest Si atoms in a plan view of the silicon plane viewed from the c-axis direction.

The side surfaces of the hexagonal column are the (1-100) plane, the (0-110) plane, the (-1010) plane, and the (-1100) plane in the clockwise direction from the tip of the a1 axis in the plan view of the silicon plane viewed from the c-axis direction. ) Plane, (01-10) plane and (10-10) plane.
The diagonal planes along the diagonal lines of the hexagonal columns include six crystal planes along the intersecting direction that intersects the closest atomic direction in a plan view of the silicon surface viewed from the c-axis direction. More specifically, the diagonal surface of the hexagonal column includes six crystal planes each including two Si atoms that are not closest to each other in a plan view of the silicon surface viewed from the c-axis direction. When viewed with the Si atom located at the center as a reference, the intersecting direction of the closest atom direction is an orthogonal direction orthogonal to the closest atom direction.

The diagonal surface of the hexagonal prism is a (11-20) plane, a (1-210) plane, a (-2110) plane, a (-1-120) plane, and a ( -12-10) plane and (2-1-10) plane are included.
The crystal direction of the unit cell is defined by the normal direction of the crystal plane. The normal direction of the (1-100) plane is the [1-100] direction. The normal direction of the (0-110) plane is the [0-110] direction. The normal direction of the (-1010) plane is the [-1010] direction. The normal direction of the (-1100) plane is the [-1100] direction. The normal direction of the (01-10) plane is the [01-10] direction. The normal direction of the (10-10) plane is the [10-10] direction.

  The normal direction of the (11-20) plane is the [11-20] direction. The normal direction of the (1-210) plane is the [1-210] direction. The normal direction of the (-2110) plane is the [-2110] direction. The normal line direction of the (-1-120) plane is the [-1-120] direction. The normal direction of the (-12-10) plane is the [-12-10] direction. The normal direction of the (2-1-10) plane is the [2-1-10] direction.

The hexagonal crystal has 6-fold symmetry, and an equivalent crystal plane and an equivalent crystal orientation exist every 60 °. For example, the (1-100) plane, the (0-110) plane, the (-1010) plane, the (-1100) plane, the (01-10) plane, and the (10-10) plane form equivalent crystal planes. ing.
Further, the [1-100] direction, the [0-110] direction, the [-1010] direction, the [-1100] direction, the [01-10] direction, and the [10-10] direction form equivalent crystal directions. ing. Further, the [11-20] direction, the [1-210] direction, the [-2110] direction, the [-1-120] direction, the [-12-10] direction, and the [2-1-10] direction are equivalent. It forms the crystal direction.

The c-axis is the [0001] direction ([000-1] direction). The a1 axis is in the [2-1-10] direction ([-2110] direction). The a2 axis is in the [-12-10] direction ([1-210] direction). The a3 axis is in the [-1-120] direction ([11-20] direction).
The (0001) plane and the (000-1) plane are collectively referred to as the c-plane. The [0001] direction and the [000-1] direction are collectively referred to as the c-axis direction. The (11-20) plane and the (-1-120) plane are collectively referred to as the a plane. The [11-20] direction and the [-1-120] direction are collectively referred to as the a-axis direction. The (1-100) plane and the (-1100) plane are collectively referred to as the m-plane. The [1-100] direction and the [-1100] direction are collectively referred to as the m-axis direction.

FIG. 3 is a perspective view of the SiC semiconductor device 1 according to the first embodiment of the present invention viewed from one angle, and is a perspective view showing a first example of the reforming lines 22A to 22D. FIG. 4 is a perspective view of the SiC semiconductor device 1 shown in FIG. 3 viewed from another angle.
FIG. 5 is an enlarged view of the area V shown in FIG. FIG. 6 is an enlarged view of the area VI shown in FIG. FIG. 7 is a plan view of SiC semiconductor device 1 shown in FIG. FIG. 8 is a sectional view taken along the line VIII-VIII shown in FIG. 7.

Referring to FIGS. 3 to 8, SiC semiconductor device 1 includes a SiC semiconductor layer 2. The SiC semiconductor layer 2 includes 4H—SiC single crystal as an example of a hexagonal SiC single crystal. The SiC semiconductor layer 2 (SiC semiconductor chip) is formed in a rectangular parallelepiped chip shape.
The SiC semiconductor layer 2 has a first main surface 3 on one side, a second main surface 4 on the other side, and side surfaces 5A, 5B, 5C, 5D connecting the first main surface 3 and the second main surface 4. is doing. The first main surface 3 and the second main surface 4 are formed in a quadrangular shape (square shape in this embodiment) in a plan view (hereinafter, simply referred to as “plan view”) viewed from their normal direction Z. ..

The first main surface 3 is an element formation surface on which a semiconductor element is formed. Second main surface 4 of SiC semiconductor layer 2 is a ground surface having a grinding mark. Side surfaces 5A to 5D are each a smooth cleavage plane facing the crystal plane of the SiC single crystal. The side surfaces 5A to 5D have no grinding marks.
The thickness TL of the SiC semiconductor layer 2 may be 40 μm or more and 200 μm or less. The thickness TL may be 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, 80 μm or more and 100 μm or less, 100 μm or more and 120 μm or less, 120 μm or more and 140 μm or less, 140 μm or more and 160 μm or less, 160 μm or more and 180 μm or less, or 180 μm or more and 200 μm or less. The thickness TL is preferably 60 μm or more and 150 μm or less.

In this embodiment, the first main surface 3 and the second main surface 4 face the c-plane of the SiC single crystal. The first main surface 3 faces the (0001) surface (silicon surface). Second main surface 4 faces the (000-1) plane (carbon surface) of the SiC single crystal.
The first main surface 3 and the second main surface 4 have an off-angle θ that is inclined with respect to the c-plane of the SiC single crystal at an angle of 10 ° or less in the [11-20] direction. The normal direction Z is inclined by the off angle θ with respect to the c-axis ([0001] direction) of the SiC single crystal.

  The off angle θ may be 0 ° or more and 5.0 ° or less. The off angle θ is 0 ° or more and 1.0 ° or less, 1.0 ° or more and 1.5 ° or less, 1.5 ° or more and 2.0 ° or less, 2.0 ° or more and 2.5 ° or less, 2.5. ° to 3.0 °, 3.0 ° to 3.5 °, 3.5 ° to 4.0 °, 4.0 ° to 4.5 ° or 4.5 ° to 5.0 ° It may be set within the following range of angles. The off angle θ preferably exceeds 0 °. The off angle θ may be less than 4.0 °.

The off angle θ may be set in a range of an angle of 3.0 ° or more and 4.5 ° or less. In this case, it is preferable that the off-angle θ is set in a range of 3.0 ° or more and 3.5 ° or less, or 3.5 ° or more and 4.0 ° or less.
The off angle θ may be set in a range of an angle of 1.5 ° or more and 3.0 ° or less. In this case, it is preferable that the off angle θ is set in the range of an angle of 1.5 ° or more and 2.0 ° or less, or 2.0 ° or more and 2.5 ° or less.

  The length of each of the side surfaces 5A to 5D may be 0.5 mm or more and 10 mm or less. The surface areas of the side faces 5A to 5D are equal to each other in this form. When the first main surface 3 and the second main surface 4 are formed in a rectangular shape in plan view, the surface areas of the side surfaces 5A and 5C may be different from the surface areas of the side surfaces 5B and 5D. The surface areas of the side surfaces 5A and 5C may be smaller than the surface areas of the side surfaces 5B and 5D, or may be larger than the surface areas of the side surfaces 5B and 5D.

In this embodiment, the side surface 5A and the side surface 5C extend along the first direction X and face each other in the second direction Y intersecting the first direction X. In this embodiment, the side surface 5B and the side surface 5D extend along the second direction Y and face each other in the first direction X. The second direction Y is more specifically a direction orthogonal to the first direction X.
In this embodiment, the first direction X is set to the m-axis direction ([1-100] direction) of the SiC single crystal. The second direction Y is set in the a-axis direction ([11-20] direction) of the SiC single crystal.

Side surface 5A and side surface 5C are formed by the a-plane of the SiC single crystal and face each other in the a-axis direction. The side surface 5A is formed by the (-1-120) plane of the SiC single crystal. The side surface 5C is formed by the (11-20) plane of the SiC single crystal.
Side surface 5B and side surface 5D are formed by the m-plane of the SiC single crystal and face each other in the m-axis direction. Side surface 5B is formed by the (-1100) plane of the SiC single crystal. Side surface 5D is formed by the (1-100) plane of the SiC single crystal.

The side surfaces 5A and 5C are inclined with respect to the normal to the c-axis direction ([0001] direction) of the SiC single crystal with respect to the normal to the first main surface 3 of the SiC semiconductor layer 2. You may form the surface.
In this case, side surface 5A and side surface 5C have an off angle θ with respect to the normal line of first main surface 3 of SiC semiconductor layer 2 when the normal line of first main surface 3 of SiC semiconductor layer 2 is 0 °. It may be inclined at a corresponding angle. The angle according to the off angle θ may be equal to the off angle θ, or may be an angle larger than 0 ° and smaller than the off angle θ.

On the other hand, side surface 5B and side surface 5D extend in a plane along the normal line of first main surface 3 of SiC semiconductor layer 2. More specifically, the side surface 5B and the side surface 5D are formed substantially perpendicular to the first main surface 3 and the second main surface 4.
In this embodiment, the SiC semiconductor layer 2 has a laminated structure including an n ⁺ type SiC semiconductor substrate 6 (second impurity region) and an n type SiC epitaxial layer 7 (first impurity region). The second main surface 4 of the SiC semiconductor layer 2 is formed by the SiC semiconductor substrate 6.

The SiC epitaxial layer 7 forms the first main surface 3 of the SiC semiconductor layer 2. Side surfaces 5A to 5D of SiC semiconductor layer 2 are formed by SiC semiconductor substrate 6 and SiC epitaxial layer 7.
The SiC epitaxial layer 7 has an n-type impurity concentration equal to or lower than the n-type impurity concentration of the SiC semiconductor substrate 6. More specifically, the n-type impurity concentration of SiC epitaxial layer 7 is less than the n-type impurity concentration of SiC semiconductor substrate 6. The n-type impurity concentration of the SiC semiconductor substrate 6 may be 1.0 × 10 ¹⁸ cm ⁻³ or more and 1.0 × 10 ²¹ cm ⁻³ or less. The SiC epitaxial layer 7 may have an n-type impurity concentration of 1.0 × 10 ¹⁵ cm ⁻³ or more and 1.0 × 10 ¹⁸ cm ⁻³ or less.

  The thickness TS of the SiC semiconductor substrate 6 may be 40 μm or more and 150 μm or less. The thickness TS is 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, 90 μm or more and 100 μm or less, 100 μm or more 110 μm or less, 110 μm or more 120 μm or less, 120 μm or more and 130 μm or less, It may be 130 μm or more and 140 μm or less or 140 μm or more and 150 μm or less. The thickness TS is preferably 40 μm or more and 130 μm or less. By thinning the SiC semiconductor substrate 6, the resistance value can be reduced by shortening the current path.

  The thickness TE of the SiC epitaxial layer 7 may be 1 μm or more and 50 μm or less. The thickness TE is 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more, 35 μm or more 40 μm or less, 40 μm or more and 45 μm or less, or It may be 45 μm or more and 50 μm or less. The thickness TE is preferably 5 μm or more and 15 μm or less.

An active region 8 and an outer region 9 are set in the SiC semiconductor layer 2. The active region 8 is a region in which a Schottky barrier diode D, which is an example of a semiconductor element, is formed. The outer region 9 is a region outside the active region 8.
Active region 8 is set in the central portion of SiC semiconductor layer 2 with a space from the side surfaces 5A to 5D of SiC semiconductor layer 2 to the inner region in plan view. Active region 8 is set in a rectangular shape having four sides parallel to side surfaces 5A to 5D of SiC semiconductor layer 2 in a plan view.

The outer region 9 is set in a region between the side surfaces 5A to 5D of the SiC semiconductor layer 2 and the peripheral edge of the active region 8. The outer region 9 is set to have an endless shape (square ring shape in this embodiment) that surrounds the active region 8 in a plan view.
Main surface insulating layer 10 is formed on first main surface 3 of SiC semiconductor layer 2. The main surface insulating layer 10 selectively covers the active region 8 and the outer region 9. The main surface insulating layer 10 may have a single layer structure made of a silicon oxide (SiO ₂ ) layer or a silicon nitride (SiN) layer.

The main surface insulating layer 10 may have a laminated structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed on the silicon nitride layer. The silicon nitride layer may be formed on the silicon oxide layer. The main surface insulating layer 10 has a single layer structure made of a silicon oxide layer in this embodiment.
Main surface insulating layer 10 has insulating side surfaces 11A, 11B, 11C and 11D exposed from side surfaces 5A to 5D of SiC semiconductor layer 2. The insulating side surfaces 11A to 11D are continuous with the side surfaces 5A to 5D. The insulating side surfaces 11A to 11D are formed flush with the side surfaces 5A to 5D. The insulating side surfaces 11A to 11D are cleaved surfaces.

The thickness of the main surface insulating layer 10 may be 1 μm or more and 50 μm or less. The thickness of the main surface insulating layer 10 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.
A first principal surface electrode layer 12 is formed on the principal surface insulating layer 10. The first principal surface electrode layer 12 is formed in the central portion of the SiC semiconductor layer 2 with a space from the side surfaces 5A to 5D of the SiC semiconductor layer 2 to the inner region in a plan view.

A passivation layer 13 (insulating layer) is formed on the main surface insulating layer 10. The passivation layer 13 may have a single layer structure including a silicon oxide layer or a silicon nitride layer.
The passivation layer 13 may have a laminated structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed on the silicon nitride layer. The silicon nitride layer may be formed on the silicon oxide layer. In this embodiment, the passivation layer 13 has a single layer structure made of a silicon nitride layer.

The side surfaces 14A, 14B, 14C, 14D of the passivation layer 13 are formed in a space from the side surfaces 5A-5D of the SiC semiconductor layer 2 to the inner region in a plan view. The passivation layer 13 exposes the peripheral portion of the first main surface 3 of the SiC semiconductor layer 2 in a plan view. The passivation layer 13 exposes the main surface insulating layer 10.
A subpad opening 15 is formed in the passivation layer 13 to expose a part of the first principal surface electrode layer 12 as a pad region. Sub-pad opening 15 is formed in a square shape having four sides parallel to side surfaces 5A to 5D of SiC semiconductor layer 2 in a plan view.

The thickness of the passivation layer 13 may be 1 μm or more and 50 μm or less. The thickness of the passivation layer 13 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.
A resin layer 16 (insulating layer) is formed on the passivation layer 13. The passivation layer 13 and the resin layer 16 form one insulating laminated structure (insulating layer). In FIG. 7, the resin layer 16 is shown by hatching.

The resin layer 16 may include a negative type or positive type photosensitive resin. In this form, the resin layer 16 contains polybenzoxazole as an example of a positive type photosensitive resin. The resin layer 16 may include polyimide as an example of a negative type photosensitive resin.
The resin side surfaces 17A, 17B, 17C, 17D of the resin layer 16 are formed at intervals from the side surfaces 5A to 5D of the SiC semiconductor layer 2 to the inner region in a plan view. The resin layer 16 exposes the peripheral portion of the first main surface 3 of the SiC semiconductor layer 2 in a plan view. The resin layer 16 exposes the main surface insulating layer 10 together with the passivation layer 13. In this embodiment, the resin side surfaces 17A to 17D of the resin layer 16 are flush with the side surfaces 14A to 14D of the passivation layer 13.

The resin side surfaces 17A to 17D of the resin layer 16 are portions that define the dicing streets when the SiC semiconductor device 1 is cut out from one SiC semiconductor wafer. In this form, the side surfaces 14A to 14D of the passivation layer 13 are also the portions that define the dicing streets.
By exposing the peripheral portion of the first main surface 3 of the SiC semiconductor layer 2 from the resin layer 16 and the passivation layer 13, it is not necessary to physically cut the resin layer 16 and the passivation layer 13. Thereby, the SiC semiconductor device 1 can be smoothly cut out from one SiC semiconductor wafer. Moreover, the insulation distance from the side surfaces 5A to 5D of the SiC semiconductor layer 2 can be increased.

  The distance between the side surfaces 5A to 5D and the resin side surfaces 17A to 17D (side surfaces 14A to 14D) may be 1 μm or more and 25 μm or less. The distance between the side surfaces 5A to 5D and the resin side surfaces 17A to 17D (side surfaces 14A to 14D) is 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, or 20 μm or more and 25 μm or less. Good. Of course, the side surfaces 14A to 14D of the passivation layer 13 may be formed flush with the side surfaces 5A to 5D of the SiC semiconductor layer 2.

A pad opening 18 is formed in the resin layer 16 to expose a part of the first principal surface electrode layer 12 as a pad region. The pad opening 18 is formed in a quadrangular shape having four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2 in a plan view.
The pad opening 18 communicates with the sub pad opening 15. The inner wall of the pad opening 18 is formed flush with the inner wall of the subpad opening 15. The inner wall of pad opening 18 may be located on the side surfaces 5A to 5D of SiC semiconductor layer 2 with respect to the inner wall of subpad opening 15. The inner wall of pad opening 18 may be located in the inner region of SiC semiconductor layer 2 with respect to the inner wall of subpad opening 15. The resin layer 16 may cover the inner wall of the subpad opening 15.

The thickness of the resin layer 16 may be 1 μm or more and 50 μm or less. The thickness of the resin layer 16 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.
Second main surface electrode layer 19 is formed on second main surface 4 of SiC semiconductor layer 2. The second principal surface electrode layer 19 forms an ohmic contact with the second principal surface 4 (SiC semiconductor substrate 6) of the SiC semiconductor layer 2.

A plurality of reforming lines 22A to 22D (reforming layers) are formed on the side surfaces 5A to 5D of the SiC semiconductor layer 2. The reforming lines 22A to 22D are the reforming line 22A formed on the side surface 5A, the reforming line 22B formed on the side surface 5B, the reforming line 22C formed on the side surface 5C, and the reforming line formed on the side surface 5D. Includes quality line 22D.
The reforming lines 22A and 22C are formed on the a-plane of the SiC single crystal, and the reforming lines 22B and 22D are formed on the m-plane of the SiC single crystal. The reforming line 22A is formed on the side surface 5A by one layer or a plurality of layers (two or more layers, two layers in this embodiment). The reforming line 22C is formed on the side surface 5C by one layer or a plurality of layers (two or more layers, two layers in this embodiment).

The reforming line 22B is formed in one layer or a plurality of layers (two or more layers, one layer in this embodiment) on the side surface 5B. The reforming line 22D is formed as one layer or a plurality of layers (two or more layers; one layer in this embodiment) on the side surface 5D. The number of the reforming lines 22B and 22D is preferably less than the number of the reforming lines 22A and 22C.
The modification lines 22A to 22D include a layered region in which a part of the SiC single crystal forming the side surfaces 5A to 5D is modified to have a property different from that of the SiC single crystal. The modification lines 22A to 22D include regions modified to have properties such as density, refractive index, mechanical strength (crystal strength), or other physical properties different from those of the SiC single crystal.

  The modification lines 22A to 22D may include at least one layer of a melt-recuring layer, a defect layer, a dielectric breakdown layer, or a refractive index changing layer. The melt-rehardened layer is a layer in which a part of the SiC semiconductor layer 2 is melted and then hardened again. The defect layer is a layer including voids and cracks formed in the SiC semiconductor layer 2. The dielectric breakdown layer is a layer in which a part of the SiC semiconductor layer 2 has undergone dielectric breakdown. The refractive index variable layer is a layer in which a part of the SiC semiconductor layer 2 has a refractive index different from that of the SiC single crystal.

The modification lines 22A to 22D extend in a strip shape along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. The tangential direction of the first main surface 3 is a direction orthogonal to the normal direction Z. The tangential direction includes a first direction X (m-axis direction of SiC single crystal) and a second direction Y (a-axis direction of SiC single crystal).
The plurality of reforming lines 22A are each formed in a strip shape extending linearly along the m-axis direction on the side surface 5A. The plurality of reforming lines 22A are formed so as to be displaced from each other in the normal direction Z. The plurality of reforming lines 22A may be formed at intervals in the normal direction Z. The plurality of reforming lines 22A may overlap each other in the normal direction Z.

The plurality of reforming lines 22A each have a thickness TR in the normal direction Z. The thicknesses TR of the plurality of reforming lines 22A may be equal to or different from each other. The total thickness Tall of the reforming lines 22A is determined by the total value of the thicknesses TR of the plurality of reforming lines 22A.
The one-layer reforming line 22B is formed in a strip shape linearly extending along the a-axis direction on the side surface 5B. The one-layer modified line 22B has a thickness TR in the normal direction Z. The total thickness Tall of the reforming line 22B is determined by the thickness TR of the one-layer reforming line 22B.

Of course, a plurality of reforming lines 22B may be formed on the side surface 5B. In this case, the plurality of reforming lines 22B are formed so as to deviate from each other in the normal direction Z. The plurality of reforming lines 22B may be formed at intervals in the normal direction Z. The plurality of reforming lines 22B may overlap each other in the normal direction Z.
The thicknesses TR of the plurality of reforming lines 22B may be equal to or different from each other. The total thickness Tall of the reforming lines 22B is determined by the total value of the thicknesses TR of the plurality of reforming lines 22B.

The plurality of reforming lines 22C are each formed in a strip shape that linearly extends along the m-axis direction on the side surface 5C. The plurality of reforming lines 22C are formed so as to be offset from each other in the normal direction Z. The plurality of reforming lines 22C may be formed at intervals in the normal direction Z. The plurality of reforming lines 22C may overlap each other in the normal direction Z.
The plurality of reforming lines 22C each have a thickness TR in the normal direction Z. The thicknesses TR of the plurality of reforming lines 22C may be equal to or different from each other. The total thickness Tall of the reforming lines 22C is determined by the total value of the thicknesses TR of the plurality of reforming lines 22C.

The one-layer reforming line 22D is formed in a strip shape extending linearly along the a-axis direction on the side surface 5D. The one-layer reforming line 22D has a thickness TR in the normal direction Z. The total thickness Tall of the reforming line 22D is determined by the thickness TR of the one-layer reforming line 22D.
Of course, a plurality of reforming lines 22D may be formed on the side surface 5D. In this case, the plurality of reforming lines 22D are formed so as to be offset from each other in the normal direction Z. The plurality of reforming lines 22D may be formed at intervals in the normal direction Z. The plurality of reforming lines 22D may overlap each other in the normal direction Z.

The thicknesses TR of the plurality of reforming lines 22D may be equal to or different from each other. The total thickness Tall of the reforming lines 22D is determined by the total value of the thicknesses TR of the plurality of reforming lines 22D.
The thicknesses TR of the reforming lines 22A to 22D may be equal to each other or different from each other. The total thickness Tall of the reforming lines 22A and 22C may be equal to each other or different from each other. The total thickness Tall of the reforming lines 22B and 22D may be equal to each other or different from each other.

The total thickness Tall of the modified lines 22A to 22D is preferably equal to or less than the thickness TL of the SiC semiconductor layer 2 (TR ≦ TL). The total thickness Tall is more preferably less than the thickness TS of the SiC semiconductor substrate 6 (TR <TS). The total thickness Tall may be equal to or more than the thickness TE of the SiC epitaxial layer 7 (TR ≧ TE).
The ratio Tall / TL of the total thickness Tall to the thickness TL of the SiC semiconductor layer 2 is preferably 0.1 or more and less than 1.0, respectively. The ratio Tall / TL is 0.1 or more and 0.2 or less, 0.2 or more and 0.4 or less, 0.4 or more and 0.6 or less, 0.6 or more and 0.8 or less, or 0.8 or more and less than 1.0. May be

The ratio Tall / TL is 0.1 to 0.2, 0.2 to 0.3, 0.3 to 0.4, 0.4 to 0.5, 0.5 to 0. It may be 6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, or 0.9 or more and less than 1.0. The ratio Tall / TL is preferably 0.2 or more and 0.5 or less, respectively.
The ratio Tall / TS of the total thickness Tall to the thickness TS of the SiC semiconductor substrate 6 is more preferably 0.1 or more and less than 1.0, respectively. The ratio Tall / TS is 0.1 or more and 0.2 or less, 0.2 or more and 0.4 or less, 0.4 or more and 0.6 or less, 0.6 or more and 0.8 or less, or 0.8 or more and 1. It may be less than zero.

The ratio Tall / TS is 0.1 to 0.2, 0.2 to 0.3, 0.3 to 0.4, 0.4 to 0.5, 0.5 to 0. It may be 6 or less, 0.6 or more and 0.7 or less, 0.7 or more and 0.8 or less, 0.8 or more and 0.9 or less, or 0.9 or more and less than 1.0. The ratio Tall / TS is preferably 0.2 or more and 0.5 or less, respectively.
The reforming lines 22A to 22D are formed at a distance from the first main surface 3 to the second main surface 4 of the SiC semiconductor layer 2. The reforming lines 22A to 22D expose the surface layer portion of the first main surface 3 of the SiC semiconductor layer 2 from the side surfaces 5A to 5D. That is, the modified lines 22A to 22D are not formed in the main surface insulating layer 10, the passivation layer 13 and the resin layer 16.

The modified lines 22A to 22D are formed at a distance from the second main surface 4 of the SiC semiconductor layer 2 to the first main surface 3. The reforming lines 22A to 22D expose the surface layer portion of the second main surface 4 of the SiC semiconductor layer 2 from the side surfaces 5A to 5D.
The reforming lines 22A to 22D are formed on the SiC semiconductor substrate 6. The reforming lines 22A to 22D are formed at a distance from the boundary between the SiC semiconductor substrate 6 and the SiC epitaxial layer 7 to the second main surface 4. The reforming lines 22A to 22D expose the SiC epitaxial layer 7 in the surface layer portion of the first main surface 3 of the SiC semiconductor layer 2.

The reforming line 22A and the reforming line 22B may be connected to each other at a corner connecting the side surface 5A and the side surface 5B in the SiC semiconductor layer 2. The reforming line 22B and the reforming line 22C may be continuous with each other at a corner portion connecting the side surface 5B and the side surface 5C in the SiC semiconductor layer 2.
The reforming line 22C and the reforming line 22D may be connected to each other at a corner connecting the side surface 5C and the side surface 5D in the SiC semiconductor layer 2. The reforming line 22D and the reforming line 22A may be connected to each other at a corner connecting the side surface 5D and the side surface 5A in the SiC semiconductor layer 2.

The reforming lines 22A to 22D may be integrally formed so as to surround the SiC semiconductor layer 2. That is, the reforming lines 22A to 22D may form one endless (annular) reforming line that surrounds the SiC semiconductor layer 2 on the side surfaces 5A to 5D of the SiC semiconductor layer 2.
The reforming lines 22A to 22D are formed on the side surfaces 5A to 5D of the SiC semiconductor layer 2 with different occupation ratios RA, RB, RC, RD. The occupation ratio RA is a ratio of the reforming line 22A to the side surface 5A. The occupation rate RB is a rate occupied by the reforming line 22B on the side surface 5B. The occupation ratio RC is a ratio of the reforming line 22C to the side surface 5C. The occupation ratio RD is the ratio of the reforming line 22D to the side surface 5D.

  More specifically, the occupation ratios RA to RD differ depending on the crystal plane of the SiC single crystal. The occupation rates RB, RD of the reforming lines 22B, 22D formed on the m-plane of the SiC single crystal are equal to or lower than the occupation rates RA, RC of the reforming lines 22A, 22C formed on the a-plane of the SiC single crystal (RB, RD ≦ RA, RC). More specifically, the occupation rates RB and RD are less than the occupation rates RA and RC (RB, RD <RA, RC).

The occupation rates RA and RC of the reforming lines 22A and 22C may be equal to each other or may be different from each other. The occupation rates RB and RD of the reforming lines 22B and 22D may be equal to each other or may be different from each other.
The occupation ratios RA to RD are adjusted by the number of the reforming lines 22A to 22D, the total thickness Tall, the total surface area, and the like. In this embodiment, as an example, the occupation ratios RA to RD (total thickness Tall and total surface area) of the reforming lines 22A to 22D are adjusted by adjusting the number of the reforming lines 22A to 22D each having the same thickness TR. I am adjusting.

That is, the number of the reforming lines 22B and 22D is less than the number of the reforming lines 22A and 22C, respectively. Further, the total thickness Tall of the reforming lines 22B and 22D is less than the total thickness Tall of the reforming lines 22A and 22C, respectively. The total surface area of the reforming lines 22B and 22D is less than the total surface area of the reforming lines 22A and 22C, respectively.
These are structures in which the occupancy ratios RB, RD of the reforming lines 22B, 22D are made less than the occupancy ratios RA, RC of the reforming lines 22A, 22C by a relatively simple design.

Under the condition that the occupation ratios RB and RD are less than the occupation ratios RA and RC, the number of the reforming lines 22B and 22D may be set to be equal to or more than the number of the reforming lines 22A and 22C, respectively. The thickness TR of the reforming lines 22B and 22D may be set to be greater than or equal to the thickness TR of the reforming lines 22A and 22C, respectively, under the condition that the occupancy ratios RB and RD are less than the occupancy ratios RA and RC. ..
With reference to FIG. 5, the reforming line 22A includes a plurality of a-plane reforming portions 28 (reforming portions). In other words, the reforming line 22A is formed by an assembly of a plurality of a-plane reforming portions 28. The plurality of a-plane modified portions 28 are portions where the SiC single crystal exposed from the side surface 5A is modified to have a property different from that of the SiC single crystal. The region around each a-plane modified portion 28 on the side surface 5A may be modified to have a property different from that of the SiC single crystal.

The plurality of a-plane modifying portions 28 connect one end portion 28a located on the first main surface 3 side, the other end portion 28b located on the second main surface 4 side, and one end portion 28a and the other end portion 28b. Each includes a connection portion 28c.
The plurality of a-plane modified portions 28 are each formed in a linear shape extending in the normal direction Z. As a result, the plurality of a-plane modified portions 28 are formed in a striped shape as a whole. The plurality of a-plane reforming portions 28 may include a plurality of a-plane reforming portions 28 formed in a tapered shape in which the width in the m-axis direction narrows from the one end portion 28a side to the other end portion 28b side.

  The plurality of a-plane modified portions 28 are formed at intervals in the m-axis direction so as to face each other in the m-axis direction. The plurality of a-plane modified portions 28 may overlap each other in the m-axis direction. A strip-shaped region extending in the m-axis direction is formed by a line connecting one ends 28a of the plurality of a-plane reforming portions 28 and a line connecting the other ends 28b of the plurality of a-plane reforming portions 28. The reforming line 22A is formed by this strip-shaped region.

The plurality of a-plane modified portions 28 may each have a notch formed by notching the side surface 5A. The plurality of a-plane modified portions 28 may respectively form recesses recessed from the side surface 5A in the a-axis direction. The plurality of a-plane modified portions 28 may be formed in a dot shape (dot shape) according to the length in the normal direction Z and the width in the m-axis direction.
In the m-axis direction, the pitch PR between the central portions of the plurality of a-plane modified portions 28 adjacent to each other may be more than 0 μm and 20 μm or less. The pitch PR may be more than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less.

In the m-axis direction, the width WR of each a-plane modified portion 28 may be more than 0 μm and 20 μm or less. The width WR may be more than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less.
The reforming line 22C has the same structure as the reforming line 22A except that it is formed on the side surface 5C. The description of the reforming line 22A is applied mutatis mutandis to the description of the reforming line 22C by replacing “side surface 5A” with “side surface 5C”.

  With reference to FIG. 6, the reforming line 22D includes a plurality of m-plane reforming units 29 (reforming units). In other words, the reforming line 22D is formed by an assembly of a plurality of m-plane reforming portions 29. The plurality of m-plane modified portions 29 are portions where the SiC single crystal exposed from the side surface 5D is modified to have a property different from that of the SiC single crystal. A region around each m-plane modified portion 29 on the side surface 5D may be modified to have a property different from that of the SiC single crystal.

The plurality of m-plane modified portions 29 connect the one end portion 29a located on the first principal surface 3 side, the other end portion 29b located on the second principal surface 4 side, and the one end portion 29a and the other end portion 29b. Each includes a connection portion 29c.
The plurality of m-plane modified portions 29 are each formed in a linear shape extending in the normal direction Z. As a result, the plurality of m-plane modified portions 29 are formed in stripes as a whole. The plurality of m-plane reforming portions 29 may include a plurality of m-plane reforming portions 29 formed in a tapered shape in which the width in the a-axis direction narrows from the one end portion 29a side to the other end portion 29b side.

  The plurality of m-plane modified portions 29 are formed at intervals in the a-axis direction so as to face each other in the a-axis direction. The plurality of m-plane modified portions 29 may overlap each other in the a-axis direction. A strip-shaped region extending in the a-axis direction is formed by a line connecting one ends 29a of the plurality of m-plane reforming portions 29 and a line connecting the other ends 29b of the plurality of m-plane reforming portions 29. The reforming line 22D is formed by this strip-shaped region.

Each of the m-plane modified portions 29 may have a cutout portion formed by cutting out the side surface 5D. The plurality of m-plane modified portions 29 may each form recesses recessed from the side surface 5D in the m-axis direction. The plurality of m-plane modified portions 29 may be formed in a dot shape (dot shape) according to the length in the normal direction Z and the width in the a-axis direction.
The pitch PR between the central portions of the plurality of m-plane modified portions 29 adjacent to each other in the a-axis direction may be 0 μm or more and 20 μm or less. The pitch PR may be 0 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less.

Regarding the a-axis direction, the width WR of each m-plane modified portion 29 may be more than 0 μm and 20 μm or less. The width WR may be more than 0 μm and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, or 15 μm or more and 20 μm or less.
The reforming line 22B has the same structure as the reforming line 22D except that it is formed on the side surface 5B. The description of the reforming line 22D is applied mutatis mutandis to the description of the reforming line 22B by replacing “side surface 5D” with “side surface 5B”.

  Referring to FIG. 8, in active region 8, an n-type diode region 35 is formed in the surface layer portion of first main surface 3 of SiC semiconductor layer 2. In this form, diode region 35 is formed in the central portion of first main surface 3 of SiC semiconductor layer 2. In this form, diode region 35 is set in a rectangular shape having four sides parallel to side surfaces 5A to 5D of SiC semiconductor layer 2 in a plan view.

  The n-type impurity concentration of diode region 35 may be equal to or higher than the n-type impurity concentration of SiC epitaxial layer 7. In this embodiment, the diode region 35 is formed by utilizing a part of the SiC epitaxial layer 7. The n-type impurity concentration of diode region 35 is equal to the n-type impurity concentration of SiC epitaxial layer 7. Diode region 35 may be formed by introducing an n-type impurity into the surface layer portion of SiC epitaxial layer 7.

In the outer region 9, a p ⁺ type guard region 36 is formed in the surface layer portion of the first main surface 3 of the SiC semiconductor layer 2. The guard region 36 is formed in a strip shape extending along the diode region 35 in a plan view.
More specifically, the guard region 36 is formed in an endless shape (for example, a square ring, a square ring with chamfered corners, or a circular ring) that surrounds the diode region 35 in a plan view. Thereby, the guard area 36 is formed as a guard ring area. The diode region 35 is defined by the guard region 36 in this form. The active area 8 is defined by the guard area 36.

The p-type impurity in the guard region 36 may not be activated. In this case, the guard region 36 is formed as a non-semiconductor region. The p-type impurity in the guard region 36 may be activated. In this case, the guard region 36 is formed as a p-type semiconductor region.
The above-mentioned main surface insulating layer 10 is formed on the first main surface 3 of the SiC semiconductor layer 2. A diode opening 37 exposing the diode region 35 is formed in the main surface insulating layer 10. The diode opening 37 exposes not only the diode region 35 but also the inner peripheral edge of the guard region 36. The diode opening 37 is formed in a square shape having four sides parallel to the side surfaces 5A to 5D of the SiC semiconductor layer 2 in a plan view.

The above-mentioned first main surface electrode layer 12 is formed on the main surface insulating layer 10. The first principal surface electrode layer 12 enters the diode opening 37 from above the insulating layer. The first principal surface electrode layer 12 is electrically connected to the diode region 35 in the diode opening 37.
More specifically, the first principal surface electrode layer 12 forms a Schottky junction with the diode region 35. As a result, a Schottky barrier diode D having the first principal surface electrode layer 12 as an anode and the diode region 35 as a cathode is formed. The passivation layer 13 and the resin layer 16 described above are formed on the main surface insulating layer 10.

FIG. 9 is a perspective view showing an SiC semiconductor wafer 41 used for manufacturing the SiC semiconductor device 1 shown in FIG.
The SiC semiconductor wafer 41 is a member that serves as a base for the SiC semiconductor substrate 6. The SiC semiconductor wafer 41 includes a 4H—SiC single crystal as an example of a hexagonal SiC single crystal. In this embodiment, the SiC semiconductor wafer 41 has an n-type impurity concentration corresponding to the n-type impurity concentration of the SiC semiconductor substrate 6.

The SiC semiconductor wafer 41 is formed in a plate shape or a disk shape. The SiC semiconductor wafer 41 may be formed in a disc shape. The SiC semiconductor wafer 41 has a first wafer main surface 42 on one side, a second wafer main surface 43 on the other side, and a wafer side surface 44 connecting the first wafer main surface 42 and the second wafer main surface 43. ing.
The thickness TW of the SiC semiconductor wafer 41 exceeds the thickness TS of the SiC semiconductor substrate 6 (TS <TW). The thickness TW of the SiC semiconductor wafer 41 is adjusted to the thickness TS of the SiC semiconductor substrate 6 by grinding.

  The thickness TW may be more than 150 μm and 750 μm or less. The thickness TW may be more than 150 μm and 300 μm or less, 300 μm or more and 450 μm or less, 450 μm or more and 600 μm or less, or 600 μm or more and 750 μm or less. Considering the grinding time of the SiC semiconductor wafer 41, the thickness TW is preferably more than 150 μm and 500 μm or less. The thickness TW is typically 300 μm or more and 450 μm or less.

The first wafer main surface 42 and the second wafer main surface 43 face the c-plane of the SiC single crystal in this embodiment. The first wafer main surface 42 faces the (0001) surface (silicon surface). The second wafer main surface 43 faces the (000-1) plane (carbon surface) of the SiC single crystal.
The first wafer main surface 42 and the second wafer main surface 43 have an off angle θ that is inclined at an angle of 10 ° or less in the [11-20] direction with respect to the c-plane of the SiC single crystal. The normal direction Z of the first wafer main surface 42 is inclined by the off angle θ with respect to the c-axis ([0001] direction) of the SiC single crystal.

  The off angle θ may be 0 ° or more and 5.0 ° or less. The off angle θ is 0 ° or more and 1.0 ° or less, 1.0 ° or more and 1.5 ° or less, 1.5 ° or more and 2.0 ° or less, 2.0 ° or more and 2.5 ° or less, 2.5. ° to 3.0 °, 3.0 ° to 3.5 °, 3.5 ° to 4.0 °, 4.0 ° to 4.5 ° or 4.5 ° to 5.0 ° It may be set within the following range of angles. The off angle θ preferably exceeds 0 °. The off angle θ may be less than 4.0 °.

The off angle θ may be set in a range of an angle of 3.0 ° or more and 4.5 ° or less. In this case, it is preferable that the off-angle θ is set in a range of 3.0 ° or more and 3.5 ° or less, or 3.5 ° or more and 4.0 ° or less.
The off angle θ may be set in a range of an angle of 1.5 ° or more and 3.0 ° or less. In this case, it is preferable that the off angle θ is set in the range of an angle of 1.5 ° or more and 2.0 ° or less, or 2.0 ° or more and 2.5 ° or less.

  The SiC semiconductor wafer 41 includes a first wafer corner portion 45 connecting the first wafer main surface 42 and the wafer side surface 44, and a second wafer corner portion 46 connecting the second wafer main surface 43 and the wafer side surface 44. The first wafer corner portion 45 has a first chamfered portion 47 that is inclined downward from the first wafer main surface 42 toward the wafer side surface 44. The second wafer corner portion 46 has a second chamfered portion 48 that is inclined downward from the second wafer main surface 43 toward the wafer side surface 44.

The first chamfered portion 47 may be formed in a convex curved shape. The second chamfered portion 48 may be formed in a convex curved shape. First chamfer 47 and second chamfer 48 suppress cracks in SiC semiconductor wafer 41.
On the wafer side surface 44 of the SiC semiconductor wafer 41, one orientation flat 49 is formed as an example of a mark indicating the crystal orientation of the SiC single crystal. The orientation flat 49 is a cutout portion formed on the wafer side surface 44 of the SiC semiconductor wafer 41. In this embodiment, the orientation flat 49 extends linearly along the a-axis direction ([11-20] direction) of the SiC single crystal.

On the wafer side surface 44 of the SiC semiconductor wafer 41, a plurality of (for example, two) orientation flats 49 indicating crystal orientations may be formed. The plurality (for example, two) of orientation flats 49 may include a first orientation flat and a second orientation flat.
The first orientation flat may be a notch extending linearly along the a-axis direction ([11-20] direction) of the SiC single crystal. The second orientation flat may be a cutout portion that linearly extends along the m-axis direction ([1-100] direction) of the SiC single crystal.

On the first main surface 42 of the SiC semiconductor wafer 41, a plurality of device formation regions 51 respectively corresponding to the SiC semiconductor device 1 are set. The plurality of device formation regions 51 are set in a matrix array with intervals in the m-axis direction ([1-100] direction) and the a-axis direction ([11-20] direction).
Each device formation region 51 has four sides 52A, 52B, 52C and 52D along the crystal orientation of the SiC single crystal. The four sides 52A to 52D correspond to the four side surfaces 5A to 5D of the SiC semiconductor layer 2, respectively. That is, the four sides 52A to 52D are two sides 52A and 52C along the m-axis direction ([1-100] direction) and two sides 52B and 52D along the a-axis direction ([11-20] direction). Including.

The plurality of device formation regions 51 are each partitioned by a grid-like planned cutting line 53 extending along the m-axis direction ([1-100] direction) and the a-axis direction ([11-20] direction). The planned cutting line 53 includes a plurality of first planned cutting lines 54 and a plurality of second planned cutting lines 55.
Each of the plurality of first cut lines 54 extends along the m-axis direction ([1-100] direction). Each of the plurality of second planned cutting lines 55 extends along the a-axis direction ([11-20] direction). After a predetermined structure is formed in the plurality of device formation regions 51, the plurality of SiC semiconductor devices 1 are cut out by cutting the SiC semiconductor wafer 41 along the planned cutting lines 53.

10A to 10M are cross-sectional views showing an example of a method for manufacturing the SiC semiconductor device 1 shown in FIG. In FIGS. 10A to 10M, for convenience of description, only the regions where the three SiC semiconductor devices 1 are formed are shown, and the other regions are not shown.
Referring to FIG. 10A, in manufacturing SiC semiconductor device 1, first, SiC semiconductor wafer 41 is prepared (see also FIG. 9). Next, the n-type SiC epitaxial layer 7 is formed on the first wafer main surface 42 of the SiC semiconductor wafer 41.

In the step of forming the SiC epitaxial layer 7, SiC is epitaxially grown from the first wafer main surface 42 of the SiC semiconductor wafer 41. The thickness TE of the SiC epitaxial layer 7 may be 1 μm or more and 50 μm or less.
Thereby, SiC semiconductor wafer structure 61 including SiC semiconductor wafer 41 and SiC epitaxial layer 7 is formed. The SiC semiconductor wafer structure 61 includes a first main surface 62 and a second main surface 63.

First main surface 62 and second main surface 63 of SiC semiconductor wafer structure 61 correspond to first main surface 3 and second main surface 4 of SiC semiconductor layer 2, respectively. The thickness TWS of the SiC semiconductor wafer structure 61 may be more than 150 μm and 800 μm or less. The thickness TWS is preferably more than 150 μm and 550 μm or less.
Next, referring to FIG. 10B, p ⁺ type guard region 36 is formed on first main surface 62 of SiC semiconductor wafer structure 61. The step of forming guard region 36 includes a step of selectively introducing a p-type impurity into the surface layer portion of first main surface 62 of SiC semiconductor wafer structure 61 through an ion implantation mask (not shown). More specifically, guard region 36 is formed in the surface layer portion of SiC epitaxial layer 7.

Guard region 36 partitions active region 8 and outer region 9 in SiC semiconductor wafer structure 61. An n-type diode region 35 is defined in a region (active region 8) surrounded by the guard region 36.
Diode region 35 may be formed by selectively introducing an n-type impurity into the surface layer portion of first main surface 62 of SiC semiconductor wafer structure 61 through an ion implantation mask (not shown).

Next, referring to FIG. 10C, main surface insulating layer 10 is formed on first main surface 62 of SiC semiconductor wafer structure 61. The main surface insulating layer 10 contains silicon oxide (SiO ₂ ). The main surface insulating layer 10 may be formed by a CVD (Chemical Vapor Deposition) method or an oxidation treatment method (for example, a thermal oxidation treatment method).
Next, referring to FIG. 10D, a mask 64 having a predetermined pattern is formed on main surface insulating layer 10. The mask 64 has a plurality of openings 65. The plurality of openings 65 respectively expose regions in the main surface insulating layer 10 where the diode openings 37 are to be formed.

Then, an unnecessary portion of main surface insulating layer 10 is removed by an etching method through mask 64. As a result, the diode opening 37 is formed in the main surface insulating layer 10. After forming the diode opening 37, the mask 64 is removed.
Next, referring to FIG. 10E, a base electrode layer 66 serving as a base of first main surface electrode layer 12 is formed on first main surface 62 of SiC semiconductor wafer structure 61. The base electrode layer 66 is formed over the entire first main surface 62 of the SiC semiconductor wafer structure 61 and covers the main surface insulating layer 10. The first principal surface electrode layer 12 may be formed by a vapor deposition method, a sputtering method or a plating method.

Next, referring to FIG. 10F, a mask 67 having a predetermined pattern is formed on base electrode layer 66. The mask 67 has an opening 68 that exposes a region of the base electrode layer 66 other than the region where the first principal surface electrode layer 12 is to be formed.
Then, an unnecessary portion of the base electrode layer 66 is removed by an etching method through the mask 67. As a result, the base electrode layer 66 is divided into the plurality of first main surface electrode layers 12. After forming the first main surface electrode layer 12, the mask 67 is removed.

Next, referring to FIG. 10G, passivation layer 13 is formed on first main surface 62 of SiC semiconductor wafer structure 61. The passivation layer 13 contains silicon nitride (SiN). The passivation layer 13 may be formed by a CVD method.
Next, referring to FIG. 10H, resin layer 16 is applied onto passivation layer 13. The resin layer 16 collectively covers the active region 8 and the outer region 9. The resin layer 16 may include polybenzoxazole as an example of a positive type photosensitive resin.

Next, referring to FIG. 10I, the resin layer 16 is selectively exposed and then developed. As a result, the pad opening 18 is formed in the resin layer 16. Further, the dicing streets 69 along the planned cutting line 53 (sides 52A to 52D of each device forming area 51) are partitioned into the resin layer 16.
Then, unnecessary portions of the passivation layer 13 are removed. The unnecessary portion of the passivation layer 13 may be removed by the etching method with the resin layer 16 interposed therebetween. As a result, the subpad opening 15 is formed in the passivation layer 13. Further, the dicing street 69 along the planned cutting line 53 is divided into the passivation layer 13.

In this embodiment, the step of removing the unnecessary portion of the passivation layer 13 using the resin layer 16 has been described. However, the resin layer 16 and the pad opening 18 may be formed after the subpad opening 15 is formed in the passivation layer 13.
In this case, prior to the step of forming the resin layer 16, an unnecessary portion of the passivation layer 13 is removed by an etching method using a mask, and the sub pad opening 15 is formed. According to this step, the passivation layer 13 can be formed into an arbitrary shape.

Next, referring to FIG. 10J, second main surface 63 of SiC semiconductor wafer structure 61 (second wafer main surface 43 of SiC semiconductor wafer 41) is ground. As a result, the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41) is thinned. Further, a grinding mark is formed on the second main surface 63 of the SiC semiconductor wafer structure 61.
The SiC semiconductor wafer structure 61 is ground to a thickness TWS corresponding to the thickness TL of the SiC semiconductor layer 2. The SiC semiconductor wafer structure 61 may be ground to a thickness TWS of 40 μm or more and 200 μm or less.

That is, the SiC semiconductor wafer 41 is ground until the thickness TW corresponds to the thickness TS of the SiC semiconductor substrate 6. The SiC semiconductor wafer 41 may be ground to a thickness TW of 40 μm or more and 150 μm or less.
Next, with reference to FIG. 10K, a plurality of reforming lines 70 (reforming layers) that are the bases of the reforming lines 22A to 22D are formed. In the step of forming the reforming line 70, the laser light irradiation device 71 irradiates the SiC semiconductor wafer structure 61 with pulsed laser light.

In this embodiment, the laser light is applied to the SiC semiconductor wafer structure 61 from the first main surface 62 side of the SiC semiconductor wafer structure 61 through the main surface insulating layer 10. The laser light may be directly applied to the SiC semiconductor wafer structure 61 from the second main surface 63 side of the SiC semiconductor wafer structure 61.
The condensing part (focus) of the laser light is set in the middle of the SiC semiconductor wafer structure 61 in the thickness direction. The irradiation position of the laser light on the SiC semiconductor wafer structure 61 is moved along the planned cutting line 53 (four sides 52A to 52D of each device formation region 51).

More specifically, the irradiation position of the laser light on the SiC semiconductor wafer structure 61 is moved along the first planned cutting line 54. The irradiation position of the laser light on the SiC semiconductor wafer structure 61 is moved along the second planned cutting line 55.
As a result, the SiC semiconductor wafer structure 61 extends in the middle of the thickness direction along the planned cutting line 53 (four sides 52A to 52D of each device formation region 51), and the crystalline state of the SiC single crystal is different from that of the other region. Form a plurality of reforming lines 70 having different properties.

The plurality of reforming lines 70 are formed one layer or a plurality of layers in a one-to-one correspondence with the four sides 52A to 52D of each device forming region 51. In this embodiment, two layers of reforming lines 70 are formed on the two sides 52A and 52C of each device forming area 51, and one layer of reforming line 70 is formed on the two sides 52B and 52D of each device forming area 51. Formed respectively.
The two reforming lines 70 along the sides 52A and 52C of the device forming region 51 include the a-plane reforming portions 28, respectively. The two reforming lines 70 along the sides 52B and 52D of the device forming region 51 include the m-plane reforming portion 29, respectively.

The plurality of modified lines 70 are also laser processing marks formed in the middle of the SiC semiconductor wafer structure 61 in the thickness direction. More specifically, the a-plane reforming portion 28 and the m-plane reforming portion 29 of the reforming line 70 are laser processing marks.
The condensing portion (focus) of laser light, laser energy, pulse duty ratio, irradiation speed, etc. are arbitrary depending on the position, size, shape, thickness, etc. of the reforming line 70 (reforming lines 22A to 22D) to be formed. Is determined by the value of.

Next, referring to FIG. 10L, second main surface electrode layer 19 is formed on second main surface 63 of SiC semiconductor wafer structure 61. The second principal surface electrode layer 19 may be formed by a vapor deposition method, a sputtering method or a plating method.
Prior to the step of forming second main surface electrode layer 19, annealing treatment may be performed on second main surface 63 (ground surface) of SiC semiconductor wafer structure 61. The annealing process may be performed by a laser annealing process method using a laser beam.

  According to the laser annealing method, the SiC single crystal in the surface layer portion of the second main surface 63 of the SiC semiconductor wafer structure 61 is modified to form a Si amorphous layer. In this case, SiC semiconductor device 1 having a Si amorphous layer on the surface layer portion of second main surface 4 of SiC semiconductor layer 2 is manufactured. On the second main surface 4 of the SiC semiconductor layer 2, grinding marks and Si amorphous layer coexist. According to the laser annealing method, the ohmic property of the second main surface electrode layer 19 with respect to the second main surface 4 of the SiC semiconductor layer 2 can be improved.

Next, referring to FIG. 10M, a plurality of SiC semiconductor devices 1 are cut out from SiC semiconductor wafer structure 61. In this step, a tape-shaped support member 73 is attached to the second main surface 63 side of the SiC semiconductor wafer structure 61.
Next, an external force is applied to the planned cutting line 53 from the second main surface 63 side of the SiC semiconductor wafer structure 61 via the support member 73. The external force on the planned cutting line 53 may be applied by a pressing member such as a blade.

In another form, the support member 73 may be attached to the first main surface 62 side of the SiC semiconductor wafer structure 61. In this case, an external force may be applied to the scheduled cutting line 53 from the first main surface 62 side of the SiC semiconductor wafer structure 61 via the support member 73. The external force may be applied by a pressing member such as a blade.
In still another form, a stretchable support member 73 may be attached to the first main surface 62 side or the second main surface 63 side of the SiC semiconductor wafer structure 61. In this case, SiC semiconductor wafer structure 61 may be cleaved by stretching elastic support member 73 in the m-axis direction and the a-axis direction.

When cleaving SiC semiconductor wafer structure 61 using supporting member 73, it is preferable that supporting member 73 be attached to second main surface 63 side of SiC semiconductor wafer structure 61 with few obstacles.
In this way, the SiC semiconductor wafer structure 61 is cleaved from the reforming line 70 (reforming lines 22A to 22D) along the planned cutting line 53, and the plurality of SiC semiconductor devices 1 are one SiC semiconductor wafer structure. 61 (SiC semiconductor wafer 41) is cut out.

  The portion of the reforming line 70 along the side 52A of each device forming region 51 becomes the reforming line 22A. The portion of the reforming line 70 along the side 52B of each device forming region 51 becomes the reforming line 22B. The portion of the reforming line 70 along the side 52C of each device forming region 51 becomes the reforming line 22C. The portion of the reforming line 70 along the side 52D of each device forming region 51 becomes the reforming line 22D. The SiC semiconductor device 1 is manufactured through the steps including the above.

  In this embodiment, the step of grinding SiC semiconductor wafer structure 61 (FIG. 10J) is performed prior to the step of forming reforming line 70 (reforming lines 22A to 22D) (FIG. 10K). However, the step of grinding the SiC semiconductor wafer structure 61 (FIG. 10J) is performed at any timing after the step of preparing the SiC semiconductor wafer 41 (FIG. 10A) and before the step of forming the second main surface electrode layer 19 (FIG. 10L). Can be implemented in.

For example, the step of grinding SiC semiconductor wafer structure 61 (FIG. 10J) may be performed prior to the step of forming SiC epitaxial layer 7 (FIG. 10A). Further, the step of grinding SiC semiconductor wafer structure 61 (FIG. 10J) may be performed after the step of forming reforming line 70 (reforming lines 22A to 22D) (FIG. 10K).
In addition, in the grinding step (FIG. 10J) of the SiC semiconductor wafer structure 61, after the step of preparing the SiC semiconductor wafer 41 (FIG. 10A), the step of forming the reforming line 70 (reforming lines 22A to 22D) (FIG. 10K) is performed. It may be implemented in multiple times at any previous timing. The step of grinding the SiC semiconductor wafer structure 61 (FIG. 10J) is performed at any timing after the step of preparing the SiC semiconductor wafer 41 (FIG. 10A) and before the step of forming the second principal surface electrode layer 19 (FIG. 10L). May be carried out in multiple times.

FIG. 11 is a perspective view showing the semiconductor package 74 incorporating the SiC semiconductor device 1 shown in FIG. 3 through the sealing resin 79.
With reference to FIG. 11, the semiconductor package 74 is a so-called TO-220 type in this embodiment. The semiconductor package 74 includes the SiC semiconductor device 1, a pad portion 75, a heat sink 76, a plurality (two in this embodiment) of terminals 77, a plurality (two in this embodiment) of conductive wires 78, and a sealing resin 79. The pad portion 75, the heat sink 76, and the plurality of terminals 77 form a lead frame as an example of an object to be connected.

The pad portion 75 includes a metal plate. The pad portion 75 may include iron, gold, silver, copper, aluminum, or the like. The pad portion 75 is formed in a quadrangular shape in a plan view. Pad portion 75 has a plane area equal to or larger than the plane area of SiC semiconductor device 1. SiC semiconductor device 1 is arranged on pad portion 75.
The second principal surface electrode layer 19 of the SiC semiconductor device 1 is electrically connected to the pad portion 75 via the conductive bonding material 80. The conductive bonding material 80 is interposed in the region between the second principal surface electrode layer 19 and the pad portion 75.

  The conductive bonding material 80 may be a metallic paste or solder. The metallic paste may be a conductive paste containing Au (gold), Ag (silver) or Cu (copper). The conductive bonding material 80 is preferably made of solder. The solder may be lead-free type solder. The solder may include at least one of SnAgCu, SnZnBi, SnCu, SnCuNi, or SnSbNi.

The heat sink 76 is connected to one side of the pad portion 75. In this form, the pad portion 75 and the heat sink 76 are formed by a single metal plate. A through hole 76 a is formed in the heat sink 76. The through hole 76a is formed in a circular shape.
The plurality of terminals 77 are arranged along the side opposite to the heat sink 76 with respect to the pad portion 75. Each of the plurality of terminals 77 includes a metal plate. The terminal 77 may include iron, gold, silver, copper, aluminum, or the like.

The plurality of terminals 77 include a first terminal 77A and a second terminal 77B. The first terminal 77A and the second terminal 77B are arranged at intervals along the side of the pad portion 75 opposite to the heat sink 76. The first terminal 77A and the second terminal 77B extend in a strip shape along a direction orthogonal to the arrangement direction thereof.
The plurality of conducting wires 78 may be bonding wires or the like. The plurality of conductors 78 include conductors 78A and conductors 78B. Conductor 78A is electrically connected to first terminal 77A and first main surface electrode layer 12 of SiC semiconductor device 1. As a result, the first terminal 77A is electrically connected to the first main surface electrode layer 12 of the SiC semiconductor device 1 via the conducting wire 78A.

The conducting wire 78B is electrically connected to the second terminal 77B and the pad portion 75. As a result, the second terminal 77B is electrically connected to the second main surface electrode layer 19 of the SiC semiconductor device 1 via the conducting wire 78B. The second terminal 77B may be formed integrally with the pad portion 75.
The sealing resin 79 seals the SiC semiconductor device 1, the pad portion 75, and the lead wires 78 so as to expose a part of the heat sink 76 and the terminals 77. The sealing resin 79 is formed in a rectangular parallelepiped shape.

  The form of the semiconductor package 74 is not limited to TO-220. As the semiconductor package 74, SOP (Small Outline Package), QFN (Quad For Non Lead Package), DFP (Dual Flat Package), DIP (Dual Inline Package), QFP (Quad Flat Package), SIP (Single Inline Package) or SOJ (Small Outline J-leaded Package) or various forms similar thereto may be applied.

  As described above, SiC semiconductor device 1 includes reforming lines 22A to 22D having different occupation ratios RA to RD depending on the crystal planes of the SiC single crystal. More specifically, the occupation rates RB, RD of the reforming lines 22B, 22D formed on the m-plane of the SiC single crystal are the occupation rates RA of the reforming lines 22A, 22C formed on the a-plane of the SiC single crystal. , RC or less (RB, RD ≦ RA, RC). More specifically, the occupation rates RB and RD are less than the occupation rates RA and RC (RB, RD <RA, RC).

The SiC single crystal is easily cracked along the closest atomic direction (see also FIG. 1 and FIG. 2) in a plan view when the c-plane (silicon surface) is viewed from the c-axis direction, and the SiC single crystal is broken in the direction intersecting the closest atomic direction. Along the way, it has the property of being hard to crack. The closest atom direction is the a-axis direction and its equivalent direction. The direction of intersection of the closest atom directions is the m-axis direction and its equivalent direction.
Therefore, in the forming step of the reforming line 70, the crystal plane along the closest atomic direction of the SiC single crystal has a property of being relatively easily cracked, and thus the reforming line having a relatively large occupation ratio. The SiC single crystal can be appropriately cut (cleaved) without forming 70 (see also FIG. 10L). The crystal planes along the closest atomic direction are the m-plane and its equivalent plane.

That is, in the process of forming the reforming line 70, the occupation rate of the reforming line 70 along the second planned cutting line 55 extending in the a-axis direction is changed to the reforming line 70 along the first planned cutting line 54 extending in the m-axis direction. Can be smaller than the occupation ratio of.
On the other hand, the reforming line 70 having a relatively large occupation ratio is formed on the crystal plane along the crossing direction of the closest atomic directions of the SiC single crystal. Accordingly, since inappropriate cutting (cleavage) of the SiC semiconductor wafer structure 61 can be suppressed, it is possible to appropriately suppress the occurrence of cracks due to the physical properties of the SiC single crystal. The crystal planes along the direction of intersection of the closest atomic directions are the a-plane and its equivalent plane.

Further, in the SiC semiconductor device 1, the number of reforming lines 22B and 22D formed on the m-plane of the SiC single crystal is less than the number of reforming lines 22A and 22C formed on the a-plane of the SiC single crystal.
The SiC single crystal is easily cracked along the closest atomic direction (see also FIG. 1 and FIG. 2) in a plan view when the c-plane (silicon surface) is viewed from the c-axis direction, and the SiC single crystal is broken in the direction intersecting the closest atomic direction. Along the way, it has the property of being hard to crack. The closest atom direction is the a-axis direction and its equivalent direction. The direction of intersection of the closest atom directions is the m-axis direction and its equivalent direction.

Therefore, in the process of forming the reforming line 70, the SiC single crystal is appropriately cut (cleavage) with respect to the crystal plane along the closest atomic direction of the SiC single crystal without increasing the number of the reforming lines 70. it can.
That is, in the process of forming the reforming line 70, the number of reforming lines 70 along the second planned cutting line 55 extending in the a-axis direction is equal to the number of reforming lines 70 along the first planned cutting line 54 extending in the m-axis direction. It can be less than the number.

  On the other hand, a relatively large number of reforming lines 70 are formed on the crystal plane of the SiC single crystal along the intersecting direction of the closest atomic directions. Thereby, since the SiC semiconductor wafer structure 61 can be appropriately cut (cleaved), the occurrence of cracks due to the physical properties of the SiC single crystal is appropriately suppressed on the side surfaces 5A and 5D of the SiC semiconductor layer 2 after the cutting (cleavage). it can. The crystal planes along the direction of intersection of the closest atomic directions are the a-plane and its equivalent plane.

  As described above, according to the SiC semiconductor device 1, the occupation ratios RA to RD and the number of the reforming lines 22A to 22D with respect to the side surfaces 5A to 5D can be adjusted by utilizing the physical properties of the SiC single crystal. Accordingly, it is possible to appropriately reduce the formation region of the reforming lines 22A to 22D with respect to the side surfaces 5A to 5D. Therefore, the influence on the SiC semiconductor layer 2 due to the modified lines 22A to 22D can be reduced. Further, it is possible to reduce the time required for the process of forming the reforming line 70.

The influence of the reforming line on the SiC semiconductor layer 2 is, for example, the variation of the electrical characteristics of the SiC semiconductor layer 2 caused by the reforming line, the occurrence of cracks in the SiC semiconductor layer 2 originating from the reforming line, and the like. Is exemplified.
The variation of the leakage current characteristic is exemplified as the variation of the electrical characteristic of the SiC semiconductor layer 2 due to the reforming line. The SiC semiconductor device may be sealed with a sealing resin 79 as shown in FIG.

In this case, it is conceivable that mobile ions in the sealing resin 79 enter the SiC semiconductor layer 2 via the modification line. In a structure in which a plurality of reforming lines are formed at intervals along the normal direction Z over the entire side surfaces 5A to 5D, the risk of current path formation due to such an external structure increases.
Further, in a structure in which a plurality of modified lines are formed along the normal direction Z over the entire side surfaces 5A to 5D of the SiC semiconductor layer 2, the risk of cracking of the SiC semiconductor layer 2 is increased. Therefore, like the SiC semiconductor device 1, by limiting the formation region of the reforming lines 22A to 22D, it is possible to suppress fluctuations in the electrical characteristics of the SiC semiconductor layer 2 and the occurrence of cracks.

Further, according to the SiC semiconductor device 1, since the step of thinning the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41) is performed, the reforming lines 22B and 22D (reforming line 70) of one layer are formed. Even in this case, the SiC semiconductor wafer structure 61 can be appropriately cleaved.
In other words, according to the thinned SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41), the plurality of reforming lines 22B and 22D (reforming line 70) are not formed at intervals in the normal direction Z. In addition, the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41) can be appropriately cleaved. This can further reduce the influence on the SiC semiconductor layer 2 due to the reforming lines 22A to 22D. Further, it is possible to reduce the time required for the process of forming the reforming line 70.

In this case, second main surface 4 of SiC semiconductor layer 2 is a ground surface. SiC semiconductor device 1 preferably includes SiC semiconductor layer 2 having a thickness TL of 40 μm or more and 200 μm or less. The SiC semiconductor layer 2 having such a thickness TL can be appropriately cut out from the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41).
The thickness TS of the SiC semiconductor substrate 6 in the SiC semiconductor layer 2 may be 40 μm or more and 150 μm or less. In the SiC semiconductor layer 2, the thickness TE of the SiC epitaxial layer 7 may be 1 μm or more and 50 μm or less. The thinning of the SiC semiconductor layer 2 is also effective in reducing the resistance value.

Further, according to SiC semiconductor device 1, reforming lines 22A to 22D are formed at intervals from first main surface 3 of SiC semiconductor layer 2 to second main surface 4. Stress easily concentrates at the corners connecting the first main surface 3 and the side surfaces 5A to 5D of the SiC semiconductor layer 2.
Therefore, by forming the modified lines 22A to 22D at intervals from the corners connecting the first main surface 3 and the side surfaces 5A to 5D of the SiC semiconductor layer 2, cracks occur at the corners of the SiC semiconductor layer 2. Can be properly suppressed.

  Particularly, according to the SiC semiconductor device 1, the modified lines 22A to 22D are formed on the SiC semiconductor substrate 6 while avoiding the SiC epitaxial layer 7. That is, the modified lines 22A to 22D expose the SiC epitaxial layer 7 in which the main part of the semiconductor element (Schottky barrier diode D in this embodiment) is formed. Thereby, the influence on the semiconductor element due to the reforming lines 22A to 22D can be appropriately reduced.

Further, according to SiC semiconductor device 1, reforming lines 22A to 22D are formed at intervals from second main surface 4 of SiC semiconductor layer 2 to first main surface 3. Stress is likely to concentrate at the corners connecting second main surface 4 and side surfaces 5A to 5D of SiC semiconductor layer 2.
Therefore, by forming the modified lines 22A to 22D at intervals from the corners connecting the second main surface 4 and the side surfaces 5A to 5D of the SiC semiconductor layer 2, generation of cracks at the corners of the SiC semiconductor layer 2. Can be properly suppressed.

Further, according to SiC semiconductor device 1, main surface insulating layer 10 and first main surface electrode layer 12 formed on first main surface 3 of SiC semiconductor layer 2 are included. The main surface insulating layer 10 has insulating side surfaces 11A to 11D continuous with the side surfaces 5A to 5D of the SiC semiconductor layer 2.
The main surface insulating layer 10 enhances the insulating property between the side surfaces 5A to 5D of the SiC semiconductor layer 2 and the first main surface electrode layer 12 in the structure in which the modified lines 22A to 22D are formed. Thereby, in the structure in which the modified lines 22A to 22D are formed on the side surfaces 5A to 5D of the SiC semiconductor layer 2, the stability of the electrical characteristics of the SiC semiconductor layer 2 can be improved.

FIG. 12A is a perspective view showing the SiC semiconductor device 1 shown in FIG. 3, and is a perspective view showing a second form example of the reforming lines 22A to 22D. In the following, structures corresponding to those described for SiC semiconductor device 1 are designated by the same reference numerals, and description thereof will be omitted.
In the first embodiment, a plurality of layers of reforming lines 22A and 22C and one layer of reforming lines 22B and 22D are formed. On the other hand, in the second mode example, under the condition that the occupation ratios RB and RD are less than the occupation ratios RA and RC (RB, RD <RA, RC), a plurality of layers (three layers in this embodiment) are modified. A plurality of layers (two layers in this embodiment) of reforming lines 22B and 22D, which are less than the number of the quality lines 22A and 22C and the reforming lines 22A and 22C, are formed.

The reforming lines 22A to 22D according to the second embodiment are formed by adjusting the condensing portion (focal point) of laser light in the process of forming the reforming line 70 (reforming lines 22A to 22D) ( See also FIG. 10K).
Even when the reforming lines 22A to 22D according to the second embodiment are formed, it is possible to achieve the same effect as when the reforming lines 22A to 22D according to the first embodiment are formed. However, the reforming lines 22A to 22D according to the first embodiment are preferable from the viewpoint of time saving of the forming process of the reforming lines 70 (reforming lines 22A to 22D).

12B is a perspective view showing the SiC semiconductor device 1 shown in FIG. 3, and is a perspective view showing a third form example of the reforming lines 22A to 22D. In the following, structures corresponding to those described for SiC semiconductor device 1 are designated by the same reference numerals, and description thereof will be omitted.
In the first embodiment, a plurality of layers of reforming lines 22A and 22C and one layer of reforming lines 22B and 22D are formed. On the other hand, in the third mode example, under the condition that the occupation ratios RB and RD are less than the occupation ratios RA and RC (RB, RD <RA, RC), one reforming line 22A, 22C and one layer Reforming lines 22B and 22D are formed.

That is, the reforming lines 22A to 22D according to the third embodiment are formed on the side surfaces 5A to 5D of the SiC semiconductor layer 2 one by one in a one-to-one correspondence relationship. The thickness TR of the one-layer reforming lines 22B and 22D is less than the thickness TR of the one-layer reforming lines 22A and 22C, respectively.
Even when the reforming lines 22A to 22D according to the third embodiment are formed, it is possible to achieve the same effect as when the reforming lines 22A to 22D according to the first embodiment are formed. In particular, according to the reforming lines 22A to 22D according to the third embodiment, it is not necessary to form the plurality of reforming lines 22A to 22D along the normal direction Z, and thus the reforming line 70 (the reforming line 22A 22D) can be further shortened.

12C is a perspective view showing the SiC semiconductor device 1 shown in FIG. 3, and is a perspective view showing a fourth form example of the reforming lines 22A to 22D. In the following, structures corresponding to those described for SiC semiconductor device 1 are designated by the same reference numerals, and description thereof will be omitted.
In the first embodiment, a plurality of layers of reforming lines 22A and 22C and one layer of reforming lines 22B and 22D are formed. On the other hand, in the fourth embodiment, the exclusive ratios RB and RD are changed to a plurality of layers (two layers in this embodiment) under the condition that the exclusive ratios RA and RC are less than (RB, RD <RA, RC). A plurality of layers (four layers in this embodiment) of reforming lines 22B and 22D, which are more than the number of the quality lines 22A and 22C and the reforming lines 22A and 22C, are formed. The number of the reforming lines 22B and 22D may be the same as the number of the reforming lines 22A and 22C.

The reforming lines 22A to 22D according to the fourth embodiment are formed by adjusting the condensing portion (focal point) of laser light in the process of forming the reforming line 70 (reforming lines 22A to 22D) ( See also FIG. 10K).
Even when the reforming lines 22A to 22D according to the fourth example are formed, it is possible to achieve the same effect as when the reforming lines 22A to 22D according to the first example are formed. However, the reforming lines 22A to 22D according to the first embodiment are preferable from the viewpoint of time saving of the forming process of the reforming lines 70 (reforming lines 22A to 22D).

FIG. 12D is a perspective view showing the SiC semiconductor device 1 shown in FIG. 3, and is a perspective view showing a fifth form example of the reforming lines 22A to 22D. In the following, structures corresponding to those described for SiC semiconductor device 1 are designated by the same reference numerals, and description thereof will be omitted.
The reforming lines 22B and 22D according to the first embodiment are formed in a strip shape linearly extending along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. On the other hand, the modified lines 22B and 22D according to the fifth embodiment are formed in a strip shape that is inclined downward from the first main surface 3 of the SiC semiconductor layer 2 toward the second main surface 4. More specifically, the reforming lines 22B and 22D according to the fifth example embodiment each include a first end region 81, a second end region 82, and an inclined region 83.

First end region 81 is located on the first main surface 3 side of SiC semiconductor layer 2 in the vicinity of the corner of SiC semiconductor layer 2. Second end region 82 is located on the second main surface 4 side of SiC semiconductor layer 2 with respect to first end region 81 in the vicinity of the corner of SiC semiconductor layer 2.
The inclined region 83 linearly inclines in a region between the first end region 81 and the second end region 82 from the first main surface 3 toward the second main surface 4. The inclined region 83 may be inclined downward from the first main surface 3 toward the second main surface 4 in a concave curved shape (curved shape). The inclined region 83 may be downwardly inclined in a convex curved shape (curved shape) from the first main surface 3 toward the second main surface 4.

  In this embodiment, the reforming lines 22A and 22C are formed in a strip shape linearly extending along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. However, like the reforming lines 22B and 22D, the reforming lines 22A and 22C may also be formed in a strip shape that is inclined downward from the first main surface 3 of the SiC semiconductor layer 2 toward the second main surface 4. .. The reforming lines 22A and 22C may also include the first end region 81, the second end region 82, and the inclined region 83, respectively.

  The reforming lines 22A to 22D according to the fifth embodiment are formed by adjusting the condensing portion (focal point) of laser light in the process of forming the reforming line 70 (reforming lines 22A to 22D) ( See also FIG. 10K). Even when the reforming lines 22A to 22D according to the fifth example are formed, it is possible to obtain the same effect as when the reforming lines 22A to 22D according to the first example are formed.

Particularly, according to the reforming lines 22B and 22D according to the fifth embodiment, the cleavage start points can be formed in the regions of the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41) in different thickness directions. Thus, the SiC semiconductor wafer structure 61 can be appropriately cleaved even when the reforming lines 22B and 22D formed of one layer are formed.
FIG. 12E is a perspective view showing the SiC semiconductor device 1 shown in FIG. 3, and is a perspective view showing a sixth form example of the reforming lines 22A to 22D. In the following, structures corresponding to those described for SiC semiconductor device 1 are designated by the same reference numerals, and description thereof will be omitted.

  The reforming lines 22B and 22D according to the first embodiment are formed in a strip shape linearly extending along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. On the other hand, the modified lines 22B and 22D according to the sixth embodiment are formed in a strip shape that is inclined downward from the first main surface 3 of the SiC semiconductor layer 2 toward the second main surface 4. More specifically, the reforming lines 22B and 22D according to the sixth example embodiment each include a first end region 81, a second end region 82, and an inclined region 83.

First end region 81 is located on the first main surface 3 side of SiC semiconductor layer 2 in the vicinity of one corner of SiC semiconductor layer 2. First end region 81 extends linearly along the tangential direction of first main surface 3 of SiC semiconductor layer 2.
Second end region 82 is located on the second main surface 4 side of SiC semiconductor layer 2 with respect to first end region 81 in the vicinity of the other corner of SiC semiconductor layer 2. Second end region 82 extends linearly along the tangential direction of first main surface 3 of SiC semiconductor layer 2.

The inclined region 83 connects the first end region 81 and the second end region 82. The inclined region 83 linearly inclines downward from the first end region 81 toward the second end region 82. The inclined region 83 may be downwardly inclined in a concave curve shape from the first end region 81 toward the second end region 82.
In this embodiment, the reforming lines 22A and 22C are formed in a strip shape linearly extending along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. However, like the reforming lines 22B and 22D, the reforming lines 22A and 22C may also be formed in a strip shape that is inclined downward from the first main surface 3 of the SiC semiconductor layer 2 toward the second main surface 4. .. The reforming lines 22A and 22C may also include the first end region 81, the second end region 82, and the inclined region 83, respectively.

  The reforming lines 22A to 22D according to the sixth example are formed by adjusting the condensing portion (focus) of the laser light in the process of forming the reforming line 70 (reforming lines 22A to 22D) ( See also FIG. 10K). Even when the reforming lines 22A to 22D according to the sixth example are formed, it is possible to achieve the same effect as when the reforming lines 22A to 22D according to the first example are formed.

In particular, according to the reforming lines 22B and 22D according to the sixth embodiment, the cleavage starting points can be formed in regions of the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41) in different thickness directions. Thus, the SiC semiconductor wafer structure 61 can be appropriately cleaved even when the reforming lines 22B and 22D formed of one layer are formed.
12F is a perspective view showing the SiC semiconductor device 1 shown in FIG. 3, and is a perspective view showing a seventh form example of the reforming lines 22A to 22D. In the following, structures corresponding to those described for SiC semiconductor device 1 are designated by the same reference numerals, and description thereof will be omitted.

  The reforming lines 22B and 22D according to the first embodiment are formed in a strip shape linearly extending along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. On the other hand, the modified lines 22B and 22D according to the seventh embodiment have strip shapes extending in a curved shape (curved shape) meandering toward the first main surface 3 and the second main surface 4 of the SiC semiconductor layer 2. Has been formed. More specifically, the reforming lines 22B and 22D according to the seventh mode example include a plurality of first regions 87, a plurality of second regions 88, and a plurality of connecting regions 89, respectively.

The plurality of first regions 87 are located in the region on the first main surface 3 side of SiC semiconductor layer 2. The plurality of second regions 88 are located in the region on the second main surface 4 side of the SiC semiconductor layer 2 with respect to the plurality of first regions 87. The plurality of inclined regions 83 respectively connect the corresponding first region 87 and second region 88.
In this embodiment, the reforming lines 22A and 22C are formed in a strip shape linearly extending along the tangential direction of the first main surface 3 of the SiC semiconductor layer 2. However, like the reforming lines 22B and 22D, the reforming lines 22A and 22C also have a strip shape extending in a curved shape (curved shape) meandering toward the first main surface 3 and the second main surface 4 of the SiC semiconductor layer 2. It may be formed in. That is, the reforming lines 22A and 22C may also include the plurality of first regions 87, the plurality of second regions 88, and the plurality of connection regions 89, respectively.

  The meandering cycle of the reforming lines 22B and 22D (reforming lines 22A and 22C) is arbitrary. The reforming lines 22B and 22D (reforming lines 22A and 22C) may each be formed in one strip shape extending in a concave curve from the first main surface 3 toward the second main surface 4. In this case, the reforming lines 22B and 22D (reforming lines 22A and 22C) may include two first regions 87, one second region 88, and two connecting regions 89, respectively.

Further, the reforming lines 22B and 22D (reforming lines 22A and 22C) may each be formed in one strip shape extending in a convex curved shape from the second main surface 4 toward the first main surface 3. In this case, the reforming lines 22B and 22D (reforming lines 22A and 22C) may include one first region 87, two second regions 88, and two connecting regions 89, respectively.
The reforming lines 22A to 22D according to the seventh embodiment are formed by adjusting the condensing portion (focus) of the laser light in the process of forming the reforming line 70 (reforming lines 22A to 22D) ( See also FIG. 10K). Even when the reforming lines 22A to 22D according to the seventh example are formed, it is possible to obtain the same effect as when the reforming lines 22A to 22D according to the first example are formed.

Particularly, according to the reforming lines 22B and 22D according to the seventh embodiment, the cleavage starting points can be formed in the regions of the SiC semiconductor wafer structure 61 (SiC semiconductor wafer 41) in different thickness directions. Thus, the SiC semiconductor wafer structure 61 can be appropriately cleaved even when the reforming lines 22B and 22D formed of one layer are formed.
FIG. 12G is a perspective view showing the SiC semiconductor device shown in FIG. 3, and is a perspective view showing an eighth example of the reforming line. In the following, structures corresponding to those described for SiC semiconductor device 1 are designated by the same reference numerals, and description thereof will be omitted.

In the first exemplary embodiment, under the condition that the occupation ratios RB and RD are less than the occupation ratios RA and RC (RB, RD <RA, RC), the reforming lines 22A and 22C of a plurality of layers and the reforming line 22B of one layer. , 22D are formed.
On the other hand, in the second embodiment, the exclusive ratios RB and RD are plural layers (two or more layers. In this embodiment, two or more layers under the conditions of the exclusive ratios RA and RC or more (RB, RD ≧ RA, RC). The reforming lines 22A, 22C of one layer and the reforming lines 22B, 22D of one layer or a plurality of layers (one layer in this embodiment), which is less than the number of the reforming lines 22A, 22C, are formed. The reforming lines 22B and 22D are preferably composed of one layer.

It is preferable that the reforming lines 22B and 22D be formed at a distance from the first main surface 3 to the second main surface 4 of the SiC semiconductor layer 2 as in the first embodiment. Further, it is preferable that reforming lines 22B and 22D be formed at a distance from second main surface 4 of SiC semiconductor layer 2 to first main surface 3.
The reforming lines 22A to 22D according to the eighth example are formed by adjusting the condensing portion (focus) of laser light in the process of forming the reforming line 70 (reforming lines 22A to 22D) ( See also FIG. 10K).

Even when the reforming lines 22A to 22D according to the eighth embodiment are formed, the formation region of the reforming lines 22B and 22D can be limited. As a result, the same effect as when the reforming lines 22A to 22D according to the first embodiment are formed can be obtained.
From the viewpoint of time saving of the forming process of the reforming line 70 (reforming lines 22A to 22D), it is almost the same as that of the first embodiment. However, from the viewpoint of the occupation ratios RA to RD, the reforming lines 22A to 22D according to the first embodiment are more preferable.

First form example, second form example, third form example, fourth form example, fifth form example, sixth form example, seventh form example and eighth form example (hereinafter, simply "first to eighth form An SiC semiconductor device 1 including at least two of the reforming lines 22A to 22D according to the example) may be formed at the same time.
In addition, the features of the reforming lines 22A to 22D according to the first to eighth example embodiments can be combined between them in any manner and in any manner. That is, the reforming lines 22A to 22D having a form in which at least two of the features of the reforming lines 22A to 22D according to the first to eighth exemplary embodiments are combined may be adopted.

For example, the characteristics of the reforming lines 22A to 22D according to the fifth mode example may be combined with the characteristics of the reforming lines 22A to 22D according to the sixth mode example and the seventh mode example. In this case, a strip-shaped modified linearly inclined from the first main surface 3 of the SiC semiconductor layer 2 toward the second main surface 4 and meandering toward the first main surface 3 and the second main surface 4 of the SiC semiconductor layer 2. Quality lines 22A to 22D are formed.
FIG. 13 is a perspective view showing the SiC semiconductor device 91 according to the second embodiment of the present invention, and is a perspective view showing a structure to which the reforming lines 22A to 22D according to the first embodiment are applied. In the following, structures corresponding to those described for SiC semiconductor device 1 are designated by the same reference numerals, and description thereof will be omitted.

  In this form, the reforming lines 22A to 22D according to the first form example are applied. However, instead of or in addition to the reforming lines 22A to 22D according to the first mode example, the second mode example, the third mode example, the fourth mode example, the fifth mode example, the sixth mode example, the seventh mode. The reforming lines 22A to 22D according to the example or the eighth embodiment may be adopted. Further, the reforming lines 22A to 22D having a form in which at least two of the features of the reforming lines 22A to 22D according to the first to eighth embodiments are combined may be adopted.

Referring to FIG. 13, in this embodiment, insulating side surfaces 11A to 11D of main surface insulating layer 10 are formed at a distance from side surfaces 5A to 5D of SiC semiconductor layer 2 in an inner region in a plan view. Main surface insulating layer 10 exposes the peripheral portion of first main surface 3 of SiC semiconductor layer 2 in a plan view.
Main surface insulating layer 10 exposes the peripheral portion of first main surface 3 of SiC semiconductor layer 2 together with resin layer 16 and passivation layer 13. In this embodiment, the insulating side surfaces 11A to 11D of the main surface insulating layer 10 are flush with the resin side surfaces 17A to 17D of the resin layer 16 and the side surfaces 14A to 14D of the passivation layer 13. In this embodiment, the insulating side surfaces 11A to 11D of the principal surface insulating layer 10 are also the portions that define the dicing streets.

The main surface insulating layer 10 is formed by performing the step of removing the main surface insulating layer 10 by an etching method after the step of removing the passivation layer 13 in the step of FIG. 10I described above.
In this case, in the step of FIG. 10K described above, laser light may be directly irradiated from the first main surface 62 side of the SiC semiconductor wafer structure 61 to the inside of the SiC semiconductor wafer structure 61 without the main surface insulating layer 10. ..

As described above, the SiC semiconductor device 91 can also achieve the same effects as those described for the SiC semiconductor device 1. However, in order to improve the insulation between the side surfaces 5A to 5D of the SiC semiconductor layer 2 and the first principal surface electrode layer 12, the structure of the SiC semiconductor device 1 according to the first embodiment is preferable.
FIG. 14 is a perspective view of the SiC semiconductor device 101 according to the third embodiment of the present invention seen from one angle, and is a perspective view showing a structure to which the reforming lines 22A to 22D according to the first embodiment are applied. It is a figure. FIG. 15 is a perspective view of the SiC semiconductor device 101 shown in FIG. 14 seen from another angle. FIG. 16 is a plan view showing SiC semiconductor device 101 shown in FIG. FIG. 17 is a plan view with the resin layer 129 removed from FIG.

In this form, the reforming lines 22A to 22D according to the first form example are applied. That is, in the manufacturing process of the SiC semiconductor device 101, the same processes as the processes of FIGS. 10A to 10M described above are applied.
In the SiC semiconductor device 101, in place of or in addition to the reforming lines 22A to 22D according to the first embodiment, second embodiment, third embodiment, fourth embodiment, fifth embodiment, sixth embodiment. The reforming lines 22A to 22D according to the seventh embodiment example or the eighth embodiment example may be adopted. Further, the reforming lines 22A to 22D having a form in which at least two of the features of the reforming lines 22A to 22D according to the first to eighth embodiments are combined may be adopted.

Referring to FIGS. 14 to 17, SiC semiconductor device 101 includes a SiC semiconductor layer 102. The SiC semiconductor layer 102 includes 4H—SiC single crystal as an example of a SiC single crystal made of hexagonal crystal. The SiC semiconductor layer 102 (SiC semiconductor chip) is formed in a rectangular parallelepiped chip shape.
The SiC semiconductor layer 102 has a first main surface 103 on one side, a second main surface 104 on the other side, and side surfaces 105A, 105B, 105C, 105D connecting the first main surface 103 and the second main surface 104. is doing. The first main surface 103 and the second main surface 104 are formed in a quadrangular shape (rectangular shape in this embodiment) in a plan view (hereinafter, simply referred to as “plan view”) viewed from their normal direction Z. ..

The first main surface 103 is an element formation surface on which a semiconductor element is formed. The second main surface 104 of the SiC semiconductor layer 102 is a ground surface having grinding marks. Side surfaces 105A to 105D are each a smooth cleavage plane facing the crystal plane of the SiC single crystal. The side surfaces 105A to 105D have no grinding marks.
The thickness TL of the SiC semiconductor layer 102 may be 40 μm or more and 200 μm or less. The thickness TL may be 40 μm or more and 60 μm or less, 60 μm or more and 80 μm or less, 80 μm or more and 100 μm or less, 100 μm or more and 120 μm or less, 120 μm or more and 140 μm or less, 140 μm or more and 160 μm or less, 160 μm or more and 180 μm or less, or 180 μm or more and 200 μm or less. The thickness TL is preferably 60 μm or more and 150 μm or less.

In this embodiment, the first main surface 103 and the second main surface 104 face the c-plane of the SiC single crystal. The first main surface 103 faces the (0001) surface (silicon surface). Second main surface 104 faces the (000-1) plane (carbon surface) of the SiC single crystal.
The first main surface 103 and the second main surface 104 have an off-angle θ that is inclined at an angle of 10 ° or less in the [11-20] direction with respect to the c-plane of the SiC single crystal. The normal direction Z is inclined by the off angle θ with respect to the c-axis ([0001] direction) of the SiC single crystal.

  The off angle θ may be 0 ° or more and 5.0 ° or less. The off angle θ is 0 ° or more and 1.0 ° or less, 1.0 ° or more and 1.5 ° or less, 1.5 ° or more and 2.0 ° or less, 2.0 ° or more and 2.5 ° or less, 2.5. ° to 3.0 °, 3.0 ° to 3.5 °, 3.5 ° to 4.0 °, 4.0 ° to 4.5 ° or 4.5 ° to 5.0 ° It may be set within the following range of angles. The off angle θ preferably exceeds 0 °. The off angle θ may be less than 4.0 °.

The off angle θ may be set in a range of an angle of 3.0 ° or more and 4.5 ° or less. In this case, it is preferable that the off-angle θ is set in a range of 3.0 ° or more and 3.5 ° or less, or 3.5 ° or more and 4.0 ° or less.
The off angle θ may be set in a range of an angle of 1.5 ° or more and 3.0 ° or less. In this case, it is preferable that the off angle θ is set in the range of an angle of 1.5 ° or more and 2.0 ° or less, or 2.0 ° or more and 2.5 ° or less.

  Each of the side surfaces 105A to 105D may have a length of 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less). The surface areas of the side surfaces 105B and 105D exceed the surface areas of the side surfaces 105A and 105C in this embodiment. The first main surface 103 and the second main surface 104 may be formed in a square shape in a plan view. In this case, the surface areas of the side surfaces 105A and 105C are equal to the side surfaces 105B and 105D, and the surface areas of the side surfaces 105A and 105C are equal to the side surfaces 105B and 105D.

In this embodiment, the side surfaces 105A and 105C extend along the first direction X and face each other in the second direction Y intersecting the first direction X. In this embodiment, the side surface 105B and the side surface 105D extend along the second direction Y and face each other in the first direction X. The second direction Y is more specifically a direction orthogonal to the first direction X.
In this embodiment, the first direction X is set to the m-axis direction ([1-100] direction) of the SiC single crystal. The second direction Y is set in the a-axis direction ([11-20] direction) of the SiC single crystal.

  Side surface 105A and side surface 105C form the short side of SiC semiconductor layer 102 in a plan view. The side surface 105A and the side surface 105C are formed by the a-plane of the SiC single crystal and face each other in the a-axis direction. Side surface 105A is formed by the (-1-120) plane of the SiC single crystal. The side surface 105C is formed by the (11-20) plane of the SiC single crystal.

  Side surface 105B and side surface 105D form the long side of SiC semiconductor layer 102 in a plan view. Side surface 105B and side surface 105D are formed by the m-plane of a SiC single crystal and face each other in the m-axis direction. Side surface 105B is formed by the (-1100) plane of the SiC single crystal. Side surface 105D is formed of a (1-100) plane of SiC single crystal.

The side surfaces 105A and 105C are inclined with respect to the normal to the c-axis direction ([0001] direction) of the SiC single crystal with respect to the normal to the first main surface 103 of the SiC semiconductor layer 102. You may form the surface.
In this case, side surface 105A and side surface 105C have an off angle θ with respect to the normal line of first main surface 103 of SiC semiconductor layer 102 when the normal line of first main surface 103 of SiC semiconductor layer 102 is 0 °. It may be inclined at a corresponding angle. The angle according to the off angle θ may be equal to the off angle θ, or may be an angle larger than 0 ° and smaller than the off angle θ.

In this embodiment, the SiC semiconductor layer 102 has a laminated structure including an n ⁺ type SiC semiconductor substrate 106 (second impurity region) and an n type SiC epitaxial layer 107 (first impurity region). The SiC semiconductor substrate 106 and the SiC epitaxial layer 107 correspond to the SiC semiconductor substrate 6 and the SiC epitaxial layer 7 according to the first embodiment, respectively. The second main surface 104 of the SiC semiconductor layer 102 is formed by the SiC semiconductor substrate 106.

The SiC epitaxial layer 107 forms the first main surface 103 of the SiC semiconductor layer 102. Side surfaces 105A to 105D of SiC semiconductor layer 102 are formed by SiC semiconductor substrate 106 and SiC epitaxial layer 107.
The thickness TS of the SiC semiconductor substrate 106 may be 40 μm or more and 150 μm or less. The thickness TS is 40 μm or more and 50 μm or less, 50 μm or more and 60 μm or less, 60 μm or more and 70 μm or less, 70 μm or more and 80 μm or less, 80 μm or more and 90 μm or less, 90 μm or more and 100 μm or less, 100 μm or more 110 μm or less, 110 μm or more 120 μm or less, 120 μm or more and 130 μm or less, It may be 130 μm or more and 140 μm or less or 140 μm or more and 150 μm or less. The thickness TS is preferably 40 μm or more and 130 μm or less. By thinning the SiC semiconductor substrate 106, the resistance value can be reduced by shortening the current path.

  The thickness TE of the SiC epitaxial layer 107 may be 1 μm or more and 50 μm or less. The thickness TE is 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, 20 μm or more and 25 μm or less, 25 μm or more and 30 μm or less, 30 μm or more, 35 μm or more 40 μm or less, 40 μm or more and 45 μm or less, or It may be 45 μm or more and 50 μm or less. The thickness TE is preferably 5 μm or more and 15 μm or less.

The n-type impurity concentration of SiC epitaxial layer 107 is equal to or lower than the n-type impurity concentration of SiC semiconductor substrate 106. More specifically, the n-type impurity concentration of SiC epitaxial layer 107 is less than the n-type impurity concentration of SiC semiconductor substrate 106. The n-type impurity concentration of SiC semiconductor substrate 106 may be 1.0 × 10 ¹⁸ cm ⁻³ or more and 1.0 × 10 ²¹ cm ⁻³ or less. The n-type impurity concentration of SiC epitaxial layer 107 may be 1.0 × 10 ¹⁵ cm ⁻³ or more and 1.0 × 10 ¹⁸ cm ⁻³ or less.

In this embodiment, the SiC epitaxial layer 107 has a plurality of regions having different n-type impurity concentrations along the normal direction Z. More specifically, the SiC epitaxial layer 107 includes a high concentration region 108 having a relatively high n-type impurity concentration and a low concentration region 109 having a low n-type impurity concentration with respect to the high concentration region 108.
High concentration region 108 is formed in a region of SiC semiconductor layer 102 on the side of first main surface 103. The low concentration region 109 is formed in the region of the SiC semiconductor layer 102 on the second main surface 104 side with respect to the high concentration region 108.

The n-type impurity concentration of the high concentration region 108 may be 1 × 10 ¹⁶ cm ⁻³ or more and 1 × 10 ¹⁸ cm ⁻³ or less. The n-type impurity concentration of the low-concentration region 109 may be 1 × 10 ¹⁵ cm ⁻³ or more and 1 × 10 ¹⁶ cm ⁻³ or less.
The thickness of the high concentration region 108 is less than or equal to the thickness of the low concentration region 109. More specifically, the thickness of the high concentration region 108 is less than the thickness of the low concentration region 109. The thickness of high concentration region 108 is less than one half of the total thickness of SiC epitaxial layer 107.

An active region 111 and an outer region 112 are set in the SiC semiconductor layer 102. The active region 111 is a region in which a vertical MISFET (Metal Insulator Field Effect Transistor) as an example of a semiconductor element is formed. The outer region 112 is a region outside the active region 111.
Active region 111 is set in the central portion of SiC semiconductor layer 102 with a space from the side surfaces 105A to 105D of SiC semiconductor layer 102 to the inner region in plan view. Active region 111 is set in a quadrangular shape (rectangular shape in this embodiment) having four sides parallel to side surfaces 105A to 105D of SiC semiconductor layer 102 in a plan view.

The outer region 112 is set in a region between the side surfaces 105A to 105D of the SiC semiconductor layer 102 and the peripheral edge of the active region 111. The outer region 112 is set to have an endless shape (in this embodiment, a rectangular ring shape) that surrounds the active region 111 in a plan view.
A main surface insulating layer 113 is formed on the first main surface 103 of the SiC semiconductor layer 102. The main surface insulating layer 113 selectively covers the active region 111 and the outer region 112. The main surface insulating layer 113 may include silicon oxide (SiO ₂ ).

  Main surface insulating layer 113 has insulating side surfaces 114A, 114B, 114C and 114D exposed from side surfaces 105A to 105D of SiC semiconductor layer 102. The insulating side surfaces 114A to 114D are continuous with the side surfaces 105A to 105D. The insulating side surfaces 114A to 114D are formed flush with the side surfaces 105A to 105D, respectively. The insulating side surfaces 114A to 114D are cleaved surfaces.

The thickness of the resin layer 129 may be 1 μm or more and 50 μm or less. The thickness of the resin layer 129 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.
A main surface gate electrode layer 115 as one of the first main surface electrode layers is formed on the main surface insulating layer 113. Main surface gate electrode layer 115 penetrates main surface insulating layer 113 and is electrically connected to an arbitrary region of SiC semiconductor layer 102.

The main surface gate electrode layer 115 includes a gate pad 116 and gate fingers 117 and 118. The gate pad 116 and the gate fingers 117 and 118 are arranged in the active area 111.
Gate pad 116 is formed along side surface 105A of SiC semiconductor layer 102 in plan view. Gate pad 116 is formed along the central region of side surface 105A of SiC semiconductor layer 102 in plan view.

Gate pad 116 may be formed along a corner that connects any two of side surfaces 105A to 105D of SiC semiconductor layer 102 in plan view. The gate pad 116 may be formed in a rectangular shape in a plan view.
Gate fingers 117, 118 include outer gate finger 117 and inner gate finger 118. The outer gate finger 117 is pulled out from the gate pad 116 and extends in a strip shape along the peripheral edge of the active region 111.

In this embodiment, outer gate finger 117 is formed along three side surfaces 105A, 105B, 105D of SiC semiconductor layer 102 so as to partition the inner region of active region 111 from three directions.
The outer gate finger 117 has a pair of open ends 119 and 120. The pair of open ends 119 and 120 are formed in a region facing the gate pad 116 with the inner region of the active region 111 interposed therebetween. In this embodiment, the pair of open ends 119 and 120 are formed along the side surface 105C of the SiC semiconductor layer 102.

The inner gate finger 118 is drawn from the gate pad 116 to an area inside the active area 111. The inner gate finger 118 extends in a band shape in the inner region of the active region 111. The inner gate finger 118 extends from the gate pad 116 toward the side surface 105C.
A main surface source electrode layer 121 as one of the first main surface electrode layers is further formed on the main surface insulating layer 113. Main surface source electrode layer 121 penetrates main surface insulating layer 113 and is electrically connected to an arbitrary region of SiC semiconductor layer 102. In this form, the main surface source electrode layer 121 includes a source pad 122, a source routing wire 123, and a source connection portion 124.

  The source pad 122 is formed in the active region 111 at a distance from the gate pad 116 and the gate fingers 117 and 118. The source pad 122 has a C-shape (see FIG. 16) in plan view so as to cover a C-shape (inverted C-shape in FIGS. 16 and 17) sectioned by the gate pad 116 and the gate fingers 117 and 118. And in FIG. 17, it is formed in an inverted C shape.

  The source routing wiring 123 is formed in the outer region 112. The source routing wiring 123 extends in a strip shape along the active region 111. In this form, the source lead-out wiring 123 is formed in an endless shape (in this form, a square ring) surrounding the active region 111 in a plan view. The source routing wiring 123 is electrically connected to the SiC semiconductor layer 102 in the outer region 112.

  The source connecting portion 124 connects the source pad 122 and the source routing wiring 123. The source connection portion 124 is provided in a region between the pair of open ends 119 and 120 of the outer gate finger 117. The source connecting portion 124 traverses the boundary region between the source pad 122 and the active region 111 and the outer region 112, and is connected to the source leading wiring 123.

The MISFET formed in the active region 111 includes an npn type parasitic bipolar transistor due to its structure. When the avalanche current generated in the outer region 112 flows into the active region 111, the parasitic bipolar transistor is turned on. In this case, control of the MISFET may become unstable due to latch-up, for example.
Therefore, in the SiC semiconductor device 101, the structure of the main surface source electrode layer 121 is used to form an avalanche current absorption structure that absorbs the avalanche current generated in the outer region 112.

More specifically, the avalanche current generated in the outer region 112 is absorbed by the source leading wiring 123 and reaches the source pad 122 via the source connecting portion 124. When a conductive wire for external connection (for example, a bonding wire) is connected to the source pad 122, the avalanche current is taken out by this conductive wire.
As a result, it is possible to prevent the parasitic bipolar transistor from being turned on by an undesired current generated in the outer region 112. Therefore, latch-up can be suppressed, and the stability of control of the MISFET can be improved.

A gate voltage is applied to the main surface gate electrode layer 115. The gate voltage may be 10 V or more and 50 V or less (for example, about 30 V). A source voltage is applied to the main surface source electrode layer 121. The source voltage may be a reference voltage (eg, GND voltage).
A passivation layer 125 (insulating layer) is formed on the main surface insulating layer 113. The passivation layer 125 may have a single layer structure including a silicon oxide layer or a silicon nitride layer.

The passivation layer 125 may have a stacked structure including a silicon oxide layer and a silicon nitride layer. The silicon oxide layer may be formed on the silicon nitride layer. The silicon nitride layer may be formed on the silicon oxide layer. The passivation layer 125 has a single-layer structure made of a silicon nitride layer in this embodiment.
The side surfaces 126A, 126B, 126C, 126D of the passivation layer 125 are formed in a space from the side surfaces 105A to 105D of the SiC semiconductor layer 102 to the inner region in a plan view. The passivation layer 125 exposes the peripheral portion of the SiC semiconductor layer 102 in a plan view. The passivation layer 125 exposes the main surface insulating layer 113.

The thickness of the passivation layer 125 may be 1 μm or more and 50 μm or less. The thickness of the passivation layer 125 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.
The passivation layer 125 selectively covers the main surface gate electrode layer 115 and the main surface source electrode layer 121. A gate subpad opening 127 and a source subpad opening 128 are formed in the passivation layer 125. The gate subpad opening 127 exposes the gate pad 116. The source subpad opening 128 exposes the source pad 122.

A resin layer 129 (insulating layer) is formed on the passivation layer 125. The passivation layer 125 and the resin layer 129 form one insulating laminated structure (insulating layer). In FIG. 16, the resin layer 129 is shown by hatching.
The resin layer 129 may include a negative type or positive type photosensitive resin. In this embodiment, the resin layer 129 contains polybenzoxazole as an example of a positive type photosensitive resin. The resin layer 129 may include polyimide as an example of a negative type photosensitive resin.

  The resin layer 129 selectively covers the main surface gate electrode layer 115 and the main surface source electrode layer 121. The resin side surfaces 130A, 130B, 130C, 130D of the resin layer 129 are formed at intervals from the side surfaces 105A to 105D of the SiC semiconductor layer 102 to the inner region. The resin layer 129 exposes the main surface insulating layer 113 together with the passivation layer 125. In this embodiment, the resin side surfaces 130A to 130D of the resin layer 129 are flush with the side surfaces 126A to 126D of the passivation layer 125.

The resin side surfaces 130A to 130D of the resin layer 129 are portions that define the dicing streets when the SiC semiconductor device 101 is cut out from a single SiC semiconductor wafer. In this embodiment, the side surfaces 126A to 126D of the passivation layer 125 are also the portions that define the dicing streets.
By exposing the peripheral portion of the SiC semiconductor layer 102 from the resin layer 129 and the passivation layer 125, it is not necessary to physically cut the resin layer 129 and the passivation layer 125. Thereby, the SiC semiconductor device 101 can be smoothly cut out from one SiC semiconductor wafer. In addition, the insulation distance from the side surfaces 105A to 105D of the SiC semiconductor layer 102 can be increased.

  The distance between the side surfaces 105A to 105D and the resin side surfaces 130A to 130D (side surfaces 126A to 126D) may be 1 μm or more and 25 μm or less. Even if the distance between the side surfaces 105A to 105D and the resin side surfaces 130A to 130D (side surfaces 126A to 126D) is 1 μm or more and 5 μm or less, 5 μm or more and 10 μm or less, 10 μm or more and 15 μm or less, 15 μm or more and 20 μm or less, or 20 μm or more and 25 μm or less. Good. Of course, the side surfaces 126A to 126D of the passivation layer 125 may be formed flush with the side surfaces 105A to 105D of the SiC semiconductor layer 102.

A gate pad opening 131 and a source pad opening 132 are formed in the resin layer 129. The gate pad opening 131 exposes the gate pad 116. The source pad opening 132 exposes the source pad 122.
The gate pad opening 131 of the resin layer 129 communicates with the gate subpad opening 127 of the passivation layer 125. The inner wall of the gate pad opening 131 may be located outside the inner wall of the gate subpad opening 127. The inner wall of the gate pad opening 131 may be located inside the inner wall of the gate subpad opening 127. The resin layer 129 may cover the inner wall of the gate subpad opening 127.

  The source pad opening 132 of the resin layer 129 communicates with the source subpad opening 128 of the passivation layer 125. The inner wall of the gate pad opening 131 may be located outside the inner wall of the source subpad opening 128. The inner wall of the source pad opening 132 may be located inside the inner wall of the source subpad opening 128. The resin layer 129 may cover the inner wall of the source subpad opening 128.

The thickness of the resin layer 129 may be 1 μm or more and 50 μm or less. The thickness of the resin layer 129 may be 1 μm or more and 10 μm or less, 10 μm or more and 20 μm or less, 20 μm or more and 30 μm or less, 30 μm or more and 40 μm or less, or 40 μm or more and 50 μm or less.
A drain electrode layer 133 as a second main surface electrode layer is connected to the second main surface 104 of the SiC semiconductor layer 102. The maximum voltage that can be applied between the main surface source electrode layer 121 and the drain electrode layer 133 when off may be 1000 V or more and 10000 V or less.

The drain electrode layer 133 may include at least one of Ti layer, Ni layer, Au layer, Ag layer, and Al layer. The drain electrode layer 133 may have a single layer structure including a Ti layer, a Ni layer, an Au layer, an Ag layer or an Al layer.
The drain electrode layer 133 may have a laminated structure in which at least two of Ti layer, Ni layer, Au layer, Ag layer, and Al layer are laminated in an arbitrary manner. Drain electrode layer 133 may have a four-layer structure including a Ti layer, a Ni layer, an Au layer, and an Ag layer that are stacked in this order from second main surface 104 of SiC semiconductor layer 102.

The SiC semiconductor substrate 106 is formed as the drain region 134 (second impurity region) of the MISFET. The SiC epitaxial layer 107 is formed as the drift region 135 (first impurity region) of the MISFET.
On the side surfaces 105A to 105D of the SiC semiconductor layer 102, a plurality of reforming lines 22A to 22D according to the first embodiment are formed. The modified lines 22A to 22D according to the third embodiment have the structure of the modified lines 22A to 22D according to the first embodiment except that the modified semiconductor layers 22A to 22D are formed on the SiC semiconductor layer 102 instead of the SiC semiconductor layer 2. It is similar to the structure.

The description of the reforming lines 22A to 22D according to the first embodiment shall be applied to the description of the reforming lines 22A to 22D according to the third embodiment, respectively, and the reforming lines 22A to 22A according to the third embodiment. A detailed description of 22D is omitted.
FIG. 18 is an enlarged view of region XVIII shown in FIG. 17, and is a view for explaining the structure of first main surface 103 of SiC semiconductor layer 102. 19 is a sectional view taken along line XIX-XIX shown in FIG. 20 is a sectional view taken along line XX-XX shown in FIG. FIG. 21 is an enlarged view of the area XXI shown in FIG. 22 is a sectional view taken along line XXII-XXII shown in FIG. FIG. 23 is an enlarged view of the area XXIII shown in FIG.

18 to 22, in active region 111, p type body region 141 is formed in the surface layer portion of first main surface 103 of SiC semiconductor layer 102. The body region 141 defines the active region 111.
In this embodiment, body region 141 is formed over the entire area of first main surface 103 of SiC semiconductor layer 102 forming active region 111. The p-type impurity concentration of the body region 141 may be 1.0 × 10 ¹⁷ cm ⁻³ or more and 1.0 × 10 ¹⁹ cm ⁻³ or less.

In active region 111, a plurality of gate trenches 142 are formed in the surface layer portion of first main surface 103 of SiC semiconductor layer 102. The plurality of gate trenches 142 are each formed in a strip shape extending along the first direction X (m-axis direction of the SiC single crystal) in a plan view, and are spaced along the second direction Y (a-axis direction of the SiC single crystal). It is formed by leaving.
In this embodiment, each gate trench 142 extends from the peripheral portion on one side (side surface 105B side) to the peripheral portion on the other side (side surface 105D side) in the active region 111. The plurality of gate trenches 142 are formed in a stripe shape as a whole in a plan view.

Each gate trench 142 crosses an intermediate portion between the peripheral portion on one side and the peripheral portion on the other side in the active region 111. One end of each gate trench 142 is located at the peripheral portion on one side in the active region 111. The other end of each gate trench 142 is located at the other peripheral edge of the active region 111.
The length of each gate trench 142 may be 0.5 mm or more. In the cross section shown in FIG. 20, the length of each gate trench 142 is the length from the end on the connection portion side of each gate trench 142 and the outer gate finger 117 to the end on the opposite side.

In this embodiment, the length of each gate trench 142 is 1 mm or more and 10 mm or less (for example, 2 mm or more and 5 mm or less). The total extension of the one or more gate trenches 142 per unit area may be 0.5 μm / μm ² or more and 0.75 μm / μm ² or less.
Each gate trench 142 integrally includes an active trench portion 143 and a contact trench portion 144. The active trench portion 143 is a portion along the channel of the MISFET in the active region 111.

  The contact trench portion 144 is a portion mainly intended for contact with the outer gate finger 117 in the gate trench 142. The contact trench portion 144 is drawn from the active trench portion 143 to the peripheral portion of the active region 111. The contact trench portion 144 is formed in a region immediately below the outer gate finger 117. The amount of lead-out of the contact trench portion 144 is arbitrary.

Each gate trench 142 penetrates the body region 141 and reaches the SiC epitaxial layer 107. Each gate trench 142 includes a sidewall and a bottom wall. The side wall forming the long side of each gate trench 142 is formed by the a-plane of the SiC single crystal. The side wall forming the short side of each gate trench 142 is formed by the m-plane of SiC single crystal.
The sidewall of each gate trench 142 may extend along the normal direction Z. The side wall of each gate trench 142 may be formed substantially perpendicular to first main surface 103 of SiC semiconductor layer 102.

The angle formed by the side wall of each gate trench 142 with respect to first main surface 103 of SiC semiconductor layer 102 in SiC semiconductor layer 102 may be 90 ° or more and 95 ° or less (for example, 91 ° or more and 93 ° or less). .. Each gate trench 142 may be formed in a tapered shape in which the opening area on the bottom wall side is smaller than the opening area on the opening side in a cross-sectional view.
The bottom wall of each gate trench 142 is located in the SiC epitaxial layer 107. More specifically, the bottom wall of each gate trench 142 is located in the high concentration region 108 of the SiC epitaxial layer 107.

The bottom wall of each gate trench 142 faces the c-plane of the SiC single crystal. The bottom wall of each gate trench 142 has an off angle θ inclined in the [11-20] direction with respect to the c-plane of the SiC single crystal.
The bottom wall of each gate trench 142 may be formed parallel to first main surface 103 of SiC semiconductor layer 102. Of course, the bottom wall of each gate trench 142 may be formed in a convex curve shape toward the second main surface 104 of the SiC semiconductor layer 102.

With respect to the normal direction Z, the depth of each gate trench 142 may be 0.5 μm or more and 3.0 μm or less. The depth of each gate trench 142 is 0.5 μm or more and 1.0 μm or less, 1.0 μm or more and 1.5 μm or less, 1.5 μm or more and 2.0 μm or less, 2.0 μm or more and 2.5 μm or less, or 2.5 μm or more 3 It may be 0.0 μm or less.
The width of each gate trench 142 along the second direction Y may be 0.1 μm or more and 2 μm or less. The width of each gate trench 142 may be 0.1 μm or more and 0.5 μm or less, 0.5 μm or more and 1.0 μm or less, 1.0 μm or more and 1.5 μm or less, or 1.5 μm or more and 2 μm or less.

Referring to FIG. 21, the opening edge portion 146 of each gate trench 142 includes an inclined portion 147 that is inclined downward from the first main surface 103 of the SiC semiconductor layer 102 toward the inside of each gate trench 142. The opening edge portion 146 of each gate trench 142 is a corner portion that connects the first main surface 103 of the SiC semiconductor layer 102 and the sidewall of each gate trench 142.
In this embodiment, the inclined portion 147 is formed in a concave curve shape that is directed inward of the SiC semiconductor layer 102. The inclined portion 147 may be formed in a convex curve shape that is directed inward of each gate trench 142. The sloped portion 147 relaxes electric field concentration on the opening edge portion 146 of each gate trench 142.

A gate insulating layer 148 and a gate electrode layer 149 are formed in each gate trench 142. In FIG. 18, the gate insulating layer 148 and the gate electrode layer 149 are indicated by hatching.
The gate insulating layer 148 is formed of at least one of silicon oxide (SiO ₂ ), silicon nitride (SiN), aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO ₂ ), and tantalum oxide (Ta ₂ O ₃ ). Including.

Gate insulating layer 148 may have a stacked structure including a SiN layer and a SiO ₂ layer stacked in this order from the first main surface 103 side of SiC semiconductor layer 102. Gate insulating layer 148 may have a laminated structure including a SiO ₂ layer and a SiN layer, which are laminated in this order from the first main surface 103 side of SiC semiconductor layer 102. The gate insulating layer 148 may have a single layer structure including a SiO ₂ layer or a SiN layer. In this form, the gate insulating layer 148 has a single-layer structure made of a SiO ₂ layer.

The gate insulating layer 148 is formed in a film shape along the inner wall surface of the gate trench 142 so that a concave space is defined in the gate trench 142. The gate insulating layer 148 includes a first region 148a, a second region 148b, and a third region 148c.
The first region 148a is formed along the sidewall of the gate trench 142. The second region 148b is formed along the bottom wall of the gate trench 142. Third region 148c is formed along first main surface 103 of SiC semiconductor layer 102. The third region 148c of the gate insulating layer 148 forms a part of the main surface insulating layer 113.

The thickness Ta of the first region 148a is smaller than the thickness Tb of the second region 148b and the thickness Tc of the third region 148c. The ratio Tb / Ta of the thickness Tb of the second region 148b to the thickness Ta of the first region 148a may be 2 or more and 5 or less. The ratio T3 / Ta of the thickness Tc of the third region 148c to the thickness Ta of the first region 148a may be 2 or more and 5 or less.
The thickness Ta of the first region 148a may be 0.01 μm or more and 0.2 μm or less. The thickness Tb of the second region 148b may be 0.05 μm or more and 0.5 μm or less. The thickness Tc of the third region 148c may be 0.05 μm or more and 0.5 μm or less.

  By thinning the first region 148a of the gate insulating layer 148, it is possible to suppress an increase in carriers induced in the region of the body region 141 near the sidewall of each gate trench 142. This can suppress an increase in channel resistance. By thickening the second region 148b of the gate insulating layer 148, the electric field concentration on the bottom wall of each gate trench 142 can be relaxed.

By thickening the third region 148c of the gate insulating layer 148, the breakdown voltage of the gate insulating layer 148 near the opening edge portion 146 of each gate trench 142 can be improved. Further, by making the third region 148c thick, it is possible to suppress the third region 148c from disappearing by the etching method.
This can prevent the first region 148a from being removed by the etching method due to the disappearance of the third region 148c. As a result, gate electrode layer 149 can be appropriately opposed to SiC semiconductor layer 102 (body region 141) with gate insulating layer 148 interposed therebetween.

The gate insulating layer 148 further includes a bulging portion 148d that bulges toward the inside of each gate trench 142 at the opening edge portion 146 of each gate trench 142. The bulging portion 148d is formed at a corner portion that connects the first region 148a and the third region 148c of the gate insulating layer 148.
The bulging portion 148d projects inwardly toward each gate trench 142 in a convex curved shape. The bulging portion 148d narrows the opening of each gate trench 142 at the opening edge portion 146 of each gate trench 142.

The bulging portion 148d improves the withstand voltage of the gate insulating layer 148 at the opening edge portion 146. Of course, the gate insulating layer 148 having no bulged portion 148d may be formed. In addition, the gate insulating layer 148 having a uniform thickness may be formed.
The gate electrode layer 149 is embedded in each gate trench 142 with the gate insulating layer 148 interposed therebetween. More specifically, the gate electrode layer 149 is embedded in the concave space defined by the gate insulating layer 148 in each gate trench 142. The gate electrode layer 149 is controlled by the gate voltage.

The gate electrode layer 149 has an upper end portion located on the opening side of each gate trench 142. The upper end portion of the gate electrode layer 149 is formed in a concave curved shape that is recessed toward the bottom wall of each gate trench 142. The upper end portion of the gate electrode layer 149 has a constricted portion constricted along the bulging portion 148d of the gate insulating layer 148.
The cross-sectional area of the gate electrode layer 149 (cross-sectional area orthogonal to the direction in which each gate trench 142 extends) may be 0.05 μm ² or more and 0.5 μm ² or less. The cross-sectional area of the gate electrode layer 149 is defined by the product of the depth of the gate electrode layer 149 and the width of the gate electrode layer 149.

  The depth of the gate electrode layer 149 is the distance from the upper end portion to the lower end portion of the gate electrode layer 149. The width of the gate electrode layer 149 is the width of the gate trench 142 at an intermediate position between the upper end portion and the lower end portion of the gate electrode layer 149. When the upper end portion is a curved surface (concave curved shape in this embodiment), the position of the upper end portion of the gate electrode layer 149 is an intermediate position in the depth direction on the upper surface of the gate electrode layer 149.

The gate electrode layer 149 includes p-type polysilicon to which p-type impurities are added. The p-type impurity of the gate electrode layer 149 may include at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga).
The p-type impurity concentration of the gate electrode layer 149 is equal to or higher than the p-type impurity concentration of the body region 141. More specifically, the p-type impurity concentration of gate electrode layer 149 is higher than the p-type impurity concentration of body region 141.

The p-type impurity concentration of the gate electrode layer 149 may be 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²² cm ⁻³ or less. The sheet resistance of the gate electrode layer 149 may be 10 Ω / □ or more and 500 Ω / □ or less (about 200 Ω / □ in this embodiment).
Referring to FIGS. 18 and 20, gate wiring layer 150 is formed in active region 111. The gate wiring layer 150 is electrically connected to the gate pad 116 and the gate fingers 117 and 118. In FIG. 20, the gate wiring layer 150 is shown by hatching.

Gate wiring layer 150 is formed on first main surface 103 of SiC semiconductor layer 102. More specifically, the gate wiring layer 150 is formed on the third region 148c of the gate insulating layer 148.
The gate wiring layer 150 is formed along the outer gate finger 117 in this embodiment. More specifically, gate wiring layer 150 is formed along three side surfaces 105A, 105B, 105D of SiC semiconductor layer 102 so as to partition the inner region of active region 111 from three directions.

  The gate wiring layer 150 is connected to the gate electrode layer 149 exposed from the contact trench portion 144 of each gate trench 142. In this embodiment, the gate wiring layer 150 is formed by the lead portion of the gate electrode layer 149 that is led from each gate trench 142 onto the first main surface 103 of the SiC semiconductor layer 102. The upper end of the gate wiring layer 150 is connected to the upper end of the gate electrode layer 149.

With reference to FIGS. 18, 19 and 21, a plurality of source trenches 155 are formed in first main surface 103 of SiC semiconductor layer 102 in active region 111. Each source trench 155 is formed in a region between two adjacent gate trenches 142.
The plurality of source trenches 155 are each formed in a strip shape extending along the first direction X (m-axis direction of SiC single crystal). The plurality of source trenches 155 are formed in a stripe shape as a whole in a plan view. The pitch between the central portions of the source trenches 155 adjacent to each other in the second direction Y may be 1.5 μm or more and 3 μm or less.

Each source trench 155 penetrates the body region 141 and reaches the SiC epitaxial layer 107. Each source trench 155 includes a sidewall and a bottom wall. The side wall forming the long side of each source trench 155 is formed by the a-plane of the SiC single crystal. The side wall forming the short side of each source trench 155 is formed by the m-plane of SiC single crystal.
The sidewall of each source trench 155 may extend along the normal direction Z. The side wall of each source trench 155 may be formed substantially perpendicular to first main surface 103 of SiC semiconductor layer 102.

The angle formed by the sidewall of each source trench 155 in SiC semiconductor layer 102 with respect to first main surface 103 of SiC semiconductor layer 102 may be 90 ° or more and 95 ° or less (for example, 91 ° or more and 93 ° or less). .. Each source trench 155 may be formed in a tapered shape in which the opening area on the bottom wall side is smaller than the opening area on the opening side in a cross-sectional view.
The bottom wall of each source trench 155 is located in the SiC epitaxial layer 107. More specifically, the bottom wall of each source trench 155 is located in the high concentration region 108 of the SiC epitaxial layer 107. More specifically, the bottom wall of each source trench 155 is located in a region between the bottom wall of each gate trench 142 and the low concentration region 109.

The bottom wall of each source trench 155 faces the c-plane of the SiC single crystal. The bottom wall of each source trench 155 has an off angle θ inclined in the [11-20] direction with respect to the c-plane of the SiC single crystal.
The bottom wall of each source trench 155 may be formed parallel to first main surface 103 of SiC semiconductor layer 102. Of course, the bottom wall of each source trench 155 may be formed in a convex curve shape toward the second main surface 104 of the SiC semiconductor layer 102.

The depth of each source trench 155 is equal to or greater than the depth of each gate trench 142 in this embodiment. More specifically, the depth of each source trench 155 is larger than the depth of each gate trench 142.
The bottom wall of each source trench 155 is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142. Of course, the depth of each source trench 155 may be equal to the depth of each gate trench 142.

In the normal direction Z, the depth of each source trench 155 may be 0.5 μm or more and 10 μm or less (for example, about 2 μm). The ratio of the depth of each source trench 155 to the depth of each gate trench 142 may be 1.5 or more. The ratio of the depth of each source trench 155 to the depth of each gate trench 142 is preferably 2 or more.
The first-direction width of each source trench 155 may be substantially equal to the first-direction width of each gate trench 142. The width of each source trench 155 in the first direction may be greater than or equal to the width of each gate trench 142 in the first direction. The width of each source trench 155 in the first direction may be 0.1 μm or more and 2 μm or less (for example, about 0.5 μm).

A source insulating layer 156 and a source electrode layer 157 are formed in each source trench 155. In FIG. 18, the source insulating layer 156 and the source electrode layer 157 are indicated by hatching.
The source insulating layer 156 is made of at least one of silicon oxide (SiO ₂ ), silicon nitride (SiN), aluminum oxide (Al ₂ O ₃ ), zirconium oxide (ZrO ₂ ), and tantalum oxide (Ta ₂ O ₃ ). Including.

Source insulating layer 156 may have a stacked structure including a SiN layer and a SiO ₂ layer stacked in this order from the first main surface 103 side of SiC semiconductor layer 102. Source insulating layer 156 may have a laminated structure including a SiO ₂ layer and a SiN layer, which are laminated in this order from the first main surface 103 side of SiC semiconductor layer 102. The source insulating layer 156 may have a single layer structure including a SiO ₂ layer or a SiN layer. In this embodiment, the source insulating layer 156 has a single layer structure made of a SiO ₂ layer.

The source insulating layer 156 is formed in a film shape along the inner wall surface of each source trench 155 so that a concave space is defined in each source trench 155. The source insulating layer 156 includes a first region 156a and a second region 156b.
The first region 156a is formed along the sidewall of each source trench 155. The second region 156b is formed along the bottom wall of each source trench 155. The thickness Tsa of the first region 156a is smaller than the thickness Tsb of the second region 156b.

The ratio Tsb / Tsa of the thickness Tsb of the second region 156b to the thickness Tsa of the first region 156a may be 2 or more and 5 or less. The thickness Tsa of the first region 156a may be 0.01 μm or more and 0.2 μm or less. The thickness Tsb of the second region 156b may be 0.05 μm or more and 0.5 μm or less.
The thickness Tsa of the first region 156a may be substantially equal to the thickness Ta of the first region 156a of the gate insulating layer 148. The thickness Tsb of the second region 156b may be substantially equal to the thickness Tb of the second region 156b of the gate insulating layer 148. Of course, the source insulating layer 156 having a uniform thickness may be formed.

The source electrode layer 157 is embedded in each source trench 155 with the source insulating layer 156 interposed therebetween. More specifically, the source electrode layer 157 is embedded in the concave space defined by the source insulating layer 156 in each source trench 155. The source electrode layer 157 is controlled by the source voltage.
The source electrode layer 157 has an upper end portion located on the opening side of each source trench 155. The upper end of source electrode layer 157 is formed below first main surface 103 of SiC semiconductor layer 102. The upper end portion of source electrode layer 157 may be located above first main surface 103 of SiC semiconductor layer 102.

The upper end portion of the source electrode layer 157 is formed in a concave curve shape that is recessed toward the bottom wall of each source trench 155. The upper end portion of source electrode layer 157 may be formed parallel to first main surface 103 of SiC semiconductor layer 102.
The upper end portion of the source electrode layer 157 may project higher than the upper end portion of the source insulating layer 156. The upper end portion of the source electrode layer 157 may be located below the upper end portion of the source insulating layer 156. The thickness of the source electrode layer 157 may be 0.5 μm or more and 10 μm or less (for example, about 1 μm).

The source electrode layer 157 preferably contains polysilicon having a property similar to that of SiC. This can reduce the stress generated in the SiC semiconductor layer 102. In this form, the source electrode layer 157 includes p-type polysilicon to which p-type impurities have been added. In this case, the source electrode layer 157 can be formed at the same time as the gate electrode layer 149.
The p-type impurity concentration of the source electrode layer 157 is equal to or higher than the p-type impurity concentration of the body region 141. More specifically, the p-type impurity concentration of source electrode layer 157 is higher than the p-type impurity concentration of body region 141. The p-type impurity of the source electrode layer 157 may include at least one of boron (B), aluminum (Al), indium (In), or gallium (Ga).

The p-type impurity concentration of the source electrode layer 157 may be 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²² cm ⁻³ or less. The sheet resistance of the source electrode layer 157 may be 10 Ω / □ or more and 500 Ω / □ or less (about 200 Ω / □ in this embodiment).
The p-type impurity concentration of the source electrode layer 157 may be substantially equal to the p-type impurity concentration of the gate electrode layer 149. The sheet resistance of the source electrode layer 157 may be substantially equal to the sheet resistance of the gate electrode layer 149.

The source electrode layer 157 may include n-type polysilicon instead of or in addition to p-type polysilicon. The source electrode layer 157 may include at least one of tungsten, aluminum, copper, an aluminum alloy, or a copper alloy instead of or in addition to p-type polysilicon.
As described above, the SiC semiconductor device 101 has the plurality of trench gate structures 161 and the plurality of trench source structures 162. Each trench gate structure 161 includes a gate trench 142, a gate insulating layer 148, and a gate electrode layer 149. Each trench source structure 162 includes a source trench 155, a source insulating layer 156 and a source electrode layer 157.

In the surface layer portion of the body region 141, an n ⁺ type source region 163 is formed in a region along the side wall of each gate trench 142. The n-type impurity concentration of the source region 163 may be 1.0 × 10 ¹⁸ cm ⁻³ or more and 1.0 × 10 ²¹ cm ⁻³ or less. The n-type impurity of the source region 163 may be phosphorus (P).
A plurality of source regions 163 are formed along the sidewall on one side and the sidewall on the other side of each gate trench 142. Each of the plurality of source regions 163 is formed in a strip shape extending along the first direction X.

The plurality of source regions 163 are formed in a stripe shape as a whole in a plan view. Each source region 163 is exposed from the side wall of each gate trench 142 and the side wall of each source trench 155.
Thus, in the region along the sidewall of the gate trench 142 in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102, the source region from the first main surface 103 of the SiC semiconductor layer 102 toward the second main surface 104. 163, body region 141, and drift region 135 are formed in this order.

In the body region 141, a channel of the MISFET is formed in a region along the side wall of the gate trench 142. The channel is formed in the region along the sidewall of the gate trench 142 facing the a-plane of the SiC single crystal. ON / OFF of the channel is controlled by the gate electrode layer 149.
In the active region 111, a plurality of p ⁺ type contact regions 164 are formed in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. Each contact region 164 is formed in a region between two gate trenches 142 adjacent to each other in plan view. Each contact region 164 is formed in a region opposite to the gate trench 142 with respect to each source region 163.

Each contact region 164 is formed along the inner wall of each source trench 155. In this form, a plurality of contact regions 164 are formed along the inner wall of each source trench 155 with a space. Each contact region 164 is formed at a distance from each gate trench 142.
The p-type impurity concentration of each contact region 164 is higher than the p-type impurity concentration of the body region 141. The p-type impurity concentration of each contact region 164 may be 1.0 × 10 ¹⁸ cm ⁻³ or more and 1.0 × 10 ²¹ cm ⁻³ or less. The p-type impurity of each contact region 164 may be aluminum (Al).

Each contact region 164 covers the side wall and bottom wall of each source trench 155. The bottom of each contact region 164 may be formed parallel to the bottom wall of each source trench 155. More specifically, each contact region 164 integrally includes a first surface layer region 164a, a second surface layer region 164b, and an inner wall region 164c.
The first surface layer region 164a covers one side wall of the source trench 155 in the surface layer portion of the body region 141. The first surface layer region 164a is electrically connected to the body region 141 and the source region 163.

First surface layer region 164a is located in a region on the first main surface 103 side of SiC semiconductor layer 102 with respect to the bottom of source region 163. In this embodiment, first surface layer region 164a has a bottom portion extending parallel to first main surface 103 of SiC semiconductor layer 102.
In this embodiment, the bottom of the first surface layer region 164a is located in the region between the bottom of the body region 141 and the bottom of the source region 163. The bottom of first surface layer region 164a may be located in a region between first main surface 103 of SiC semiconductor layer 102 and the bottom of body region 141.

  In this embodiment, the first surface layer region 164a is drawn from the source trench 155 toward the adjacent gate trench 142. The first surface layer region 164a may extend to an intermediate region between the gate trench 142 and the source trench 155. The first surface layer region 164a is formed at a distance from the gate trench 142 to the source trench 155 side.

The second surface layer region 164b covers the other side wall of the source trench 155 in the surface layer portion of the body region 141. The second surface layer region 164b is electrically connected to the body region 141 and the source region 163.
Second surface layer region 164b is located in a region on the first main surface 103 side of SiC semiconductor layer 102 with respect to the bottom of source region 163. In this embodiment, second surface layer region 164b has a bottom portion extending parallel to first main surface 103 of SiC semiconductor layer 102.

In this embodiment, the bottom of the second surface layer region 164b is located in the region between the bottom of the body region 141 and the bottom of the source region 163. The bottom of second surface layer region 164b may be located in a region between first main surface 103 of SiC semiconductor layer 102 and the bottom of body region 141.
In this embodiment, the second surface layer region 164b is drawn out from the other side wall of the source trench 155 toward the adjacent gate trench 142. The second surface layer region 164b may extend to an intermediate region between the source trench 155 and the gate trench 142. The second surface layer region 164b is formed with a space from the gate trench 142 to the source trench 155 side.

  Inner wall region 164c is located in a region on the second main surface 104 side of SiC semiconductor layer 102 with respect to first surface layer region 164a and second surface layer region 164b (bottom portion of source region 163). Inner wall region 164c is formed in the region of SiC semiconductor layer 102 along the inner wall of source trench 155. The inner wall region 164c covers the side wall of the source trench 155.

The inner wall region 164c covers the corner portion connecting the side wall and the bottom wall of the source trench 155. The inner wall region 164c covers the bottom wall of the source trench 155 from the side wall of the source trench 155 through the corner. The bottom of the contact region 164 is formed by the inner wall region 164c.
A plurality of deep well regions 165 are formed in the surface layer portion of the first main surface 103 of the SiC semiconductor layer 102. Each deep well region 165 is also referred to as a breakdown voltage adjusting region (breakdown voltage holding region) for adjusting the breakdown voltage of the SiC semiconductor layer 102 in the active region 111.

Each deep well region 165 is formed in the SiC epitaxial layer 107. More specifically, each deep well region 165 is formed in high concentration region 108 of SiC epitaxial layer 107.
Each deep well region 165 is formed along the inner wall of each source trench 155 so as to cover each contact region 164. Each deep well region 165 is electrically connected to each contact region 164.

Each deep well region 165 is formed in a strip shape extending along each source trench 155 in a plan view. Each deep well region 165 covers the sidewall of each source trench 155.
Each deep well region 165 covers a corner connecting the side wall and the bottom wall of each source trench 155. Each deep well region 165 covers the bottom wall of each source trench 155 from the side wall of each source trench 155 through a corner. Each deep well region 165 is continuous with the body region 141 on the side wall of each source trench 155.

Each deep well region 165 has a bottom portion located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142. The bottom of each deep well region 165 may be formed parallel to the bottom wall of each source trench 155.
The p-type impurity concentration of each deep well region 165 may be substantially equal to the p-type impurity concentration of the body region 141. The p-type impurity concentration of each deep well region 165 may exceed the p-type impurity concentration of the body region 141. The p-type impurity concentration of each deep well region 165 may be less than the p-type impurity concentration of the body region 141.

The p-type impurity concentration of each deep well region 165 may be equal to or lower than the p-type impurity concentration of the contact region 164. The p-type impurity concentration of each deep well region 165 may be less than the p-type impurity concentration of the contact region 164. The p-type impurity concentration of each deep well region 165 may be 1.0 × 10 ¹⁷ cm ⁻³ or more and 1.0 × 10 ¹⁹ cm ⁻³ or less.

  Each deep well region 165 forms a pn junction with the SiC semiconductor layer 102 (high concentration region 108 of the SiC epitaxial layer 107). From this pn junction, the depletion layer spreads toward the region between the plurality of gate trenches 142 adjacent to each other. The depletion layer extends toward the region on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142.

The depletion layer extending from each deep well region 165 may overlap the bottom wall of each gate trench 142. A depletion layer extending from the bottom of each deep well region 165 may overlap the bottom wall of each gate trench 142.
18 and 20, a p-type peripheral deep well region 166 is formed in the peripheral portion of active region 111. The peripheral deep well region 166 is formed in the SiC epitaxial layer 107. More specifically, peripheral deep well region 166 is formed in high concentration region 108 of SiC epitaxial layer 107.

The peripheral deep well region 166 is electrically connected to each deep well region 165. The peripheral deep well region 166 has the same potential as each deep well region 165. The peripheral deep well region 166 is integrally formed with each deep well region 165 in this embodiment.
More specifically, the peripheral deep well region 166 is formed in a region along the inner wall of the contact trench portion 144 of each gate trench 142 in the peripheral portion of the active region 111.

The peripheral deep well region 166 covers the side wall of the contact trench portion 144 of each gate trench 142. The peripheral deep well region 166 covers a corner portion that connects the side wall and the bottom wall of each contact trench portion 144.
The peripheral deep well region 166 covers the bottom wall of each contact trench portion 144 from the side wall of each contact trench portion 144 through the corner. Each deep well region 165 is continuous with the body region 141 on the side wall of each contact trench portion 144. The bottom of the peripheral deep well region 166 is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each contact trench 144.

The peripheral deep well region 166 overlaps the gate wiring layer 150 in a plan view. The peripheral deep well region 166 faces the gate wiring layer 150 with the gate insulating layer 148 (third region 148c) interposed therebetween.
The peripheral deep well region 166 includes a lead portion 166 a drawn from each contact trench portion 144 to each active trench portion 143. The lead portion 166a is formed in the high concentration region 108 of the SiC epitaxial layer 107. The lead portion 166a extends along the side wall of each active trench portion 143 and covers the bottom wall of the active trench portion 143 through the corner portion.

The lead portion 166a covers the side wall of the active trench portion 143 of each gate trench 142. The lead portion 166a covers a corner portion that connects the side wall and the bottom wall of each active trench portion 143.
The lead portion 166a covers the bottom wall of each active trench portion 143 from the side wall of each active trench portion 143 through the corner. The lead portion 166a is continuous with the body region 141 on the side wall of each active trench portion 143. The bottom portion of lead portion 166a is located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom wall of each active trench portion 143.

The p-type impurity concentration of the peripheral deep well region 166 may be substantially equal to the p-type impurity concentration of the body region 141. The p-type impurity concentration of the peripheral deep well region 166 may exceed the p-type impurity concentration of the body region 141. The p-type impurity concentration of the peripheral deep well region 166 may be less than the p-type impurity concentration of the body region 141.
The p-type impurity concentration of the peripheral deep well region 166 may be substantially equal to the p-type impurity concentration of each deep well region 165. The p-type impurity concentration of the peripheral deep well region 166 may exceed the p-type impurity concentration of each deep well region 165. The p-type impurity concentration of the peripheral deep well region 166 may be less than the p-type impurity concentration of each deep well region 165.

The p-type impurity concentration of the peripheral deep well region 166 may be equal to or lower than the p-type impurity concentration of the contact region 164. The p-type impurity concentration of the peripheral deep well region 166 may be less than the p-type impurity concentration of the contact region 164. The p-type impurity concentration of the peripheral deep well region 166 may be 1.0 × 10 ¹⁷ cm ⁻³ or more and 1.0 × 10 ¹⁹ cm ⁻³ or less.

In the SiC semiconductor device including only the pn junction diode, the problem of electric field concentration in the SiC semiconductor layer 102 is small because of the structure in which the trench is not provided. Each deep well region 165 (peripheral deep well region 166) brings the trench gate type MISFET close to the structure of a pn junction diode.
Thereby, in the trench gate type MISFET, the electric field in the SiC semiconductor layer 102 can be relaxed. Therefore, narrowing the pitch between the plurality of deep well regions 165 adjacent to each other is effective in alleviating the electric field concentration.

Further, according to each deep well region 165 having a bottom portion on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142, the depletion layer appropriately concentrates the electric field on each gate trench 142. Can be relaxed.
The distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102 is preferably substantially constant. Accordingly, it is possible to suppress variation in the distance between the bottom of each deep well region 165 and second main surface 104 of SiC semiconductor layer 102.

Therefore, the withstand voltage (for example, breakdown withstand amount) of SiC semiconductor layer 102 can be suppressed from being limited by the form of each deep well region 165, and thus the withstand voltage can be appropriately improved.
In this form, the high concentration region 108 of the SiC epitaxial layer 107 is interposed in the region between the plurality of deep well regions 165 adjacent to each other. Thereby, the JFET (Junction Field Effect Transistor) resistance can be reduced in the region between the plurality of deep well regions 165 adjacent to each other.

  Further, in this embodiment, the bottom of each deep well region 165 is located in the high concentration region 108 of the SiC epitaxial layer 107. Thereby, the current path can be extended from the bottom of each deep well region 165 in the lateral direction parallel to the first main surface 103 of the SiC semiconductor layer 102. As a result, the current spreading resistance can be reduced. The low concentration region 109 of the SiC epitaxial layer 107 increases the breakdown voltage of the SiC semiconductor layer 102 in such a structure.

  By forming the source trench 155, p-type impurities can be introduced into the inner wall of the source trench 155. As a result, since the deep well regions 165 can be conformally formed with respect to the source trench 155, it is possible to appropriately suppress the occurrence of variations in the depth of the deep well regions 165. Further, by using each source trench 155, each deep well region 165 can be appropriately formed in a relatively deep region of the SiC semiconductor layer 102.

With reference to FIG. 21, a low resistance electrode layer 167 is formed on the gate electrode layer 149. The low resistance electrode layer 167 covers the upper end portion of the gate electrode layer 149 in each gate trench 142.
The low-resistance electrode layer 167 includes a conductive material having a sheet resistance lower than that of the gate electrode layer 149. The sheet resistance of the low resistance electrode layer 167 may be 0.01 Ω / □ or more and 10 Ω / □ or less.

  The low resistance electrode layer 167 is formed in a film shape. The low-resistance electrode layer 167 has a connection portion 167a which is in contact with the upper end portion of the gate electrode layer 149 and a non-connection portion 167b which is the opposite thereof. The connecting portion 167a and the non-connecting portion 167b of the low resistance electrode layer 167 may be formed in a concave curved shape along the upper end portion of the gate electrode layer 149. The connection portion 167a and the non-connection portion 167b of the low resistance electrode layer 167 can take various forms.

The entire connection portion 167a of the low resistance electrode layer 167 may be located above the first main surface 103 of the SiC semiconductor layer 102. The entire connection portion 167a of the low resistance electrode layer 167 may be located below the first main surface 103 of the SiC semiconductor layer 102.
The connection portion 167a of the low resistance electrode layer 167 may include a portion located above the first main surface 103 of the SiC semiconductor layer 102. Connection portion 167a of low resistance electrode layer 167 may include a portion located below first main surface 103 of SiC semiconductor layer 102.

For example, the central portion of the connection portion 167a of the low resistance electrode layer 167 is located below the first main surface 103 of the SiC semiconductor layer 102, and the peripheral portion of the connection portion 167a of the low resistance electrode layer 167 is the SiC semiconductor layer 102. It may be located above the first main surface 103.
The entire non-connection portion 167b of low resistance electrode layer 167 may be located above first main surface 103 of SiC semiconductor layer 102. The entire non-connection portion 167b of the low resistance electrode layer 167 may be located below the first main surface 103 of the SiC semiconductor layer 102.

The non-connection portion 167b of the low resistance electrode layer 167 may include a portion located above the first main surface 103 of the SiC semiconductor layer 102. The non-connection portion 167b of the low resistance electrode layer 167 may include a portion located below the first main surface 103 of the SiC semiconductor layer 102.
For example, the central portion of the non-connection portion 167b of the low resistance electrode layer 167 is located below the first main surface 103 of the SiC semiconductor layer 102, and the peripheral portion of the non-connection portion 167b of the low resistance electrode layer 167 is the SiC semiconductor layer. It may be located above the first main surface 103 of 102.

The low-resistance electrode layer 167 has an edge portion 167c which is in contact with the gate insulating layer 148. The edge portion 167c of the low resistance electrode layer 167 is in contact with a corner portion connecting the first region 148a and the second region 148b in the gate insulating layer 148.
The edge portion 167c of the low resistance electrode layer 167 is in contact with the third region 148c of the gate insulating layer 148. More specifically, the edge portion 167c of the low resistance electrode layer 167 is in contact with the bulging portion 148d of the gate insulating layer 148.

The edge portion 167c of the low resistance electrode layer 167 is formed in a region on the first main surface 103 side of the SiC semiconductor layer 102 with respect to the bottom portion of the source region 163. The edge portion 167c of the low resistance electrode layer 167 is formed in a region closer to the first main surface 103 of the SiC semiconductor layer 102 than a boundary region between the body region 141 and the source region 163.
Therefore, the edge portion 167c of the low-resistance electrode layer 167 faces the source region 163 with the gate insulating layer 148 interposed therebetween. The edge portion 167c of the low resistance electrode layer 167 does not face the body region 141 with the gate insulating layer 148 interposed therebetween.

Accordingly, it is possible to suppress the formation of a current path in the region of the gate insulating layer 148 between the low resistance electrode layer 167 and the body region 141. The current path may be formed by undesired diffusion of the electrode material of the low resistance electrode layer 167 with respect to the gate insulating layer 148.
In particular, the design in which the edge portion 167c of the low resistance electrode layer 167 is connected to the third region 148c (corner portion of the gate insulating layer 148) of the relatively thick gate insulating layer 148 reduces the risk of forming a current path. Effective above.

  With respect to the normal direction Z, the total thickness Tall of the low resistance electrode layer 167 is equal to or less than the thickness TG of the gate electrode layer 149 (Tr ≦ TG). The total thickness Tall of the low resistance electrode layer 167 is preferably less than the thickness TG of the gate electrode layer 149 (Tr <TG). More specifically, the total thickness Tall of the low-resistance electrode layer 167 is more preferably half or less of the thickness TG of the gate electrode layer 149 (Tr ≦ TG / 2).

The ratio Tr / TG of the total thickness Tall of the low resistance electrode layer 167 to the thickness TG of the gate electrode layer 149 is 0.01 or more and 1 or less. The thickness TG of the gate electrode layer 149 may be 0.5 μm or more and 3 μm or less. The total thickness Tall of the low resistance electrode layer 167 may be 0.01 μm or more and 3 μm or less.
The current supplied in each gate trench 142 flows through the low resistance electrode layer 167 having a relatively low sheet resistance and is transmitted to the entire gate electrode layer 149. Accordingly, the entire gate electrode layer 149 (the entire area of the active region 111) can be quickly changed from the off state to the on state, so that delay in switching response can be suppressed.

In particular, in the case of the gate trench 142 having a length on the order of millimeters (length of 1 mm or more), it takes time to transmit the current, but the low resistance electrode layer 167 can appropriately suppress the delay of the switching response. .. That is, the low resistance electrode layer 167 is formed as a current diffusion electrode layer that diffuses a current in each gate trench 142.
Further, as the cell structure becomes finer, the width, depth, cross-sectional area, and the like of the gate electrode layer 149 become smaller, so that there is a concern that the switching response may be delayed due to the increase in the electrical resistance in each gate trench 142. ..

However, according to the low-resistance electrode layer 167, the entire gate electrode layer 149 can be quickly changed from the off state to the on state, so that delay in switching response due to miniaturization can be appropriately suppressed.
20, the low resistance electrode layer 167 also covers the upper end portion of the gate wiring layer 150 in this embodiment. The portion of the low resistance electrode layer 167 that covers the upper end portion of the gate wiring layer 150 is integrally formed with the portion of the low resistance electrode layer 167 that covers the upper end portion of the gate electrode layer 149. Thus, the low resistance electrode layer 167 covers the entire area of the gate electrode layer 149 and the entire area of the gate wiring layer 150.

Therefore, the current supplied from the gate pad 116 and the gate fingers 117 and 118 to the gate wiring layer 150 is supplied to the entire gate electrode layer 149 and the gate wiring layer 150 via the low resistance electrode layer 167 having a relatively low sheet resistance. Transmitted.
Accordingly, the entire gate electrode layer 149 (the entire area of the active region 111) can be quickly switched from the off state to the on state through the gate wiring layer 150, and thus the delay of the switching response can be suppressed.

Particularly, in the case of the gate trench 142 having a length on the order of millimeters, the delay of the switching response can be appropriately suppressed by the low resistance electrode layer 167 covering the upper end portion of the gate wiring layer 150.
The low resistance electrode layer 167 includes a polycide layer. The polycide layer is formed by silicidizing a portion of the gate electrode layer 149 forming the surface layer portion with a metal material. More specifically, the polycide layer is composed of a p-type polycide layer containing a p-type impurity added to the gate electrode layer 149 (p-type polysilicon). The polycide layer preferably has a specific resistance of 10 μΩ · cm or more and 110 μΩ · cm or less.

The sheet resistance in the gate trench 142 in which the gate electrode layer 149 and the low resistance electrode layer 167 are embedded is not more than the sheet resistance of the gate electrode layer 149 alone. The sheet resistance in the gate trench 142 is preferably less than or equal to the sheet resistance of n-type polysilicon doped with n-type impurities.
The sheet resistance in the gate trench 142 is similar to the sheet resistance of the low resistance electrode layer 167. That is, the sheet resistance in the gate trench 142 may be 0.01 Ω / □ or more and 10 Ω / □ or less. The sheet resistance in the gate trench 142 is preferably less than 10Ω / □.

The low resistance electrode layer 167 may include at least one of TiSi, TiSi ₂ , NiSi, CoSi, CoSi ₂ , MoSi ₂ or WSi ₂ . Among these, NiSi, CoSi ₂ and TiSi ₂ among these species are suitable as a polycide layer forming the low resistance electrode layer 167, since their specific resistance values and temperature dependences are relatively small.
Source sub-trench 168 communicating with each source trench 155 is formed in a region along the upper end of source electrode layer 157 on first main surface 103 of SiC semiconductor layer 102. The source sub-trench 168 forms a part of the side wall of each source trench 155.

In this form, the source sub-trench 168 is formed in an endless shape (square ring shape in this form) surrounding the upper end of the source electrode layer 157 in a plan view. The source sub-trench 168 borders the upper end of the source electrode layer 157.
The source sub-trench 168 is formed by digging a part of the source insulating layer 156. More specifically, source sub-trench 168 is formed by digging the upper end portion of source insulating layer 156 and the upper end portion of source electrode layer 157 from first main surface 103 of SiC semiconductor layer 102.

The upper end portion of the source electrode layer 157 has a shape that is narrowed inward with respect to the lower end portion of the source electrode layer 157. The lower end portion of the source electrode layer 157 is a portion of the source electrode layer 157 located on the bottom wall side of each source trench 155. The width of the upper end of the source electrode layer 157 in the first direction may be smaller than the width of the lower end of the source electrode layer 157 in the first direction.
The source sub-trench 168 is formed in a tapered shape in which the bottom area is smaller than the opening area in cross-sectional view. The bottom wall of source sub-trench 168 may be formed in a convex curve shape toward second main surface 104 of SiC semiconductor layer 102.

The source region 163, the contact region 164, the source insulating layer 156, and the source electrode layer 157 are exposed from the inner wall of the source sub-trench 168. The first surface layer region 164a and the second surface layer region 164b of the contact region 164 are exposed from the inner wall of the source sub-trench 168.
At least the first region 156a of the source insulating layer 156 is exposed from the bottom wall of the source sub-trench 168. In the source insulating layer 156, the upper end of the first region 156a is located below the first main surface 103 of the SiC semiconductor layer 102.

  The opening edge portion 169 of each source trench 155 includes an inclined portion 170 that is inclined downward from the first main surface 103 of the SiC semiconductor layer 102 toward the inside of each source trench 155. The opening edge portion 169 of each source trench 155 is a corner portion that connects the first main surface 103 of the SiC semiconductor layer 102 and the side wall of each source trench 155. The inclined portion 170 of each source trench 155 is formed by the source sub-trench 168.

In this form, the inclined portion 170 is formed in a concave curve shape that is directed inward of the SiC semiconductor layer 102. The inclined portion 170 may be formed in a convex curve shape that is directed inward of the source sub-trench 168. The sloped portion 170 relaxes electric field concentration on the opening edge portion 169 of each source trench 155.
22 and 23, active region 111 has an active main surface 171 forming a part of first main surface 103 of SiC semiconductor layer 102. The outer region 112 has an outer main surface 172 that forms a part of the first main surface 103 of the SiC semiconductor layer 102. The outer main surface 172 is connected to the side surfaces 105A to 105D of the SiC semiconductor layer 102 in this embodiment.

Active main surface 171 and outer main surface 172 face the c-plane of the SiC single crystal, respectively. Further, active main surface 171 and outer main surface 172 each have an off-angle θ that is inclined in the [11-20] direction with respect to the c-plane of the SiC single crystal.
Outer main surface 172 is located closer to second main surface 104 of SiC semiconductor layer 102 than active main surface 171. In this embodiment, outer region 112 is formed by digging first main surface 103 of SiC semiconductor layer 102 toward second main surface 104. Therefore, outer main surface 172 is formed in a region recessed to second main surface 104 side of SiC semiconductor layer 102 with respect to active main surface 171.

Outer main surface 172 may be located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142. The outer main surface 172 may be formed at a depth position substantially equal to the bottom wall of each source trench 155. The outer main surface 172 may be located substantially flush with the bottom wall of each source trench 155.
The distance between outer main surface 172 and second main surface 104 of SiC semiconductor layer 102 may be substantially equal to the distance between the bottom wall of each source trench 155 and second main surface 104 of SiC semiconductor layer 102.

Outer main surface 172 may be located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom wall of each source trench 155. Outer main surface 172 may be located on the second main surface 104 side of SiC semiconductor layer 102 in the range of 0 μm to 1 μm with respect to the bottom wall of each source trench 155.
The SiC epitaxial layer 107 is exposed from the outer main surface 172. More specifically, high concentration region 108 of SiC epitaxial layer 107 is exposed from outer main surface 172 of outer region 112. Outer main surface 172 faces low-concentration region 109 of SiC epitaxial layer 107 with high-concentration region 108 of SiC epitaxial layer 107 interposed therebetween.

In this form, the active region 111 is divided into a plateau by the outer region 112. The active region 111 is formed as a plate-like active plateau 173 protruding upward from the outer region 112.
Active plateau 173 includes active sidewalls 174 connecting active major surface 171 and outer major surface 172. The active side wall 174 defines a boundary area between the active area 111 and the outer area 112. First main surface 103 of SiC semiconductor layer 102 is formed by active main surface 171, outer main surface 172, and active sidewall 174.

In this embodiment, the active side wall 174 extends along the normal direction Z of the active main surface 171 (outer main surface 172). Active side wall 174 is formed by the m-plane and a-plane of the SiC single crystal.
The active side wall 174 may have an inclined surface that is inclined downward from the active main surface 171 toward the outer main surface 172. The inclination angle of active side wall 174 is an angle formed between active side wall 174 and active main surface 171 in SiC semiconductor layer 102.

  In this case, the inclination angle of the active sidewall 174 may be more than 90 ° and 135 ° or less. The inclination angle of the active sidewall 174 may be more than 90 ° and 95 ° or less, 95 ° or more and 100 ° or less, 100 ° or more and 110 ° or less, 110 ° or more and 120 ° or less, or 120 ° or more and 135 ° or less. The inclination angle of the active side wall 174 is preferably more than 90 ° and not more than 95 °.

The SiC epitaxial layer 107 is exposed from the active sidewall 174. More specifically, high concentration region 108 of SiC epitaxial layer 107 is exposed from active sidewall 174.
At least the body region 141 is exposed from the region of the active side wall 174 on the active main surface 171 side. 22 and 23 show an example in which the body region 141 and the source region 163 are exposed from the active side wall 174.

In the outer region 112, a p ⁺ type diode region 181 (impurity region), a p-type outer deep well region 182, and a p-type are formed on the surface layer portion of the first main surface 103 (outer main surface 172) of the SiC semiconductor layer 102. Field limit structure 183 is formed.
The diode region 181 is formed in the region between the active sidewall 174 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in the outer region 112. The diode region 181 is formed at a distance from the active side wall 174 and the side surfaces 105A to 105D.

The diode region 181 extends in a strip shape along the active region 111 in a plan view. In this form, the diode region 181 is formed in an endless shape (a square ring in this form) surrounding the active region 111 in a plan view.
The diode region 181 overlaps with the source leading wiring 123 in a plan view. The diode region 181 is electrically connected to the source leading wiring 123. The diode region 181 forms part of the avalanche current absorption structure.

The diode region 181 forms a pn junction with the SiC semiconductor layer 102. More specifically, diode region 181 is located in SiC epitaxial layer 107. Therefore, diode region 181 forms a pn junction with SiC epitaxial layer 107.
More specifically, diode region 181 is located in high concentration region 108 of SiC epitaxial layer 107. Therefore, the diode region 181 forms a pn junction with the high concentration region 108. As a result, a pn junction diode Dpn having the diode region 181 as an anode and the SiC semiconductor layer 102 as a cathode is formed.

The entire diode region 181 is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142. The bottom of diode region 181 is located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom wall of each source trench 155.
The bottom of the diode region 181 may be formed at a depth position substantially equal to the bottom of the contact region 164. The bottom of the diode region 181 may be located substantially flush with the bottom of the contact region 164.

The p-type impurity concentration of the diode region 181 is substantially equal to the p-type impurity concentration of the contact region 164. The p-type impurity concentration of the diode region 181 is higher than the p-type impurity concentration of the body region 141. The p-type impurity concentration of the diode region 181 may be 1.0 × 10 ¹⁸ cm ⁻³ or more and 1.0 × 10 ²¹ cm ⁻³ or less.
The outer deep well region 182 is formed in a region between the active sidewall 174 and the diode region 181 in plan view. In this embodiment, the outer deep well region 182 is formed with a space from the active side wall 174 toward the diode region 181 side. The outer deep well region 182 is also referred to as a breakdown voltage adjusting region (breakdown voltage holding region) for adjusting the breakdown voltage of the SiC semiconductor layer 102 in the outer region 112.

The outer deep well region 182 extends in a strip shape along the active region 111 in a plan view. In this form, the outer deep well region 182 is formed in an endless shape (in this form, a square ring) surrounding the active region 111 in a plan view.
The outer deep well region 182 is electrically connected to the source leading wiring 123 via the diode region 181. The outer deep well region 182 may form a part of the pn junction diode Dpn. The outer deep well region 182 may form part of an avalanche current absorption structure.

The entire outer deep well region 182 is located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142. The bottom of outer deep well region 182 is located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom wall of each source trench 155.
The bottom of outer deep well region 182 is located closer to second main surface 104 of SiC semiconductor layer 102 than the bottom of diode region 181. The bottom of the outer deep well region 182 may be formed at a depth position substantially equal to the bottom of each deep well region 165. The bottom of the outer deep well region 182 may be located substantially flush with the bottom of each deep well region 165.

The distance between the bottom of outer deep well region 182 and outer major surface 172 may be approximately equal to the distance between the bottom of each deep well region 165 and the bottom wall of each source trench 155.
The distance between the bottom of the outer deep well region 182 and the second main surface 104 of the SiC semiconductor layer 102 is substantially equal to the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102. Good.

Thereby, the distance between the bottom of the outer deep well region 182 and the second main surface 104 of the SiC semiconductor layer 102, and the distance between the bottom of each deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102. It is possible to suppress the occurrence of variations between the two.
Therefore, it is possible to prevent the breakdown voltage (for example, breakdown withstand amount) of SiC semiconductor layer 102 from being limited by the form of outer deep well region 182 and the form of each deep well region 165, so that the breakdown voltage can be appropriately improved. ..

The bottom of outer deep well region 182 may be located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom of each deep well region 165. The bottom of outer deep well region 182 may be located on the second main surface 104 side of SiC semiconductor layer 102 in the range of 0 μm to 1 μm with respect to the bottom of each deep well region 165.
The inner peripheral edge of the outer deep well region 182 may extend to the vicinity of the boundary region between the active region 111 and the outer region 112. The outer deep well region 182 may cross the boundary region between the active region 111 and the outer region 112.

The inner peripheral edge of the outer deep well region 182 may cover a corner connecting the active sidewall 174 and the outer major surface 172. The inner peripheral edge of the outer deep well region 182 may further extend along the active side wall 174 and be connected to the body region 141.
In this embodiment, the outer peripheral edge of the outer deep well region 182 covers the diode region 181 from the second main surface 104 side of the SiC semiconductor layer 102. The outer deep well region 182 may overlap the source leading wiring 123 in a plan view. The outer peripheral edge of the outer deep well region 182 may be formed with a space from the diode region 181 toward the active sidewall 174 side.

The p-type impurity concentration of the outer deep well region 182 may be equal to or lower than the p-type impurity concentration of the diode region 181. The p-type impurity concentration of the outer deep well region 182 may be lower than the p-type impurity concentration of the diode region 181.
The p-type impurity concentration of the outer deep well region 182 may be substantially equal to the p-type impurity concentration of each deep well region 165. The p-type impurity concentration of the outer deep well region 182 may be substantially equal to the p-type impurity concentration of the body region 141.

The p-type impurity concentration of the outer deep well region 182 may exceed the p-type impurity concentration of the body region 141. The p-type impurity concentration of the outer deep well region 182 may be lower than the p-type impurity concentration of the body region 141.
The p-type impurity concentration of the outer deep well region 182 may be equal to or lower than the p-type impurity concentration of the contact region 164. The p-type impurity concentration of the outer deep well region 182 may be less than the p-type impurity concentration of the contact region 164. The p-type impurity concentration of the outer deep well region 182 may be 1.0 × 10 ¹⁷ cm ⁻³ or more and 1.0 × 10 ¹⁹ cm ⁻³ or less.

Field limit structure 183 is formed in a region between diode region 181 and side surfaces 105A to 105D of SiC semiconductor layer 102 in plan view. In this embodiment, the field limit structure 183 is formed with a space from the side surfaces 105A to 105D toward the diode region 181 side.
The field limit structure 183 includes one or more (for example, 2 or more and 20 or less) field limit regions 184. The field limit structure 183, in this embodiment, includes a field limit region group having a plurality (five) of field limit regions 184A, 184B, 184C, 184D, 184E.

The field limit regions 184A to 184E are formed in this order at intervals along the direction away from the diode region 181. Each of the field limit regions 184A to 184E extends in a strip shape along the peripheral edge of the active region 111 in a plan view.
More specifically, the field limit regions 184A to 184E are each formed in an endless shape (square ring shape in this embodiment) surrounding the active region 111 in a plan view. The field limiting areas 184A to 184E are also referred to as FLR (Field Limiting Ring) areas.

In this embodiment, the bottoms of field limit regions 184A to 184E are located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom of diode region 181.
In this embodiment, the innermost field limit region 184A of the field limit regions 184A to 184E covers the diode region 181 from the second main surface 104 side of the SiC semiconductor layer 102. The field limit region 184A may overlap with the above-mentioned source lead wiring 123 in a plan view.

The field limit region 184A is electrically connected to the source leading wiring 123 via the diode region 181. The field limit region 184A may form a part of the pn junction diode Dpn. The field limit region 184A may form a part of the avalanche current absorption structure.
The entire field limit regions 184A to 184E are located on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the bottom wall of each gate trench 142. The bottoms of field limit regions 184A to 184E are located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottom walls of each source trench 155.

The field limit regions 184A to 184E may be formed at substantially the same depth position as each deep well region 165 (outer deep well region 182). The bottoms of the field limit regions 184A to 184E may be located substantially on the same plane as the bottoms of the deep well regions 165 (outer deep well regions 182).
The bottoms of the field limit regions 184A to 184E may be located on the outer main surface 172 side with respect to the bottoms of the deep well regions 165 (outer deep well regions 182). The bottoms of field limit regions 184A to 184E may be located on the second main surface 104 side of SiC semiconductor layer 102 with respect to the bottoms of each deep well region 165 (outer deep well region 182).

  The widths between the field limit regions 184A to 184E adjacent to each other may be different from each other. The width between the field limit regions 184A to 184E adjacent to each other may increase in the direction away from the active region 111. The width between the field limit regions 184A to 184E adjacent to each other may be smaller in the direction away from the active region 111.

The depths of the field limit regions 184A to 184E may be different from each other. The depth of the field limit regions 184A to 184E may be smaller in the direction away from the active region 111. The depth of the field limit regions 184A to 184E may increase in the direction away from the active region 111.
The p-type impurity concentration of field limit regions 184A to 184E may be equal to or lower than the p-type impurity concentration of diode region 181. The p-type impurity concentration of field limit regions 184A to 184E may be lower than the p-type impurity concentration of diode region 181.

The p-type impurity concentration of field limit regions 184A to 184E may be equal to or lower than the p-type impurity concentration of outer deep well region 182. The p-type impurity concentration of field limit regions 184A to 184E may be lower than the p-type impurity concentration of outer deep well region 182.
The p-type impurity concentration of the field limit regions 184A to 184E may be equal to or higher than the p-type impurity concentration of the outer deep well region 182. The p-type impurity concentration of field limit regions 184A to 184E may be higher than the p-type impurity concentration of outer deep well region 182.

The p-type impurity concentration of the field limit regions 184A to 184E may be 1.0 × 10 ¹⁵ cm ⁻³ or more and 1.0 × 10 ¹⁸ cm ⁻³ or less. It is preferable that the p-type impurity concentration of the diode region 181> the p-type impurity concentration of the outer deep well region 182> the p-type impurity concentration of the field limit regions 184A to 184E.
The field limit structure 183 reduces electric field concentration in the outer region 112. The number, width, depth, p-type impurity concentration, etc. of the field limit regions 184 can take various values depending on the electric field to be relaxed.

In this form, the field limit structure 183 includes the diode region 181 and one or more field limit regions 184 formed in the region between the side surfaces 105A to 105D of the SiC semiconductor layer 102 in plan view.
However, the field limit structure 183 is replaced with the region between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102, and one or more formed in the region between the active sidewall 174 and the diode region 181 in plan view. A plurality of field limit areas 184 may be included.

  The field limit structure 183 includes one or more field limit regions 184 formed in a region between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in plan view, and the active sidewall 174 in plan view. And one or more field limit regions 184 formed in the region between the diode regions 181.

An outer insulating layer 191 is formed on first main surface 103 of SiC semiconductor layer 102 in outer region 112. The outer insulating layer 191 forms a part of the main surface insulating layer 113. The outer insulating layer 191 forms a part of the insulating side surfaces 114A to 114D of the principal surface insulating layer 113.
The outer insulating layer 191 selectively covers the diode region 181, the outer deep well region 182, and the field limit structure 183 in the outer region 112. The outer insulating layer 191 is formed in a film shape along the active sidewall 174 and the outer main surface 172. The outer insulating layer 191 is continuous with the gate insulating layer 148 on the active main surface 171. More specifically, the outer insulating layer 191 is continuous with the third region 148c of the gate insulating layer 148.

The outer insulating layer 191 may include silicon oxide. The outer insulating layer 191 may include another insulating film such as silicon nitride. In this embodiment, the outer insulating layer 191 is formed of the same insulating material species as the gate insulating layer 148.
The outer insulating layer 191 includes a first region 191a and a second region 191b. The first region 191 a of the outer insulating layer 191 covers the active sidewall 174. The second region 191b of the outer insulating layer 191 covers the outer main surface 172.

The thickness of the second region 191b of the outer insulating layer 191 may be equal to or less than the thickness of the first region 191a of the outer insulating layer 191. The thickness of the second region 191b of the outer insulating layer 191 may be less than the thickness of the first region 191a of the outer insulating layer 191.
The thickness of the first region 191a of the outer insulating layer 191 may be substantially equal to the thickness of the first region 191a of the gate insulating layer 148. The thickness of the second region 191b of the outer insulating layer 191 may be substantially equal to the thickness of the third region 148c of the gate insulating layer 148. Of course, the outer insulating layer 191 having a uniform thickness may be formed.

22 and 23, SiC semiconductor device 101 further includes a sidewall 192 covering active sidewall 174. The sidewalls 192 protect and reinforce the active plateau 173 from the outer region 112 side.
In addition, the sidewall 192 forms a step reducing structure that reduces the step formed between the active main surface 171 and the outer main surface 172. When the upper layer structure (covering layer) that covers the boundary region between the active region 111 and the outer region 112 is formed, the upper layer structure covers the sidewall 192. The sidewall 192 enhances the flatness of the upper layer structure.

The sidewall 192 may have an inclined portion 193 that is inclined downward from the active main surface 171 toward the outer main surface 172. The sloped portion 193 can appropriately reduce the step.
The inclined portion 193 of the sidewall 192 may be formed in a concave curve shape toward the SiC semiconductor layer 102 side. The inclined portion 193 of the sidewall 192 may be formed in a convex curve shape that faces the side opposite to the SiC semiconductor layer 102.

The inclined portion 193 of the sidewall 192 may extend in a plane from the active main surface 171 side toward the outer main surface 172 side. The inclined portion 193 of the sidewall 192 may linearly extend from the active main surface 171 side toward the outer main surface 172 side.
The inclined portion 193 of the sidewall 192 may be formed in a stepwise downward shape from the active main surface 171 toward the outer main surface 172. That is, the inclined portion 193 of the sidewall 192 may have one or a plurality of stepped portions that are recessed toward the outer main surface 172 side. The plurality of stepped portions increase the surface area of the inclined portion 193 of the sidewall 192 and enhance the adhesion to the upper layer structure.

The inclined portion 193 of the sidewall 192 may include a plurality of raised portions that are raised toward the outside of the sidewall 192. The plurality of raised portions increase the surface area of the inclined portion 193 of the sidewall 192 and enhance the adhesion to the upper layer structure.
The inclined portion 193 of the sidewall 192 may include a plurality of depressions that are recessed toward the inside of the sidewall 192. The plurality of depressions increase the surface area of the inclined portion 193 of the sidewall 192 and increase the adhesion to the upper layer structure.

The sidewall 192 is formed in self-alignment with the active principal surface 171. More specifically, the side wall 192 is formed along the active side wall 174. In this form, the sidewall 192 is formed in an endless shape (in this form, a square ring) surrounding the active region 111 in a plan view.
The sidewalls 192 preferably include p-type polysilicon doped with p-type impurities. In this case, the sidewall 192 can be formed at the same time as the gate electrode layer 149 and the source electrode layer 157.

  The p-type impurity concentration of the sidewall 192 is equal to or higher than the p-type impurity concentration of the body region 141. More specifically, the p-type impurity concentration of the sidewall 192 is higher than the p-type impurity concentration of the body region 141. The p-type impurity of the sidewall 192 may include at least one of boron (B), aluminum (Al), indium (In), and gallium (Ga).

The p-type impurity concentration of the sidewall 192 may be 1 × 10 ¹⁸ cm ⁻³ or more and 1 × 10 ²² cm ⁻³ or less. The sheet resistance of the sidewall 192 may be 10 Ω / □ or more and 500 Ω / □ or less (about 200 Ω / □ in this embodiment).
The p-type impurity concentration of the sidewall 192 may be substantially equal to the p-type impurity concentration of the gate electrode layer 149. The sheet resistance of the sidewall 192 may be substantially equal to the sheet resistance of the gate electrode layer 149.

The sidewall 192 may include n-type polysilicon instead of or in addition to p-type polysilicon. The sidewall 192 may include at least one of tungsten, aluminum, copper, an aluminum alloy, or a copper alloy instead of or in addition to the p-type polysilicon.
The sidewall 192 may include an insulating material. In this case, the sidewall 192 can enhance the insulating property of the active region 111 with respect to the outer region 112.

  19 to 23, an interlayer insulating layer 201 is formed on first main surface 103 of SiC semiconductor layer 102. The interlayer insulating layer 201 forms a part of the main surface insulating layer 113. The interlayer insulating layer 201 forms a part of the insulating side surfaces 114A to 114D of the principal surface insulating layer 113. The main surface insulating layer 113 has a laminated structure including the gate insulating layer 148 (outer insulating layer 191) and the interlayer insulating layer 201.

The interlayer insulating layer 201 selectively covers the active region 111 and the outer region 112. More specifically, the interlayer insulating layer 201 selectively covers the third region 148c of the gate insulating layer 148 and the outer insulating layer 191.
The interlayer insulating layer 201 is formed in a film shape along the active main surface 171 and the outer main surface 172. The interlayer insulating layer 201 selectively covers the trench gate structure 161, the gate wiring layer 150, and the trench source structure 162 in the active region 111. The interlayer insulating layer 201 selectively covers the diode region 181, the outer deep well region 182, and the field limit structure 183 in the outer region 112.

The interlayer insulating layer 201 is formed along the outer surface (slope 193) of the sidewall 192 in the boundary region between the active region 111 and the outer region 112. The interlayer insulating layer 201 forms a part of the upper layer structure that covers the sidewall 192.
The interlayer insulating layer 201 may include silicon oxide or silicon nitride. The interlayer insulating layer 201 may include PSG (Phosphor Silicate Glass) and / or BPSG (Boron Phosphor Silicate Glass) as an example of silicon oxide.

Interlayer insulating layer 201 may have a laminated structure including a PSG layer and a BPSG layer that are laminated in this order from the first main surface 103 side of SiC semiconductor layer 102. Interlayer insulating layer 201 may have a laminated structure including a BPSG layer and a PSG layer that are laminated in this order from the first main surface 103 side of SiC semiconductor layer 102.
A gate contact hole 202, a source contact hole 203, and a diode contact hole 204 are formed in the interlayer insulating layer 201. An anchor hole 205 is formed in the interlayer insulating layer 201.

The gate contact hole 202 exposes the gate wiring layer 150 in the active region 111. The gate contact hole 202 may be formed in a strip shape along the gate wiring layer 150. The opening edge portion of the gate contact hole 202 is formed in a convex curve shape that extends toward the inside of the gate contact hole 202.
Source contact hole 203 exposes source region 163, contact region 164, and trench source structure 162 in active region 111. The source contact hole 203 may be formed in a band shape along the trench source structure 162 and the like. The opening edge portion of the source contact hole 203 is formed in a convex curve shape that extends toward the inside of the source contact hole 203.

The diode contact hole 204 exposes the diode region 181 in the outer region 112. The diode contact hole 204 may be formed in a strip shape (more specifically, an endless shape) extending along the diode region 181.
The diode contact hole 204 may expose the outer deep well region 182 and / or the field limit structure 183. The opening edge portion of the diode contact hole 204 is formed in a convex curve shape that is directed into the diode contact hole 204.

  The anchor hole 205 is formed by digging the interlayer insulating layer 201 in the outer region 112. The anchor hole 205 is formed in a region between the diode region 181 and the side surfaces 105A to 105D of the SiC semiconductor layer 102 in a plan view. More specifically, anchor hole 205 is formed in a region between field limit structure 183 and side surfaces 105A to 105D of SiC semiconductor layer 102 in plan view.

Anchor hole 205 exposes first main surface 103 (outer main surface 172) of SiC semiconductor layer 102. An opening edge portion of the anchor hole 205 is formed in a convex curve shape that is directed into the anchor hole 205.
With reference to FIG. 17, the anchor hole 205 extends in a strip shape along the active region 111 in a plan view. In this form, the anchor hole 205 is formed in an endless shape (a square ring in this form) surrounding the active region 111 in a plan view.

In this form, one anchor hole 205 is formed in a portion of the interlayer insulating layer 201 that covers the outer region 112. However, a plurality of anchor holes 205 may be formed in the portion of the interlayer insulating layer 201 that covers the outer region 112.
A main surface gate electrode layer 115 and a main surface source electrode layer 121 are formed on the interlayer insulating layer 201. Main surface gate electrode layer 115 and main surface source electrode layer 121 each have a laminated structure including barrier electrode layer 206 and main electrode layer 207 that are laminated in this order from the first main surface 103 side of SiC semiconductor layer 102. ing.

The barrier electrode layer 206 may have a single-layer structure including a titanium layer or a titanium nitride layer. Barrier electrode layer 206 may have a laminated structure including a titanium layer and a titanium nitride layer, which are laminated in this order from the first main surface 103 side of SiC semiconductor layer 102.
The thickness of the main electrode layer 207 is larger than the thickness of the barrier electrode layer 206. The main electrode layer 207 includes a conductive material having a resistance value smaller than that of the barrier electrode layer 206. The main electrode layer 207 may include at least one of aluminum, copper, an aluminum alloy, or a copper alloy.

The main electrode layer 207 may include at least one of an aluminum-silicon alloy, an aluminum-silicon-copper alloy, or an aluminum-copper alloy. The main electrode layer 207 includes an aluminum-silicon-copper alloy in this form.
The outer gate finger 117 of the main surface gate electrode layer 115 enters the gate contact hole 202 from above the interlayer insulating layer 201. The outer gate finger 117 is electrically connected to the gate wiring layer 150 in the gate contact hole 202. Accordingly, the electric signal from the gate pad 116 is transmitted to the gate electrode layer 149 via the outer gate finger 117.

  The source pad 122 of the main surface source electrode layer 121 enters the source contact hole 203 and the source sub-trench 168 from above the interlayer insulating layer 201. The source pad 122 is electrically connected to the source region 163, the contact region 164, and the source electrode layer 157 in the source contact hole 203 and the source sub-trench 168.

The source electrode layer 157 may be formed using a partial region of the source pad 122. The source electrode layer 157 may be formed by a portion of the source pad 122 that has entered each source trench 155.
The source routing wiring 123 of the main surface source electrode layer 121 enters the diode contact hole 204 from above the interlayer insulating layer 201. The source routing wiring 123 is electrically connected to the diode region 181 in the diode contact hole 204.

The source connection portion 124 of the main surface source electrode layer 121 is drawn out from the active region 111 across the sidewall 192 to the outer region 112. The source connection portion 124 forms a part of the upper layer structure that covers the sidewall 192.
The passivation layer 125 described above is formed on the interlayer insulating layer 201. The passivation layer 125 is formed in a film shape along the interlayer insulating layer 201. The passivation layer 125 selectively covers the active region 111 and the outer region 112 via the interlayer insulating layer 201.

The passivation layer 125 is drawn from the active region 111 across the sidewall 192 to the outer region 112. The passivation layer 125 forms a part of the upper layer structure that covers the sidewall 192.
Referring to FIG. 22, passivation layer 125 penetrates into anchor hole 205 from above interlayer insulating layer 201 in outer region 112. The passivation layer 125 is connected to the first main surface 103 (outer main surface 172) of the SiC semiconductor layer 102 in the anchor hole 205. On the outer surface of the passivation layer 125, a recess 211 that is recessed following the anchor hole 205 is formed in a region located above the anchor hole 205.

The resin layer 129 is formed on the passivation layer 125. The resin layer 129 is formed in a film shape along the passivation layer 125. The resin layer 129 selectively covers the active region 111 and the outer region 112 with the passivation layer 125 and the interlayer insulating layer 201 interposed therebetween.
The resin layer 129 extends from the active region 111 across the sidewall 192 to the outer region 112. The resin layer 129 forms a part of the upper layer structure that covers the sidewall 192.

Referring to FIG. 22, resin layer 129 has an anchor portion that has entered recess 211 of passivation layer 125 in outer region 112. Thus, the outer region 112 is provided with an anchor structure for increasing the connection strength of the resin layer 129.
The anchor structure includes an uneven structure (Uneven Structure) formed on the first main surface 103 of the SiC semiconductor layer 102 in the outer region 112. The concavo-convex structure (anchor structure) more specifically includes a concavo-convex formed by utilizing the interlayer insulating layer 201 covering the outer main surface 172. More specifically, the uneven structure (anchor structure) includes anchor holes 205 formed in the interlayer insulating layer 201.

The resin layer 129 meshes with the anchor hole 205. In this embodiment, the resin layer 129 meshes with the anchor hole 205 via the passivation layer 125. As a result, the connection strength of the resin layer 129 to the first main surface 103 of the SiC semiconductor layer 102 can be increased, so that peeling of the resin layer 129 can be suppressed.
As described above, the SiC semiconductor device 101 can also achieve the same effects as those described for the SiC semiconductor device 1. According to SiC semiconductor device 101, second main surface 104 of SiC semiconductor layer 102 extends from the boundary region (pn junction) between SiC semiconductor layer 102 and deep well region 165 to the bottom wall of gate trench 142. The depletion layer can be expanded toward the side region.

  Thereby, the current path of the short-circuit current flowing between the main surface source electrode layer 121 and the drain electrode layer 133 can be narrowed. Further, the depletion layer extending from the boundary region between the SiC semiconductor layer 102 and the deep well region 165 can reduce the feedback capacitance Crss in inverse proportion. Therefore, it is possible to provide the SiC semiconductor device 101 capable of improving the short circuit resistance and reducing the feedback capacitance Crss.

The depletion layer extending from the boundary region (pn junction) between the SiC semiconductor layer 102 and the deep well region 165 may overlap the bottom wall of the gate trench 142. In this case, the depletion layer extending from the bottom of the deep well region 165 may overlap the bottom wall of the gate trench 142.
Moreover, according to the SiC semiconductor device 101, since the region occupied by the depletion layer in the SiC semiconductor layer 102 can be increased, the feedback capacitance Crss can be reduced in inverse proportion. The feedback capacitance Crss is an electrostatic capacitance between the gate electrode layer 149 and the drain electrode layer 133.

Further, according to SiC semiconductor device 101, the distance between the bottom of each deep well region 165 and second main surface 104 of SiC semiconductor layer 102 is substantially constant. Accordingly, it is possible to suppress variation in the distance between the bottom of each deep well region 165 and second main surface 104 of SiC semiconductor layer 102.
Therefore, the withstand voltage (for example, breakdown withstand amount) of SiC semiconductor layer 102 can be suppressed from being limited by the form of deep well region 165, and thus the withstand voltage can be appropriately improved.

Further, according to SiC semiconductor device 101, diode region 181 is formed in outer region 112. The diode region 181 is electrically connected to the main surface source electrode layer 121. This allows the avalanche current generated in the outer region 112 to flow into the main surface source electrode layer 121 via the diode region 181.
That is, the avalanche current generated in the outer region 112 can be absorbed by the diode region 181 and the main surface source electrode layer 121. As a result, the stability of the operation of the MISFET can be improved.

Further, according to SiC semiconductor device 101, outer deep well region 182 is formed in outer region 112. Thereby, the breakdown voltage of SiC semiconductor layer 102 in outer region 112 can be adjusted.
Particularly, in the SiC semiconductor device 101, the outer deep well region 182 is formed at a depth position substantially equal to that of the deep well region 165. More specifically, the bottom of the outer deep well region 182 is located substantially flush with the bottom of the deep well region 165.

The distance between the bottom of outer deep well region 182 and second main surface 104 of SiC semiconductor layer 102 is substantially equal to the distance between the bottom of deep well region 165 and second main surface 104 of SiC semiconductor layer 102.
Accordingly, the distance between the bottom of the outer deep well region 182 and the second main surface 104 of the SiC semiconductor layer 102 and the distance between the bottom of the deep well region 165 and the second main surface 104 of the SiC semiconductor layer 102 are set. It is possible to suppress the occurrence of variations between them.

Therefore, it is possible to prevent the breakdown voltage (for example, breakdown withstand amount) of SiC semiconductor layer 102 from being limited by the form of outer deep well region 182 and the form of deep well region 165. As a result, the breakdown voltage can be appropriately improved.
Particularly, in the SiC semiconductor device 101, the outer region 112 is formed in the region on the second main surface 104 side of the SiC semiconductor layer 102 with respect to the active region 111. As a result, the position of the bottom of the outer deep well region 182 can be appropriately approximated to the position of the bottom of the deep well region 165.

That is, when forming outer deep well region 182, it is not necessary to introduce the p-type impurity into a relatively deep position of the surface layer portion of first main surface 103 of SiC semiconductor layer 102. Therefore, it is possible to properly prevent the position of the bottom of the outer deep well region 182 from being greatly displaced from the position of the bottom of the deep well region 165.
Moreover, in SiC semiconductor device 101, outer main surface 172 of outer region 112 is located substantially flush with the bottom wall of source trench 155. Thus, when p-type impurities are introduced into the bottom wall of the source trench 155 and the outer main surface 172 of the outer region 112 with the same energy, the deep well region 165 and the outer deep well region 182 are located at substantially equal depth positions. Can be formed into

As a result, it is possible to more appropriately suppress the position of the bottom portion of the outer deep well region 182 from being greatly displaced from the position of the bottom portion of the deep well region 165.
Further, according to SiC semiconductor device 101, field limit structure 183 is formed in outer region 112. Thereby, in the outer region 112, the electric field relaxation effect by the field limit structure 183 can be obtained. Therefore, the breakdown resistance of the SiC semiconductor layer 102 can be appropriately improved.

Further, according to the SiC semiconductor device 101, the active region 111 is formed as the plate-like active plateau 173. Active plateau 173 includes active sidewalls 174 connecting active major surface 171 of active region 111 and outer major surface 172 of outer region 112.
In a region between the active main surface 171 and the outer main surface 172, a step reduction structure that reduces a step between the active main surface 171 and the outer main surface 172 is formed. The step reducing structure includes a sidewall 192.

  Thereby, the step between the active main surface 171 and the outer main surface 172 can be appropriately reduced. Therefore, the flatness of the upper layer structure formed on the sidewall 192 can be appropriately improved. In the SiC semiconductor device 101, the interlayer insulating layer 201, the main surface source electrode layer 121, the passivation layer 125, and the resin layer 129 are formed as an example of the upper layer structure.

Further, according to SiC semiconductor device 101, an anchor structure for increasing the connection strength of resin layer 129 is formed in outer region 112. The anchor structure includes an uneven structure (Uneven Structure) formed on the first main surface 103 of the SiC semiconductor layer 102 in the outer region 112.
More specifically, the concavo-convex structure (anchor structure) includes a concavo-convex formed by utilizing interlayer insulating layer 201 formed on first main surface 103 of SiC semiconductor layer 102 in outer region 112. More specifically, the uneven structure (anchor structure) includes anchor holes 205 formed in the interlayer insulating layer 201.

The resin layer 129 meshes with the anchor hole 205. In this embodiment, the resin layer 129 meshes with the anchor hole 205 via the passivation layer 125. As a result, the connection strength of the resin layer 129 to the first main surface 103 of the SiC semiconductor layer 102 can be increased, so that peeling of the resin layer 129 can be appropriately suppressed.
Further, according to the SiC semiconductor device 101, the trench gate structure 161 in which the gate electrode layer 149 is embedded in the gate trench 142 with the gate insulating layer 148 interposed therebetween is formed. In this trench gate structure 161, the gate electrode layer 149 is covered with the low resistance electrode layer 167 in the limited space of the gate trench 142. With such a structure, the effect described with reference to FIG. 24 can be obtained.

FIG. 24 is a graph for explaining the sheet resistance in the gate trench 142. In FIG. 24, the vertical axis represents sheet resistance [Ω / □], and the horizontal axis represents items. FIG. 24 shows the first bar graph BL1, the second bar graph BL2, and the third bar graph BL3.
The first bar graph BL1 represents the sheet resistance in the gate trench 142 in which n-type polysilicon is buried. The second bar graph BL2 represents the sheet resistance in the gate trench 142 filled with p-type polysilicon.

The third bar graph BL3 represents the sheet resistance in the gate trench 142 in which the gate electrode layer 149 (p-type polysilicon) and the low resistance electrode layer 167 are embedded. Here, a case where the low resistance electrode layer 167 made of TiSi ₂ (p-type titanium silicide) as an example of polycide (silicide) is formed will be described.
With reference to the first bar graph BL1, the sheet resistance in the gate trench 142 in which the n-type polysilicon was buried was 10Ω / □. Referring to the second bar graph BL2, the sheet resistance in the gate trench 142 in which p-type polysilicon was embedded was 200Ω / □. With reference to the third bar graph BL3, the sheet resistance in the gate trench 142 in which the gate electrode layer 149 (p-type polysilicon) and the low resistance electrode layer 167 were embedded was 2Ω / □.

The p-type polysilicon has a work function different from that of the n-type polysilicon. With the structure in which the p-type polysilicon is buried in the gate trench 142, the gate threshold voltage Vth can be increased by about 1V.
However, p-type polysilicon has a sheet resistance several tens of times (here, 20 times) higher than the sheet resistance of n-type polysilicon. Therefore, when p-type polysilicon is used as the material of the gate electrode layer 149, the energy loss significantly increases as the parasitic resistance in the gate trench 142 (hereinafter simply referred to as “gate resistance”) increases.

  On the other hand, according to the structure having the low resistance electrode layer 167 on the gate electrode layer 149 (p-type polysilicon), the sheet resistance is 100 minutes as compared with the case where the low resistance electrode layer 167 is not formed. It can be reduced to 1 or less. That is, according to the structure having the low resistance electrode layer 167, the sheet resistance can be reduced to one fifth or less as compared with the gate electrode layer 149 containing n-type polysilicon.

  As described above, according to the structure having the low-resistance electrode layer 167, the sheet resistance in the gate trench 142 can be reduced while increasing the gate threshold voltage Vth (for example, about 1V). Thereby, the gate resistance can be reduced, so that the current can be efficiently diffused along the trench gate structure 161. As a result, the switching delay can be shortened.

Further, according to the structure having the low resistance electrode layer 167, it is not necessary to increase the p-type impurity concentration of the body region 141 and the p-type impurity concentration of the contact region 164. Therefore, it is possible to appropriately increase the gate threshold voltage Vth while suppressing an increase in channel resistance.
The low resistance electrode layer 167 may include at least one of TiSi, TiSi ₂ , NiSi, CoSi, CoSi ₂ , MoSi ₂ or WSi ₂ . Among these, NiSi, CoSi ₂ and TiSi ₂ among these species are suitable as a polycide layer forming the low resistance electrode layer 167, since their specific resistance values and temperature dependences are relatively small.

As a result of further verification by the inventors of the present application, when TiSi ₂ was adopted as the material of the low resistance electrode layer 167, an increase in the leak current between the gate and the source was observed when a low electric field was applied. On the other hand, when CoSi ₂ was adopted, no increase in the leak current between the gate and the source was observed when a low electric field was applied. Considering this point, CoSi ₂ is considered to be most preferable as the polycide layer forming the low resistance electrode layer 167.

Further, in the SiC semiconductor device 101, the gate wiring layer 150 is covered with the low resistance electrode layer 167. As a result, the gate resistance of the gate wiring layer 150 can be reduced.
In particular, in the structure in which the gate electrode layer 149 and the gate wiring layer 150 are covered with the low resistance electrode layer 167, the current can be efficiently diffused along the trench gate structure 161. Therefore, it is possible to appropriately reduce the switching delay.

FIG. 25 is an enlarged view of a region corresponding to FIG. 18, showing an SiC semiconductor device 221 according to the fourth embodiment of the present invention. FIG. 26 is a sectional view taken along line XXVI-XXVI shown in FIG. In the following, structures corresponding to those described for SiC semiconductor device 101 are designated by the same reference numerals, and description thereof will be omitted.
25 and 26, SiC semiconductor device 221 includes an outer gate trench 222 formed in first main surface 103 of SiC semiconductor layer 102 in active region 111. The outer gate trench 222 extends in a strip shape along the peripheral portion of the active region 111.

Outer gate trench 222 is formed in a region immediately below outer gate finger 117 on first main surface 103 of SiC semiconductor layer 102. The outer gate trench 222 extends along the outer gate finger 117.
More specifically, outer gate trench 222 is formed along three side surfaces 105A, 105B, 105D of SiC semiconductor layer 102 so as to partition the inner region of active region 111 from three directions. The outer gate trench 222 may be formed in an endless shape (for example, a square ring shape) that surrounds the inner region of the active region 111.

The outer gate trench 222 communicates with the contact trench portion 144 of each gate trench 142. As a result, the outer gate trench 222 and the gate trench 142 are formed by one trench.
The gate wiring layer 150 is embedded in the outer gate trench 222. The gate wiring layer 150 is connected to the gate electrode layer 149 at the communication portion between the gate trench 142 and the outer gate trench 222.

A low resistance electrode layer 167 that covers the gate wiring layer 150 is formed in the outer gate trench 222. In this case, the low resistance electrode layer 167 that covers the gate electrode layer 149 and the low resistance electrode layer 167 that covers the gate wiring layer 150 are located in one trench.
As described above, the SiC semiconductor device 221 can also achieve the same effects as those described for the SiC semiconductor device 101. Further, according to SiC semiconductor device 221, it is not necessary to pull out gate wiring layer 150 onto first main surface 103 of SiC semiconductor layer 102.

Thereby, at the opening edge portion 146 of the gate trench 142 (outer gate trench 222), it is possible to suppress the gate wiring layer 150 from facing the SiC semiconductor layer 102 with the gate insulating layer 148 interposed therebetween. As a result, it is possible to suppress the concentration of the electric field at the opening edge portion 146 of the gate trench 142 (outer gate trench 222).
FIG. 27 is an enlarged view of a region corresponding to FIG. 21, showing an SiC semiconductor device 231 according to the fifth embodiment of the present invention. In the following, structures corresponding to those described for SiC semiconductor device 101 are designated by the same reference numerals, and description thereof will be omitted.

Referring to FIG. 27, SiC epitaxial layer 107 in this embodiment includes a high concentration region 108, a low concentration region 109, and a concentration gradient region 232 interposed between high concentration region 108 and low concentration region 109.
In the SiC epitaxial layer 107, the concentration gradient region 232 is formed in the outer region 112 in addition to the active region 111. The concentration gradient region 232 is formed over the entire area of the SiC epitaxial layer 107.

  The concentration gradient region 232 has a concentration gradient in which the n-type impurity concentration gradually decreases from the high concentration region 108 toward the low concentration region 109. In other words, the concentration gradient region 232 has a concentration gradient in which the n-type impurity concentration gradually increases from the low concentration region 109 toward the high concentration region 108. The concentration gradient region 232 suppresses a rapid change in the n-type impurity concentration in the region between the high concentration region 108 and the low concentration region 109.

When the SiC epitaxial layer 107 includes the concentration gradient region 232, the n-type impurity concentration of the high concentration region 108 is preferably 1.5 times or more and 5 times or less the n-type impurity concentration of the low concentration region 109. The n-type impurity concentration of the high-concentration region 108 may be 3 times or more and 5 times or less the n-type impurity concentration of the low-concentration region 109.
The thickness of the concentration gradient region 232 may be 0.5 μm or more and 2.0 μm or less. The thickness of the concentration gradient region 232 may be 0.5 μm or more and 1.0 μm or less, 1.0 μm or more and 1.5 μm or less, or 1.5 μm or more and 2.0 μm or less.

Although detailed description is omitted, the gate trench 142, the source trench 155, the deep well region 165, the outer deep well region 182, and the like described above are formed in the high concentration region 108.
That is, the gate trench 142, the source trench 155, the deep well region 165, the outer deep well region 182, and the like described above have the first main surface 103 with respect to the boundary region between the high concentration region 108 and the concentration gradient region 232 in the SiC semiconductor layer 102. It is formed in the region on the side.

As described above, the SiC semiconductor device 231 can also achieve the same effects as those described for the SiC semiconductor device 101.
FIG. 28 is an enlarged view of a region corresponding to FIG. 18, showing an SiC semiconductor device 241 according to the sixth embodiment of the present invention. In the following, structures corresponding to those described for SiC semiconductor device 101 are designated by the same reference numerals, and description thereof will be omitted.

  With reference to FIG. 28, the gate trench 142 is formed in a lattice shape in a plan view in this embodiment. More specifically, the gate trench 142 includes a plurality of first gate trenches 242 and a plurality of second gate trenches 243. The plurality of first gate trenches 242 and the plurality of second gate trenches 243 form an active trench portion 143.

The plurality of first gate trenches 242 are formed at intervals in the second direction Y and are formed in strips extending in the first direction X, respectively. The plurality of first gate trenches 242 are formed in a stripe shape as a whole in a plan view.
The side wall forming the long side in each first gate trench 242 is formed by the a-plane of the SiC single crystal. The side wall forming the short side in each first gate trench 242 is formed by the m-plane of SiC single crystal.

The plurality of second gate trenches 243 are formed at intervals in the first direction X and are each formed in a strip shape extending along the second direction Y. The plurality of second gate trenches 243 are formed in a stripe shape as a whole in a plan view.
The side wall forming the long side in each second gate trench 243 is formed by the m-plane of the SiC single crystal. The side wall forming the short side in each second gate trench 243 is formed by the a-plane of the SiC single crystal.

The plurality of first gate trenches 242 and the plurality of second gate trenches 243 intersect each other. As a result, one grid-shaped gate trench 142 is formed in plan view. A plurality of cell regions 244 are defined in the region surrounded by the gate trench 142.
The plurality of cell regions 244 are arranged in a matrix form at intervals in the first direction X and the second direction Y in a plan view. The plurality of cell regions 244 are formed in a quadrangular shape in a plan view. In each cell region 244, the body region 141 is exposed from the side wall of the gate trench 142. Body region 141 is exposed from the side wall formed by the m-plane and a-plane of the SiC single crystal in gate trench 142.

Of course, the gate trench 142 may be formed in a honeycomb shape as one aspect of the lattice shape in a plan view. In this case, the plurality of cell regions 244 may be arranged in a zigzag pattern at intervals in the first direction X and the second direction Y. Further, in this case, the plurality of cell regions 244 may be formed in a hexagonal shape in a plan view.
Each source trench 155 is formed in the center of each cell region 244 in plan view. Each source trench 155 is formed in a pattern that appears on a cut surface that appears when the cell region 244 is cut along the first direction X. In addition, each source trench 155 is formed in a pattern that appears on a cut surface that appears when the cell region 244 is cut along the second direction Y.

More specifically, each source trench 155 is formed in a rectangular shape in plan view. The four sidewalls of each source trench 155 are formed by the m-plane and a-plane of the SiC single crystal.
The planar shape of each source trench 155 is arbitrary. Each source trench 155 may be formed in a triangular shape, a pentagonal shape, a polygonal shape such as a hexagonal shape, or a circular shape or an elliptical shape in a plan view.

The sectional view taken along the line XIX-XIX in FIG. 28 corresponds to the sectional view shown in FIG. The sectional view taken along the line XX-XX in FIG. 28 corresponds to the sectional view shown in FIG.
As described above, the SiC semiconductor device 241 can also achieve the same effects as those described for the SiC semiconductor device 101.
Although the embodiment of the present invention has been described, the embodiment of the present invention can be implemented in other forms.

  In each of the above-described embodiments, the side surfaces 5A and 105A and the side surfaces 5C and 105C of the SiC semiconductor layers 2 and 102 face the a-plane of the SiC single crystal, and the side surfaces 5B and 105B and the side surfaces 5D and 105D are the m-plane of the SiC single crystal. The form facing the above has been described. However, the side surfaces 5A, 105A and the side surfaces 5C, 105C may face the m-plane of the SiC single crystal, and the side surfaces 5B, 105B and the side surfaces 5D, 105D may face the a-plane of the SiC single crystal.

  In each of the above-described embodiments, the example in which the continuously extending strip-shaped reforming lines 22A to 22D are formed has been described. However, in each of the above-described embodiments, the reformed lines 22A to 22D having a broken line belt shape (broken line shape) may be formed. That is, the reforming lines 22A to 22D may be formed in a strip shape that extends intermittently. In this case, one, two, or three of the reforming lines 22A to 22D may be formed in a band shape with a broken line, and the rest may be formed in a band shape.

In the above-described third to sixth embodiments, the example in which the plurality of gate trenches 142 (first gate trenches 242) extending along the m-axis direction ([1-100] direction) of the SiC single crystal has been described. ..
However, a plurality of gate trenches 142 (first gate trenches 242) extending along the a-axis direction ([11-20] direction) of the SiC single crystal may be formed. In this case, a plurality of source trenches 155 extending along the a-axis direction ([11-20] direction) of the SiC single crystal are formed.

In the above-described third to sixth embodiments, the example in which the source electrode layer 157 is embedded in the source trench 155 with the source insulating layer 156 sandwiched therebetween has been described. However, the source electrode layer 157 may be directly embedded in the source trench 155 without the source insulating layer 156.
In the above third to sixth embodiments, the example in which the source insulating layer 156 is formed along the side wall and the bottom wall of the source trench 155 has been described.

However, the source insulating layer 156 may be formed along the side wall of the source trench 155 so as to expose the bottom wall of the source trench 155. The source insulating layer 156 may be formed along the side wall and the bottom wall of the source trench 155 so as to expose a part of the bottom wall of the source trench 155.
Further, the source insulating layer 156 may be formed along the bottom wall of the source trench 155 so as to expose the side wall of the source trench 155. The source insulating layer 156 may be formed along the side wall and the bottom wall of the source trench 155 so as to expose a part of the side wall of the source trench 155.

  In the above third to sixth embodiments, the example in which the gate electrode layer 149 and the gate wiring layer 150 including p-type polysilicon to which p-type impurities are added has been described. However, in the case where the increase in the gate threshold voltage Vth is not emphasized, the gate electrode layer 149 and the gate wiring layer 150 are replaced with or in addition to the p-type polysilicon, and the n-type polysilicon doped with the n-type impurity is used. May be included.

In this case, the low resistance electrode layer 167 may be formed by silicidizing a portion of the gate electrode layer 149 (n-type polysilicon) forming the surface layer portion with a metal material. That is, the low resistance electrode layer 167 may include n-type polycide. With such a structure, the gate resistance can be reduced.
In the above third to sixth embodiments, ap ⁺ type SiC semiconductor substrate (106) may be adopted instead of the n ⁺ type SiC semiconductor substrate 106. According to this structure, an IGBT (Insulated Gate Bipolar Transistor) can be provided instead of the MISFET. In this case, in each of the above-described embodiments, the "source" of the MISFET is read as the "emitter" of the IGBT, and the "drain" of the MISFET is read as the "collector" of the IGBT.

In each of the above-described embodiments, a structure in which the conductivity type of each semiconductor portion is inverted may be adopted. That is, the p-type portion may be the n-type and the n-type portion may be the p-type.
Each of the above-described embodiments can also be applied to a semiconductor device using a semiconductor material different from SiC. The semiconductor material different from SiC may be a compound semiconductor material. The compound semiconductor material may be one or both of gallium nitride (GaN) and gallium oxide (Ga ₂ O ₃ ).

  For example, the third to sixth embodiments described above may be compound semiconductor devices including a vertical type compound semiconductor MISFET in which a compound semiconductor material is used instead of SiC. In a compound semiconductor, magnesium may be adopted as a p-type impurity (acceptor). Further, germanium (Ge), oxygen (O), or silicon (Si) may be adopted as the n-type impurity (donor).

Hereinafter, examples of the features extracted from this specification and the drawings will be shown.
The modified layer is formed by modifying the SiC single crystal of the SiC semiconductor layer to another property. Therefore, considering the influence of the modified layer on the SiC semiconductor layer, it is not desirable to form a plurality of modified layers on the entire side surface of the SiC semiconductor layer. Examples of the influence of the modified layer on the SiC semiconductor layer include changes in the electrical characteristics of the SiC semiconductor layer caused by the modified layer and the occurrence of cracks in the SiC semiconductor layer starting from the modified layer. It

The following [A1] to [A20] and [B1] to [B25] are intended to provide a SiC semiconductor device capable of reducing the influence of the modified layer on the SiC semiconductor layer.
[A1] A first side surface including a SiC single crystal of hexagonal crystal, a first main surface as an element formation surface, a second main surface opposite to the first main surface, and an a surface of the SiC single crystal. And a SiC semiconductor layer having a second side surface facing the m-plane of the SiC single crystal and a first exclusive ratio formed on the first side surface of the SiC semiconductor layer and having a property different from that of the SiC single crystal. A modified first modified layer and a modified second layer formed on the second side surface of the SiC semiconductor layer at a second occupancy rate less than the first occupancy rate and modified to a property different from that of the SiC single crystal. A SiC semiconductor device comprising: two modified layers.

  According to this SiC semiconductor device, the first modified layer and the second modified layer are formed at different occupancy rates depending on the crystal plane of the SiC single crystal. The SiC single crystal is easily cracked along the closest atomic direction (a-axis direction and its equivalent direction) of Si atoms in a plan view when the c-plane is viewed from the c-axis direction, and the SiC single crystal crosses the closest atomic direction (m-axis direction). And its equivalent direction).

Therefore, the crystal planes (m-planes and their equivalent planes) in the SiC single crystal, which have a relatively fragile property, can be appropriately cut without forming a modified layer having a relatively large occupation ratio. As a result, it is possible to reduce the formation region of the modified layer, so that the influence of the modified layer on the SiC semiconductor layer can be reduced.
[A2] A first side surface including a SiC single crystal made of hexagonal crystal, a first main surface as an element formation surface, a second main surface opposite to the first main surface, and an a surface of the SiC single crystal. And a SiC semiconductor layer having a second side surface facing the m-plane of the SiC single crystal, and formed on the first side surface of the SiC semiconductor layer at intervals along a direction normal to the first main surface. A plurality of first modified layers modified to have a property different from that of the SiC single crystal, and a plurality of first modified layers formed on the second side surface of the SiC semiconductor layer, the number being less than the number of the first modified layers. An SiC semiconductor device, comprising: one or a plurality of second modified layers modified to have properties different from those of a SiC single crystal.

  According to this SiC semiconductor device, the first modified layer and the second modified layer are formed in different numbers depending on the crystal plane of the SiC single crystal. The SiC single crystal is easily cracked along the closest atomic direction (a-axis direction and its equivalent direction) of Si atoms in a plan view when the c-plane is viewed from the c-axis direction, and the SiC single crystal crosses the closest atomic direction (m-axis direction). And its equivalent direction).

Therefore, the crystal planes (m-plane and equivalent planes) of the SiC single crystal which are relatively easily broken can be appropriately cut without increasing the number of modified layers. As a result, it is possible to reduce the formation region of the modified layer, so that the influence of the modified layer on the SiC semiconductor layer can be reduced.
[A3] A plurality of the first modified layers are formed on the first side surface of the SiC semiconductor layer at intervals along the normal direction of the first main surface, and the number of the first modified layers is The one or more second modified layers less than are formed on the second side surface of the SiC semiconductor layer at intervals along the normal direction of the first main surface. SiC semiconductor device.

[A4] The first modified layer has a first thickness in the normal direction of the first main surface, and the second modified layer has the first thickness in the normal direction of the first main surface. The SiC semiconductor device according to any one of A1 to A3, which has a second thickness equal to or less than the thickness.
[A5] The SiC semiconductor according to any one of A1 to A4, wherein the first modified layer is formed at a distance from the first main surface of the SiC semiconductor layer to the second main surface. apparatus.

[A6] The SiC semiconductor according to any one of A1 to A5, wherein the second modified layer is formed with a space from the first main surface to the second main surface of the SiC semiconductor layer. apparatus.
[A7] The SiC semiconductor according to any one of A1 to A6, wherein the first modified layer is formed at a distance from the second main surface of the SiC semiconductor layer to the first main surface. apparatus.
[A8] The SiC semiconductor according to any one of A1 to A7, wherein the second modified layer is formed at a distance from the second main surface of the SiC semiconductor layer to the first main surface. apparatus.

[A9] The first modified layer extends linearly, curvedly, or in a broken line along the a-axis direction of the SiC single crystal, and the second modified layer is the m-axis of the SiC single crystal. The SiC semiconductor device according to any one of A1 to A8, which extends in a straight line shape, a curved line shape, or a broken line shape along the direction.
[A10] The SiC semiconductor device according to any one of A1 to A9, wherein the first main surface of the SiC semiconductor layer faces the c-plane of the SiC single crystal.

[A11] Any one of A1 to A10, wherein the first main surface of the SiC semiconductor layer has an off-angle inclined at an angle of 0 ° or more and 10 ° or less with respect to the c-plane of the SiC single crystal. The SiC semiconductor device according to one.
[A12] The SiC semiconductor device according to A11, wherein the off-angle is 5 ° or less.
[A13] The SiC semiconductor device according to A11 or A12, wherein the off-angle is more than 0 ° and less than 4 °.

[A14] The SiC semiconductor device according to any one of A1 to A13, wherein the SiC single crystal is a 2H (Hexagonal) -SiC single crystal, a 4H-SiC single crystal, or a 6H-SiC single crystal.
[A15] The SiC semiconductor device according to any one of A1 to A14, wherein the second main surface of the SiC semiconductor layer is a ground surface.

[A16] The SiC semiconductor device according to any one of A1 to A15, wherein the first side surface of the SiC semiconductor layer is a cleavage plane, and the second side surface of the SiC semiconductor layer is a cleavage plane.
[A17] The SiC semiconductor device according to any one of A1 to A16, wherein the SiC semiconductor layer has a thickness of 40 μm or more and 200 μm or less.

  [A18] The SiC semiconductor layer includes a SiC semiconductor substrate and a SiC epitaxial layer, and has a laminated structure in which the first main surface is formed by the SiC epitaxial layer, and the first modified layer is the The SiC semiconductor device according to any one of A1 to A17, which is formed on a SiC semiconductor substrate and the second modified layer is formed on the SiC semiconductor substrate.

[A19] The SiC semiconductor device according to A18, wherein the SiC epitaxial layer has a thickness equal to or less than the thickness of the SiC semiconductor substrate.
[A20] The SiC semiconductor device according to A18 or A19, wherein the SiC semiconductor substrate has a thickness of 40 μm or more and 150 μm or less, and the SiC epitaxial layer has a thickness of 1 μm or more and 50 μm or less.

  [B1] a first side surface including a SiC single crystal made of hexagonal crystal, a first main surface as an element forming surface, a second main surface opposite to the first main surface, and an a surface of the SiC single crystal And a SiC semiconductor layer having a second side surface facing the m-plane of the SiC single crystal, and a first side surface of the SiC semiconductor layer having a first thickness in a direction normal to the first main surface. A first modified layer formed in a first occupancy ratio and having a property different from that of the SiC single crystal, and a second thickness equal to or less than the first thickness with respect to a normal direction of the first main surface. And a second modified layer formed on the second side surface of the SiC semiconductor layer at a second occupancy rate less than the first occupancy rate and modified to a property different from that of the SiC single crystal. A SiC semiconductor device including.

  [B2] A hexagonal SiC single crystal, a first main surface as an element formation surface, a second main surface formed of a ground surface opposite to the first main surface, and a surface of the SiC single crystal a-plane A SiC semiconductor layer having a first side surface and a second side surface facing the m-plane of the SiC single crystal; and a first semiconductor layer having a first thickness in a direction normal to the first main surface. A first modified layer formed on the first side surface at a first exclusive ratio and modified to have a property different from that of the SiC single crystal; and a first modified layer having a thickness equal to or less than the first thickness in a direction normal to the first main surface. A second modification that has a second thickness and is formed on the second side surface of the SiC semiconductor layer at a second occupancy rate less than the first occupancy rate and has a property different from that of the SiC single crystal. A SiC semiconductor device including a layer.

  [B3] A first major surface as an element formation surface, a second major surface opposite to the first major surface, and an a-plane of the SiC single crystal, including a SiC single crystal made of hexagonal crystal, and a cleavage plane. And a SiC semiconductor layer having a second side surface composed of a cleavage plane and facing the m-plane of the SiC single crystal, and having a first thickness in a direction normal to the first main surface. A first modified layer formed on the first side surface of the SiC semiconductor layer in a first exclusive ratio and modified to have a property different from that of the SiC single crystal; and the first modified surface with respect to a normal direction of the first main surface. A second thickness less than or equal to a first thickness, formed on the second side surface of the SiC semiconductor layer at a second occupation ratio less than the first occupation ratio, and modified to a property different from that of the SiC single crystal. And a modified second modified layer.

  [B4] A first main surface as an element formation surface, a second main surface opposite to the first main surface, and a first side surface facing the a-plane of the SiC single crystal, including a SiC single crystal of hexagonal crystal And a SiC semiconductor layer having a second side surface facing the m-plane of the SiC single crystal and having a thickness of 40 μm or more and 200 μm or less, and a first thickness in a direction normal to the first main surface. And a first modified layer formed on the first side surface of the SiC semiconductor layer at a first exclusive ratio and modified to a property different from that of the SiC single crystal, and a normal line of the first main surface. Has a second thickness that is less than or equal to the first thickness with respect to a direction, is formed on the second side surface of the SiC semiconductor layer at a second occupancy rate less than the first occupancy rate, and has a property different from that of the SiC single crystal. And a second modified layer that has been modified into a SiC semiconductor device.

  [B5] A first main surface as an element formation surface, a second main surface opposite to the first main surface, and a first side surface facing the a-plane of the SiC single crystal, including a SiC single crystal of hexagonal crystal And a laminated structure including a SiC semiconductor substrate having a second side surface facing the m-plane of the SiC single crystal and forming the second main surface and a SiC epitaxial layer forming the first main surface. The SiC semiconductor layer has a first thickness in the normal direction to the first main surface, and is formed at a first exclusive ratio in a portion of the SiC semiconductor substrate that forms the first side surface of the SiC semiconductor layer. The SiC semiconductor substrate has a first modified layer modified to have a property different from that of the SiC single crystal, and a second thickness equal to or less than the first thickness with respect to a normal direction of the first main surface. Forming the second side surface of the SiC semiconductor layer in Is divided into formed by the second exclusive proportion of the first less than proprietary ratio, and a second modified layer modified in different properties from that of the SiC single crystal, SiC semiconductor device.

[B6] The SiC semiconductor device according to B5, wherein the SiC epitaxial layer has a thickness equal to or less than the thickness of the SiC semiconductor substrate.
[B7] The SiC semiconductor device according to B5 or B6, wherein the SiC semiconductor substrate has a thickness of 40 μm or more and 150 μm or less, and the SiC epitaxial layer has a thickness of 1 μm or more and 50 μm or less.

  [B8] A plurality of the first modified layers are formed on the first side surface of the SiC semiconductor layer at intervals along the normal direction of the first main surface, and the number of the first modified layers is One or more of the second modified layers below are formed on the second side surface of the SiC semiconductor layer at intervals along the normal direction of the first main surface. The SiC semiconductor device according to any one of claims.

  [B9] A first main surface as an element formation surface, a second main surface opposite to the first main surface, and a first side surface facing the a-plane of the SiC single crystal, including a SiC single crystal of hexagonal crystal And a SiC semiconductor layer having a second side surface facing the m-plane of the SiC single crystal, and a first side surface of the SiC semiconductor layer having a first thickness in a direction normal to the first main surface. A plurality of first modified layers formed at intervals along the normal direction of the first main surface and modified to have a property different from that of the SiC single crystal; and a normal line of the first main surface. Has a second thickness that is less than or equal to the first thickness with respect to a direction, is formed on the second side surface of the SiC semiconductor layer in a number less than the number of the first modified layer, and has a property different from that of the SiC single crystal. And one or more second modified layers that have been modified to a SiC semiconductor device.

  [B10] A first main surface as an element formation surface, which includes a SiC single crystal made of hexagonal crystal, a second main surface which is a ground surface opposite to the first main surface, and a surface of the SiC single crystal on the a-plane. A SiC semiconductor layer having a first side surface and a second side surface facing the m-plane of the SiC single crystal; and a first semiconductor layer having a first thickness in a direction normal to the first main surface. A plurality of first modified layers formed on the first side surface at intervals along the normal direction of the first main surface and modified to have a property different from that of the SiC single crystal; A second thickness that is less than or equal to the first thickness with respect to a surface normal direction, and is formed on the second side surface of the SiC semiconductor layer in a number less than the number of the first modified layers, And one or more second modified layers modified to have different properties from the above.

  [B11] A SiC single crystal composed of a hexagonal crystal is included, which faces a first main surface as an element formation surface, a second main surface opposite to the first main surface, an a surface of the SiC single crystal, and a cleavage plane. And a SiC semiconductor layer having a second side surface composed of a cleavage plane and facing the m-plane of the SiC single crystal, and having a first thickness in a direction normal to the first main surface. A plurality of first modified layers that are formed on the first side surface of the SiC semiconductor layer at intervals along the normal direction of the first main surface and that are modified to have properties different from those of the SiC single crystal. And a second thickness equal to or less than the first thickness with respect to the normal direction of the first main surface and less than the number of the first modified layers formed on the second side surface of the SiC semiconductor layer. And one or more second modified layers modified to have properties different from those of the SiC single crystal. Body apparatus.

  [B12] A first main surface as an element formation surface, a second main surface opposite to the first main surface, and a first side surface facing the a-plane of the SiC single crystal, including a SiC single crystal of hexagonal crystal And a SiC semiconductor layer having a second side surface facing the m-plane of the SiC single crystal and having a thickness of 40 μm or more and 200 μm or less, and a first thickness in a direction normal to the first main surface. A plurality of first semiconductor layers that are formed on the first side surface of the SiC semiconductor layer at intervals along the normal direction of the first main surface and that are modified to have properties different from those of the SiC single crystal. A modified layer and a second thickness that is less than or equal to the first thickness with respect to a direction normal to the first main surface, and the second number of the SiC semiconductor layers is less than the first modified layer. One or more second modified layers formed on the side surface and modified to have properties different from those of the SiC single crystal; A SiC semiconductor device including:

  [B13] A first main surface as an element formation surface, a second main surface opposite to the first main surface, and a first side surface facing the a-plane of the SiC single crystal, including a SiC single crystal made of hexagonal crystal And a laminated structure including a SiC semiconductor substrate having a second side surface facing the m-plane of the SiC single crystal and forming the second main surface and a SiC epitaxial layer forming the first main surface. The SiC semiconductor layer has a first thickness in a direction normal to the first main surface, and a method of forming the first main surface on a portion of the SiC semiconductor substrate that forms the first side surface of the SiC semiconductor layer. A plurality of first modified layers formed at intervals along a line direction and modified to have properties different from those of the SiC single crystal; and the first thickness or less with respect to a normal direction of the first main surface. A second thickness of S in the SiC semiconductor substrate. One or more second modified layers, which are formed in a number less than the number of the first modified layers in a portion forming the second side surface of the C semiconductor layer and are modified to have properties different from those of the SiC single crystal. And a SiC semiconductor device.

[B14] The SiC semiconductor device according to B13, wherein the SiC epitaxial layer has a thickness equal to or less than the thickness of the SiC semiconductor substrate.
[B15] The SiC semiconductor device according to B13 or B14, wherein the SiC semiconductor substrate has a thickness of 40 μm or more and 150 μm or less, and the SiC epitaxial layer has a thickness of 1 μm or more and 50 μm or less.

[B16] The SiC semiconductor according to any one of B1 to B15, wherein the first modified layer is formed with a space from the first main surface to the second main surface of the SiC semiconductor layer. apparatus.
[B17] The SiC semiconductor according to any one of B1 to B16, wherein the second modified layer is formed at a distance from the first main surface of the SiC semiconductor layer to the second main surface. apparatus.
[B18] The SiC semiconductor according to any one of B1 to B17, wherein the first modified layer is formed at a distance from the second main surface of the SiC semiconductor layer to the first main surface. apparatus.

[B19] The SiC semiconductor according to any one of B1 to B18, wherein the second modified layer is formed at a distance from the second main surface of the SiC semiconductor layer to the first main surface. apparatus.
[B20] The first modified layer extends in a linear shape, a curved shape, or a broken line shape along the m-axis direction of the SiC single crystal, and the second modified layer is an a-axis of the SiC single crystal. The SiC semiconductor device according to any one of B1 to B19, which extends in a straight line shape, a curved line shape, or a broken line shape along the direction.

[B21] The SiC semiconductor device according to any one of B1 to B20, wherein the first main surface of the SiC semiconductor layer faces the c-plane of the SiC single crystal.
[B22] Any one of B1 to B21, wherein the first main surface of the SiC semiconductor layer has an off-angle inclined at an angle of 0 ° or more and 10 ° or less with respect to the c-plane of the SiC single crystal. The SiC semiconductor device according to one.

[B23] The SiC semiconductor device according to B22, wherein the off-angle is 5 ° or less.
[B24] The SiC semiconductor device according to B22 or B23, wherein the off-angle is more than 0 ° and less than 4 °.
[B25] The SiC semiconductor device according to any one of B1 to B24, wherein the SiC single crystal is composed of 2H (Hexagonal) -SiC single crystal, 4H-SiC single crystal, or 6H-SiC single crystal.

This specification does not limit any combination of the features shown in the first to sixth embodiments. The first to sixth embodiments can be combined in any aspect and in any form therebetween. That is, a form in which the features shown in the first to sixth embodiments are combined in any form and any form may be adopted.
In addition, various design changes can be made within the scope of the matters described in the claims.

1 SiC semiconductor device 2 SiC semiconductor layer 3 1st main surface of SiC semiconductor layer 4 2nd main surface of SiC semiconductor layer 5A Side surface of SiC semiconductor layer 5B Side surface of SiC semiconductor layer 5C Side surface of SiC semiconductor layer 5D Side surface of SiC semiconductor layer 6 SiC semiconductor substrate 7 SiC epitaxial layer 22A reforming line 22B reforming line 22C reforming line 22D reforming line 28 a-plane reforming section (reforming section)
29 m plane reforming section (reforming section)
81 SiC semiconductor device 101 SiC semiconductor device 102 SiC semiconductor layer 103 First main surface 104 of SiC semiconductor layer Second main surface 105A of SiC semiconductor layer 105A Side surface of SiC semiconductor layer 105B Side surface of SiC semiconductor layer 105C Side surface of SiC semiconductor layer 105D SiC Side surface of semiconductor layer 106 SiC semiconductor substrate 107 SiC epitaxial layer θ Off angle RA Exclusive ratio RB Exclusive ratio RC Exclusive ratio RD Exclusive ratio Z Normal direction X First direction (m-axis direction)
Y second direction (a-axis direction)

Claims (20)

An SiC semiconductor chip having a laminated structure including a SiC semiconductor substrate and a SiC epitaxial layer, having an element formation surface formed by the SiC epitaxial layer, and a side surface formed by the SiC semiconductor substrate and the SiC epitaxial layer,
A SiC semiconductor device, comprising: a reformed layer that is reformed to have a property different from that of the SiC semiconductor substrate, the reformed layer being formed on a portion of the side surface of the SiC semiconductor substrate spaced apart from the SiC epitaxial layer.   The SiC semiconductor device according to claim 1, wherein the modified layer is formed in a strip shape extending along the element formation surface.   The SiC semiconductor device according to claim 1, wherein the side surface is a cleavage plane.   The SiC semiconductor chip according to any one of claims 1 to 3, wherein the SiC semiconductor chip is located on the opposite side of the element formation surface and has a back surface that is a grinding surface formed by the SiC semiconductor substrate. Semiconductor device.   The SiC semiconductor device according to claim 4, wherein the modified layer is formed with a space from the back surface to the element formation surface side.   The SiC semiconductor device according to claim 1, wherein the modified layer extends linearly or curvedly.   7. The reformed layer is formed by an assembly of a plurality of reformed portions each extending in a normal direction of the element forming surface and facing each other in a tangential direction of the element forming surface. 2. The SiC semiconductor device according to item 1.   The SiC semiconductor device according to claim 1, wherein the SiC semiconductor chip is made of hexagonal crystal.   The SiC semiconductor device according to claim 1, wherein the element formation surface has an off angle.   The SiC semiconductor device according to any one of claims 1 to 9, wherein the SiC epitaxial layer has a thickness less than a thickness of the SiC semiconductor substrate. An SiC semiconductor chip having a first main surface as an element formation surface, a second main surface opposite to the first main surface, and a side surface,
A first conductivity type first impurity region formed in a surface layer portion of the first main surface so as to be exposed from the first main surface and the side surface;
The impurity concentration of the first conductivity type exceeds the impurity concentration of the first conductivity type of the first impurity region, is exposed from the second main surface and the side surface, and is electrically connected to the first impurity region. A second impurity region of the first conductivity type formed in a region on the second main surface side with respect to the first impurity region,
A SiC semiconductor device, comprising: a modified layer that is formed on a portion of the side surface where the second impurity region is exposed with a space from the first impurity region and that is modified to have a property different from that of the SiC semiconductor chip. ..   The SiC semiconductor device according to claim 11, wherein the modified layer is formed in a strip shape extending along the first main surface.   The SiC semiconductor device according to claim 11, wherein the side surface is a cleavage plane.   The SiC semiconductor device according to claim 11, wherein the second main surface is a ground surface.   The SiC semiconductor device according to claim 11, wherein the modified layer is formed with a space from the second main surface toward the first main surface.   The SiC semiconductor device according to claim 11, wherein the modified layer extends linearly or curvedly.   The reformed layer includes a plurality of reformed portions that extend in a normal direction of the first main surface and face each other in a tangential direction of the first main surface, respectively. The SiC semiconductor device described.   The SiC semiconductor device according to claim 11, wherein the SiC semiconductor chip is made of hexagonal crystal.   The SiC semiconductor device according to claim 11, wherein the first main surface has an off angle.   The SiC semiconductor device according to any one of claims 11 to 19, wherein the second impurity region has a thickness that exceeds the thickness of the first impurity region.

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