JP2021163806A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

To provide a semiconductor device capable of preventing crack propagation and also capable of suppressing the occurrence of further cracks.SOLUTION: A semiconductor device 100 includes an element formation region 110 where a circuit element is formed; and a protective wall formation region 120 where one or more protective walls 121, 122 are formed around the element formation region 110. In the element formation region 110, an anti-reflective film 111p is formed on the top face of the top layer of multilayer wiring 111 that electrically connects to each of the circuit elements. In the protective wall formation region 120, the one or more protective walls 121, 122 each have a multilayer wiring structure, and an anti-reflective film 121p is formed on a top face other than the top layer of the protective wall 122 located on the outermost edge of the protective walls 121, 122. Passivation films P1, P2 are formed on the top face of the element formation region 110 and the protective wall formation region 120, and the whole area of the top face of the top layer of the protective wall 122 is in contact with the passivation film P1.SELECTED DRAWING: Figure 4

Description

The present invention relates to a semiconductor device and a method for manufacturing the same.

The semiconductor manufacturing process includes a dicing step of moving a circular rotary blade called a dicing blade along a scribing region to cut it when separating a plurality of semiconductor chips formed on a wafer-shaped semiconductor substrate. Is done.

Since cracks may occur from the cut surface in this dicing step, a ring shape called a guard ring or the like is formed along the peripheral edge of the element forming region so that the cracks do not propagate to the element forming region inside the semiconductor chip. The structure of is formed for each semiconductor chip. Further, there is a protective wall that not only prevents cracks from propagating into the device forming region but also prevents moisture and gas from entering. For example, double or more metal walls are formed around the device forming region, and the uppermost layers of adjacent metal walls are integrated with each other above the grooved contact hole to cause moisture and corrosion in the device forming region. A semiconductor device that prevents the ingress of sex gas has been proposed (see, for example, Patent Document 1).

Japanese Unexamined Patent Publication No. 2013-128140

On one aspect, it is an object of the present invention to provide a semiconductor device capable of preventing the propagation of cracks and suppressing the occurrence of further cracks.

In one embodiment, the semiconductor device
It has an element forming region in which a plurality of circuit elements are formed on a semiconductor substrate, and a protective wall forming region in which one or more protective walls are formed around the element forming region in a plan view.
In the element forming region, a refractory metal film is formed on the upper surface of the uppermost layer of the multilayer wiring electrically connected to each of the plurality of circuit elements.
In the protective wall forming region, the one or more protective walls have a multi-layer wiring structure, and the high melting point is placed on an upper surface other than the uppermost layer of the protective wall located at the outermost edge of the uppermost layers of the one or more protective walls. A metal film is formed,
A passivation film is formed on the uppermost surfaces of the element forming region and the protective wall forming region, and the entire upper surface of the uppermost layer of the protective wall located at the outermost edge is in contact with the passivation film.

On one aspect, it is possible to provide a semiconductor device capable of preventing the propagation of cracks and suppressing the occurrence of further cracks.

FIG. 1 is a schematic top view showing a semiconductor wafer on which the semiconductor device according to the first embodiment is formed. FIG. 2 is an enlarged view of the semiconductor wafer shown in FIG. FIG. 3 is an enlarged view showing one of the plurality of semiconductor devices shown in FIG. FIG. 4 is a schematic view showing a cross section taken along the line AA shown in FIG. FIG. 5 is an explanatory diagram showing a method of manufacturing a semiconductor device according to the first embodiment. FIG. 6 is an explanatory diagram showing a method of manufacturing a semiconductor device according to the first embodiment. FIG. 7 is an explanatory diagram showing a method of manufacturing a semiconductor device according to the first embodiment. FIG. 8 is an explanatory diagram showing a method of manufacturing a semiconductor device according to the first embodiment. FIG. 9 is an explanatory diagram showing a method of manufacturing a semiconductor device according to the first embodiment. FIG. 10 is an explanatory diagram showing a method of manufacturing a semiconductor device according to the first embodiment. FIG. 11 is an explanatory diagram showing a method of manufacturing a semiconductor device according to the first embodiment. FIG. 12 is an explanatory diagram showing a method of manufacturing a semiconductor device according to the first embodiment. FIG. 13 is an explanatory diagram showing a method of manufacturing a semiconductor device according to the first embodiment. FIG. 14 is an explanatory diagram showing a method of manufacturing a semiconductor device according to the first embodiment. FIG. 15 is an explanatory diagram showing a method of manufacturing a semiconductor device according to the first embodiment. FIG. 16 is a schematic view showing a cross section of the semiconductor device according to the second embodiment. FIG. 17 is an explanatory diagram showing a method of manufacturing a semiconductor device according to the second embodiment. FIG. 18 is an explanatory diagram showing a method of manufacturing a semiconductor device according to the second embodiment.

In the semiconductor device according to the embodiment of the present invention, an element forming region in which a plurality of circuit elements are formed is formed on the semiconductor substrate, and one or more protective walls are formed around the element forming region in a plan view. A refractory metal film is formed on the upper surface of the uppermost layer of the multilayer wiring that has a protective wall forming region and is electrically connected to a plurality of circuit elements in the element forming region. One or more protective walls have a multi-layer wiring structure, and a refractory metal film is formed on the upper surface other than the uppermost layer of the protective wall located at the outermost edge of the uppermost layers of one or more protective walls, and an element forming region is formed. A passivation film is formed on the uppermost surface of the protective wall forming region, and the entire upper surface of the uppermost layer of the protective wall located at the outermost edge is in contact with the passivation film.

The semiconductor device according to the embodiment of the present invention is based on the following findings.

In the wiring process of forming a multilayer wiring in a semiconductor manufacturing process, a refractory metal film may be formed on the upper surface of the metal wiring in order to ensure processing accuracy by photolithography. In addition, if the main component of the metal wiring is aluminum, electromigration and the like are likely to occur. Therefore, for the purpose of suppressing these occurrences, a titanium nitride film that also functions as a refractory metal film covers the entire upper surface of the metal wiring. Are often laminated.
A passivation film is formed on the entire surface of the semiconductor chip so that moisture and gas do not enter the device forming region.

When each film is formed in this way, for example, in a conventional semiconductor device as described in Patent Document 1, the protective wall can suppress the propagation of cracks, and the occurrence of defects due to migration and the surface surface. It is possible to suppress the infiltration of water and gas.
However, when the titanium nitride film is formed on the uppermost layer of the protective wall, the titanium nitride film is oxidized by the moisture infiltrated from the cracks to expand the volume, and the moisture infiltrates further from the cracks generated thereby repeatedly. As a result, cracks occur in a chain reaction in the passivation film formed on the titanium nitride film. Then, in the conventional semiconductor device, there is a problem that the reliability of the semiconductor device is lowered because moisture easily penetrates into the circuit element formed inside the element forming region.

Therefore, in the semiconductor device according to the embodiment of the present invention, in the protective wall forming region, one or more protective walls have a multi-layer wiring structure, and the protective wall located at the outermost edge of the uppermost layer of the one or more protective walls. A refractory metal film is formed on the upper surface other than the uppermost layer. Further, in this semiconductor device, a passivation film is formed on the uppermost surfaces of the element forming region and the protective wall forming region, and the entire upper surface of the uppermost layer of the protective wall located at the outermost edge is in contact with the passivation film. In other words, in this semiconductor device, the refractory metal film is not arranged over the entire upper surface of the uppermost layer of the protective wall located at least the outermost edge of the one or more protective walls.
As a result, even if moisture infiltrates through cracks that reach the upper surface of the uppermost layer of the outermost protective wall during dicing, the refractory metal film is not arranged there, so that the refractory metal film, especially titanium nitride, is formed. It is possible to suppress the chain of cracks caused by the expansion of the film.
That is, in the semiconductor device according to the embodiment of the present invention, it is possible to prevent the propagation of cracks in the dicing step and suppress the occurrence of further cracks starting from the protective wall.

Further, the semiconductor device according to the embodiment of the present invention exists inside the protective wall because it suppresses the occurrence of further cracks starting from the protective wall located at the outermost edge as described above. It is difficult for cracks to reach the element forming region, and there is little risk that the refractory metal film will expand due to moisture. Therefore, in the element forming region, by arranging the titanium nitride film on the upper surface of the uppermost layer of the multilayer wiring, it is possible to suppress the occurrence of electromigration, stress migration, etc. in the metal wiring on the uppermost layer.

Further, in the method for manufacturing a semiconductor device according to an embodiment of the present invention, there is an element forming region in which a plurality of circuit elements are formed on a semiconductor substrate, and one or more protective walls around the element forming region in a plan view. It is a method of manufacturing a semiconductor device having a protective wall forming region in which is formed. The method for manufacturing this semiconductor device is a step of forming a multi-layer wiring electrically connected to a plurality of circuit elements in an element forming region and a protective wall forming region, and forming one or more protective walls having a multi-layer wiring structure. This includes a step of forming a refractory metal film on the upper surface of the uppermost layer of the multilayer wiring and one or more protective walls, and a step of forming a passivation film on the uppermost surface of the device forming region and the protective wall forming region. Further, in this method of manufacturing a semiconductor device, a refractory metal film is formed from the entire upper surface of the uppermost layer of the protective wall located at least the outermost edge of one or more protective walls before the passivation film is formed in the protective wall forming region. Includes the step of removing.
Thereby, the semiconductor device according to the embodiment of the present invention can be manufactured by the method for manufacturing the semiconductor device according to the embodiment of the present invention.
In the method of manufacturing this semiconductor device, the refractory metal film is removed from the entire upper surface of the uppermost layer of the protective wall located at least the outermost edge of one or more protective walls before the passivation film is formed. However, it is not limited to this. For example, among the uppermost layers of the multilayer wiring and one or more protective walls, a step of forming a refractory metal film on the upper surface other than the uppermost layer of the protective wall located at the outermost edge, and the most in the element forming region and the protective wall forming region. The upper surface may include a step of forming a passivation film so as to be in contact with the entire upper surface of the uppermost layer of the protective wall located at the outermost edge.

Next, each embodiment of the semiconductor device of the present invention will be described with reference to the drawings.
The dimensions, materials, shapes, relative arrangements, and the like of each component exemplified in the embodiment may be appropriately changed depending on the configuration of the device to which the present invention is applied, various conditions, and the like.

In each drawing, the same components may be designated by the same reference numerals and duplicate description may be omitted.
Further, in the drawings, the X direction, the Y direction, and the Z direction are orthogonal to each other. The direction including the X direction and the direction opposite to the X direction (-X direction) is called "X-axis direction", and the direction opposite to the Y direction (upward) and the Y direction (-Y direction, down). The direction including the direction) is referred to as the "Y-axis direction", and the direction including the Z direction and the direction opposite to the Z direction (-Z direction) is the "Z-axis direction" (height direction, thickness direction). That is.
Further, the plane including the X-axis direction and the Y-axis direction is referred to as an "XY plane", the plane including the X-axis direction and the Z-axis direction is referred to as an "XZ plane", and the plane including the Y-axis direction and the Z-axis direction is referred to as "X-axis direction". It is called "YZ plane".

(First Embodiment)
(Semiconductor substrate)
FIG. 1 is a schematic top view showing a semiconductor wafer on which the semiconductor device according to the first embodiment is formed.
As shown in FIG. 1, when the semiconductor wafer W, which is a silicon semiconductor substrate, is viewed in a plan view, the plurality of semiconductor devices 100 are formed on the surface of the semiconductor wafer W.
The shape, structure, size and material of the semiconductor wafer W are not particularly limited and may be appropriately selected depending on the intended purpose.

FIG. 2 is an enlarged view of the semiconductor wafer shown in FIG.
As shown in FIG. 2, the plurality of semiconductor devices 100 are divided into a rectangular shape by a scribe region S, which is a cutting region when the semiconductor chip is separated, and each has an element forming region 110 and a protective wall forming region 120, respectively.
The shape and size of the scribe region S are not particularly limited and may be appropriately selected depending on the intended purpose.

<Semiconductor device>
FIG. 3 is an enlarged view showing one of the plurality of semiconductor devices shown in FIG.
As shown in FIG. 3, in the protective wall forming region 120 of the semiconductor device 100, a first protective wall 121 and a second protective wall 122 are formed so as to double surround the element forming region 110. There is.
Such a protective wall may be referred to as a guard ring, a seal ring, a moisture-resistant ring, a metal ring, a crack stop, or the like.

FIG. 4 is a schematic view showing a cross section taken along the line AA shown in FIG.
As shown in FIG. 4, in the semiconductor device 100, a first protective wall 121 and a second protective wall 122 are formed in the protective wall forming region 120. The first protective wall 121 and the second protective wall 122 have a depth equivalent to that of the multilayer wiring 111 of the element forming region 110.
Further, on the uppermost surface, passivation films P1 and P2 are formed so that moisture and gas do not enter the element forming region 110.

<< Element formation area >>
A plurality of circuit elements and a multilayer wiring 111 for electrically connecting the plurality of circuit elements are formed in the element forming region 110.
Examples of the plurality of circuit elements include a transistor, a capacitance, a resistor, a fuse, and the like. In FIG. 4, a transistor Tr is shown as an example of the plurality of circuit elements.

-Multi-layer wiring-
The multilayer wiring 111 is arranged above the plurality of circuit elements, and by electrically connecting the plurality of circuit elements, for example, a reference voltage generating circuit or the like is formed.
The multilayer wiring 111 is provided so as to penetrate from the interlayer insulating film L1 to the interlayer insulating film L4. The multilayer wiring 111 is formed by laminating a structure in which a metal wiring is arranged on the upper surface of the plug and the side surface of the metal wiring is covered with a barrier metal film and an antireflection film.

The barrier metal films 111a, 111e, 111i, 111m are formed as bases for the metal wirings 111c, 111g, 111k, 111o laminated on the upper surfaces of the interlayer insulating films L1, L2, L3, L4, respectively. It is also formed inside via holes provided by etching from the upper surfaces of the interlayer insulating films L1, L2, L3, and L4.
The barrier metal films 111a, 111e, 111i, 111m are formed of a titanium film and a titanium nitride film (hereinafter, referred to as "Ti / TiN film").

The plugs 111b, 111f, 111j, 111n are formed by depositing tungsten inside a via hole on which a barrier metal film is formed.

The metal wirings 111c, 111g, 111k, 111o are formed by depositing Al—Cu, which is an aluminum alloy, on the upper surface of the plugs 111b, 111f, 111j, 111n and the upper surface of the barrier metal film located around the plugs 111c, 111g, 111k, 111o.

The antireflection films 111d, 111h, 111l, 111p as the refractory metal film are formed on the entire upper surface of the metal wirings 111c, 111g, 111k, 111o. That is, a refractory metal film is formed on the upper surface of the uppermost layer of the multilayer wiring 111.
The antireflection films 111d, 111h, 111l, 111p are formed of a Ti / TiN film like the barrier metal films 111a, 111e, 111i, 111m.
A barrier metal film formed of a Ti / TiN film can also be said to be a refractory metal film.

The interlayer insulating films L1, L2, L3, and L4 are silicon oxide films (hereinafter referred to as "BPSG films") to which phosphorus and boron are added in the present embodiment. For example, other silicon oxide films and silicon carbide films are used. , A laminated structure with a silicon carbon nitride film or the like may be used.

<< Protective wall formation area >>
As described above, the protective wall forming region 120 is formed with the first protective wall 121 and the second protective wall 122 so as to double surround the element forming region 110.
Such a protective wall may be referred to as a guard ring, a seal ring, a moisture-resistant ring, a metal ring, a crack stop, or the like.

-First protective wall-
The first protective wall 121 is provided so as to penetrate the interlayer insulating film L1 from the interlayer insulating film L4. The first protective wall 121 is formed by laminating a structure in which metal wiring is arranged on the upper surface of the plug and the side surface of the metal wiring is covered with a barrier metal film and an antireflection film.

The barrier metal films 121a, 121e, 121i, 121m are formed as bases for the metal wirings 121c, 121g, 121k, 121o laminated on the upper surfaces of the interlayer insulating films L1, L2, L3, and L4, respectively. It is also formed inside the groove-shaped via holes provided by etching from the upper surfaces of the interlayer insulating films L1, L2, L3, and L4. The groove-shaped via holes are continuously formed in a groove shape so as to surround the element forming region 110.
The barrier metal films 121a, 121e, 121i, 121m are formed of a Ti / TiN film.

The groove-shaped plugs 121b, 121f, 121j, 121n are formed by depositing tungsten on the inside of the groove-shaped via hole with a barrier metal film as a base.

The metal wirings 121c, 121g, 121k, 121o are formed by depositing Al-Cu on the upper surface of the groove-shaped plugs 121b, 121f, 121j, 121n and the upper surface of the barrier metal film located around the groove plugs 121b, 121f, 121j, 121n.

The antireflection films 121d, 121h, 121l, 121p as the refractory metal film are formed on the entire upper surface of the metal wiring 121c, 121g, 121k, 121o. That is, a refractory metal film is formed on the upper surface of the uppermost layer of the first protective wall 121.
The antireflection films 121d, 121h, 121l, 121p are formed of a Ti / TiN film like the barrier metal films 121a, 121e, 121i, 121m.

As described above, since the refractory metal film is formed on a part of the upper surface and the lower surface of the metal wiring, the semiconductor device 100 is on the peripheral edge of the metal wiring even if the metal wiring contains aluminum or copper. Since aluminum and copper are less likely to diffuse from the metal wiring to the interlayer insulating film, electromigration and the like can be suppressed. Further, since the refractory metal film formed on the upper surface of the metal wiring functions as an antireflection film, the processing accuracy by photolithography can be improved.

-Second protective wall-
In the second protective wall 122, since the refractory metal film on the upper surface of the metal wiring in the uppermost layer of the first protective wall 121 is removed in the entire area, the entire upper surface of the metal wiring in the uppermost layer is in contact with the passivation film P1. It has the same structure as the first protective wall 121 except that it has a structure similar to that of the first protective wall 121. In other words, as compared with the first protective wall 121, the upper surface of the metal wiring 122o, which is the uppermost layer of the second protective wall 122, is different in that the refractory metal film is not arranged.
As a result, even if water infiltrates through the cracks that reach the upper surface of the metal wiring 122o during dicing, it is possible to prevent cracks from occurring in the passivation films P1 and P2 due to volume expansion due to oxidation of the refractory metal film. That is, the second protective wall 122 can prevent the propagation of cracks and suppress the occurrence of further cracks starting from the second protective wall 122.

Further, the first protective wall 121 and the second protective wall 122 adjacent to each other are arranged apart from each other. As for the distance between the first protective wall 121 and the second protective wall 122, even if the Ti / TiN film of the second protective wall 122 expands and cracks occur, the cracks are the first protective wall 121. It is preferable to separate them to the extent that they do not reach.
As a result, when the cracks during dicing reach other layers other than the uppermost layer, even if further cracks are generated starting from the second protective wall 122, the cracks are adjacent to the first protective wall. It can be made difficult to propagate to 121.

<< Passivation Membrane >>
The passivation film P1 is a silicon oxide film formed by plasma, and is formed on the uppermost surface of the entire surface of the semiconductor wafer W, that is, the entire surface of the element forming region 110, the protective wall forming region 120, and the scribe region S.
The passivation film P2 is a silicon nitride film formed by plasma, and like the passivation film P1, is formed on the uppermost surface of the entire area of the element forming region 110, the protective wall forming region 120, and the scribe region S.
When cracks occur in these passivation films P1 and P2, moisture and gas easily infiltrate. Therefore, it is necessary to prevent cracks from occurring at least during manufacturing.

As described above, in the semiconductor device 100, the refractory metal film is formed on the upper surface other than the uppermost layer of the protective wall 122 located at the outermost edge of the uppermost layers of the protective walls 121 and 122, and the element forming region 110 and the element forming region 110 are formed. Passivation films P1 and P2 are formed on the uppermost surface of the protective wall forming region 120, and the entire upper surface of the uppermost layer of the protective wall 122 located at the outermost edge is in contact with the passivation film P1.

(Manufacturing method of semiconductor device)
Next, a method of manufacturing the semiconductor device according to the first embodiment will be described.
The method for manufacturing the semiconductor device 100 according to the first embodiment includes an element forming step and a wiring step.

<Element formation process>
The element forming step is a step of forming a plurality of circuit elements in the element forming region 110, and is sometimes referred to as a front end. Here, as an example of forming the circuit element, FIG. 5 shows an example in which the transistor Tr is formed on the semiconductor wafer W.

The transistor Tr is formed by structurally combining a P-type well region 1, a separation oxide film 2, a gate oxide film 3, a source / drain region 4, and a gate electrode 5.
In order to form the transistor Tr, first, boron is injected into a part of the active region separated by the separation oxide film 2 which is LOCOS (LOCal Oxidation of Silicon) to form the P-type well region 1. Next, an N-type channel-doped region is formed on a part of the surface of the P-type well region 1, and a gate oxide film 3 is formed on the channel-doped region. Next, a low-concentration phosphorus is injected into the polysilicon film formed on the gate oxide film 3 to form the gate electrode 5. Next, a high-concentration N-type source / drain region 4 is formed on the surface of the P-type well region 1 at a position sandwiching the channel-doped region under the gate oxide film 3.
Then, the interlayer insulating film L1 which is a BPSG film is formed over the entire semiconductor wafer W.

It should be noted that these are formed by photolithography in which a necessary portion is photomasked.
Further, in the present embodiment, the separation oxide film is LOCOS, but the present invention is not limited to this, and for example, STI (Shallow Trench Isolation) may be used.

<Back end of line>
The wiring step is a step of forming a multilayer wiring 111 that is electrically connected to a plurality of circuit elements in the element forming region 110, and is sometimes referred to as a back end. Further, in this wiring step, at the same time as forming the multilayer wiring 111, the first protective wall 121 and the second protective wall 122 having the multilayer wiring structure are formed in the protective wall forming region 120.

Specifically, first, on the upper surface of the interlayer insulating film L1, via holes are provided by selective etching by photolithography at the positions where the circuit elements are connected and the protective walls are provided (see FIG. 6), and then Ti / TiN. A barrier metal film, which is a film, is formed over the entire wafer (see FIG. 7).

Next, after depositing tungsten on the barrier metal film (see FIG. 8), the tungsten plug 111b is formed in the via hole by flattening the interlayer insulating film L1 so as to leave the barrier metal film on the upper surface. (See FIG. 9).

Next, after forming the metal wiring of Al—Cu on the flattened surface, that is, the barrier metal film and the upper surface of the plug 111b, an antireflection film (melting point metal film) which is a Ti / TiN film is formed over the entire wafer. (See FIG. 10).

Then, in the element forming region 110, the shape as a metal wiring for electrically connecting a plurality of circuit elements, and in the protective wall forming region 120, a ring shape surrounding the element forming region 110, a refractory metal film and a metal. The wiring and barrier metal film are selectively etched and removed by photolithography.

Then, as shown in FIG. 11, a part of the multilayer wiring 111 which is a combination of the barrier metal film 111a, the plug 111b, the metal wiring 111c, and the antireflection film 111d is formed in the element forming region 110. At the same time, in the protective wall forming region 120, a part of the first protective wall 121 combined with the barrier metal film 121a, the grooved plug 121b, the metal wiring 121c and the antireflection film 121d, and the barrier metal film 122a , The grooved plug 122b, the metal wiring 122c, and a part of the second protective wall 122 of the combination of the refractory metal film 122d are formed.
Next, as shown in FIG. 12, the interlayer insulating film L2, which is a BPSG film, is formed over the entire wafer.

By repeating such a process in the wiring process, a structure made of a barrier metal film, a (grooved) plug, a metal wiring, and a refractory metal film is sequentially laminated, so that the multilayer wiring 111 other than the uppermost layer, the first The protective wall 121 and the second protective wall 122 are formed.
Next, the formation of the uppermost layer will be described.

FIG. 13 shows a state in which a refractory metal film containing a titanium nitride film is formed on the upper surface of the uppermost layer of the multilayer wiring 111, the first protective wall 121, and the second protective wall 122.
From this state, the refractory metal film formed above the second protective wall 122 is selectively etched and removed by photolithography (see FIG. 14). That is, in the protective wall forming region 120, the antireflection film which is a refractory metal film is removed from the entire upper surface of the metal wiring 122o which is the uppermost layer of the second protective wall 122 located at the outermost edge.

Then, as shown in FIG. 15, the multilayer wiring 111 is reflected in the shape of a metal wiring for electrically connecting a plurality of circuit elements, and the first protective wall 121 is reflected in the shape of a ring surrounding the element forming region 110. The prevention film, metal wiring and barrier metal film are removed by etching. Since the antireflection film has already been removed from the second protective wall 122, the metal wiring and the barrier metal film are removed in a ring shape.

Finally, the passivation film P1 is formed on the uppermost surface of the entire wafer, and then the passivation film P2 is formed (see FIG. 4).
By such a manufacturing method, the semiconductor device 100 according to the first embodiment can be manufactured.

As described above, in the first embodiment, the refractory metal film is formed on the upper surface other than the uppermost layer of the protective wall 122 located at the outermost edge of the uppermost layers of the protective walls 121 and 122, and the element forming region is formed. Passivation films P1 and P2 are formed on the uppermost surfaces of the 110 and the protective wall forming region 120, and the entire upper surface of the uppermost layer of the protective wall 122 located at the outermost edge is in contact with the passivation film P1. In other words, in the protective wall forming region 120, the titanium nitride film is not arranged on the entire upper surface of the metal wiring 122o on the uppermost layer of the second protective wall 122 located at the outermost edge.
As a result, even if water enters from the crack that reaches the upper surface of the uppermost layer of the second protective wall 122 during dicing, the titanium nitride film is not arranged there, so that the crack that occurs due to the expansion of the titanium nitride film. Chain can be suppressed. That is, in the first embodiment, the protective wall can prevent the propagation of cracks in the dicing step, and can suppress the occurrence of further cracks starting from the protective wall that has prevented the propagation of cracks.

(Second Embodiment)
The second embodiment is an embodiment in which the metal wiring of the uppermost layer of the multilayer wiring functions as a bonding pad in the first embodiment.
Specifically, as shown in FIG. 16, the metal wiring 111q on the uppermost layer of the multilayer wiring has a larger area than the other metal wirings 111c, 111g, 111k, and is a pad when viewed in a plan view. It is formed in a shape. Further, the antireflection film 111r formed on the upper surface of the metal wiring 111q is removed by etching leaving the end portion. Further, the passivation films P1 and P2 located above the passivation films P1 and P2 are removed by etching, and openings 111s are provided.
Thereby, in the second embodiment, the metal wiring of the uppermost layer of the multilayer wiring can be used as the bonding pad.

Further, an insulating film 111t is formed on the side wall of the opening 111s so that the antireflection film 111r is not exposed from the opening 111s.
Thereby, in the second embodiment, the titanium nitride contained in the antireflection film 111r can be prevented from expanding in volume due to oxidation, and the occurrence of cracks in the passivation film P can be suppressed.

Next, a method of manufacturing the semiconductor device according to the second embodiment will be described.
The method for manufacturing a semiconductor device according to the second embodiment includes an opening forming step in addition to the steps in the first embodiment.

<Opening process>
In FIG. 17, metal wiring 111q having a larger area than other metal wirings 111c, 111g, 111k is formed on the uppermost layer of the multilayer wiring, and passivation films P1 and P2 are formed on the uppermost surface. Indicates the state of being.
From this state, the antireflection film 111r and the passivation films P1 and P2 formed above the metal wiring 111q are removed by etching to form the opening 111s (see FIG. 18).

Next, an insulating film 111t is formed on the side wall of the opening 111s so that the antireflection film 111r is not exposed from the opening 111s (see FIG. 16).

As described above, in the second embodiment, when the opening 111s is formed and the metal wiring 111q of the uppermost layer of the multilayer wiring 111 is used as the bonding pad, the antireflection film 111r on the upper surface of the metal wiring 111q is the opening. An insulating film 111t is formed on the side wall of the opening 111s so as not to be exposed from the 111s.
As a result, the volume of titanium nitride contained in the antireflection film 111r can be prevented from expanding due to oxidation, and the occurrence of cracks in the passivation films P1 and P2 can be suppressed.

In the present embodiment, when the opening 111s is formed, the end portion of the antireflection film 111r is left and removed, but the present invention is not limited to this, from the viewpoint that the titanium nitride does not expand and cracks are not generated in the periphery thereof. , The antireflection film 111r over the entire upper surface of the metal wiring 111q may be removed.
Further, in the present embodiment, the insulating film 111t is formed on the side wall of the opening 111s, but if the titanium nitride of the antireflection film 111r remaining at the end expands, cracks do not occur in the periphery thereof. It is not necessary to form the insulating film 111t.

As described above, the semiconductor device according to the embodiment of the present invention has an element forming region in which a plurality of circuit elements are formed on a semiconductor substrate, and one or more protections around the element forming region in a plan view. It has a protective wall forming region on which a wall is formed, and in the element forming region, a refractory metal film is formed on the upper surface of the uppermost layer of a multilayer wiring that is electrically connected to a plurality of circuit elements. In the protective wall forming region, one or more protective walls have a multi-layer wiring structure, and a refractory metal film is formed on an upper surface other than the uppermost layer of the protective wall located at the outermost edge of the uppermost layers of one or more protective walls. A passivation film is formed on the uppermost surfaces of the element forming region and the protective wall forming region, and the entire upper surface of the uppermost layer of the protective wall located at the outermost edge is in contact with the passivation film.
As a result, the semiconductor device according to the embodiment of the present invention can prevent the propagation of cracks and suppress the occurrence of further cracks.

In each embodiment, the depth of the protective wall is set to be the same as the depth of the multi-layer wiring, but if it is possible to prevent the propagation of cracks progressing toward the element forming region and suppress the infiltration of moisture and gas, this is the case. It is not limited to.
Further, although the material of the metal wiring is Al—Cu, the material is not limited to this, and for example, other aluminum alloys such as aluminum and Al—Si—Cu may be used.
Further, the thickness of each film is not particularly limited and can be appropriately selected depending on the intended purpose.

100 Semiconductor device 110 Element formation area 111 Multi-layer wiring 111a, 111e, 111i, 111m Barrier metal film 111b, 111f, 111j, 111n plug 111c, 111g, 111k, 111o, 111q Metal wiring 111d, 111h, 111l, 111p, 111r Antireflection Film (high melting point metal film)
111s Opening 111t Insulation film 120 Protective wall forming area 121 First protective wall 121a, 121e, 121i, 121m Barrier metal film 121b, 121f, 121j, 121n Grooved plug 121c, 121g, 121k, 121o Metal wiring 121d, 121h, 121l, 121p Antireflection film (high melting point metal film)
122 Second protective wall (protective wall located on the outermost edge)
122a, 122e, 122i, 122m Barrier metal film 122b, 122f, 122j, 122n Grooved plug 122c, 122g, 122k, 122o Metal wiring 122d, 122h, 122l Antireflection film (high melting point metal film)
W Semiconductor wafer (semiconductor substrate)
L1, L2, L3, L4 interlayer insulating film
P1, P2 passivation membrane
S scribe area
Tr transistor (an example of a circuit element)

Claims (11)

It has an element forming region in which a plurality of circuit elements are formed on a semiconductor substrate, and a protective wall forming region in which one or more protective walls are formed around the element forming region in a plan view.
In the element forming region, a refractory metal film is formed on the upper surface of the uppermost layer of the multilayer wiring electrically connected to each of the plurality of circuit elements.
In the protective wall forming region, the one or more protective walls have a multi-layer wiring structure, and the high melting point is placed on an upper surface other than the uppermost layer of the protective wall located at the outermost edge of the uppermost layers of the one or more protective walls. A metal film is formed,
A semiconductor characterized in that a passivation film is formed on the uppermost surfaces of the element forming region and the protective wall forming region, and the entire upper surface of the uppermost layer of the protective wall located at the outermost edge is in contact with the passivation film. Device. The semiconductor device according to claim 1, wherein the refractory metal film contains titanium nitride. The semiconductor device according to claim 1 or 2, wherein the multilayer wiring and the one or more protective walls have a structure in which a plurality of structures in which metal wiring is arranged on the upper surface of the plug are laminated, respectively. The semiconductor device according to claim 3, wherein other than the structure of the uppermost layer of the protective wall located at the outermost edge, other than the side surface of the metal wiring is covered with the refractory metal film. The semiconductor device according to claim 3 or 4, wherein the metal wiring in the multilayer wiring and one or more protective walls contains aluminum. The semiconductor device according to any one of claims 3 to 5, wherein an opening is provided above the metal wiring in the uppermost layer of the multilayer wiring. The semiconductor device according to claim 6, wherein an insulating film is formed on the inner wall of the opening so that the refractory metal film formed on the metal wiring is not exposed from the opening. The semiconductor device according to any one of claims 1 to 7, wherein when two or more protective walls are formed, the protective walls adjacent to each other are separated from each other. When two or more of the protective walls are formed, any of claims 1 to 8 in which the refractory metal film is formed on the upper surface of the uppermost layer of the protective wall other than the protective wall located at the outermost edge. The semiconductor device described in Crab. A semiconductor device having an element forming region in which a plurality of circuit elements are formed on a semiconductor substrate, and a protective wall forming region in which one or more protective walls are formed around the element forming region in a plan view. It ’s a manufacturing method,
In the element forming region and the protective wall forming region
A step of forming a multi-layer wiring electrically connected to each of the plurality of circuit elements and forming one or more protective walls having a multi-layer wiring structure.
A step of forming a refractory metal film on the upper surface of the uppermost layer of the multilayer wiring and one or more protective walls, and
A step of forming a passivation film on the uppermost surface of the element forming region and the protective wall forming region is included.
In the protective wall forming region
A semiconductor comprising a step of removing the refractory metal film from the entire upper surface of the uppermost layer of the protective wall located at least on the outermost edge of the one or more protective walls before forming the passivation film. Manufacturing method of the device. A semiconductor device having an element forming region in which a plurality of circuit elements are formed on a semiconductor substrate, and a protective wall forming region in which one or more protective walls are formed around the element forming region in a plan view. It ’s a manufacturing method,
In the element forming region and the protective wall forming region
A step of forming a multi-layer wiring electrically connected to each of the plurality of circuit elements and forming one or more protective walls having a multi-layer wiring structure.
A step of forming a melting point metal film on an upper surface other than the uppermost layer of the protective wall located at the outermost edge of the multilayer wiring and the uppermost layer of the one or more protective walls.
A semiconductor characterized by comprising a step of forming a passivation film on the uppermost surfaces of the element forming region and the protective wall forming region so as to be in contact with the entire upper surface of the uppermost layer of the protective wall located at the outermost edge. Manufacturing method of the device.

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