JP2021141546A - Two-stage correlation noise elimination circuit - Google Patents

Abstract

To provide a two-stage correlation noise elimination circuit that can be applied to a high-definition solid-state image sensor with a small-scale circuit configuration so as to remove a correlation noise in an output signal of a solid-state image sensor or a CDS circuit with high accuracy.SOLUTION: A two-stage correlation noise elimination circuit includes a first correlated noise elimination unit 11 to which an output signal of a solid-state image sensor is input, clamps the reset voltage level in the solid-state image sensor in each pixel unit, gain-converts a signal voltage level with inverting first gain, and outputs the signal, and a second correlated noise elimination unit 12 that samples the reset voltage level in the first correlated noise elimination unit 11, and samples the signal voltage level of the first correlated noise elimination unit 11 to perform gain-conversion with non-inverting second gain and output the signal. The second correlated noise elimination unit 12 includes a switched capacitor input stage 121 that samples the reset voltage level from the first correlated noise elimination unit 11, and samples the signal voltage level to transfer the signal to a capacitive negative feedback circuit.SELECTED DRAWING: Figure 1

Description

The present invention relates to a noise reduction circuit of a solid-state image sensor, and more particularly to a two-stage correlation noise removal circuit that removes correlation noise in an output signal of a solid-state image sensor or a CDS circuit.

For solid-state image sensors such as CCD image sensors and CMOS image sensors, in order to reduce random noise (reset noise) that occurs when resetting each pixel and fixed pattern noise that occurs due to variations in the characteristics of the source follower transistors in the pixel. , A CDS circuit that performs correlation double sampling (CDS) processing on the output signal of the solid-state image sensor may be arranged. In particular, the reset noise is a signal because the fluctuation of the reset voltage level immediately after the pixel reset (the signal potential immediately after the reset of the floating diffusion region) appears in the form of being superimposed on the signal voltage level at the time of reading the signal of the captured and received pixel as it is. Correlated noise with respect to voltage.

For example, FIG. 4 is a diagram showing an arrangement example of a typical CDS circuit in the prior art. The CDS circuit 51 is typically between a solid-state image sensor 50 configured as an area image sensor or a linear image sensor and an analog / digital (A / D) conversion circuit 52 that converts an analog signal into a digital signal. Be placed. Then, the CDS circuit 51 inputs the output signal of the solid-state image sensor as an input signal Vin, clamps or samples the reset voltage level immediately after the pixel reset in each pixel unit, and signals the signal voltage at the time of reading the signal of the captured and received pixel. The level is sampled, a signal indicating the difference between the two is output as an output signal Vo to the A / D conversion circuit 52, and the A / D conversion circuit 52 converts the level into a digital signal. In addition, another circuit such as automatic offset adjustment, automatic temperature compensation, automatic gain adjustment, or overvoltage / overcurrent protection may be arranged between the CDS circuit 51 and the A / D conversion circuit 52.

As this CDS circuit, an inverting amplification type correlation noise removal circuit is generally used, and input conversion noise is generated by inputting an output signal of a solid-state image sensor and appropriately amplifying and outputting a signal from which reset noise has been removed. It is possible to further reduce it. However, the one-stage CDS circuit may not be able to sufficiently remove the influence of the reset noise, and the switching noise based on the switching operation of the one-stage CDS circuit may remain as the correlation noise. It is an obstacle to aiming for high dynamic range and high S / N.

Therefore, it is known that the total noise can be further reduced by forming the CDS circuit in two stages (see, for example, Non-Patent Documents 1, 2 and 3).

IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.51, NO.2, pp.185-193, February 2004 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL.53, NO.7, pp.1737-1739, July 2006 Journal of the Institute of Visual Media, Vol. 62, No. 3, pp. 303-306, 2008

As described above, when removing the correlation noise due to the reset noise in the output signal of the solid-state image sensor, even if the influence of the reset noise can be removed by the one-stage CDS circuit, the switching operation of the one-stage CDS circuit. The switching noise based on the above remains as the correlation noise, which is an obstacle in aiming at a high dynamic range and a high S / N.

On the other hand, as a correlated noise removing circuit, for example, as disclosed in Non-Patent Document 2, a two-stage CDS circuit is used, and a method of suppressing the correlated noise generated in the first-stage CDS circuit has been devised. Since the non-inverting amplification type circuit adopted in the CDS circuit of the stage is a fully differential type, the circuit scale is large and it becomes difficult to arrange it between the signal lines (narrow pitch column) in the solid-state image sensor. Therefore, it has been difficult to apply the two-stage CDS circuit to a high-definition solid-state image sensor by the prior art.

Therefore, an object of the present invention is to remove the correlation noise in the output signal of the solid-state image sensor or the CDS circuit with high accuracy in view of the above-mentioned problems, and to obtain a high-definition solid-state image sensor with a circuit configuration smaller than that of the prior art. It is an object of the present invention to provide a two-stage correlation noise elimination circuit which can be applied to a high dynamic range and a high S / N.

The two-stage correlated noise removing circuit of the present invention is a two-stage correlated noise removing circuit that removes the correlated noise in the output signal of the solid-state imaging element or the CDS circuit, and inputs the output signal of the solid-state imaging element to perform the solid-state imaging. The reset voltage level immediately after the pixel reset in the element is clamped to a constant level for each pixel, and the signal voltage level at the time of reading the signal of the captured and received pixel in the solid-state imaging element is gain-converted by the first gain of inversion and output. The output voltages from the first correlated noise removing unit and the first correlated noise removing unit are input, the reset voltage level of the first correlated noise removing unit is sampled, and the signal voltage level of the first correlated noise removing unit is sampled. The second correlated noise removing unit is provided with a second correlated noise removing unit that samples the voltage, converts the gain with a non-inverting second gain, and outputs the voltage. The second correlated noise removing unit inputs the output voltage from the first correlated noise removing unit. A switched capacitor input stage that samples the reset voltage level of the first correlated noise removing unit at the output voltage and samples the signal voltage level of the first correlated noise removing unit and transfers it to the capacitive negative feedback circuit. It is characterized by having.

Further, in the two-stage correlated noise elimination circuit of the present invention, the first gain and the second gain are both composed of a fixed gain, and the second gain is set to a value lower than the first gain. And.

Further, in the two-stage correlation noise elimination circuit of the present invention, either one or both of the first gain and the second gain is configured as a variable gain, and the second gain always operates at a value lower than the first gain. It is characterized by doing.

Further, in the two-stage correlation noise removing circuit of the present invention, the second correlation noise removing unit is characterized by having an offset adjusting means for adjusting two types of reference voltage values.

Further, in the two-stage correlated noise removing circuit of the present invention, the switched capacitor input stage is characterized by having an adjusting means for adjusting the output timing of the second correlated noise removing unit.

Further, in the two-stage correlated noise removing circuit of the present invention, the switched capacitor input stage includes a first switch for inputting an output voltage from the first correlated noise removing unit at one terminal and the first switch. The second switch has a capacitance and a third switch for connecting the other terminal to one terminal, and a second switch and a fourth switch for connecting the other terminal of the capacitance to one terminal, respectively. The other terminal constitutes the output unit of the switched capacitor input stage, and each of the other terminal of the third switch and the other terminal of the fourth switch is a reference for generating the first reference voltage. The signal state at the output from the first correlated noise removing unit connected to the power source and AC-coupled via the first switch and the second switch with reference to the first reference voltage is set to the third switch and the signal state. It is characterized in that it operates so as to sample and output by a signal relay by switching the fourth switch.

Further, in the two-stage correlated noise removing circuit of the present invention, the second correlated noise removing unit constitutes the output unit of the switched capacitor input stage after the switched capacitor input stage. The operational amplifier has an operational amplifier that connects the other terminal to the negative input terminal, and a feedback capacitance and a reset switch that connect one terminal to the negative input terminal of the operational amplifier. It is connected to the reference power supply that generates the reference voltage of 2, and the other terminal of the feedback capacitance and the other terminal of the reset switch are connected to the output terminals of the operational amplifier, respectively, and when the reset switch is off, the feedback The output voltage of the operational amplifier coupled to the capacitance is fed back to the negative input terminal of the operational amplifier, and when the reset switch is turned on, the output voltage of the operational amplifier operates so as to be clamped to the second reference voltage. It is a feature.

Further, in the two-stage correlation noise removal circuit of the present invention, the second correlation noise removal unit is driven by an operation clock supplied for each scanning period for the first to fourth switches and the reset switch. It is characterized in that it operates according to a drive pattern divided into four operation phases.

According to the present invention, it is possible to remove the correlation noise in the output signal of the solid-state image sensor or the CDS circuit with high accuracy with a circuit configuration smaller than that of the prior art, and it is possible to increase the dynamic range and increase the S / N ratio. ..

It is the whole circuit diagram of the two-stage correlation noise elimination circuit of one Example by this invention. It is a figure which shows the drive clock pattern of each operation phase in the two-stage correlation noise elimination circuit of one Example by this invention. It is a circuit diagram which shows the circuit connection state of each operation phase of the 2nd correlation noise removal part in the 2 stage correlation noise removal circuit of 1 Example by this invention. It is a figure which shows the arrangement example of the typical CDS circuit in the prior art.

Hereinafter, the two-stage correlation noise elimination circuit 1 of the embodiment according to the present invention will be described with reference to FIGS. 1 to 3. FIG. 1 is an overall circuit diagram of a two-stage correlation noise elimination circuit 1 according to an embodiment of the present invention.

The two-stage correlation noise elimination circuit 1 of this embodiment is used by replacing the CDS circuit 51 shown in FIG. 4, and the output signal of the solid-state imaging element is input as an input signal Vin, and the reset voltage level immediately after the pixel reset is performed. (Signal potential immediately after resetting the floating diffusion region) is clamped to a constant level for each pixel, the signal voltage level at the time of signal reading of the captured and received pixels is output, and the signal indicating the difference between the two is output signal Vo. This is a circuit that outputs the signal to the A / D conversion circuit 52 and converts it into a digital signal by the A / D conversion circuit 52. Instead of replacing the CDS circuit 51 shown in FIG. 4, a two-stage correlation noise elimination circuit according to an embodiment of the present invention is placed after the CDS circuit 51 that outputs signals of the reset voltage level and the signal voltage level. 1 may be used, and in any case, automatic offset adjustment, automatic temperature compensation, automatic gain adjustment, or overvoltage / overcurrent between the two-stage correlation noise elimination circuit 1 and the A / D conversion circuit 52. Other circuits such as protection may be provided. Further, the two-stage correlation noise removal circuit 1 according to the present invention has a configuration in which the correlation noise in the output signal of the solid-state image sensor is removed in the analog region and the waveform is shaped so that the digital CDS can also be used in the digital region. It has become.

(Overall circuit configuration)
The two-stage correlated noise removing circuit 1 shown in FIG. 1 is composed of a first correlated noise removing unit 11 and a second correlated noise removing unit 12.

Although the circuit configuration itself of the first correlation noise removing unit 11 is composed of a so-called gain conversion circuit, the output signal of the solid-state image sensor is input as an input signal Vin, and the reset voltage level immediately after the pixel reset in the solid-state image sensor Is clamped to a constant level for each pixel, and the signal voltage level at the time of signal reading of the captured and received pixels in the solid-state image sensor is gain-converted by the first gain of inversion and output to the second correlation noise removing unit 12.

More specifically, in the first correlation noise removing unit 11, the input signal Vin is input to one terminal of the capacitance Cc1, and the other terminal of the capacitance Cc1 is connected to the negative input terminal of the operational amplifier OP1. That is, the input signal Vin AC-coupled by the capacitance Cc1 is input to the negative input terminal of the operational amplifier OP1.

Further, the positive input terminal of the operational amplifier OP1 is connected to a reference power supply that generates a reference voltage VRC1. That is, the reference voltage VRC1 is always input to the positive input terminal of the operational amplifier OP1.

Further, one terminal of the feedback capacitance Cf1 is connected to the negative input terminal of the operational amplifier OP1, and the other terminal of the feedback capacitance Cf1 is connected to the output terminal of the operational amplifier OP1. The reset switch RT1 is connected between both terminals of the feedback capacitance Cf1. That is, when the reset switch RT1 is off, the output voltage of the operational amplifier OP1 coupled to the feedback capacitance Cf1 is fed back to the negative input terminal of the operational amplifier OP1, and when the reset switch RT1 is on, the output voltage of the operational amplifier OP1 becomes the reference voltage VRC1. By being clamped, the reset voltage level immediately after the pixel reset can be clamped to a constant level for each pixel.

Therefore, the output voltage Vf of the operational amplifier OP1 is inverted with respect to the input signal Vin in the first correlation noise removing unit 11, the reset voltage level is clamped to the reference voltage VRC1, and the capacitance values of Cc1 and Cf1 are adjusted. The output signal of the first gain G1 can be generated.

On the other hand, the second correlated noise removing unit 12 inputs the output voltage Vf from the first correlated noise removing unit 11, samples the reset voltage level of the first correlated noise removing unit 11, and the first correlated noise removing unit 11. This is a circuit in which the signal voltage level of the above is sampled, gain-converted by a non-inverting second gain, output to the A / D conversion circuit 52 as an output signal Vo, and converted into a digital signal by the A / D conversion circuit 52.

More specifically, in the second correlated noise removing unit 12, the output voltage Vf from the first correlated noise removing unit 11 is input, and the reset voltage level of the first correlated noise removing unit 11 at the output voltage Vf is sampled. A switched capacitor input stage 121 is provided which samples the signal voltage level of the first correlation noise removing unit 11 and transfers it to the capacitance negative feedback circuit.

A first switch P1 for inputting the output voltage Vf from the first correlation noise removing unit 11 at one terminal is arranged in the switched capacitor input stage 121, and the other terminal of the first switch P1 is one of the capacitances Cc2. It is connected to the terminal of. Further, the other terminal of the capacitance Cc2 is connected to one terminal of the second switch P2. The other terminal of the second switch P2 is connected to the negative input terminal of the operational amplifier OP2. That is, the output voltage Vf from the first correlation noise removing unit 11 can be AC-coupled by the capacitance Cc2 via the first switch P1 and the second switch P2.

Further, the one terminal of the capacitance Cc2 is connected to one terminal of the third switch P3, and the other terminal of the capacitance Cc2 is connected to one terminal of the fourth switch P4. Each of the other terminal of the third switch P3 and the other terminal of the fourth switch P4 is connected to a reference power source that generates a reference voltage VRB. That is, the switched capacitor input stage 121 determines the signal state at the output voltage Vf from the first correlated noise removing unit 11 which is AC-coupled via the first switch P1 and the second switch P2 with reference to the reference voltage VRB. It can be input to the negative input terminal of the operational amplifier OP2 while being securely held by the signal relay by switching the third switch P3 and the fourth switch P4 (the reference voltage VRC1 is re-clamped to the reference voltage VRB).

The subsequent stage of the switched capacitor input stage 121 in the second correlated noise removing unit 12 is composed of a so-called capacitive negative feedback circuit together with the capacitance Cc2, and the other terminal of the second switch P2 is connected to the negative input terminal of the operational amplifier OP2. That is, the input signal Vf AC-coupled by the capacitance Cc2 is input to the negative input terminal of the operational amplifier OP2.

Further, the positive input terminal of the operational amplifier OP2 is connected to a reference power supply that generates a reference voltage VRC2. That is, the reference voltage VRC2 is always input to the positive input terminal of the operational amplifier OP2.

Further, one terminal of the feedback capacitance Cf2 is connected to the negative input terminal of the operational amplifier OP2, and the other terminal of the feedback capacitance Cf2 is connected to the output terminal of the operational amplifier OP2. The reset switch RT2 is connected between both terminals of the feedback capacitance Cf2. That is, when the reset switch RT2 is off, the output voltage of the operational amplifier OP2 coupled to the feedback capacitance Cf2 is fed back to the negative input terminal of the operational amplifier OP2, and when the reset switch RT2 is on, the output voltage of the operational amplifier OP2 becomes the reference voltage VRC2. By being clamped, the reset voltage level immediately after the reset in the first correlation noise removing unit 11 can be clamped to a constant level.

Therefore, the output voltage Vo of the operational amplifier OP2 is not inverted with respect to the output voltage Vf from the first correlated noise removing unit 11 in the second correlated noise removing unit 12, and the reset voltage level is clamped to the reference voltage to Cc2. And the capacitance value of Cf2 can be adjusted to generate the output signal of the second gain G2.

Details will be described in more detail later, but as a whole of the two-stage correlation noise elimination circuit 1, the signal indicating the difference in signal voltage level at the time of signal reading of the captured and received pixels from the reset voltage level Vr is defined as vs. G1. If = -Cc1 / Cf1 = -1, G2 = Cc2 / Cf2 = 1, the output voltage Vo at the time of sampling vs is represented by Vo = 3 × VRC2-2 × VRB + vs, and if VRC2 = VRB, then Vo = VRC2 + vs, and the influence of the reset voltage level Vr is removed (clamped at the reference voltage VRC2). Therefore, the two-stage correlation noise elimination circuit 1 clamps the reset voltage level to the reference voltage in a state of being inverted with respect to the input signal Vin, and further obtains the first gain G1 by adjusting the capacitance values of Cc1 and Cf1. The output signal after the gain adjustment by the second gain G2 by adjusting the capacitance values of Cc2 and Cf2 can be output to the A / D conversion circuit.

That is, the two-stage correlation noise removal circuit 1 of this embodiment constitutes two-stage correlation noise removal, and aims to increase the S / N ratio of the signal before the A / D conversion process. In particular, the second correlated noise removing unit 12 in the two-stage correlated noise removing circuit 1 of this embodiment is in a non-inverting state with respect to the input signal Vf from the first correlated noise removing unit 11, and the first correlated noise removing unit 11 It is possible to remove the correlated noise generated in the circuit, and the overall configuration of the circuit is reduced in size, which contributes to high definition of the CMOS area image sensor in particular.

Further, the two-stage correlation noise elimination circuit 1 of this embodiment can adjust two types of reference voltages VRB and VRC2, and the degree of freedom of offset adjustment by adjusting the reference voltages VRB and VRC2 before the A / D conversion process. The dynamic range is increased by improving the degree of freedom of gain adjustment by the first gain G1 by adjusting the capacitance values of Cc1 and Cf1 and the second gain G2 by adjusting the capacitance values of Cc2 and Cf2. Is possible. It should be noted that Cc1, Cf1 and Cc2 and Cf2 may each have an automatic gain adjustment function as a variable capacitance (including switching selection of a plurality of types of capacitances), and may be amplified or attenuated (Attenuator). ) Can be set at will. When the first gain is G1 and the second gain is G2, the input conversion noise is proportional to 1 / (G1 × √G2). Therefore, in order to improve the correlation noise removal performance of the two-stage correlation noise removal circuit 1 as a whole, in the two-stage correlation noise removal circuit 1 of this embodiment, both the first gain G1 and the second gain G2 are fixed gains. When it is composed of, it is preferable that the second gain G2 is set to a value lower than the first gain G1. Further, in the two-stage correlation noise elimination circuit 1 of the present embodiment, when either or both of the first gain G1 and the second gain G2 are configured with variable gains, the second gain G2 is the first gain G1. It is preferable to operate at a lower value at all times.

Further, since the two-stage correlated noise removing circuit 1 of this embodiment is provided with the switched capacitor input stage 121 on the input side of the second correlated noise removing unit 12, the switched capacitor input stage 121 is the first. The output timing of the two-correlated noise removing unit 12 can be easily adjusted, which is advantageous for securing the timing margin of the A / D conversion process.

(Circuit operation)
FIG. 2 is a diagram showing a drive clock pattern of each operation phase in the two-stage correlation noise elimination circuit 1 shown in FIG. Further, FIG. 3 is a circuit diagram showing a circuit connection state of each operation phase of the second correlated noise removing unit 12 shown in FIG.

In FIG. 2, a CMOS area image sensor is assumed as a solid-state image sensor, and the output signal of the solid-state image sensor (input signal Vin of the two-stage correlation noise removal circuit 1) is described as changing in the negative direction by light irradiation. do. Further, in order to enhance the understanding of the operation, G1 = −Cc1 / Cf1 = -1, G2 = Cc2 / Cf2 = 1 and VRC2 = VRB are described in FIG. This is optional, but here VRC2 = VRC1).

Further, in FIG. 2, the first to fourth switches P1, P2, P3, P4 and the reset switches RT1 and RT2 in the two-stage correlation noise elimination circuit 1 shown in FIG. 1 are solid from the control clock generator (not shown). It is assumed that the image sensor is driven by an operation clock supplied for each horizontal scanning period, and the high state shown in FIG. 2 means the switch is on “ON” and the low state means the switch is off “OFF”.

As shown in FIG. 2, the two-stage correlation noise removal circuit 1 shown in FIG. 1 has a first correlation in the second correlation noise removal unit 12 according to a drive pattern divided into four operation phases (1) to (4). It operates non-inverting the input signal Vf from the noise removing unit 11, which is non-inverting the output signal Vf of the first correlated noise removing unit 11 and is generated when the first correlated noise removing unit 11 is reset. The waveform of the signal voltage from which the correlation noise is removed is shaped and output. The two-stage correlated noise elimination circuit 1 shown in FIG. 1 has a noise reduction effect higher than that of the conventional CDS circuit, and has a small-scale circuit configuration. Since the arrangement is possible, it is possible to increase the dynamic range and S / N of the high-definition solid-state image sensor. Hereinafter, the operation will be described more specifically.

<Operation phase (1)>
First, in the second correlated noise removing unit 12, both ends of the capacitance Cc2 are set to the OFF state of the first switch P1 and the second switch P2 in the switched capacitor input stage 121, and the ON state of the third switch P3 and the fourth switch P4. It is connected to a reference power source that generates a reference voltage VRB to reset it, and further, the operational amplifier OP2 and the feedback capacitor Cf2 are reset by setting the reset switch RT2 to the ON state (see FIG. 3A). Further, the first correlation noise removing unit 11 also turns on the reset switch RT1 and resets the input signal Vf from the first correlation noise removing unit 11 to the reference voltage VRC1. At the end of this operation phase (1), the third switch P3, the fourth switch P4, and the reset switch RT2 are turned off. At this time, the output voltage Vo of the second correlation noise removing unit 12 is VRC2, and in this example, VRC2 = VRB.

<Operation phase (2)>
Next, after the first switch P1 and the second switch P2 are turned on, the reset switch RT1 is turned off and the reset voltage level Vr output from the first correlated noise removing unit 11 is set to the second correlated noise removing unit 12. (See FIG. 3 (b)). At this time, the input voltage of the second correlated noise removing unit 12 becomes the reset voltage level Vr output from the first correlated noise removing unit 11, and strictly speaking, it is generated by the ON / OFF operation of the reset switch RT1 at the reference voltage VRC1. It is a value in which the correlation noise is superimposed. At this time, the output voltage Vo of the second correlation noise removing unit 12 is 2 × VRC2-Vr. At the end of this operation phase (2), the second switch P2 is turned off.

<Operation phase (3)>
Next, the fourth switch P4 is turned on, and the terminal on the operational amplifier OP2 side of the capacitance Cc2 is connected to the voltage VRB (see FIG. 3C). Immediately after this, the voltage level Vr + vs in the input signal Vf from the first correlated noise removing unit 11 is input, that is, the first reset voltage level Vr input from the first correlated noise removing unit 11 corresponds to the pixel signal output. A value obtained by superimposing the output signal voltage level vs of the correlated noise removing unit 11 is applied to the input unit of the second correlated noise removing unit 12, and the voltage Vr + vs is sampled in the capacitance Cc2 in the second correlated noise removing unit 12. At this time, the output voltage Vo of the second correlation noise removing unit 12 is 2 × VRC2-Vr as in the above operation phase (2) because the second switch P2 remains in the OFF state. At the end of this operation phase (3), the first switch P1 and the fourth switch P4 are turned off.

<Operation phase (4)>
Next, the second switch P2 and the third switch P3 are turned on, and the electric charge sampled in the capacitance Cc2 is transferred to the feedback capacitance Cf2 (see FIG. 4D). At this time, since the first gain G1 = -1 and the second gain G2 = 1 in this example, the output voltage Vo of the second correlation noise removing unit 12 is 3 × VRC2-2 × VRB + vs, and the first correlation noise. The reset voltage level Vr on which the correlation noise generated in the removing unit 11 is superimposed is removed. Therefore, the residual correlated noise from the first correlated noise removing unit 11 (that is, the residual amount of the reset noise of the image sensor and the switching noise based on the switching operation of the first correlated noise removing unit 11 remains as the correlated noise). Will be removed. Since VRC2 = VRB in this example, the output voltage Vo of the second correlation noise removing unit 12 is VRC2 + vs. That is, the reference voltage can be freely changed by adjusting VRC2 and VRB, and the gain can be adjusted by the first gain G1 by adjusting the capacitance values of Cc1 and Cf1 and the second gain G2 by adjusting the capacitance values of Cc2 and Cf2. Yes, it enables a high dynamic range. At the end of this operation phase (4), the second switch P2 is turned off.

By sequentially executing the operation phases (1) to (4), the two-stage correlated noise elimination circuit 1 shown in FIG. 1 outputs an output signal so as to reduce the correlated noise with respect to the output signal of the solid-state image sensor or the CDS circuit. Can be formatted and output, and high dynamic range and high S / N can be achieved.

(Operation check)
The operation of the two-stage correlation noise elimination circuit 1 shown in FIG. 1 when driven by the drive clock pattern shown in FIG. 2 was confirmed. Vr = 1.5V, VRC2 = 1.3V, VRB = 1.3V, vs = 0.2V, the first gain G1 = -1, and the second gain G2 = 1. From the above, the output voltage in each operation phase is as follows: operation phase (1): VRC2 = 1.3V, operation phase (2), (3): 2 × VRC2-Vr = 2 ・ 1.3-1.5 = 1. .1V, operation phase (4): 3 × VRC2-2 × VRB + vs = 0.2 + 3 ・ 1.3-2 ・ 1.3 = 1.5V, but confirmed that it is operating according to theory bottom. Further, it was confirmed that the two-stage correlated noise removing circuit 1 of this embodiment can achieve a higher S / N of 3 dB or more as compared with the case where the correlated noise removing is not performed. In the two-stage correlation noise removal circuit 1 shown in FIG. 1, even if the influence of the pixel reset noise can be removed by the first-stage first-stage correlation noise removal unit 11, the switching operation of the first-stage correlation noise removal unit 11 The amount of the switching noise remaining as the correlation noise based on the above can be suppressed by the second correlation noise removing unit 12, and a high dynamic range and a high S / N can be realized.

Although the present invention has been described above with reference to examples of specific embodiments, the present invention is not limited to the examples of the above-described embodiments, and various modifications can be made without departing from the technical idea. Therefore, the present invention is not limited to the examples of the above-described embodiments, but is limited only by the description of the scope of claims.

According to the present invention, it is possible to remove the correlation noise in the output signal of the solid-state image sensor or the CDS circuit with a circuit configuration smaller than that of the prior art, and to achieve a high dynamic range and a high S / N ratio. It is useful for removing correlated noise in the output signal of an image sensor or a CDS circuit.

1 2-stage correlated noise removal circuit 11 1st correlation noise removal unit 12 2nd correlation noise removal unit 121 Switched capacitor input stage P1 1st switch in switched capacitor input stage P2 2nd switch in switched capacitor input stage 3rd switch in P3 switched capacitor input stage 4th switch in P4 switched capacitor input stage OP1 Operational amplifier in 1st correlation noise removal section OP2 Operational amplifier in 2nd correlation noise removal section RT1 Reset switch in 1st correlation noise removal section RT2 Reset switch in the second correlated noise removal unit Cc1 Capacity for AC coupling in the first correlation noise removal unit Cf1 Feedback capacity of the operational amplifier in the first correlation noise removal unit Cc2 Switched capacitor input stage in the second correlation noise removal unit Capacitance Cf2 Return capacity of operational amplifier in the second correlated noise removing unit VRC1 Reference voltage in the first correlated noise removing unit VRC2 Reference voltage in the second correlated noise removing unit VRB Reference voltage in the switched capacitor input stage Vin input signal (solid-state imaging element) Output signal)
Vf Output signal of the first correlation noise removal unit (input signal of the second correlation noise removal unit)
Vo output signal (output of the second correlation noise removal unit)
Vr Reset voltage level output from the first correlated noise removal unit vs Signal voltage level output from the first correlated noise removal unit 50 Solid-state image sensor 51 Correlated double sampling (CDS) circuit 52 Analog / digital (A / D) Conversion circuit

Claims (8)

A two-stage correlation noise removal circuit that removes correlation noise in the output signal of a solid-state image sensor or CDS circuit.
The output signal of the solid-state image sensor is input, the reset voltage level immediately after the pixel reset in the solid-state image sensor is clamped to a constant level for each pixel, and the signal voltage at the time of reading the signal of the captured and received pixel in the solid-state image sensor. The first correlation noise remover that converts the level to the first gain of inversion and outputs it,
The output voltage from the first correlated noise removing unit is input, the reset voltage level of the first correlated noise removing unit is sampled, and the signal voltage level of the first correlated noise removing unit is sampled to obtain a non-inverting second. It is equipped with a second correlation noise remover that converts the gain with the gain and outputs it.
The second correlated noise removing unit inputs the output voltage from the first correlated noise removing unit, samples the reset voltage level of the first correlated noise removing unit at the output voltage, and removes the first correlated noise. A two-stage correlated noise elimination circuit characterized by having a switched capacitor input stage that samples the signal voltage level of the unit and transfers it to a capacitive negative feedback circuit. The two-stage correlation noise according to claim 1, wherein both the first gain and the second gain are composed of a fixed gain, and the second gain is set to a value lower than the first gain. Removal circuit. The first aspect of the invention, wherein one or both of the first gain and the second gain are configured by a variable gain, and the second gain always operates at a value lower than the first gain. Two-stage correlation noise removal circuit. The two-stage correlated noise removing circuit according to any one of claims 1 to 3, wherein the second correlated noise removing unit has an offset adjusting means for adjusting two types of reference voltage values. The two-stage correlation noise removal according to any one of claims 1 to 4, wherein the switched capacitor input stage has an adjusting means for adjusting the output timing of the second correlation noise removal unit. circuit. The switched capacitor input stage is
The first switch that inputs the output voltage from the first correlation noise removal unit at one terminal, and
The capacity to connect the other terminal of the first switch to one terminal and the third switch,
It has a second switch and a fourth switch that connect the other terminal of the capacitance to one terminal, respectively.
The other terminal of the second switch constitutes an output unit of the switched capacitor input stage, and each of the other terminal of the third switch and the other terminal of the fourth switch is a first reference. The signal state at the output from the first correlation noise removing unit, which is connected to the reference power source that generates a voltage and is AC-coupled via the first switch and the second switch with reference to the first reference voltage. The two-stage correlated noise removing circuit according to any one of claims 1 to 5, wherein the signal relay by switching between the third switch and the fourth switch operates to sample and output. The second correlated noise removing unit is an operational amplifier that connects the other terminal of the second switch constituting the output unit of the switched capacitor input stage to a negative input terminal after the switched capacitor input stage. And a feedback capacitance and a reset switch, one of which is connected to the negative input terminal of the operational amplifier.
The positive input terminal of the operational amplifier is connected to a reference power supply that generates a second reference voltage, and the other terminal of the feedback capacitance and the other terminal of the reset switch are connected to the output terminal of the operational amplifier, respectively.
When the reset switch is off, the output voltage of the operational amplifier coupled to the feedback capacitance is fed back to the negative input terminal of the operational amplifier, and when the reset switch is on, the output voltage of the operational amplifier becomes the second reference voltage. The two-stage correlated noise elimination circuit according to claim 6, characterized in that it operates so as to be clamped. The second correlation noise removing unit drives the first to fourth switches and the reset switch by an operation clock supplied for each scanning period, and operates according to a drive pattern divided into four operation phases. 7. The two-stage correlation noise removal circuit according to claim 7.

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