CN114679555A

CN114679555A - Solid-state imaging device, AD converter circuit, and current compensation circuit

Info

Publication number: CN114679555A
Application number: CN202111498642.5A
Authority: CN
Inventors: 森下玄
Original assignee: Renesas Electronics Corp
Current assignee: Renesas Electronics Corp
Priority date: 2020-12-24
Filing date: 2021-12-09
Publication date: 2022-06-28
Also published as: JP2022101408A; US11528441B2; US20220210364A1; JP7531390B2

Abstract

The present disclosure relates to a solid-state imaging device, an AD converter circuit, and a current compensation circuit. It is an object of the present invention to provide a technique for reducing variations in bias voltage. An analog-to-digital converter includes a comparator including a first amplifier and a second amplifier input to an output of the first amplifier. The first amplifier is a differential type amplifier and includes one input terminal for receiving a signal and the other input terminal for receiving a reference signal varying at a predetermined slope. The second amplifier is a single-ended type amplifier, and determines an auto-zero voltage through an auto-zero operation of the first amplifier based on the amplified voltage, and includes a self-bias circuit using the auto-zero voltage as a bias voltage. The comparator is a plurality of comparators which are a plurality of comparators arranged in the row direction, and outputs a digital value based on an analog voltage input to the other input terminal in a parallel operation.

Description

Solid-state imaging device, AD converter circuit, and current compensation circuit

Cross Reference to Related Applications

The disclosure of Japanese patent application No. 2020-.

Technical Field

The present disclosure relates to a solid-state imaging device, and is applicable to, for example, an analog-to-digital converter of a solid-state imaging device.

Background

The solid-state imaging device has a pixel array in which a plurality of pixels are arranged in a matrix. Each column of the pixel array is provided with a vertical signal line. A CMOS (complementary metal oxide semiconductor) image sensor is an exemplary solid-state imaging device. With the CMOS image sensor, each pixel includes at least one photoelectric conversion element and an amplification transistor that outputs an electric signal (luminance signal) corresponding to the electric charge accumulated in the photoelectric conversion element to a vertical signal line.

In a CMOS image sensor, an additional column circuit is provided for each column of the pixel array. Each column circuit is provided with an AD converter circuit (hereinafter referred to as an analog-to-digital converter) for converting an electric signal of a corresponding pixel into a digital signal.

The comparator for the analog-to-digital converter compares and judges the luminance signal voltage output from the pixel via the vertical signal line and the reference voltage. Generally, a comparator is composed of several stages of amplifiers, for example, in a two-stage amplifier configuration, a low-speed signal comparison operation is performed at a first-stage amplifier, an operation frequency band is narrowed, and gain up-regulation is performed at a second-stage amplifier. Further, the amplifiers are provided with current source transistors, and control electrodes of the respective current source transistors are provided with bias voltages from a common bias circuit.

The disclosed techniques are listed below.

[ patent document 1] Japanese unexamined patent application publication 2020-

Patent document 1 discloses that a bias voltage is supplied to an amplifier from a common bias circuit.

Disclosure of Invention

However, for example, when a large number of analog-to-digital converters operate in parallel, the bias voltage may fluctuate due to noise on a common bias line that supplies the bias voltage to the second stage amplifier of each analog-to-digital converter.

Other objects and novel features will become apparent from the description and drawings of the specification.

An outline of representative contents of the present disclosure will be briefly described below.

That is, an analog-to-digital converter includes a comparator including a first amplifier and a second amplifier which is input to one output of the first amplifier. The first amplifier is a differential type amplifier and includes one input terminal for receiving a signal and the other input terminal for receiving a reference signal varying at a predetermined slope. The second amplifier is a single-ended amplifier. The second amplifier determines an auto-zero voltage based on the voltage of the first amplifier amplified by the auto-zero operation, and includes a self-bias circuit using the auto-zero voltage as a bias voltage. And the comparator is a plurality of comparators which are a plurality of comparators arranged in the row direction, and the comparator outputs a digital value based on an analog voltage input to the other input terminal in the parallel operation.

According to the present disclosure, variation in bias voltage can be reduced.

Drawings

Fig. 1 is a configuration diagram showing a solid-state imaging device according to an embodiment;

fig. 2 is a block diagram showing a pixel of a solid-state imaging device according to an embodiment;

FIG. 3 is a block diagram illustrating the comparator shown in FIG. 1;

fig. 4 is a circuit diagram showing an exemplary configuration of the reference voltage generating circuit shown in fig. 1;

fig. 5 is a circuit diagram showing an example of the configuration of the bias generating circuit shown in fig. 4;

FIG. 6 is a block diagram illustrating the analog-to-digital converter shown in FIG. 3;

fig. 7 is a diagram showing a state in which AZ switches of the first amplifier and the second amplifier are turned on;

fig. 8 is a diagram showing a state in which the AZ switch of the first amplifier is turned off and the AZ switch of the second amplifier is turned on;

fig. 9 is a diagram showing a state in which AZ switches of the first amplifier and the second amplifier are turned off;

fig. 10 is a diagram showing the states of the first amplifier and the second amplifier after the auto-zero operation;

fig. 11 is a graph showing the current of the second amplifier;

fig. 12 is a diagram for explaining the configuration and operation of a current compensation circuit;

fig. 13 is a diagram showing the currents of the second amplifier and the current compensation circuit;

Fig. 14 is a timing diagram illustrating the operation of the comparator shown in fig. 1;

fig. 15 is a configuration diagram showing a comparator;

fig. 16 is a diagram showing the operation principle of the integrating type analog-to-digital converter; and

fig. 17 is a diagram for explaining a problem in the comparator shown in fig. 15.

Detailed Description

The embodiments will be described below with reference to the drawings. For clarity of explanation, the following description and drawings are appropriately omitted and simplified. In the following description, the same component elements are denoted by the same reference numerals, and a repetitive description thereof may be omitted. It should be noted that the drawings may be schematically represented for clarity of explanation, but are merely examples and do not limit the interpretation of the disclosure.

In order to make the solid-state imaging device clearer in the present embodiment, first, problems of the solid-state imaging device found by the present inventors are explained with reference to fig. 15 to 17. Fig. 15 is a configuration diagram showing a comparator. Fig. 16 is a diagram showing the operation principle of the integrating analog-to-digital converter. Fig. 17 is a diagram for explaining a problem of the comparator shown in fig. 15.

As described above, the solid-state imaging device includes the analog-to-digital converter having the comparator. As shown in fig. 15, a comparator 50 constituting an integrating analog-to-digital converter compares a Luminance Signal (LS) output from a pixel with a RAMP signal (RAMP) as a reference voltage. The comparator 50 includes a first amplifier 51, a second amplifier 52, and a binarization circuit 54. In fig. 15, an exemplary configuration is shown in which the first amplifier 51 is configured with a fully differential amplifier and the second amplifier 52 is configured with a differential amplifier.

The input terminal 51a of the first amplifier 51 is connected to the terminal 51e, and the Luminance Signal (LS) output from the pixel is input to the terminal 51a via the capacitive element C1M. Further, the input terminal 51b of the first amplifier 51 is connected to the terminal 51f, and the terminal 51b is input with a RAMP signal (RAMP) via the capacitive element C1P.

The output terminal 51C of the first amplifier 51 and the input terminal 52a of the second amplifier 52 are connected via a capacitive element C2P. Further, the output terminal 51d of the first amplifier 51 and the input terminal 52b of the second amplifier 52 are connected via a capacitive element C2M.

The first amplifier 51 and the second amplifier 52 must first determine a judgment reference voltage for comparison. The operation for determining this is called an initialization operation or an auto-zero operation. Therefore, the respective amplifiers are operated at their optimum operating points independently of the DC level of the external signal by the auto-zero operation for turning off (turning off the switches) the switches AZ1, AZ2 between the input and output terminals of the first amplifier 51 and between the input and output terminals of the second amplifier 52. The capacitive elements C1P, C1M, C2P, and C2M are sampling capacities of auto-zero levels. A voltage corresponding to the Luminance Signal (LS) is generated by the capacitive element C1M. The capacitive element C1P generates a voltage corresponding to the RAMP signal (RAMP). The capacitive element C2P generates a voltage corresponding to the output voltage of the output terminal 51C. The capacitive element C2M generates a voltage corresponding to the output voltage of the output terminal 51 d.

The output terminal 52c of the second amplifier 52 is connected to the binarization circuit 54. The binarization circuit 54 includes a p-channel mos (pmos) transistor MP51, an n-channel mos (NMOS) transistor MN51, and an NMOS transistor MN 53. The control signal (RSTB) is input to the gate of the PMOS transistor. Further, the output of the second amplifier 52 is input to the gate of the NMOS transistor MN 51. Further, the control signal (EN) is input to the gate of the NMOS transistor MN 51. The binarization circuit 54 includes an inverter circuit. Note that in the disclosed figures, PMOS transistors are marked with circles at the gates to distinguish them from NMOS transistors.

In the first amplifier 51, the differential comparator using the NMOS transistor CS1 as a current source is composed of two NMOS transistors, and the two

input terminals

51a, 51b are connected to the gates. The source of NMOS transistor CS1 is connected to a line providing ground potential (AGND 1).

In the second amplifier 52, the differential comparator using the PMOS transistor CS2 as a current source is composed of two PMOS transistors, and the two

input terminals

52a, 52b are connected to the gates. The source of the PMOS transistor CS2 is connected to a line supplying a power supply potential (AVDD 2). The gate of the NMOS transistor is connected to the output node N2 of the differential comparator. The PMOS transistor CS3 and the NMOS transistor are source-grounded amplification circuits for inputting the gate of the NMOS transistor. The PMOS transistor CS3 is a load transistor that operates as a constant current source. The source of the PMOS transistor CS3 is connected to a line supplied with a power supply potential (AVDD 2).

At the first amplifier 51 of the first stage, a1 times and at the second amplifier 52 of the second stage, a2 times. Therefore, a large current flows through the PMOS transistor CS2 as a constant current source transistor of the second amplifier 52, and the output voltage (VOUT2P) of the output node N2 of the second amplifier 52 changes sharply. Therefore, noise may appear on the common bias line CBL that supplies the bias voltage (BIASP) to the PMOS transistor CS 2.

Incidentally, the current (i11) of the NMOS transistor CS1 as the constant current source transistor of the first amplifier 51 is smaller than the current (i12) of the PMOS transistor CS2 of the second amplifier 52. Further, the current (i11) is larger than the current (i13) of the PMOS transistor CS3 as a constant current source transistor. The magnitude of the current is an example, and is not limited thereto.

In the integrating analog-to-digital converter shown in fig. 15, as shown in fig. 16, when the voltage of the RAMP signal (RAMP) crosses the voltage of the Luminance Signal (LS) from the pixel, the output of the comparator 50 is inverted. Since the Voltage (VDR) of the Luminance Signal (LS) of the dark pixel is higher than the Voltage (VBR) of the Luminance Signal (LS) of the bright pixel, the operation time of the dark pixel is earlier. That is, the operation time differs depending on the brightness. Therefore, the second amplifier 52 of the comparator 50 on the bright pixel side is affected by the operation of the comparator 50 on the dark pixel side through the common bias line CBL.

For example, as shown by an arrow PX1 in fig. 17, when an object in which most of the row direction of the pixel array PA is dark and a part of the center is bright is imaged, many dark pixel (black pixel) comparators will be input with pixel signals having similar values. Thus, the outputs of the comparators of many analog-to-digital converters ADC are inverted simultaneously. This affects the comparators corresponding to the bright pixels (gray pixels) via the common bias line CBL. A stripe pattern appears in the bright pixels (gray pixels).

On the other hand, as shown by an arrow PX2 in fig. 17, when the line direction of the subject is mostly bright and a part of the center is dark, pixel signals having similar values are input to the comparators of many bright pixels (white pixels). This results in the outputs of the plurality of comparators being inverted simultaneously. However, this simultaneous inversion occurs after the inversion operation of the comparator corresponding to the dark pixel (gray pixel). Therefore, the comparator corresponding to the dark pixel (gray pixel) is not affected.

When the outputs of a large number of comparators are inverted simultaneously in this way, noise may be generated due to current variation or the like, and the noise affects the common bias line CBL. Furthermore, current fluctuations during the analog-to-digital conversion period can lead to errors. Then, as the number of columns that are simultaneously inverted increases, such a problem becomes more serious, and thus the effect also increases as the number of pixels increases. Although the second amplifier 52 has been described as an example of a differential type amplifier, even a single-ended type amplifier using a common bias line has the same problem.

Therefore, in a solid-state image pickup device in which a plurality of analog-to-digital converters operate in parallel, it is found that noise on a common bias line is a problem in the case where the common bias line is used in the second amplifier constituting the comparator of the analog-to-digital converter. Such noise causes fluctuation of the bias voltage, and the performance of the solid-state imaging device cannot be improved.

Further, the number of analog-to-digital converters mounted on the solid-state imaging device is typically thousands, requiring power reduction of the analog-to-digital converters. Therefore, we have also proposed a solid-state imaging device that reduces power consumption.

A solid-state imaging device according to an embodiment will be described with reference to fig. 1. Fig. 1 is a configuration diagram showing a solid-state imaging device according to an embodiment.

The solid-state imaging device 1 includes a Pixel Array (PA)17, a control Circuit (CTL)10, a row selection circuit (RSL)11, a reference voltage generation circuit (RVG)12, and a bias circuit (BIS) 13. Further, the solid-state imaging device 1 includes a counter Circuit (CNT)14, a horizontal transfer circuit (HTR)15, a signal processing circuit (SIP)16, and a plurality of analog-to-digital converters 18. The solid-state imaging device 1 is, for example, a CMOS image sensor.

The row selection circuit 11 is controlled by the control circuit 10, and in the pixel array 17, a plurality of pixels 19 are arranged in a matrix in a plurality of rows and columns, and the plurality of pixels 19 are sequentially selected row by row to enable the control lines 111 of the selected row.

The pixel array 17 includes a plurality of pixels 19. In the pixel array 17, a plurality of pixels 19 are arranged in a matrix composed of a plurality of rows and a plurality of columns. The respective pixels 19 are activated in response to the corresponding plurality of control lines 111 being activated. Then, each of the pixels 19 that are enabled outputs a luminance signal voltage of a voltage corresponding to the amount of incident light to the corresponding luminance signal line 197. The operation of the pixels 19 is controlled by the control circuit 10.

In the pixel array 17, video and screen images are photoelectrically converted for each pixel line, and a Luminance Signal (LS) is output to the analog-to-digital converter 18. The analog-to-digital converters 18 are provided in plurality, and the plurality of analog-to-digital converters 18 correspond to the respective vertical signal lines 197. For example, there are provided thousands of analog-to-digital converters 18. The analog-to-digital converters 18 are arranged in columns in the image sensor, and perform digital-to-analog conversion on the luminance signal voltages output to the vertical signal lines 197.

The analog-to-digital converter 18 is an integral type analog-to-digital converter, and is arranged in a plurality of columns for each vertical signal line 197. The analog-to-digital converter 18 includes a comparator 20 and a latch 40. The comparator fig. 20 compares the RAMP signal (RAMP) generated by the reference voltage generating circuit 12 with the Luminance Signal (LS) acquired from each row of pixels through the vertical signal line 197. The latch 40 holds the count result of the counter circuit 14 for counting the comparison time of the comparator 20. The output of each latch 40 is transmitted to the signal processing circuit 16 via the horizontal transmission circuit 15. The specific configuration and function of the comparator 20 will be described in detail later.

In the analog-to-digital converter 18, the comparator 20 arranged for each column compares the Luminance Signal (LS) read out from the vertical signal line 197 with a RAMP signal (RAMP) which is a slope waveform that changes linearly. At this time, the counter circuit 14 operates, and the potential of the RAMP signal (RAMP) having a RAMP waveform changes in one-to-one correspondence with the counter value, converting the potential of the Luminance Signal (LS) into a digital signal. The change of the RAMP signal (RAMP) converts the change of voltage into the change of time, and by counting the voltage of a certain period (clock), the voltage is converted into a digital value. Then, when the Luminance Signal (LS) and the RAMP signal (RAMP) cross, the output of the comparator 20 is inverted, and the count value of the counter circuit 14 at this time is held in the latch 40 to complete analog-to-digital conversion.

After the above-described analog-to-digital conversion period ends, the data held in the latch 40 is input to the signal processing circuit 16 through the horizontal transfer circuit 15, and a two-dimensional image is generated through predetermined signal processing.

The pixels 19 constituting the pixel array 17 shown in fig. 1 will be described with reference to fig. 2. Fig. 2 is a block diagram showing a pixel of a solid-state imaging device according to an embodiment.

The pixel 19 includes a photoelectric conversion element photodiode 191, for example, four NMOS transistors. The four transistors are, for example, a reset transistor 192, a transfer transistor 193, a row select transistor 194, and an amplification transistor 195.

The reset transistor 192 resets the floating diffusion 196 to a predetermined voltage level according to a reset control signal (RST). The transmission transistor 193 transmits the electric signal generated by the photodiode 191 according to a transmission control signal (TX). The row selection transistor 194 outputs a Luminance Signal (LS), which is an analog signal transmitted from the amplification transistor 195 to the vertical signal line 197, according to a row selection Signal (SEL). The amplifying transistor 195 amplifies the potential of the floating diffusion 196. Here, the reset control signal (RST), the transfer control signal (TX), and the row selection Signal (SEL) are supplied from the row selection circuit 11 via a plurality of control lines 111.

The photodiode 191 photoelectrically converts the amount of electrons corresponding to the amount of incident light. When the transmission control signal (TX) is at a high level (hereinafter, simply referred to as an H level), the transmission transistor 193 is in an on state, and transmits electrons photoelectrically converted by the photodiode 191 to the floating diffusion 196.

When the row selection Signal (SEL) is at the H level, the amplification transistor 195 and the vertical signal line 197 are connected. The floating diffusion 196 is connected to the gate electrode of the amplifying transistor 195 to constitute a pixel current source and a source follower circuit. Therefore, a voltage corresponding to the potential of the floating diffusion 196 is output to the vertical signal line 197.

More specifically, by setting the pixel 19 to the H level and turning on the transfer transistor 193, the charge of the photodiode 191 is transferred to the floating diffusion 196 to initialize the photodiode 191. Next, the pixel 19 is set to a low level (hereinafter, abbreviated as an L level) to turn off the transfer transistor 193, and photoelectric conversion is performed for a predetermined period of time to accumulate electric charges.

At the time of reading, by setting the reset control signal (RST) to the H level, the reset transistor 192 is turned on, and the floating diffusion 196 is reset. Subsequently, with the row selection Signal (SEL) being at the H level, the row selection transistor 194 is connected to the vertical signal line 197 to constitute a source follower circuit. When the reset control signal (RST) changes to the L level and the reset transistor 192 turns off, the vertical signal line 197 is output with a voltage value of a dark state (also referred to as "dark voltage") before the electric charges from the photodiode 191 are transferred.

Next, the transfer control signal (TX) becomes H level, the transfer transistor 193 is turned on, and the stored charge is photoelectrically converted by the photodiode 191 and transferred to the floating diffusion 196. The floating diffusion 196 changes in accordance with the transferred electric charges, and outputs a voltage value (also referred to as "signal voltage") corresponding to the pixel light amount to the vertical signal line 197.

By making the difference between the dark voltage and the signal voltage an image signal, a so-called correlated double sampling (CDS: correlated double sampling) operation can be performed to cancel the influence of the DC component variation of the pixels 19 and the reset noise.

When the reading of the pixel 19 is completed, the row selection Signal (SEL) becomes the L level, and the row selection transistor 194 is turned off. These read operations are performed in parallel for a row of pixels 19. The plurality of pixels 19 arranged in one row are read in parallel by a read operation. Accordingly, each of the reset control signal (RST), the transfer control signal (TX), and the row selection Signal (SEL) of the reset transistor 192, the transfer transistor 193, and the row selection transistor 194 is shared in a row.

An outline of the comparator 20 will be described with reference to fig. 3. Fig. 3 is a block diagram illustrating the comparator shown in fig. 1.

The comparator 20 includes a first amplifier 21, a second amplifier 22, and a binarization circuit 24. The comparator 20 compares the voltage of the Luminance Signal (LS) output from the pixel 19 to the vertical signal line 197 with the voltage of the RAMP signal (RAMP) supplied to the reference voltage signal line 121. When the RAMP signal (RAMP) is small, the output signal (OUT) at its output line 241 operates to output the H level.

The output terminal 21c of the first amplifier 21 and the input terminal 21a of the first amplifier 21 are connected via a switch AZ 11. Here, the input terminal 21a is also referred to as a negative input terminal or an inverting input terminal. The output terminal 21c is also referred to as a positive output terminal. Further, the output terminal 21d of the first amplifier 21 and the input terminal 21b of the first amplifier 21 are connected via a switch AZ 12. Here, the input terminal 21b is also referred to as a positive input terminal or a non-inverting input terminal. The output terminal 21d is also referred to as a negative output terminal. Therefore, by the auto-zero operation of turning on the switches AZ11, AZ12 between the input and output terminals of the first amplifier 21, the first amplifier 21 can be operated at an optimum operating point without depending on the external DC level.

The input terminal 21a of the first amplifier 21 is connected to the luminance signal line 197 from the pixel 19 via the capacitive element C11. Accordingly, a voltage corresponding to the input voltage of the vertical signal line 197 is generated. Hereinafter, this is referred to as a luminance signal voltage. The input terminal 21b of the first amplifier 21 is connected to the reference voltage signal line 121 via a capacitive element C12.

The output terminal 21c of the first amplifier 21 is connected to the input terminal 22a of the second amplifier 22 without passing through a capacitive element. The output terminal 22b of the second amplifier 22 is input to the binarization circuit 24.

The reference voltage generation circuit 12 and the bias circuit 13 will be described with reference to fig. 4 and 5. Fig. 4 is a circuit diagram showing an exemplary configuration of the reference voltage generating circuit shown in fig. 1. Fig. 5 is a circuit diagram showing an example of the configuration of the bias generating circuit shown in fig. 1.

As shown in fig. 4, the reference voltage generation circuit 12 includes an operational amplifier 122 and a current DAC (digital-to-analog converter) 123. The positive input terminal 122a of the operational amplifier 122 is shorted to the output terminal 122c, and the positive input terminal 122a is connected to the current DAC 123 controlled by the control circuit 10. The output terminal 122c is connected to the reference voltage signal line 121, and the reference voltage generating circuit 12 outputs a RAMP signal (RAMP) as shown in fig. 16. The reference voltage generation circuit 12 decreases the voltage of the RAMP signal (RAMP) from a predetermined initial voltage with a predetermined slope.

As shown in fig. 5, the bias circuit 13 includes a constant current source 133 and a PMOS transistor 132. The constant current source 133 is connected to the source and gate of the PMOS transistor 132, and outputs a bias Voltage (VBIAS) to the bias signal line 131.

The counter circuit 14 shown in fig. 1 is controlled by the control circuit 10 and is connected to the latch 40 of each analog-to-digital converter 18 via a counter signal line 141.

The configuration and function of the comparator 20 of the analog-to-digital converter 18 will be described with reference to fig. 6. Fig. 6 is a block diagram of the analog-to-digital converter shown in fig. 3. In the present embodiment, the first conductivity type is a p-channel or an n-channel, and the second conductivity type is an n-channel or a p-channel.

The first amplifier 21 includes PMOS transistors MP11 to MP14 and NMOS transistors MN11 to MN 13. The first amplifier 21 acts as a differential type amplifier to amplify the differential incoming voltage.

The source of the PMOS transistor MP11 and the source of the PMOS transistor MP12 are connected to the power supply line 31, and the power supply line 31 is supplied with a power supply potential (AVDD). The drain of the PMOS transistor MP11 is connected to the drain of the NMOS transistor MN11, and the node N11 is formed by a connection point. Further, the drain and gate of the PMOS transistor MP11 are connected, and the connection point is connected to the gate of the PMOS transistor MP 12. The drain of the PMOS transistor MP12 is connected to the drain of the NMOS transistor MN12, and the output node N12 (output terminal 21c) of the first amplifier 21 is formed through its connection point.

Sources of the NMOS transistor MN11 and the NMOS transistor MN12 are connected to each other, and the connection point is connected to a drain of the NMOS transistor MN 13. The source of the NMOS transistor MN13 is connected to the ground line (ground conductor) 32, and the ground line (ground conductor) 32 is supplied with a reference potential or ground potential (AGND). The gate of the NMOS transistor MN11 is connected to the first electrode of the capacitive element C12, and the node N13 (input terminal 21b) is formed by the connection point. Then, the second electrode of the capacitive element C12 is connected to the reference voltage signal line 121 to supply a RAMP signal (RAMP). The gate of the NMOS transistor MN12 is connected to the first electrode of the capacitive element C11, and the node N14 (input terminal 21a) is formed by the connection point. Then, the second electrode of the capacitive element C11 is connected to the vertical signal line 197 to supply a Luminance Signal (LS).

The gate of the NMOS transistor MN13 is also connected to the bias signal line 131 and the first electrode of the capacitive element C13. Then, the second electrode of the capacitive element C13 is connected to the ground line 32.

The source of the PMOS transistor MP13 is connected to the node N11, and the drain of the PMOS transistor MP13 is connected to the node N13. The source of the PMOS transistor MP14 is connected to the node N12, and the drain of the PMOS transistor MP14 is connected to the node N14. The gates of the PMOS transistors MP13, MP14 are commonly connected to a signal line supplied with a first AZ signal (AZ 1B). The first AZ signal (AZ1B) is an active signal of L level, and is supplied from the control circuit 10.

In the first amplifier 21 having such a configuration, the current mirror circuit is constituted by PMOS transistors MP11, MP 12. Further, the differential comparator of the NMOS transistor MN13 constituting the current source is constituted by NMOS transistors MN11, MN 12. Further, the PMOS transistors MP13, MP14 correspond to the switches AZ11, AZ12 shown in fig. 3, and function as auto-zero switches (AZ switches). The capacitive elements C11 and C12 serve as AZ-level sampling capacitors. Then, the output signal (VOUT1) of the first amplifier 21 is output from the output node N12 to the second amplifier 22 via the output terminal 21 c.

The second amplifier 22 includes a PMOS transistor MP21, NMOS transistors MN21, MN22, and a capacitive element C21 as an AZ-stage sampling capacitor. The second amplifier 22 functions as a single-ended type amplifier for amplifying one input voltage. Then, the self-bias circuit 221 is constituted by NMOS transistors MN21, MN22, and a capacitive element C21.

The source of the PMOS transistor MP21 is connected to the power supply line 31, and the gate of the PMOS transistor MP21 is connected to the output terminal 21c of the first amplifier 21 via the input terminal 22 a. The drain of the PMOS transistor MP21 is connected to the drain of the NMOS transistor MN21, and the node N21 is formed by a connection point.

The source of the NMOS transistor MN21 is connected to the ground line 32, the gate of the NMOS transistor MN21 is connected to the first electrode of the capacitive element C21, and the node N22 is formed by a connection point. The second electrode of the capacitive element C21 is connected to the ground line 32.

The drain of NMOS transistor MN22 is connected to node N21, and the source of NMOS transistor MN22 is connected to node N22. The gate of the NMOS transistor MN22 is commonly connected to a signal line supplied with a second AZ signal (AZ 2T). The second AZ signal (AZ2T) is an active high signal and is provided by the control circuit 10.

In the second amplifier 22 having such a configuration, the PMOS transistor MP21 is configured as an amplifier circuit for an input gate. The PMOS transistor MP21 is also referred to as an amplifier stage transistor. The NMOS transistor MN21 also serves as a constant current source. Further, the NMOS transistor MN22 functions as an AZ switch, and the capacitive element C21 functions as an AZ-stage sampling capacitor.

The auto-zero operation of the first amplifier 21 will be described. To perform the auto-zero operation, a reset level (dark voltage) is input to the vertical signal line 197, and an initial voltage of the reference voltage generation circuit 12 is input to the reference voltage signal line 121.

The gate of the PMOS transistor MP14 constituting the switch AZ11 and the gate of the PMOS transistor MP13 constituting the switch AZ12 are supplied with a first AZ signal (AZ1B) for collectively performing the auto-zero operation. The PMOS transistors MP13, MP14 turn on at the falling timing of the first AZ signal (AZ1B), and the first amplifier 21 is in the auto-zero state. When the gate voltages of the NMOS transistor MN11 and the NMOS transistor MN12 are equal, an operation point is determined and the circuit is balanced.

Subsequently, the PMOS transistors MP13, MP14 turn off at the rising timing of the first AZ signal (AZ1B), and the gates of the NMOS transistor MN11 and the NMOS transistor MN12 are both floating. At this time, the difference between the voltage of the vertical signal line 197 and the gate voltage of the NMOS transistor MN12 is held at the capacitive element C11, and the difference between the voltage of the reference voltage signal line 121 and the gate voltage of the NMOS transistor MN11 is held at the capacitive element C12.

The auto-zero operation and the self-bias circuit of the second amplifier 22 will be described with reference to fig. 7 to 9. Fig. 7 is a diagram showing a state in which AZ switches of the first amplifier and the second amplifier are turned on. Fig. 8 is a diagram showing a state in which the AZ switch of the first amplifier is turned off and the AZ switch of the second amplifier is turned on. Fig. 9 is a diagram showing a state in which AZ switches of the first amplifier and the second amplifier are turned off.

As shown in fig. 7, the switch AZ11 as the AZ switch of the first amplifier 21 and the NMOS transistor MN22 as the AZ switch of the second amplifier 22 are turned on. When the noise voltage of the first amplifier 21 is Vn1 and the noise voltage of the second amplifier 22 is Vn2, the respective noise voltages are represented by equations (1) and (2) shown in fig. 7. Where k is boltzmann's constant, T is absolute temperature, C1 is the capacitance of capacitive element C11, and C2 is the capacitance of capacitive element C21.

As shown in fig. 8, at time t1, when the switch AZ11 is turned off and the NMOS transistor MN22 remains turned on, the noise voltage Vn1 of the first amplifier 21 is stored in the capacitive element C11. The output voltage (V1) of the first amplifier 21 is represented by equation (3) shown in fig. 8. Where a1 is the gain of the first amplifier 21. Given the operating point voltage VAZ of the second amplifier 22, VAZ is optimized with the noise of the first amplifier 21.

As shown in fig. 9, at a timing t2(> t1), when the NMOS transistor MN22 is turned off while the holding switch AZ11 is turned off, the following voltage is stored and held in the capacitive element C21. When the voltage of the capacitive element C21 is Vbias, the voltage is represented by equation (4) shown in fig. 9.

Accordingly, the gate of the NMOS transistor MN21 is supplied with Vbias as a predetermined voltage, and when the output signal (OUT1) of the first amplifier 21 is at the L level, a constant current (i2) flows to the NMOS transistor MN 21. The self-bias circuit 221 is configured by NMOS transistors MN21, MN22, and a capacitive element C21, and the capacitive element C21 supplies a bias voltage (Vbias).

Since the output current value determined by the auto-zero operation is held by the capacitance element C21 until the output of the second amplifier 22 is inverted, the resistance of the inversion point of the second amplifier 22 and the process variation do not deteriorate.

Next, the current compensation circuit will be described with reference to fig. 10 to 13. Fig. 10 is a diagram showing states of the first amplifier and the second amplifier after the auto-zero operation. Fig. 11 is a diagram showing the current of the second amplifier. Fig. 12 is a diagram for explaining the arrangement and operation of the current compensation circuit. Fig. 13 is a diagram showing the currents of the second amplifier and the current compensation circuit.

As shown in fig. 10, in an initial state of analog-to-digital (AD) conversion, the voltage of the RAMP signal (RAMP) at the reference voltage signal line 121 is higher than the voltage of the Luminance Signal (LS) at the vertical signal line 197. Therefore, the output signal (OUT1) of the first amplifier 21 is at the H level, and the input voltage of the second amplifier 22 is at the H level. Therefore, since the PMOS transistor MP21 is in the off state, the output signal (OUT2) of the second amplifier 22 is at the L level. At this time, no current flows between the drain and the source of the NMOS transistor MN 21.

When the voltage of the RAMP signal (RAMP) in the reference voltage signal line 121 becomes smaller than the voltage of the Luminance Signal (LS) in the vertical signal line 197, the output signal (OUT1) of the first amplifier 21 is inverted to the L level. At this time, the PMOS transistor MP21 is turned on, and the drain current of the PMOS transistor MP21 flows through the NMOS transistor MN21 to stabilize the current. The second amplifier 22 may limit the current to a constant current (i2), but may not flow continuously all the time. Therefore, the current change of the second amplifier 22 occurs before and after the output inversion of the first amplifier 21. Therefore, a so-called power level difference (inrush current) occurs in which the states of the analog power supplies are different, which may cause an analog-to-digital conversion error.

Therefore, the second amplifier 22 preferably adds a current compensation circuit 23. The current compensation circuit 23 includes PMOS transistors MP31, NMOS transistors MN31, MN 32. The NMOS transistor MN31 is opposite in polarity to the amplifier stage transistor and is also referred to as a current switch transistor. The NMOS transistor MN32 is also referred to as a current compensation transistor.

As shown in fig. 12, in the current compensation circuit 23, the source of the NMOS transistor MN31 is connected to the power supply line 31, and the gate of the NMOS transistor MN31 is connected to the output terminal 21c of the first amplifier 21. The NMOS transistor MN31 is opposite in polarity to the PMOS transistor MP 21. The drain of the NMOS transistor MN31 is connected to the source of the PMOS transistor MP31, and the gate of the NMOS transistor MN31 is connected to the node N21 of the second amplifier 22. The NMOS transistor MN31 is connected in series with the PMOS transistor MP 31. The drain of the PMOS transistor MP31 as a current switch is connected to the drain of the NMOS transistor MN 32. The source of NMOS transistor MN32 is connected to ground line 32, and the gate of NMOS transistor MN32 is connected to node N22 of the second amplifier.

The PMOS transistor MP31 functions as a current switch to turn on and off the current path. The gate level of the PMOS transistor MP31 is controlled by the output signal (OUT2) of the second amplifier 22. When the output signal (OUT2) of the second amplifier 22 is at the L level, the PMOS transistor MP31 is turned on, and a constant current (i3) flows into the current compensation circuit 23. When the output signal (OUT2) of the second amplifier 22 exceeds the threshold voltage of the PMOS transistor MP31, the PMOS transistor MP31 turns off, thereby cutting off the constant current (i3) flowing through the current compensation circuit 23.

If the output signal (OUT1) of the first amplifier 21 is at the H level, the PMOS transistor MP21 is turned off and the NMOS transistor MN31 is turned on. At this time, no current flows in the second amplifier 22, and the output signal (OUT2) of the second amplifier 22 is at the L level. Therefore, the PMOS transistor MP31 is turned on, and a current flows through the current compensation circuit 23.

On the other hand, if the output signal (OUT1) of the first amplifier 21 is at the L level, the PMOS transistor MP21 is turned on and the NMOS transistor MN31 is turned off. At this time, a current flows through the second amplifier 22, and the output signal (OUT2) of the second amplifier 22 is at the H level. Therefore, the PMOS transistor MP31 is turned off, and no current flows through the current compensation circuit 23.

Therefore, as shown in fig. 13, when a current flows through the second amplifier 22, no current flows to the current compensation circuit 23. And when no current flows to the second amplifier 22, the current flows to the current compensation circuit 23. That is, during a period in which the current of the second amplifier 22 stops before the amplification of the second amplifier 22 starts or after the amplification is completed, the current compensation circuit 23 flows the same amount of compensation current as the current flowing through the current source to the current compensation transistor. Therefore, a current flows through one of the second amplifier 22 and the current compensation circuit 23, the currents of the second amplifier 22 and the current compensation circuit 23 become constant, and a power supply level difference is not generated. The current of the second amplifier 22 is the same as the current amount of the current compensation circuit 23. The current of the current compensation circuit 23 is also referred to as a compensation current.

As shown in fig. 6, the binarization circuit 24 includes PMOS transistors MP41, MP42 and NMOS transistors MN41, MN42, MN 43. Then, the inverter circuit is constituted by a PMOS transistor MP42 and an NMOS transistor MN 42.

The source of the PMOS transistor MP41 is connected to the power supply line 31, and the gate of the PMOS transistor MP41 is connected to the signal line 103 supplied with the Reset Signal (RSTB). The drain of the PMOS transistor MP41 is connected to the drain of the NMOS transistor MN43, and the node N41 is formed by a connection point.

The source of the NMOS transistor MN43 is connected to the drain of the NMOS transistor MN41, and the gate of the NMOS transistor MN43 is connected to the signal line 104 supplied with the enable signal (EN). The source of the NMOS transistor MN41 is connected to the ground line 32, and the gate is connected to the output terminal 22b of the second amplifier 22.

The PMOS transistor MP42 has a source connected to the power supply line 33 supplied with the power supply potential (LVDD), and a gate connected to the node N41. The drain of the PMOS transistor MP42 is connected to the drain of the NMOS transistor MN42, and the output node N42 is formed by a connection point. The source of the NMOS transistor MN42 is connected to ground 32, and the gate is connected to node N41.

When the Reset Signal (RSTB) is at the L level, the PMOS transistor MP41 is turned on. Therefore, the node N41 becomes H level. When the Reset Signal (RSTB) becomes H level, the node N41 maintains H level by holding voltage to a parasitic capacitance element such as wiring capacitance.

In the analog-to-digital conversion, when the enable signal (EN) is at the H level, the binarization circuit 24 is enabled. When the voltage of the output signal (OUT2) of the second amplifier 22 as the input voltage of the binarization circuit 24 exceeds the threshold voltage of the NMOS transistor MN41, the NMOS transistor MN41 turns on and the node N41 is pulled down to the L level. Accordingly, the output signal (OUT) of the binarization circuit 24 becomes H level, thereby confirming the output. It should be noted that the output signal (OUT) outputs the H level and the L level of the output signal (OUT) having the magnitude of the power supply potential LVDD.

Incidentally, the current (i1) of the NMOS transistor MN13 as the constant current source transistor of the first amplifier 21 is smaller than the current (i11) of the NMOS transistor CS1 as the constant current source transistor of the first amplifier 51, as shown in fig. 6. For example, when the current consumption of the first amplifier 51 is 5 μ a, the current consumption of the first amplifier 21 is 2.8 μ a. Further, the current (i2) of the NMOS transistor MN21 as the constant current source transistor of the second amplifier 22 is much smaller than the current (i12) of the PMOS transistor CS2 as the constant current source transistor of the second amplifier 52, as shown in fig. 6. For example, when the current consumption of the second amplifier 52 is 25 μ a, the current consumption of the second amplifier 22 is 0.7 μ a. The current (i3) of the NMOS transistor MN32 of the current compensation circuit 23 is equivalent to the current (i2) of the NMOS transistor MN21, and is smaller than the current (i1) of the NMOS transistor MN 13.

The operation of the analog-to-digital converter 18 follows. Fig. 14 is a timing diagram illustrating the operation of the analog-to-digital converter shown in fig. 1.

First, details of each signal shown in fig. 14 are described. The period of operation shown in fig. 14 is a period required for one analog-to-digital conversion. The period of such operation can be divided into six phases, in particular according to the operating conditions: period I through period VI. Period I is a reset period (RST). The period II is a setting period of the dark voltage. Period III is an analog-to-digital conversion period of the dark voltage. The period IV is a period for control by the transmission control signal (TX). The period V is a setting period of the signal voltage. The period VI is an analog-to-digital conversion period of the signal voltage.

The RAMP signal (RAMP) is scanned in an analog-to-digital conversion period (period III) of the dark voltage and an analog-to-digital conversion period (period VI) of the signal voltage, and maintains a predetermined voltage (initial voltage) in another period. The Luminance Signal (LS) outputs a dark voltage in period II and period III, and outputs a signal voltage in period V and period VI.

The reset control signal (RST) and the transmission control signal (TX) are signals that control the pixels 19 to reset the pixels 19 by activating (H level) the reset control signal (RST) in the period I. Further, in the period IV, reading of the signal voltage is performed by activating the transmission control signal (TX).

The first AZ signal (AZ1B), the second AZ signal (AZ2T) in the period II perform an auto-zero operation of the first amplifier 21 and the second amplifier 22 of the comparator 20. The first amplifier 21 and the second amplifier 22 are initialized by activating the first AZ signal (AZ1B) and the second AZ signal (AZ 2T). Here, the first AZ signal (AZ1B) is active at the L level, and the second AZ signal (AZ2T) is active at the H level. The active period of the second AZ signal (AZ2T) is longer than the active period of the second AZ signal (AZ 1B).

The Reset Signal (RSTB) and the enable signal (EN) are signals for controlling the binarization circuit 24 in the comparator 20. The reset operation is performed when the Reset Signal (RSTB) is at the L level. The enable signal EN is enabled at the H level. The periods I, II, IV, V are set to the reset non-enabled state, and the analog-to-digital conversion period of the Dark voltage (period III), the analog-to-digital conversion period of the signal voltage (period VI) are set to the non-reset enabled state.

The period I is a reset period of the pixel 19. The analog-to-digital converter 18 does not require any particular operation.

Period II is the auto-zero operation period of the comparator 20. In the first half of period II, the switches AZ11 and AZ12 inserted between the input and output terminals of the first amplifier 21 are closed. That is, the input terminal 21a and the output terminal 21c of the first amplifier 21 are connected in an on state, and the input terminal 21b and the output terminal 21d of the first amplifier 21 are connected in an on state. Further, the node N21 and the node N22 of the second amplifier 22 are connected in the on state.

In the latter half of period II, the switches AZ11 and AZ12 between the input and output terminals of the first amplifier 21 are opened. That is, the input terminal 21a and the output terminal 21c of the first amplifier 21 are connected in the off state, and the input terminal 21b and the output terminal 21d of the first amplifier 21 are connected in the off state. Further, the node N21 and the node N22 of the second amplifier 22 are connected in the on state.

Meanwhile, a dark voltage is applied to the vertical signal line 197 connected to the comparator 20 as a Luminance Signal (LS) from the pixel 19. An initial voltage as a RAMP signal (RAMP) is applied to the reference voltage signal line 121 of the comparator 20.

As will be described in more detail below. In the comparator 20, in the first half of the period II, the first AZ signal (AZ1B) is supplied at the L level, and the second AZ signal (AZ2T) is supplied at the H level. Accordingly, the PMOS transistors MP13, MP14 as the AZ switches of the first amplifier 21 are turned on. Similarly, the NMOS transistor MN22 as the AZ switch of the second amplifier 22 is turned on. This corresponds to the state shown in fig. 7.

In the latter half of period II, the first AZ signal (AZ1B) switches to the H level. Accordingly, the PMOS transistors MP13, MP14 as the AZ switches of the first amplifier 21 are turned off. This corresponds to the state shown in fig. 8.

When the period II ends, the second AZ signal (AZ2T) switches to the L level. Accordingly, the NMOS transistor MN22, which is the AZ switch of the second amplifier 22, is turned off. This corresponds to the state shown in fig. 9.

In this way, the analog-to-digital converter 18 first samples the initial voltage (offset level) of the reference voltage generation circuit 12, the dark voltage (reset level) of the pixel 19, and the AZ level for each column using the comparator 20. These are stored in the capacitive elements C11 and C12, and the capacitive elements C11 and C12 are AZ-level sampling capacitances. The offset levels of the first amplifier 21 and the second amplifier 22 store charges in the capacitive element C21.

Period III is an analog-to-digital conversion period of the dark voltage. The electric charge is accumulated in the second amplifier 22 of the capacitive element C21, and the potential of the node N22 is at a level capable of turning on the NMOS transistor MN21 and the NMOS transistor MN32 of the current compensation circuit 23. At this time, as shown in fig. 14, the output signal (OUT1) of the first amplifier 21 is at the H level, and the output signal (VOUT2) of the second amplifier 22 is at the L level. This corresponds to the state shown in fig. 10. Therefore, the NMOS transistors MN31, MN32 of the current compensation circuit 23 and the PMOS transistor MP31 as a current switch maintain the on state. A very small current flows through the NMOS transistor MN 32.

In the first amplifier 21 of the comparator 20, in the period III, the gate side nodes N13, N14 of the NMOS transistors MN11, MN12 of the capacitive elements C11, C12, which are sampling capacitances accumulated during the auto-zero operation, are at High Impedance (HiZ). Therefore, the gate inputs of the NMOS transistors MN11, MN12 constituting the differential transistors change with the RAMP change of the RAMP signal (RAMP) by the reference voltage generation circuit 12, and the comparison of the voltage level of the Luminance Signal (LS) is started. Then, after the RAMP signal (RAMP) and the Luminance Signal (LS) cross, the output signal (OUT1) of the first amplifier 21 abruptly changes from the H level (high level) to the L level (low level). The intersection of the RAMP signal (RAMP) and the Luminance Signal (LS) is also referred to as a comparison point.

As a result, the PMOS transistor MPT21 of the second amplifier 22 is turned on, current starts to flow, and the output signal OUT2 of the second amplifier 22 changes from the L level to the H level. Here, the NMOS transistor MN21 is turned on, and a very small current flows. The PMOS transistor MP31 as a current switch of the current compensation circuit 23 is switched to an off state by the output signal (OUT2) of the second amplifier 22 changing from the L level to the H level. Therefore, the current path of the current compensation circuit 23 is cut off, and no current flows to the NMOS transistor MN 32.

The period IV and the period V are an operation of reading a signal from the corresponding pixel 19 and a period for waiting for the signal voltage to stabilize. The analog-to-digital converter 18 prepares for signal voltage conversion such as restoring the potential of the RAMP signal (RAMP) of the reference voltage generating circuit 12 to its original potential.

The period VI is a period for performing analog-to-digital conversion of the signal voltage. The vertical signal line 197 continues to receive the luminance signal voltage from the pixel 19. In the movement of the period IV and the period V over the pixel 19, the signal voltage is input instead of the dark voltage. In period VI, the comparator 20 operates for each column in the same manner as in period III.

According to the present embodiment, there are one or more effects described below.

(1) When the auto-zero operation ends by turning off the switch AZ11 in the first amplifier 21, noise is accumulated in the capacitive element C11. At this time, since the auto-zero operation of the second amplifier 22 is performed, a correct operation point including the noise of the first amplifier 21 can be ensured. That is, the noise of the first amplifier 21 can be eliminated.

(2) The self-bias voltage may be set in the auto-zero operation of the second amplifier 22. With the self-bias voltage, kickback bias through the common bias line is prevented. Therefore, an analog-to-digital conversion error is reduced, and high image quality can be achieved.

(3) By providing a current compensation circuit in the second amplifier 22, the temporal variation of the current can be eliminated. Therefore, even if a single-ended amplifier is used, the analog-to-digital conversion error is reduced, and high image quality comparable to all differential amplifiers can be achieved.

(4) Since the second amplifier 22 is a single-ended amplifier, the area and power consumption can be reduced.

(5) Since no capacitive element is connected to the output terminal of the first amplifier 21, the power consumption of the first amplifier 21 can be reduced.

Although the disclosure made by the public has been specifically described based on the embodiments, the present disclosure is not limited to the above-described embodiments, and needless to say, various modifications may be made.

For example, as for the comparator, the polarity (conductivity type) of the transistor of the comparator 20 in the present embodiment is configured to be the opposite polarity (opposite conductivity type), and the connected power supply potential and the ground potential may also be configured to be the reverse on the circuit.

Claims

1. An analog-to-digital converter comprising:

a comparator including a first amplifier and a second amplifier, the second amplifier being input to one output of the first amplifier,

wherein the first amplifier is a differential type amplifier and includes one input terminal for receiving a signal and the other input terminal for receiving a reference signal varying with a predetermined slope,

Wherein the second amplifier is a single-ended amplifier,

wherein the second amplifier determines an auto-zero voltage based on an amplified voltage by auto-zero operating the first amplifier, and includes a self-bias circuit using the auto-zero voltage as a bias voltage, and

wherein the comparator is plural, the comparator is plural comparators arranged in a row direction, and the comparator outputs a digital value based on an analog voltage input to the other input terminal in a parallel operation.

2. An analog-to-digital converter as claimed in claim 1,

wherein the self-bias circuit comprises a capacitive element for maintaining the auto-zero voltage.

3. An analog-to-digital converter as claimed in claim 2,

wherein the voltage holding electrode of the capacitive element is not connected to the voltage holding electrode of the capacitive element of another comparator.

4. An analog-to-digital converter as claimed in claim 1,

wherein the second amplifier comprises an amplifier stage transistor and a current source,

wherein the analog-to-digital converter further comprises a current compensation circuit comprising a current compensation transistor, and

wherein the current compensation transistor is of opposite polarity to the amplifier stage transistor, and

Wherein the current compensation circuit causes a compensation current of the same amount as that of the current source to flow to the current compensation transistor when a current does not flow to the second amplifier.

5. The analog-to-digital converter of claim 4, further comprising:

a current switching transistor connected in series to the current compensation transistor and input to an output of the second amplifier,

wherein the current switching transistor turns on or off the compensation current flowing to the current compensation transistor based on the output of the second amplifier.

6. A current compensation circuit for use with a single-ended amplifier, the single-ended amplifier including an amplifier stage transistor and a current source, comprising:

a current compensation transistor of opposite polarity to the amplifier stage transistor,

wherein the current compensation circuit causes a compensation current of the same amount as that of the current source to flow to the current compensation transistor when a current does not flow to the single-ended amplifier before amplification of the single-ended amplifier starts or after amplification is completed.

7. The current compensation circuit of claim 6, further comprising:

a current switching transistor connected in series with the current compensation transistor and input to an output of the single-ended amplifier,

Wherein the current switching transistor turns on or off the compensation current flowing to the current compensation transistor based on the output of the single-ended amplifier.

8. A solid-state imaging device comprising:

a pixel array in which a plurality of pixels for outputting luminance signal voltages to signal lines, the luminance signal voltages corresponding to an amount of incident light, are arranged in a matrix;

a reference voltage generating circuit outputting a reference voltage of a ramp signal having a predetermined slope to the ramp signal line;

an analog-to-digital converter for analog-to-digital converting the luminance signal voltage to read the plurality of pixels from the pixel array; and

a control circuit for controlling the analog-to-digital converter,

wherein the analog-to-digital converter includes a plurality of comparators arranged for each pixel line of a column, compares the luminance signal voltage with the reference voltage, and outputs the compared signal,

wherein each comparator comprises;

a first amplifier that compares the luminance signal voltage with the reference voltage and inverts an output at a predetermined comparison point; and

a second amplifier that forms a current path and outputs a gain up-regulation of the output of the first amplifier when the output of the first amplifier is inverted,

Wherein the control circuit determines the auto-zero voltage of the second amplifier based on a voltage obtained by amplifying a voltage of the first amplifier at the time of the auto-zero operation.

9. The solid-state imaging device according to claim 8,

wherein the first amplifier includes a first input terminal coupled to the signal line via a first capacitive element, and a second input terminal coupled to the ramp signal line via a second capacitive element.

10. The solid-state imaging apparatus according to claim 9, further comprising:

a first switch coupled to the first capacitive element; and

a second switch coupled to the second capacitive element;

wherein the second amplifier further comprises:

a first transistor of a first conductivity type, wherein the output of the first amplifier is input to a gate; and

a second transistor of a second conductivity type coupled in series with the first transistor, the second transistor including a third switch for determining an operating point for each column at a start of operation between a gate and a drain, and a gate of the second transistor being coupled to a third capacitive element,

Wherein the control circuit controls the steps of:

(a) turning on the first switch, the second switch, and the third switch,

(b) accumulating a noise voltage of the first amplifier to the first capacitive element and the second capacitive element by turning off the first switch and the second switch while turning on the third switch, amplifying the noise voltage accumulated in the first capacitive element and the second capacitive element by the first amplifier, and determining an operating point voltage of the second amplifier, an

(c) The third switch is turned on while the first switch and the second switch are turned off, and the noise voltage and the operating point voltage of the second amplifier are accumulated in the third capacitive element.

11. The solid-state imaging apparatus according to claim 10, further comprising:

a current compensation circuit that causes a current to flow when the current does not flow to the second amplifier,

wherein the current compensation circuit comprises:

a third transistor of the second conductivity type, wherein the output of the first amplifier is input to the gate;

a fourth transistor of the second conductivity type, wherein the third capacitive element is input to the gate and is coupled in series with the third transistor; and

A fifth transistor of the first conductivity type arranged in a current path including the fourth transistor and the third transistor,

wherein the fifth transistor is turned on or off based on an output level of the second amplifier.

12. The solid-state imaging device according to claim 8,

wherein the comparator further comprises a binarization circuit for receiving the output signal of the second amplifier and outputting the output signal as an output signal of the comparator.

13. The solid-state imaging device according to claim 10,

wherein the first amplifier outputs a comparison output at a level when the first transistor is turned off until the luminance signal voltage crosses the reference voltage to the first transistor, and outputs the comparison output at a level when the first transistor is turned on after crossing to the first transistor.