JP2021128752A5 - - Google Patents

Download PDF

Info

Publication number
JP2021128752A5
JP2021128752A5 JP2020191783A JP2020191783A JP2021128752A5 JP 2021128752 A5 JP2021128752 A5 JP 2021128752A5 JP 2020191783 A JP2020191783 A JP 2020191783A JP 2020191783 A JP2020191783 A JP 2020191783A JP 2021128752 A5 JP2021128752 A5 JP 2021128752A5
Authority
JP
Japan
Prior art keywords
operand
tiles
tile
module
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2020191783A
Other languages
English (en)
Japanese (ja)
Other versions
JP7550614B2 (ja
JP2021128752A (ja
Filing date
Publication date
Priority claimed from US16/859,829 external-priority patent/US11226816B2/en
Application filed filed Critical
Publication of JP2021128752A publication Critical patent/JP2021128752A/ja
Publication of JP2021128752A5 publication Critical patent/JP2021128752A5/ja
Application granted granted Critical
Publication of JP7550614B2 publication Critical patent/JP7550614B2/ja
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

JP2020191783A 2020-02-12 2020-11-18 インメモリコンピューティングに対するデータ配置のための方法及びその方法が適用されたメモリモジュール Active JP7550614B2 (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US202062975577P 2020-02-12 2020-02-12
US62/975,577 2020-02-12
US16/859,829 2020-04-27
US16/859,829 US11226816B2 (en) 2020-02-12 2020-04-27 Systems and methods for data placement for in-memory-compute

Publications (3)

Publication Number Publication Date
JP2021128752A JP2021128752A (ja) 2021-09-02
JP2021128752A5 true JP2021128752A5 (https=) 2023-10-02
JP7550614B2 JP7550614B2 (ja) 2024-09-13

Family

ID=77177440

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2020191783A Active JP7550614B2 (ja) 2020-02-12 2020-11-18 インメモリコンピューティングに対するデータ配置のための方法及びその方法が適用されたメモリモジュール

Country Status (5)

Country Link
US (4) US11226816B2 (https=)
JP (1) JP7550614B2 (https=)
KR (1) KR102653014B1 (https=)
CN (1) CN113254359B (https=)
TW (1) TWI848184B (https=)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI850513B (zh) * 2020-03-06 2024-08-01 南韓商三星電子股份有限公司 用於記憶體內計算的方法及用於計算的系統
EP4165637A4 (en) * 2020-06-16 2024-07-10 Groq, Inc. DETERMINISTIC MEMORY CLOSE TO COMPUTATION FOR DETERMINISTIC PROCESSOR AND ENHANCED DATA MOVEMENT BETWEEN MEMORY UNITS AND PROCESSING UNITS
US11901035B2 (en) 2021-07-09 2024-02-13 Taiwan Semiconductor Manufacturing Company, Ltd. Method of differentiated thermal throttling of memory and system therefor
US12032829B2 (en) 2021-07-21 2024-07-09 Samsung Electronics Co., Ltd. Memory device performing in-memory operation and method thereof
CN116486862B (zh) 2022-01-13 2024-07-26 长鑫存储技术有限公司 地址译码电路、存储器及控制方法
US20230315920A1 (en) * 2022-04-02 2023-10-05 Intel Corporation Apparatus and method to implement homomorphic encyption and computation with dram
KR20230143014A (ko) 2022-04-04 2023-10-11 삼성전자주식회사 반도체 패키지
US12567122B1 (en) 2022-04-19 2026-03-03 Nvidia Corporation Application programming interface to modify tensor dimensions
KR20240175962A (ko) * 2023-06-14 2024-12-23 삼성전자주식회사 Dsp 및 이를 이용한 전자 장치
CN119149457A (zh) * 2023-06-16 2024-12-17 华为技术有限公司 内存系统
CN119201035A (zh) * 2023-06-26 2024-12-27 华为技术有限公司 一种数据处理的方法、芯片和计算设备
KR102814916B1 (ko) * 2023-08-23 2025-05-30 삼성전자주식회사 메모리 장치 및 그 동작 방법
EP4602600A1 (en) * 2023-12-27 2025-08-20 Yangtze Memory Technologies Co., Ltd. Memory device, memory system, and method for data calculation with the memory device
US12596490B2 (en) * 2024-03-13 2026-04-07 Nvidia Corporation Memory management using a register
US20260050543A1 (en) * 2024-08-13 2026-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Compute-in-memory systems and methods with weight update circuits

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR940004434A (ko) * 1992-08-25 1994-03-15 윌리엄 이. 힐러 스마트 다이나믹 랜덤 억세스 메모리 및 그 처리방법
US5953738A (en) * 1997-07-02 1999-09-14 Silicon Aquarius, Inc DRAM with integral SRAM and arithmetic-logic units
US6295586B1 (en) * 1998-12-04 2001-09-25 Advanced Micro Devices, Inc. Queue based memory controller
JP4250900B2 (ja) 2002-03-14 2009-04-08 ソニー株式会社 記憶装置
KR100874949B1 (ko) 2006-11-15 2008-12-19 삼성전자주식회사 단일 명령 다중 자료 프로세서 및 그것을 위한 메모리어레이 구조
US8477146B2 (en) * 2008-07-29 2013-07-02 Marvell World Trade Ltd. Processing rasterized data
US8521958B2 (en) * 2009-06-04 2013-08-27 Micron Technology, Inc. Internal processor buffer
US9542101B2 (en) * 2013-01-22 2017-01-10 Avago Technologies General Ip (Singapore) Pte. Ltd. System and methods for performing embedded full-stripe write operations to a data volume with data elements distributed across multiple modules
US20140331014A1 (en) * 2013-05-01 2014-11-06 Silicon Graphics International Corp. Scalable Matrix Multiplication in a Shared Memory System
JP6388654B2 (ja) * 2013-12-26 2018-09-12 インテル・コーポレーション メモリアクセス中のデータ並べ替え
US10185499B1 (en) * 2014-01-07 2019-01-22 Rambus Inc. Near-memory compute module
US10996959B2 (en) 2015-01-08 2021-05-04 Technion Research And Development Foundation Ltd. Hybrid processor
US9547441B1 (en) * 2015-06-23 2017-01-17 Pure Storage, Inc. Exposing a geometry of a storage device
US11079936B2 (en) 2016-03-01 2021-08-03 Samsung Electronics Co., Ltd. 3-D stacked memory with reconfigurable compute logic
US10180906B2 (en) * 2016-07-26 2019-01-15 Samsung Electronics Co., Ltd. HBM with in-memory cache manager
US10175980B2 (en) 2016-10-27 2019-01-08 Google Llc Neural network compute tile
US10242728B2 (en) 2016-10-27 2019-03-26 Samsung Electronics Co., Ltd. DPU architecture
US9922696B1 (en) * 2016-10-28 2018-03-20 Samsung Electronics Co., Ltd. Circuits and micro-architecture for a DRAM-based processing unit
EP4089531B1 (en) * 2016-12-31 2024-06-26 Intel Corporation Systems, methods, and apparatuses for heterogeneous computing
JP6988231B2 (ja) 2017-07-26 2022-01-05 富士通株式会社 情報処理装置、情報処理システム、情報処理方法及び情報処理プログラム
US10866900B2 (en) * 2017-10-17 2020-12-15 Samsung Electronics Co., Ltd. ISA extension for high-bandwidth memory
US20190130291A1 (en) * 2017-10-27 2019-05-02 Wave Computing, Inc. Dynamic reconfiguration with partially resident agents
US11373088B2 (en) 2017-12-30 2022-06-28 Intel Corporation Machine learning accelerator mechanism
KR102410566B1 (ko) * 2018-02-05 2022-06-17 삼성전자주식회사 반도체 메모리 장치, 이를 포함하는 메모리 시스템 및 반도체 메모리 장치의 동작 방법
US10572568B2 (en) 2018-03-28 2020-02-25 Intel Corporation Accelerator for sparse-dense matrix multiplication
US10664287B2 (en) 2018-03-30 2020-05-26 Intel Corporation Systems and methods for implementing chained tile operations
US10691182B2 (en) * 2019-05-20 2020-06-23 Intel Corporation Layered super-reticle computing: architectures and methods
US11237903B2 (en) * 2019-06-25 2022-02-01 Intel Corporation Technologies for providing ECC pre-provisioning and handling for cross-point memory and compute operations
US12248762B2 (en) * 2020-01-07 2025-03-11 SK Hynix Inc. Processing-in-memory (PIM) devices

Similar Documents

Publication Publication Date Title
JP2021128752A5 (https=)
Asifuzzaman et al. A survey on processing-in-memory techniques: Advances and challenges
JP7550614B2 (ja) インメモリコンピューティングに対するデータ配置のための方法及びその方法が適用されたメモリモジュール
US20250181512A1 (en) Bandwidth boosted stacked memory
US10180808B2 (en) Software stack and programming for DPU operations
CN114391135A (zh) 用于对连续分配数据执行存储器内处理操作的方法及相关存储器装置和系统
JP2018073402A (ja) Dram基盤プロセシングユニット
US20200175355A1 (en) Neural network accelerator with systolic array structure
WO2021046568A1 (en) Methods for performing processing-in-memory operations, and related memory devices and systems
CN111459552B (zh) 一种内存中并行化计算的方法及装置
Lee et al. Buffered compares: Excavating the hidden parallelism inside DRAM architectures with lightweight logic
EP3931688B1 (en) Data processing
TW202117561A (zh) 記憶體裝置及其記憶體內計算方法
WO2016180063A1 (zh) 写请求的处理方法和内存控制器
TWI850513B (zh) 用於記憶體內計算的方法及用於計算的系統
Lin et al. Thermal-constrained memory management for three-dimensional DRAM-PCM memory with deep neural network applications
CN114218150A (zh) 一种异构众核架构上cpu共享数组引导维选取策略
TWI920702B (zh) 記憶體電路及操作記憶體電路的方法
TWI919552B (zh) 記憶體電路及其操作方法
US20250173397A1 (en) Computing device having a non-volatile weight memory
KR20240118633A (ko) 메모리 장치 및 그 동작 방법
WO2025085124A2 (en) Systolic ai processor compiler
KR20250145214A (ko) 뱅크 별 비동기 실행에 기반한 pim 및 이의 동작 방법
Sun et al. A Hybrid Processing-in-Memory and Computing-in-Memory Architecture for Large Language Model Inference in Edge Devices
Sudarshan et al. Architectures-Trends, Challenges