JP2021122035A

JP2021122035A - Wiring board

Info

Publication number: JP2021122035A
Application number: JP2020014734A
Authority: JP
Inventors: 拓己大園; Takumi Osono; 久義和田; Hisayoshi Wada
Original assignee: Kyocera Corp
Current assignee: Kyocera Corp
Priority date: 2020-01-31
Filing date: 2020-01-31
Publication date: 2021-08-26
Anticipated expiration: 2040-01-31
Also published as: JP7433065B2

Abstract

To provide a wiring board that can reduce the generation of noise.SOLUTION: In a wiring board 1, a first gap located between a first plain conductor 41P and a second plain conductor 42P of a first core conductor layer 4a, and a second gap located between a first plain conductor and a second plain conductor of a first build-up conductor layer, are arranged at a first position P1. A third gap located between a first plain conductor and a second plain conductor of a second core conductor layer 4b, and a fourth gap located between a first plain conductor and a second plain conductor of a second build-up conductor layer, are arranged at a second position P2. The first position and the second position are arranged at different positions. That is, the first plain conductor and the second plain conductor have parts opposite to each other only across a core insulating plate having a thickness larger than the thickness of the first and second build-up insulating layers.SELECTED DRAWING: Figure 1

Description

本発明は、配線基板に関する。 The present invention relates to a wiring board.

特許文献１に記載のように、デジタル回路とアナログ回路とを含みデジタルグランドとアナロググランドとが分離している配線基板において、ＦＣパッド（Flip Chip Pad）とＢＧＡパッド（Ball Grid Array Pad）との配置の関係で、デジタルグランドとアナロググランドとを重ねる必要がある。 As described in Patent Document 1, in a wiring board including a digital circuit and an analog circuit in which a digital ground and an analog ground are separated, an FC pad (Flip Chip Pad) and a BGA pad (Ball Grid Array Pad) are used. Due to the arrangement, it is necessary to overlap the digital ground and the analog ground.

特開平１１−１４５５７０号公報Japanese Unexamined Patent Publication No. 11-145570

本開示に係る配線基板は、上面および下面を有するコア絶縁板と、コア絶縁板の上面に位置する第１コア導体層と、コア絶縁板の下面に位置する第２コア導体層と、コア絶縁板を貫通して、第１コア導体層と第２コア導体層とを電気的に接続するスルーホール導体と、第１コア導体層の上面に位置する第１ビルドアップ部と、第２コア導体層の下面に位置する第２ビルドアップ部と、第１ビルドアップ部の表面に位置する第１実装部と、第２ビルドアップ部の表面に位置する第２実装部と、を有している。第１ビルドアップ部は、第１コア導体層の上面に位置し、少なくとも一層の第１ビルドアップ絶縁層と、第１ビルドアップ絶縁層の上面に位置する少なくとも一層の第１ビルドアップ導体層と、第１ビルドアップ絶縁層を貫通して、第１ビルドアップ絶縁層を介して上下に対向する第１ビルドアップ導体層同士または第１ビルドアップ導体層と第１コア導体層とを電気的に接続する第１ビアホール導体と、を有している。第２ビルドアップ部は、第２コア導体層の下面に位置し、少なくとも一層の第２ビルドアップ絶縁層と、第２ビルドアップ絶縁層の下面に位置する少なくとの一層の第２ビルドアップ導体層と、第２ビルドアップ絶縁層を貫通して、第２ビルドアップ絶縁層を介して上下に対向する第２ビルドアップ導体層同士または第２ビルドアップ導体層と第２コア導体層とを電気的に接続する第２ビアホール導体と、を有している。第１コア導体層、第１ビルドアップ導体層、第２コア導体層および第２ビルドアップ導体層は、それぞれ、平面透視した場合に、第１実装部および第２実装部が互いに重なる領域において、一方向に横切る隙間を挟んで位置する第１プレーン導体と第２プレーン導体とを有している。第１コア導体層、第１ビルドアップ導体層、第２コア導体層および第２ビルドアップ導体層の第１プレーン導体同士は、スルーホール導体、第１ビアホール導体および第２ビアホール導体を介して電気的に接続されている。第１コア導体層、第１ビルドアップ導体層、第２コア導体層および第２ビルドアップ導体層の第２プレーン導体同士は、スルーホール導体、第１ビアホール導体および第２ビアホール導体を介して電気的に接続されている。隙間は、第１コア導体層の第１プレーン導体と第２プレーン導体の間に位置する第１隙間、第１ビルドアップ導体層の第１プレーン導体と第２プレーン導体の間に位置する第２隙間、第２コア導体層の第１プレーン導体と第２プレーン導体の間に位置する第３隙間、および第２ビルドアップ導体層の第１プレーン導体と第２プレーン導体の間に位置する第４隙間を含んでいる。平面透視において、第１隙間および第２隙間は第１位置に配置されており、第３隙間および第４隙間は第２位置に配置されており、第１位置と第２位置は異なる。 The wiring substrate according to the present disclosure includes a core insulating plate having an upper surface and a lower surface, a first core conductor layer located on the upper surface of the core insulating plate, a second core conductor layer located on the lower surface of the core insulating plate, and core insulation. A through-hole conductor that electrically connects the first core conductor layer and the second core conductor layer through the plate, a first build-up portion located on the upper surface of the first core conductor layer, and a second core conductor. It has a second build-up portion located on the lower surface of the layer, a first mounting portion located on the surface of the first build-up portion, and a second mounting portion located on the surface of the second build-up portion. .. The first build-up portion is located on the upper surface of the first core conductor layer and has at least one layer of the first build-up insulating layer and at least one layer of the first build-up conductor layer located on the upper surface of the first build-up insulating layer. , The first build-up conductor layers facing each other vertically through the first build-up insulating layer, or the first build-up conductor layer and the first core conductor layer are electrically connected to each other through the first build-up insulating layer. It has a first via hole conductor to be connected. The second build-up portion is located on the lower surface of the second core conductor layer, and has at least one layer of the second build-up insulating layer and at least one layer of the second build-up conductor located on the lower surface of the second build-up insulating layer. The second build-up conductor layers facing each other or the second build-up conductor layer and the second core conductor layer are electrically connected to each other through the layer and the second build-up insulating layer and vertically facing each other through the second build-up insulating layer. It has a second via hole conductor which is connected to the conductor. The first core conductor layer, the first build-up conductor layer, the second core conductor layer, and the second build-up conductor layer are formed in a region where the first mounting portion and the second mounting portion overlap each other when viewed in a plane. It has a first plane conductor and a second plane conductor located across a gap that crosses in one direction. The first plane conductors of the first core conductor layer, the first build-up conductor layer, the second core conductor layer, and the second build-up conductor layer are electrically connected to each other via the through-hole conductor, the first via-hole conductor, and the second via-hole conductor. Is connected. The second plane conductors of the first core conductor layer, the first build-up conductor layer, the second core conductor layer, and the second build-up conductor layer are electrically connected to each other via the through-hole conductor, the first via-hole conductor, and the second via-hole conductor. Is connected. The gaps are the first gap located between the first plane conductor and the second plane conductor of the first core conductor layer, and the second gap located between the first plane conductor and the second plane conductor of the first build-up conductor layer. A gap, a third gap located between the first and second plane conductors of the second core conductor layer, and a fourth located between the first and second plane conductors of the second build-up conductor layer. It contains a gap. In planar perspective, the first gap and the second gap are arranged at the first position, the third gap and the fourth gap are arranged at the second position, and the first position and the second position are different.

本開示の一実施形態に係る配線基板の要部を示す断面図である。It is sectional drawing which shows the main part of the wiring board which concerns on one Embodiment of this disclosure. 本開示の一実施形態に係る配線基板の要部において、絶縁層およびソルダーレジストを除去した状態を模式的に示す斜視図である。It is a perspective view which shows typically the state which the insulating layer and the solder resist were removed in the main part of the wiring board which concerns on one Embodiment of this disclosure. 本開示に係る配線基板の一例についてのシミュレーションモデルを示す。A simulation model for an example of the wiring board according to the present disclosure is shown.

上記のように、従来の配線基板において、デジタルグランドとアナロググランドとを対向させる必要がある場合、同一のビルドアップ部で対向させている。しかし、デジタルグランドとアナロググランドとを同一のビルドアップ部で対向させると、両グランドの距離が近くなりすぎ、干渉が大きくなる。その結果、このような配線基板はノイズ量が多くなり、信号の伝送特性が低下する。 As described above, when it is necessary to make the digital ground and the analog ground face each other in the conventional wiring board, they are made to face each other in the same build-up section. However, if the digital ground and the analog ground are opposed to each other in the same build-up portion, the distance between the two grounds becomes too close and the interference becomes large. As a result, such a wiring board has a large amount of noise, and the signal transmission characteristics are deteriorated.

本開示に係る配線基板は、第１コア導体層の第１プレーン導体と第２プレーン導体との間に位置する第１隙間と、第１ビルドアップ導体層の第１プレーン導体と第２プレーン導体との間に位置する第２隙間とは、平面透視で第１位置に配置されている。また、第２コア導体層の第１プレーン導体と第２プレーン導体との間に位置する第３隙間と、第２ビルドアップ導体層の第１プレーン導体と第２プレーン導体との間に位置する第４隙間とは、平面透視で第２位置に配置されている。そして、第１位置と第２位置とは異なる位置に配置されている。つまり、第１プレーン導体と第２プレーン導体とは、第１および第２ビルドアップ絶縁層の厚みよりも大きい厚みを有するコア絶縁板を介してのみ対向する部分を有している。したがって、第１プレーン導体と第２プレーン導体とが、互いに距離を保って対向している。その結果、第１プレーン導体と第２プレーン導体とにおける電磁波が干渉しにくく、ノイズの発生を低減することが可能な配線基板を得ることができる。 The wiring board according to the present disclosure includes a first gap located between the first plane conductor and the second plane conductor of the first core conductor layer, and the first plane conductor and the second plane conductor of the first build-up conductor layer. The second gap located between the two and the second gap is arranged at the first position in a plane perspective. Further, it is located between the third gap located between the first plane conductor and the second plane conductor of the second core conductor layer and between the first plane conductor and the second plane conductor of the second build-up conductor layer. The fourth gap is arranged at the second position in a plane perspective. Then, the first position and the second position are arranged at different positions. That is, the first plane conductor and the second plane conductor have a portion facing each other only via a core insulating plate having a thickness larger than the thickness of the first and second build-up insulating layers. Therefore, the first plane conductor and the second plane conductor face each other with a distance from each other. As a result, it is possible to obtain a wiring board in which electromagnetic waves in the first plane conductor and the second plane conductor are less likely to interfere with each other and the generation of noise can be reduced.

本開示の一実施形態に係る配線基板を、図１および２に基づいて説明する。図１は、本開示の一実施形態に係る配線基板１の要部を示す断面図である。図２は、本開示の一実施形態に係る配線基板の要部において、絶縁層（絶縁板）およびソルダーレジストを除去した状態を模式的に示す斜視図である。一実施形態に係る配線基板１は、コア絶縁板２、ビルドアップ部３、導体層４、およびソルダーレジスト６を含む。 The wiring board according to the embodiment of the present disclosure will be described with reference to FIGS. 1 and 2. FIG. 1 is a cross-sectional view showing a main part of the wiring board 1 according to the embodiment of the present disclosure. FIG. 2 is a perspective view schematically showing a state in which the insulating layer (insulating plate) and the solder resist are removed from the main part of the wiring board according to the embodiment of the present disclosure. The wiring board 1 according to the embodiment includes a core insulating plate 2, a build-up portion 3, a conductor layer 4, and a solder resist 6.

コア絶縁板２は、絶縁性を有する素材で形成されていれば特に限定されない。絶縁性を有する素材としては、例えば、エポキシ樹脂、ビスマレイミド−トリアジン樹脂、ポリイミド樹脂、ポリフェニレンエーテル樹脂などの樹脂が挙げられる。これらの樹脂は２種以上を混合して用いてもよい。コア絶縁板２の厚みは特に限定されず、例えば２００μｍ以上８００μｍ以下である。コア絶縁板２の厚みは、後述の第１ビルドアップ絶縁層５１および第２ビルドアップ導体層５２の厚みよりも大きい。 The core insulating plate 2 is not particularly limited as long as it is made of a material having an insulating property. Examples of the insulating material include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. Two or more of these resins may be mixed and used. The thickness of the core insulating plate 2 is not particularly limited, and is, for example, 200 μm or more and 800 μm or less. The thickness of the core insulating plate 2 is larger than the thickness of the first build-up insulating layer 51 and the second build-up conductor layer 52, which will be described later.

コア絶縁板２には、補強材が含まれていてもよい。補強材としては、例えば、ガラス繊維、ガラス不織布、アラミド不織布、アラミド繊維、ポリエステル繊維などの絶縁性布材が挙げられる。補強材は２種以上を併用してもよい。さらに、コア絶縁板２には、シリカ、硫酸バリウム、タルク、クレー、ガラス、炭酸カルシウム、酸化チタンなどの無機絶縁性フィラーが分散されていてもよい。 The core insulating plate 2 may contain a reinforcing material. Examples of the reinforcing material include insulating cloth materials such as glass fiber, glass non-woven fabric, aramid non-woven fabric, aramid fiber, and polyester fiber. Two or more types of reinforcing materials may be used in combination. Further, the core insulating plate 2 may be dispersed with an inorganic insulating filler such as silica, barium sulfate, talc, clay, glass, calcium carbonate, and titanium oxide.

コア絶縁板２には、コア絶縁板２の上下面を電気的に接続するために、スルーホール導体２Ｔが位置している。スルーホール導体２Ｔは、コア絶縁板２の上下面を貫通するスルーホール内に位置している。スルーホール導体２Ｔは、例えば、銅めっきなどの金属めっきからなる導体層４の一部で形成されている。スルーホール導体２Ｔは、コア絶縁板２の上面に位置する第１コア導体層４ａと、コア絶縁板２の下面に位置する第２コア導体層４ｂとに接続されている。スルーホール導体２Ｔは、図１に示すようにスルーホールの内壁面のみに形成されていてもよく、スルーホール内に充填されていてもよい。 A through-hole conductor 2T is located on the core insulating plate 2 in order to electrically connect the upper and lower surfaces of the core insulating plate 2. The through-hole conductor 2T is located in a through-hole that penetrates the upper and lower surfaces of the core insulating plate 2. The through-hole conductor 2T is formed of a part of a conductor layer 4 made of metal plating such as copper plating. The through-hole conductor 2T is connected to a first core conductor layer 4a located on the upper surface of the core insulating plate 2 and a second core conductor layer 4b located on the lower surface of the core insulating plate 2. As shown in FIG. 1, the through-hole conductor 2T may be formed only on the inner wall surface of the through-hole, or may be filled in the through-hole.

スルーホール導体２Ｔは、接続される導体層４に応じて、グランド用スルーホール導体、電源用スルーホール導体および信号用スルーホール導体が存在する。すなわち、グランド用スルーホール導体は、後述するグランド導体に接続され、電源用スルーホール導体は、後述する電源導体に接続され、信号用スルーホール導体は、後述する信号導体に接続されている。 The through-hole conductor 2T includes a ground through-hole conductor, a power supply through-hole conductor, and a signal through-hole conductor, depending on the conductor layer 4 to be connected. That is, the ground through-hole conductor is connected to the ground conductor described later, the power supply through-hole conductor is connected to the power supply conductor described later, and the signal through-hole conductor is connected to the signal conductor described later.

コア絶縁板２の上面側および下面側には、ビルドアップ部３が位置している。詳細には、第１コア導体層４ａの上面に、第１ビルドアップ部３１が位置しており、第２コア導体層４ｂの下面に、第２ビルドアップ部３２が位置している。 Build-up portions 3 are located on the upper surface side and the lower surface side of the core insulating plate 2. Specifically, the first build-up portion 31 is located on the upper surface of the first core conductor layer 4a, and the second build-up portion 32 is located on the lower surface of the second core conductor layer 4b.

第１ビルドアップ部３１は、第１ビルドアップ絶縁層５１と第１ビルドアップ導体層４ｃとが交互に積層された構造を有している。第１ビルドアップ絶縁層５１には、第１ビルドアップ絶縁層５１の上下面を電気的に接続するために、第１ビアホール導体５Ｖ１が位置している。第１ビアホール導体５Ｖ１は、第１ビルドアップ絶縁層５１を介して上下に対向する第１ビルドアップ導体層４ｃ同士、または第１ビルドアップ導体層４ｃと第１コア導体層４ａとを電気的に接続している。 The first build-up portion 31 has a structure in which the first build-up insulating layer 51 and the first build-up conductor layer 4c are alternately laminated. A first via hole conductor 5V1 is located in the first build-up insulating layer 51 in order to electrically connect the upper and lower surfaces of the first build-up insulating layer 51. The first via hole conductor 5V1 electrically connects the first build-up conductor layers 4c facing each other vertically via the first build-up insulating layer 51, or the first build-up conductor layer 4c and the first core conductor layer 4a. You are connected.

第２ビルドアップ部３２は、第２ビルドアップ絶縁層５２と第２ビルドアップ導体層４ｄとが交互に積層された構造を有している。第２ビルドアップ絶縁層５２には、第２ビルドアップ絶縁層５２の上下面を電気的に接続するために、第２ビアホール導体５Ｖ２が位置している。第２ビアホール導体５Ｖ２は、第２ビルドアップ絶縁層５２を介して上下に対向する第２ビルドアップ導体層４ｄ同士、または第２ビルドアップ導体層４ｄと第２コア導体層４ｂとを電気的に接続している。 The second build-up portion 32 has a structure in which the second build-up insulating layer 52 and the second build-up conductor layer 4d are alternately laminated. A second via hole conductor 5V2 is located in the second build-up insulating layer 52 in order to electrically connect the upper and lower surfaces of the second build-up insulating layer 52. The second via hole conductor 5V2 electrically connects the second build-up conductor layers 4d facing each other vertically via the second build-up insulating layer 52, or the second build-up conductor layer 4d and the second core conductor layer 4b. You are connected.

第１ビアホール導体５Ｖ１および第２ビアホール導体５Ｖ２は、それぞれ第１ビルドアップ絶縁層５１、および第２ビルドアップ絶縁層５２の上下面を貫通するビアホール内に位置している。これらは、例えば、銅めっきなどの金属めっきからなる導体層４の一部で形成されている。図１に示すように、第１ビアホール導体５Ｖ１および第２ビアホール導体５Ｖ２は、ビアホール内に充填されていてもよく、ビアホールの内壁面のみに形成されていてもよい。第１ビアホール導体５Ｖ１および第２ビアホール導体５Ｖ２は、接続される導体層４に応じて、グランド用ビアホール導体、電源用ビアホール導体および信号用ビアホール導体を含んでいる。すなわち、グランド用ビアホール導体は後述するグランド導体に接続され、電源用ビアホール導体は後述する電源導体に接続され、信号用ビアホール導体は後述する信号導体に接続されている。 The first via hole conductor 5V1 and the second via hole conductor 5V2 are located in the via holes penetrating the upper and lower surfaces of the first build-up insulating layer 51 and the second build-up insulating layer 52, respectively. These are formed of a part of a conductor layer 4 made of metal plating such as copper plating, for example. As shown in FIG. 1, the first via hole conductor 5V1 and the second via hole conductor 5V2 may be filled in the via hole or may be formed only on the inner wall surface of the via hole. The first via hole conductor 5V1 and the second via hole conductor 5V2 include a ground via hole conductor, a power supply via hole conductor, and a signal via hole conductor, depending on the conductor layer 4 to be connected. That is, the ground via hole conductor is connected to the ground conductor described later, the power supply via hole conductor is connected to the power supply conductor described later, and the signal via hole conductor is connected to the signal conductor described later.

第１ビルドアップ絶縁層５１および第２ビルドアップ絶縁層５２は、コア絶縁板２と同様、絶縁性を有する素材で形成されていれば特に限定されない。絶縁性を有する素材としては、例えば、エポキシ樹脂、ビスマレイミド−トリアジン樹脂、ポリイミド樹脂、ポリフェニレンエーテル樹脂などの樹脂が挙げられる。これらの樹脂は２種以上を混合して用いてもよい。一実施形態に係る配線基板１では、第１ビルドアップ部３１および第２ビルドアップ部３２のそれぞれに、第１ビルドアップ絶縁層５１および第２ビルドアップ絶縁層５２が２層存在している。この場合、それぞれの絶縁層は、同じ樹脂で形成されていてもよく、異なる樹脂で形成されていてもよい。第１ビルドアップ絶縁層５１、第２ビルドアップ絶縁層５２およびコア絶縁板２は、同じ樹脂で形成されていてもよく、異なる樹脂で形成されていてもよい。 The first build-up insulating layer 51 and the second build-up insulating layer 52 are not particularly limited as long as they are made of a material having an insulating property like the core insulating plate 2. Examples of the insulating material include resins such as epoxy resin, bismaleimide-triazine resin, polyimide resin, and polyphenylene ether resin. Two or more of these resins may be mixed and used. In the wiring board 1 according to the embodiment, two layers of the first build-up insulating layer 51 and the second build-up insulating layer 52 are present in each of the first build-up unit 31 and the second build-up unit 32, respectively. In this case, each insulating layer may be formed of the same resin or may be formed of different resins. The first build-up insulating layer 51, the second build-up insulating layer 52, and the core insulating plate 2 may be formed of the same resin or different resins.

さらに、第１ビルドアップ絶縁層５１および第２ビルドアップ絶縁層５２には、シリカ、硫酸バリウム、タルク、クレー、ガラス、炭酸カルシウム、酸化チタンなどの無機絶縁性フィラーが、分散されていてもよい。第１ビルドアップ絶縁層５１および第２ビルドアップ絶縁層５２の厚みは特に限定されず、例えば２０μｍ以上４０μｍ以下である。第１ビルドアップ絶縁層５１および第２ビルドアップ絶縁層５２が２層以上存在する場合、それぞれの絶縁層は同じ厚みを有していてもよく、異なる厚みを有していてもよい。 Further, an inorganic insulating filler such as silica, barium sulfate, talc, clay, glass, calcium carbonate, or titanium oxide may be dispersed in the first build-up insulating layer 51 and the second build-up insulating layer 52. .. The thickness of the first build-up insulating layer 51 and the second build-up insulating layer 52 is not particularly limited, and is, for example, 20 μm or more and 40 μm or less. When two or more layers of the first build-up insulating layer 51 and the second build-up insulating layer 52 are present, the respective insulating layers may have the same thickness or may have different thicknesses.

第１ビルドアップ部３１は、表面に第１実装部３１ａを有している。第１実装部３１ａには、例えば半導体集積回路素子などの電子部品が実装される。 The first build-up unit 31 has a first mounting unit 31a on its surface. Electronic components such as semiconductor integrated circuit elements are mounted on the first mounting unit 31a.

第１実装部３１ａは、第１ビルドアップ導体層４ｃの一部からなる複数の第１パッド７を備えている。第１パッド７は、比較的小さめの径を有しており、例えば、電子部品を半田を介して接続するために使用される。電子部品は、一般的に配線基板に搭載される電子部品であれば限定されない。このような電子部品としては、上記の半導体集積回路素子の他、オプトエレクトロニクス素子などが挙げられる。第１パッド７の径は、例えば５０μｍ以上１００μｍ以下であり、互いに隣接する第１パッド７の中心間距離である第１ピッチは、例えば１００μｍ以上２００μｍ以下である。第１パッド７は、デジタル用およびアナログ用に分類されており、第１実装部３１ａにおいて配置が区分されている。 The first mounting portion 31a includes a plurality of first pads 7 formed of a part of the first build-up conductor layer 4c. The first pad 7 has a relatively small diameter and is used, for example, to connect electronic components via solder. The electronic component is not limited as long as it is an electronic component generally mounted on a wiring board. Examples of such electronic components include optoelectronic elements in addition to the above-mentioned semiconductor integrated circuit elements. The diameter of the first pad 7 is, for example, 50 μm or more and 100 μm or less, and the first pitch, which is the distance between the centers of the first pads 7 adjacent to each other, is, for example, 100 μm or more and 200 μm or less. The first pad 7 is classified into a digital type and an analog type, and the arrangement is divided in the first mounting unit 31a.

第２ビルドアップ部３２は、表面に第２実装部３２ａを有している。第２実装部３２ａには、例えばマザーボードなどの電気基板が接続される。 The second build-up unit 32 has a second mounting unit 32a on its surface. An electric board such as a motherboard is connected to the second mounting portion 32a.

第２実装部３２ａは、第２ビルドアップ導体層４ｄの一部からなる複数の第２パッド８を備えている。第２パッド８は、例えば、マザーボードなどの電気基板に半田を介して接続するために使用される。第２パッド８は、通常、第１実装部３１ａに位置する第１パッド７よりも大きな径を有しており、第１パッド７と第２パッド８とは異なるピッチで位置している。第２パッド８の径は、例えば２５０μｍ以上５００μｍ以下であり、互いに隣接する第２パッド８の中心間距離である第２ピッチは、例えば５００μｍ以上１０００μｍ以下である。第２パッド８は、デジタル用およびアナログ用に分類されており、第２実装部３２ａにおいて配置が区分されている。 The second mounting portion 32a includes a plurality of second pads 8 formed of a part of the second build-up conductor layer 4d. The second pad 8 is used, for example, for connecting to an electric board such as a motherboard via solder. The second pad 8 usually has a diameter larger than that of the first pad 7 located in the first mounting portion 31a, and is located at a pitch different from that of the first pad 7 and the second pad 8. The diameter of the second pad 8 is, for example, 250 μm or more and 500 μm or less, and the second pitch, which is the distance between the centers of the second pads 8 adjacent to each other, is, for example, 500 μm or more and 1000 μm or less. The second pad 8 is classified into a digital type and an analog type, and the arrangement is divided in the second mounting unit 32a.

導体層４は、例えば銅箔や銅めっきから成る導体で形成されている。導体層４は、グランド導体、電源導体および信号導体を含んでいる。 The conductor layer 4 is formed of, for example, a conductor made of copper foil or copper plating. The conductor layer 4 includes a ground conductor, a power supply conductor, and a signal conductor.

グランド導体は、信号導体のインピーダンスの整合、および信号導体へのノイズ混入の低減のために機能する。 The ground conductor functions for matching the impedance of the signal conductor and reducing noise contamination in the signal conductor.

電源導体は、電荷の供給経路として機能する。このため、電源導体は、電子部品に近い第１実装部３１ａの直下およびその周囲に配置しておくと電気抵抗が小さくなるため有利である。したがって、電源導体につながる電源用スルーホール導体も、第１実装部３１ａの直下およびその周囲に配置しておくと電荷供給の観点から有利である。 The power conductor functions as a charge supply path. Therefore, it is advantageous to arrange the power supply conductor directly under and around the first mounting portion 31a close to the electronic component because the electric resistance becomes small. Therefore, it is advantageous from the viewpoint of charge supply if the through-hole conductor for power supply connected to the power supply conductor is also arranged directly below and around the first mounting portion 31a.

信号導体は、信号を伝送する機能を有している。信号導体は、配線基板１全体にわたりできるだけインピーダンスの値を整合するように調整されている。これにより、信号が信号導体を伝送するときの損失を低減することができる。信号導体は、２本の線状の導体層４が並行して配置される差動線路を含んでいても構わない。 The signal conductor has a function of transmitting a signal. The signal conductor is adjusted so that the impedance values are matched as much as possible over the entire wiring board 1. This makes it possible to reduce the loss when the signal is transmitted through the signal conductor. The signal conductor may include a differential line in which two linear conductor layers 4 are arranged in parallel.

導体層４は、さらにデジタル用およびアナログ用に分類されており、デジタル用グランド導体４ＧＤ、デジタル用電源導体４ＰＤ、デジタル用信号導体４ＳＤ、アナログ用グランド導体４ＧＡ、アナログ用電源導体４ＰＡ、およびアナログ用信号導体４ＳＡを含んでいる。導体層４の厚みは特に限定されず、例えば１０μｍ以上２５μｍ以下である。 The conductor layer 4 is further classified for digital and analog, digital ground conductor 4GD, digital power conductor 4PD, digital signal conductor 4SD, analog ground conductor 4GA, analog power conductor 4PA, and analog power conductor 4PA. Includes signal conductor 4SA. The thickness of the conductor layer 4 is not particularly limited, and is, for example, 10 μm or more and 25 μm or less.

第１コア導体層４ａ、第１ビルドアップ導体層４ｃ、第２コア導体層４ｂおよび第２ビルドアップ導体層４ｄは、それぞれ平面透視した場合に、第１実装部３１ａおよび第２実装部３２ａが互いに重なる領域において、一方向に横切る隙間を挟んで位置する第１プレーン導体４１Ｐおよび第２プレーン導体４２Ｐを含んでいる。 The first core conductor layer 4a, the first build-up conductor layer 4c, the second core conductor layer 4b, and the second build-up conductor layer 4d have the first mounting portion 31a and the second mounting portion 32a, respectively, when viewed in a plane. In the region overlapping with each other, the first plane conductor 41P and the second plane conductor 42P located across a gap in one direction are included.

第１コア導体層４ａの第１プレーン導体４１Ｐと、第２プレーン導体４２Ｐとの間には、第１隙間Ｌ１が位置している。第１ビルドアップ導体層４ｃの第１プレーン導体４１Ｐと第２プレーン導体４２Ｐとの間には、第２隙間Ｌ２が位置している。第１隙間Ｌ１と第２隙間Ｌ２とは、平面透視で互いに重なり合う第１位置Ｐ１に配置されている。第１隙間Ｌ１および第２隙間Ｌ２の幅は、例えば２５μｍ以上１００μｍ以下である。 A first gap L1 is located between the first plane conductor 41P of the first core conductor layer 4a and the second plane conductor 42P. A second gap L2 is located between the first plane conductor 41P and the second plane conductor 42P of the first build-up conductor layer 4c. The first gap L1 and the second gap L2 are arranged at the first position P1 which overlaps with each other in plan perspective. The width of the first gap L1 and the second gap L2 is, for example, 25 μm or more and 100 μm or less.

第２コア導体層４ｂの第１プレーン導体４１Ｐと、第２プレーン導体４２Ｐとの間には、第３隙間Ｌ３が位置している。第２ビルドアップ導体層４ｄの第１プレーン導体４１Ｐと第２プレーン導体４２Ｐとの間には、第４隙間Ｌ４が位置している。第３隙間Ｌ３と第４隙間Ｌ４とは、平面透視で互いに重なり合う第２位置Ｐ２に配置されている。第３隙間Ｌ３および第４隙間Ｌ４の幅は、例えば２５μｍ以上１００μｍ以下である。 A third gap L3 is located between the first plane conductor 41P of the second core conductor layer 4b and the second plane conductor 42P. A fourth gap L4 is located between the first plane conductor 41P and the second plane conductor 42P of the second build-up conductor layer 4d. The third gap L3 and the fourth gap L4 are arranged at the second position P2 which overlaps with each other in plan perspective. The widths of the third gap L3 and the fourth gap L4 are, for example, 25 μm or more and 100 μm or less.

上記のような、第１位置Ｐ１と第２位置Ｐ２とは、平面透視で重なり合うことなく異なる位置である。これは、第１パッド７および第２パッド８が、上述のようにそれぞれデジタル用およびアナログ用に分類されている上に、第１パッド７および第２パッド８の直径、および第１ピッチおよび第２ピッチがそれぞれ異なることにより、第１実装部３１ａと第２実装部３２ａとの間でデジタル用領域とアナログ用領域との境界を（平面透視で）一致させることが困難なことによる。このため、平面透視した場合に、第１プレーン導体４１Ｐと第２プレーン導体４２Ｐとは、いずれかの層を介して対向する部分を有している。 As described above, the first position P1 and the second position P2 are different positions without overlapping in plan perspective. This is because the first pad 7 and the second pad 8 are classified for digital and analog as described above, respectively, and the diameters of the first pad 7 and the second pad 8 and the first pitch and the first pad 8. This is because it is difficult to match the boundary between the digital region and the analog region (in plan perspective) between the first mounting portion 31a and the second mounting portion 32a because the two pitches are different from each other. Therefore, when viewed through a plane, the first plane conductor 41P and the second plane conductor 42P have a portion facing each other via any of the layers.

第１コア導体層４ａ、第１ビルドアップ導体層４ｃ、第２コア導体層４ｂおよび第２ビルドアップ導体層４ｄのそれぞれの第１プレーン導体４１Ｐ同士は、スルーホール導体２Ｔ、第１ビアホール導体５Ｖ１および第２ビアホール導体５Ｖ２を介して電気的に接続されている。つまり、第１プレーン導体４１Ｐは、コア絶縁板２の上面側と下面側とが同電位となっている。 The first plane conductors 41P of the first core conductor layer 4a, the first build-up conductor layer 4c, the second core conductor layer 4b, and the second build-up conductor layer 4d are connected to the through-hole conductor 2T and the first via-hole conductor 5V1. And are electrically connected via a second via hole conductor 5V2. That is, the first plane conductor 41P has the same potential on the upper surface side and the lower surface side of the core insulating plate 2.

第１コア導体層４ａ、第１ビルドアップ導体層４ｃ、第２コア導体層４ｂおよび第２ビルドアップ導体層４ｄのそれぞれの第２プレーン導体４２Ｐ同士は、スルーホール導体２Ｔ、第１ビアホール導体５Ｖ１および第２ビアホール導体５Ｖ２を介して電気的に接続されている。つまり、第２プレーン導体４２Ｐは、コア絶縁板２の上面側と下面側とが同電位となっている。 The second plane conductors 42P of the first core conductor layer 4a, the first build-up conductor layer 4c, the second core conductor layer 4b, and the second build-up conductor layer 4d are connected to the through-hole conductor 2T and the first via-hole conductor 5V1. And are electrically connected via a second via hole conductor 5V2. That is, in the second plane conductor 42P, the upper surface side and the lower surface side of the core insulating plate 2 have the same potential.

第１プレーン導体４１Ｐは、例えばデジタル用グランド導体４ＧＤであり、第２プレーン導体４２Ｐは、例えばアナログ用グランド導体４ＧＡである。つまり、第１プレーン導体４１Ｐは、コア絶縁板２の上面側および下面側においてデジタル用のグランドとして機能し、第２プレーン導体４２Ｐは、コア絶縁板２の上面側および下面側においてアナログ用のグランドとして機能する。 The first plane conductor 41P is, for example, a digital ground conductor 4GD, and the second plane conductor 42P is, for example, an analog ground conductor 4GA. That is, the first plane conductor 41P functions as a digital ground on the upper surface side and the lower surface side of the core insulating plate 2, and the second plane conductor 42P functions as an analog ground on the upper surface side and the lower surface side of the core insulating plate 2. Functions as.

デジタル用グランド導体４ＧＤは、デジタル用信号導体４ＳＤのインピーダンスの整合、およびノイズ混入低減のために機能する。アナログ用グランド導体４ＧＡは、アナログ用信号導体４ＳＡのインピーダンスの整合、およびノイズ混入低減のために機能する。このため、デジタル用グランド導体４ＧＤとアナログ用グランド導体４ＧＡとは、互いに間隔をあけて配置することで、例えばデジタル用の電磁波が、アナログ用の電磁波に干渉することを低減させる必要がある。つまり、グランド導体４ＧＤとアナログ用グランド導体４ＧＡとは、配線基板１の厚さ方向について間隔を大きくすることでノイズ混入低減に有利である。 The digital ground conductor 4GD functions for impedance matching of the digital signal conductor 4SD and reduction of noise mixing. The analog ground conductor 4GA functions for impedance matching of the analog signal conductor 4SA and reduction of noise mixing. Therefore, it is necessary to reduce that, for example, the digital electromagnetic wave interferes with the analog electromagnetic wave by arranging the digital ground conductor 4GD and the analog ground conductor 4GA at intervals from each other. That is, the ground conductor 4GD and the analog ground conductor 4GA are advantageous in reducing noise mixing by increasing the distance between the ground conductor 4GD and the analog ground conductor 4GA in the thickness direction of the wiring board 1.

一実施形態に係る配線基板１の両表面の一部には、ソルダーレジスト６が形成されている。ソルダーレジスト６は、例えば、アクリル変性エポキシ樹脂で形成されている。ソルダーレジスト６は、例えば第１実装部３１ａに電子部品を実装するときの熱や、第２実装部３２ａをマザーボードなどに接続するときの熱から導体層４を保護する機能を有している。 Solder masks 6 are formed on a part of both surfaces of the wiring board 1 according to the embodiment. The solder resist 6 is made of, for example, an acrylic-modified epoxy resin. The solder resist 6 has a function of protecting the conductor layer 4 from, for example, the heat when mounting electronic components on the first mounting portion 31a and the heat when connecting the second mounting portion 32a to a motherboard or the like.

一実施形態に係る配線基板１において、第１プレーン導体４１Ｐと第２プレーン導体４２Ｐとが対向している部分は、図１および２の矢印Ａで示す部分である。具体的には、第１プレーン導体４１Ｐとしてデジタル用グランド導体４ＧＤと、第２プレーン導体４２Ｐとしてアナログ用グランド導体４ＧＡとが、コア絶縁板２を介してのみ対向している。したがって、第１プレーン導体４１Ｐと第２プレーン導体４２Ｐとが、矢印Ａで示すようにコア絶縁板２の厚み分だけ距離を保って対向している。つまり、第１プレーン導体４１Ｐと第２プレーン導体４２Ｐとが、第１ビルドアップ絶縁層５１または第２ビルドアップ絶縁層５２を介して対向している場合に比べて大きな間隔を保って対向することができる。その結果、一実施形態に係る配線基板１は、第１プレーン導体４１Ｐと第２プレーン導体４２Ｐとにおける電磁波同士が干渉しにくく、ノイズの発生が低減される。 In the wiring board 1 according to the embodiment, the portion where the first plane conductor 41P and the second plane conductor 42P face each other is the portion indicated by the arrow A in FIGS. 1 and 2. Specifically, the digital ground conductor 4GD as the first plane conductor 41P and the analog ground conductor 4GA as the second plane conductor 42P face each other only via the core insulating plate 2. Therefore, the first plane conductor 41P and the second plane conductor 42P face each other with a distance of the thickness of the core insulating plate 2 as shown by the arrow A. That is, the first plane conductor 41P and the second plane conductor 42P face each other with a larger distance than when they face each other via the first build-up insulating layer 51 or the second build-up insulating layer 52. Can be done. As a result, in the wiring board 1 according to the embodiment, the electromagnetic waves in the first plane conductor 41P and the second plane conductor 42P are less likely to interfere with each other, and the generation of noise is reduced.

次に、本開示に係る配線基板の一例についてのシミュレーションモデルを図３に示す。使用した配線基板については、下記の通りである。デジタル用グランド導体とアナログ用グランド導体とがコア絶縁板を介して対向している部分は、縦０．４ｍｍおよび横１５ｍｍである。
配線基板のサイズ：縦１５ｍｍ、横１５ｍｍ、高さ０．５８２ｍｍ
コア絶縁板の厚み：０．４ｍｍ
ビルドアップ絶縁層の厚み：０．０３３ｍｍ Next, FIG. 3 shows a simulation model for an example of the wiring board according to the present disclosure. The wiring boards used are as follows. The portions of the digital ground conductor and the analog ground conductor facing each other via the core insulating plate are 0.4 mm in length and 15 mm in width.
Wiring board size: length 15 mm, width 15 mm, height 0.582 mm
Core insulation plate thickness: 0.4 mm
Build-up insulation layer thickness: 0.033mm

このような配線基板のデジタル用グランド導体とデジタル用電源導体との間に、０．１〜１ＧＨｚの電気信号を入力し、アナログ用グランド導体とアナログ用電源導体との間に混入したノイズを出力した。同様に、従来の配線基板、すなわちデジタル用グランド導体とアナログ用グランド導体とが同一ビルドアップ部内でビルドアップ絶縁層を介して対向している配線基板についても、デジタル用グランド導体とデジタル用電源導体との間に、０．１〜１ＧＨｚの電気信号を入力し、アナログ用グランド導体とアナログ用電源導体との間に混入したノイズを出力した。 An electric signal of 0.1 to 1 GHz is input between the digital ground conductor and the digital power supply conductor of such a wiring board, and the noise mixed between the analog ground conductor and the analog power supply conductor is output. bottom. Similarly, for a conventional wiring board, that is, a wiring board in which a digital ground conductor and an analog ground conductor face each other via a build-up insulating layer in the same build-up portion, the digital ground conductor and the digital power supply conductor are also used. An electric signal of 0.1 to 1 GHz was input between the two, and the noise mixed between the analog ground conductor and the analog power supply conductor was output.

図３に示すように、本開示に係る配線基板は、従来の配線基板と比較して、ノイズ量が少なくノイズの発生が低減されていることがわかる。したがって、本開示に係る配線基板は、ノイズ量が小さい良好な信号の伝送特性を発揮する。 As shown in FIG. 3, it can be seen that the wiring board according to the present disclosure has a smaller amount of noise and less noise generation than the conventional wiring board. Therefore, the wiring board according to the present disclosure exhibits good signal transmission characteristics with a small amount of noise.

本開示の配線基板は、上述の一実施形態に限定されない。例えば、上述の配線基板１では、第１ビルドアップ部３１および第２ビルドアップ部３２のそれぞれに、第１ビルドアップ絶縁層５１および第２ビルドアップ絶縁層５２がそれぞれ２層存在している。しかし、本開示の配線基板１において、第１ビルドアップ絶縁層５１および第２ビルドアップ絶縁層５２が、第１ビルドアップ部３１および第２ビルドアップ部３２のそれぞれに、１層のみ存在していてもよく、３層以上存在していてもよい。 The wiring board of the present disclosure is not limited to the above-described embodiment. For example, in the wiring board 1 described above, the first build-up section 31 and the second build-up section 32 each have two layers, a first build-up insulating layer 51 and a second build-up insulating layer 52. However, in the wiring board 1 of the present disclosure, only one layer of the first build-up insulating layer 51 and the second build-up insulating layer 52 exists in each of the first build-up portion 31 and the second build-up portion 32. There may be three or more layers.

１配線基板
２コア絶縁板
２Ｔスルーホール導体
４ａ第１コア導体層
４ｂ第２コア導体層
４ｃ第１ビルドアップ導体層
４ｄ第２ビルドアップ導体層
５１第１ビルドアップ絶縁層
５２第２ビルドアップ絶縁層
５Ｖ１第１ビア導体
５Ｖ２第２ビア導体
６ソルダーレジスト
７第１パッド
８第２パッド
３１第１ビルドアップ部
３１ａ第１実装部
３２第２ビルドアップ部
３２ａ第２実装部
４１Ｐ第１プレーン導体
４２Ｐ第２プレーン導体
４ＧＡアナログ用グランド導体
４ＧＤデジタル用グランド導体
Ｌ１第１隙間
Ｌ２第２隙間
Ｌ３第３隙間
Ｌ４第４隙間
Ｐ１第１位置
Ｐ２第２位置 1 Wiring board 2 Core insulation plate 2T Through-hole conductor 4a 1st core conductor layer 4b 2nd core conductor layer 4c 1st build-up conductor layer 4d 2nd build-up conductor layer 51 1st build-up insulation layer 52 2nd build-up insulation Layer 5V1 1st via conductor 5V2 2nd via conductor 6 Solder resist 7 1st pad 8 2nd pad 31 1st build-up part 31a 1st mounting part 32 2nd build-up part 32a 2nd mounting part 41P 1st plane conductor 42P 2nd plane conductor 4GA ground conductor for analog 4GD ground conductor for digital L1 1st gap L2 2nd gap L3 3rd gap L4 4th gap P1 1st position P2 2nd position

Claims

With a core insulation plate with top and bottom surfaces,
A first core conductor layer located on the upper surface of the core insulating plate,
A second core conductor layer located on the lower surface of the core insulating plate,
A through-hole conductor that penetrates the core insulating plate and electrically connects the first core conductor layer and the second core conductor layer.
The first build-up portion located on the upper surface of the first core conductor layer,
A second build-up portion located on the lower surface of the second core conductor layer,
The first mounting part located on the surface of the first build-up part and
The second mounting part located on the surface of the second build-up part and
Equipped with
The first build-up part
Located on the upper surface of the first core conductor layer, at least one layer of the first build-up insulating layer and
With at least one first build-up conductor layer located on the upper surface of the first build-up insulating layer,
The first build-up conductor layers that penetrate the first build-up insulating layer and face each other vertically via the first build-up insulating layer, or the first build-up conductor layer and the first core conductor layer. With the first via hole conductor that electrically connects
Have and
The second build-up part
Located on the lower surface of the second core conductor layer, at least one second build-up insulating layer and
With at least one second build-up conductor layer located on the lower surface of the second build-up insulating layer,
The second build-up conductor layers that penetrate the second build-up insulating layer and face each other vertically via the second build-up insulating layer, or the second build-up conductor layer and the second core conductor layer. The second via hole conductor that electrically connects the
Have and
The first core conductor layer, the first build-up conductor layer, the second core conductor layer, and the second build-up conductor layer are the first mounting portion and the second mounting portion, respectively, when viewed in a plane. Have a first plane conductor and a second plane conductor located across a gap across in one direction in a region where
The first core conductor layer, the first build-up conductor layer, the second core conductor layer, and the first plane conductors of the second build-up conductor layer are the through-hole conductor, the first via-hole conductor, and the said. It is electrically connected via a second via hole conductor and
The first core conductor layer, the first build-up conductor layer, the second core conductor layer, and the second plane conductors of the second build-up conductor layer are the through-hole conductor, the first via-hole conductor, and the said. It is electrically connected via a second via hole conductor and
The gap is a first gap located between the first plane conductor and the second plane conductor of the first core conductor layer, and the first plane conductor and the second plane conductor of the first build-up conductor layer. A second gap located between the two core conductor layers, a third gap located between the first plane conductor and the second plane conductor of the second core conductor layer, and the first plane conductor of the second build-up conductor layer. Includes a fourth gap located between the second plane conductor and the second plane conductor.
In planar fluoroscopy, the first gap and the second gap are arranged at the first position, the third gap and the fourth gap are arranged at the second position, and the first position and the second gap are arranged. Wiring board in different positions.

The wiring board according to claim 1, wherein the first plane conductor is a digital ground conductor, and the second plane conductor is an analog ground conductor.

The first build-up insulating layer is located on the upper surface side of the core insulating plate in two or more layers, and the second build-up insulating layer is located in two or more layers on the lower surface side of the core insulating plate. Item 2. The wiring board according to Item 1 or 2.

The first mounting portion has a plurality of first pads including a part of the first plane conductor and a part of the second plane conductor.
The second mounting portion has a plurality of second pads including a part of the first plane conductor and a part of the second plane conductor.
The wiring board according to any one of claims 1 to 3, wherein the first pitch of the plurality of first pads is different from the second pitch of the plurality of second pads.

The wiring board according to claim 4, wherein the first pitch is smaller than the second pitch.

The wiring board according to any one of claims 1 to 5, wherein a solder resist is located on the outermost layers of the first build-up section and the second build-up section.