JP2021117244A - Circuit arrangement, electro-optical device, and electronic apparatus - Google Patents

Abstract

To provide a circuit arrangement that can transmit a data voltage signal at a high speed in transmission from a display driver to an electro-optical panel through a flexible substrate.SOLUTION: A circuit arrangement 100 includes a distortion adjustment circuit 130, a first voltage withstanding buffer circuit 110, analog latch circuits AL1 to ALm, and second voltage withstanding buffer circuits BF21 to BF2m. The distortion adjustment circuit 130 adjusts waveform distortion of data voltage signal DVS in which the first to the m-th gradation voltages are multiplexed and outputs a signal after the adjustment TGS. The first voltage withstanding buffer circuit 110 buffers the signal after the adjustment TGS and outputs a first output signal QS1. The analog latch circuit ALj latches a voltage corresponding to the j-th gradation voltage in the first output signal QS1. The second voltage withstanding buffer circuit BF2j amplifies an output signal ALQj from the analog latch circuit ALj and outputs a second output signal QS2j.SELECTED DRAWING: Figure 6

Description

The present invention relates to a circuit device, an electro-optical device, an electronic device, and the like.

In a display device such as a projector, a configuration in which a substrate on which a display driver is mounted and an electro-optical panel are connected by a flexible substrate is known. For example, Patent Document 1 discloses a liquid crystal device in which a liquid crystal panel and a printed circuit board are connected via a flexible wiring board bonded to an element substrate of the liquid crystal panel, and a control circuit and an image signal processing circuit are mounted on the printed circuit board. Has been done. Further, Patent Document 2 discloses a liquid crystal display device in which a phase expansion drive video signal is supplied from the outside of the substrate to the substrate provided with the pixel array. Further, in a display device, a configuration in which a display driver is mounted on a flexible substrate connected to an electro-optical panel is known. For example, in Patent Documents 3 and 4, a drive integrated circuit is mounted on an electro-optical panel flexible circuit board, multiplexed display data is input to the drive integrated circuit from an external device, and the drive integrated circuit is displayed data. Is D / A converted into a data voltage and output to an electro-optical panel, and an electro-optical device is disclosed in which the multiplexed data voltage is demultiplexed in the electro-optical panel.

Japanese Unexamined Patent Publication No. 2005-157304 Japanese Unexamined Patent Publication No. 2008-139610 Japanese Unexamined Patent Publication No. 2015-79138 Japanese Unexamined Patent Publication No. 2016-197199

In recent years, the drive time per pixel has been shortened due to the advancement of high-definition electro-optical panels. However, since the wiring load capacitance is parasitic on the transmission path of the flexible substrate or the like, there is a problem that it is difficult to transmit the data voltage signal or the display data at high speed. That is, in a configuration in which a substrate on which a display driver is mounted and an electro-optical panel are connected by a flexible substrate, it is difficult to transmit a data voltage signal from the display driver to the electro-optic panel at high speed. Further, in a configuration in which a display driver is mounted on a flexible substrate connected to an electro-optical panel, it is difficult to transmit display data from an external device such as a display controller to the display driver at high speed.

In one aspect of the present disclosure, a data voltage signal in which the first to mth gradation voltages (m is an integer of 2 or more) are multiplexed is input from the display driver, and the waveform distortion of the data voltage signal is adjusted. The distortion adjustment circuit that outputs the adjusted signal, the first withstand voltage buffer circuit that is composed of the first withstand voltage transistor and buffers the adjusted signal and outputs the first output signal, and the first output signal. The jth analog latch circuit (j is an integer of 1 or more and m or less) includes the first to first m analog latch circuits and the first to m second withstand voltage buffer circuits to be input. The voltage corresponding to the j-th gradation voltage is latched in the first output signal, and the j-second withstand voltage buffer circuit is composed of a transistor having a second withstand voltage higher than the first withstand voltage, and the j-th It relates to a circuit device that amplifies the output signal of the analog latch circuit and outputs the second output signal to the electro-optical panel.

Further, another aspect of the present disclosure relates to an electro-optical device including the circuit device described above, the display driver, and the electro-optic panel.

Yet another aspect of the present disclosure relates to electronic devices including the circuit devices described above.

Configuration example of a conventional electro-optic device. Waveform example of a data voltage signal in a conventional electro-optic device. A first configuration example of an electro-optical device. Example of circuit configuration of display driver, circuit device and electro-optic panel. The figure explaining the operation of a display driver, a circuit device and an electro-optics panel in a phase expansion drive system. First detailed configuration example of a circuit device. Example of signal waveform in a circuit device. Detailed configuration example of the first withstand voltage buffer circuit. Detailed configuration example of the j-th analog latch circuit. A detailed configuration example of the second withstand voltage buffer circuit of the second j. The waveform diagram explaining the operation of the circuit apparatus in 1st detailed configuration example. A second detailed configuration example of a circuit device. The waveform diagram explaining the operation of the circuit apparatus in the 2nd detailed configuration example. The figure explaining the operation of a display driver, a circuit device and an electro-optics panel in a demultiplex drive system. A third detailed configuration example of a circuit device. The waveform diagram explaining the operation of the circuit apparatus in the 3rd detailed configuration example. A second configuration example of an electro-optical device. Configuration example of electronic equipment.

Hereinafter, preferred embodiments of the present disclosure will be described in detail. It should be noted that the present embodiment described below does not unreasonably limit the contents described in the claims, and not all of the configurations described in the present embodiment are essential constituent requirements.

1. 1. Electro-optic device FIG. 1 is a configuration example of a conventional electro-optical device 1. The electro-optical device 1 includes a display driver 2, a connector 3, a flexible substrate 4, an electro-optical panel 5, and a substrate 6.

The electro-optical panel 5 is a liquid crystal display panel, and one end of the flexible substrate 4 is connected to the glass substrate of the liquid crystal display panel. The board 6 is a printed circuit board, and is provided with a display driver 2 and a connector 3. By connecting the other end of the flexible substrate 4 to the connector 3, the display driver 2 and the electro-optical panel 5 are electrically connected via the wiring on the flexible substrate 4.

The data voltage signal and the control signal output by the display driver 2 are transmitted by the wiring of the flexible substrate 4 and input to the electro-optical panel 5. The display driver 2 sequentially outputs the gradation voltage corresponding to each pixel, and the time-series gradation voltage is input to the electro-optical panel 5 as a data voltage signal. Then, the gradation voltage corresponding to each selected pixel is written to the pixels sequentially selected by the control signal.

FIG. 2 is a waveform diagram of a data voltage signal in the electro-optical device 1. FIG. 2 shows an example of the waveform of the data voltage signal after passing through the flexible substrate 4, that is, at the input of the electro-optical panel 5.

In the waveform shown by the solid line, TGA corresponds to the period for driving one pixel. Since the wiring of the flexible substrate 4 has a parasitic capacitance and a parasitic resistance, and the input of the electro-optical panel 5 has a resistance for electrostatic protection, the waveform of the data voltage signal is distorted. The distortion here means that the waveform of the signal reaching the electro-optical panel 5 is deformed with respect to the original waveform of the signal output by the display driver 2. How the waveform is distorted is determined by the frequency characteristics of the transmission path, but FIG. 2 shows the waveform when the high frequency component of the rectangular wave is reduced as an example.

In order to display high quality, it is necessary to write an accurate gradation voltage to the pixel, but in order to write an accurate gradation voltage to the pixel, the data voltage signal becomes the target voltage at least at the end of the period TGA. Must have been reached. For example, if the number of pixels of the electro-optical panel 5 is doubled without changing the number of drive amplifiers of the display driver 2, the period for driving one pixel is half that of TGA, as shown in TGB. As the number of pixels increases or the frame rate increases, the period TGB becomes shorter, so that there is a high possibility that the data voltage signal does not reach the target voltage at the end of the period TGB. Since the distortion of the waveform is determined by the frequency characteristics of the transmission path, there is a limit to shortening the period TGB. That is, it becomes necessary to increase the transfer rate of the data voltage signal with the increase in the number of pixels, the increase in the frame rate, or both, but it becomes difficult to improve the transfer rate due to the distortion of the waveform caused by the flexible substrate 4 and the like.

Although FIG. 1 shows an example in which the display driver 2 is mounted on the substrate 6, the display driver 2 is mounted on the flexible substrate 4 in the electro-optic device 10 such as the demultiplex drive system. In this case, the transmission path of the data voltage signal on the flexible board 4 becomes short, but the transmission path of the display data transmitted from the display controller or the like mounted on the board 6 to the display driver 2 via the flexible board 4 becomes long. As the number of pixels or the frame rate of the electro-optical panel 5 increases, the transfer rate of display data increases, but it becomes difficult to improve the transfer rate due to the parasitic capacitance and the parasitic resistance of the flexible substrate 4.

As described above, both the type in which the display driver 2 is mounted on the substrate 6 and the type in which the display driver 2 is mounted on the flexible substrate 4 correspond to high pixel count or high frame rate. There is a problem that it becomes difficult to do.

FIG. 3 is a first configuration example of the electro-optical device 10 in the present embodiment. The electro-optical device 10 includes a display driver 12, a connector 13, a flexible substrate 14, an electro-optical panel 15, a substrate 16, and a circuit device 100.

The board 16 is a circuit board on which circuit components such as integrated circuit devices can be mounted, and is, for example, a printed circuit board. The display driver 12 and the connector 13 are mounted on the board 16. The substrate 16 may be further provided with a display controller or the like that controls the display driver 12. The display driver 12 generates a data voltage signal and a control signal for driving the electro-optical panel 15 based on the display data, and outputs the data voltage signal and the control signal. The display driver 12 is, for example, an integrated circuit device. The display driver 12 and the connector 13 are electrically connected by wiring provided on the board 16. The wiring provided on the substrate 16 is connected to the wiring provided on the flexible substrate 14 via the connector 13.

The flexible substrate 14, also called an FPC, is a circuit board that can be bent because it is flexible. FPC is an abbreviation for Flexible Printed Circuits. The circuit device 100 is mounted on the flexible substrate 14. The input terminal of the circuit device 100 is connected to the wiring provided on the flexible substrate 14, and is electrically connected to the connector 13.

The circuit device 100 is, for example, an integrated circuit device called an IC. The circuit device 100 is an IC manufactured by a semiconductor process, and is a semiconductor chip in which a circuit element is formed on a semiconductor substrate. The data voltage signal and control signal output from the display driver 12 are input to the input terminal of the circuit device 100 via the wiring provided on the board 16, the connector 13, and the wiring provided on the flexible board 14. NS.

The circuit device 100 adjusts the waveform distortion of the input data voltage signal, and outputs the data voltage signal after the distortion adjustment. Further, the circuit device 100 controls the circuit operation in the circuit device 100 based on the input control signal. Further, the circuit device 100 level-shifts the input control signal and outputs the control signal after the level shift to the electro-optical panel 15. The strain-adjusted data signal and the level-shifted control signal output from the circuit device 100 are input to the electro-optical panel 15 via the wiring provided on the flexible substrate 14.

As shown in FIG. 3, the circuit device 100 is arranged on the flexible substrate 14 at a position closer to the electro-optical panel 15 than the display driver 12. The circuit device 100 is connected between the circuit device 100 and the electro-optical panel 15 by wiring between the circuit device 100 and the electro-optical panel 15 so that the data voltage signal after distortion adjustment is not affected by the waveform distortion. Is arranged so that the wiring length of the above is less than or equal to a predetermined length. The wiring length between the circuit device 100 and the electro-optical panel 15 is equal to or less than a predetermined length according to the transfer rate of the data voltage signal required according to the resolution and frame rate of the image displayed on the electro-optical panel. Is set to. Specifically, the transfer rate of the data voltage signal when displaying a full high-definition (2K x 1K dot) image on the electro-optical panel 15 at a frame rate of 120 fps (the period for driving one pixel is about 72 ns) is about 3. When it is 6 Gbps, the wiring length between the electro-optical panel 15 and the circuit device 100 is preferably 7 cm or less. In addition, the transfer rate of the data voltage signal when displaying a full high-definition (2K x 1K dot) image on the electro-optical panel 15 at 240 fps (the period for driving one pixel is about 36 ns), which is twice the frame rate, is doubled. When it is about 7.2 Gbps, the wiring length between the electro-optical panel 15 and the circuit device 100 is preferably halved to 3.5 cm or less. In addition, the transfer rate of the data voltage signal when displaying a full high-definition (2K x 1K dot) image on the electro-optical panel 15 at 480 fps (the period for driving one pixel is about 18 ns), which is four times the frame rate, is four times. In the case of about 14.4 Gbps, the wiring length between the electro-optical panel 15 and the circuit device 100 is preferably 1.75 cm or less, which is about a quarter. In addition, the transfer rate of the data voltage signal when displaying a 4K (4K x 2K dot) image with a resolution of 4 times on the electro-optical panel 15 at a frame rate of 120 fps (the period for driving one pixel is about 72 ns) is 4 times. When it is about 14.4 Gbps, the wiring length between the electro-optical panel 15 and the circuit device 100 is preferably 1.75 cm or less, which is about a quarter.

The input terminal of the electro-optical panel 15 is connected to the output terminal of the circuit device 100 by wiring provided on the flexible substrate 14. The electro-optical panel 15 displays an image based on a data voltage signal whose waveform is molded by the circuit device 100 and a control signal whose level is shifted by the circuit device 100. The electro-optical panel 15 is also called a display panel, and is, for example, a liquid crystal display panel. The liquid crystal display panel includes a glass substrate and a pixel array formed on the glass substrate. Further, the liquid crystal display panel can include a circuit formed on the glass substrate and configured by the TFT, and a transparent electrode wiring that connects the circuit and the pixel array and is formed on the glass substrate. TFT is an abbreviation for Thin Film Transistor. When the electro-optical device 10 is applied to a projector, the electro-optical panel 15 is inserted between the light source and the projection optical system, and the light transmitted through the electro-optical panel 15 is imaged on the screen by the projection optical system. The image is projected on the screen. The electro-optical device 10 is not limited to the projector, and can be applied to various display devices. Further, the electro-optical panel 15 is not limited to the liquid crystal display panel, and may be an organic EL display panel or the like.

FIG. 4 is a circuit configuration example of the display driver 12, the circuit device 100, and the electro-optical panel 15. The display driver 12 includes a control circuit 21, D / A conversion circuits DAC1 to DACn, amplifier circuits AM1 to AMn, output terminals TD1 to TDn, and TS. n is an integer of 2 or more. The circuit device 100 includes waveform forming circuits HSC1 to HSCn, timing signal output circuits 195, input terminals TI1 to TI, TIS and output terminals TQ11 to TQ1m, TQ21 to TQ2m, ..., TQn1 to TQnm, and TQS. m is an integer of 2 or more, and "nm" means n × m. The electro-optical panel 15 includes a switch circuit 51, a pixel array 52, and input terminals TP11 to TP1m, TP21 to TP2m, ..., TPn1 to TPnm, and TPS.

Hereinafter, the operation will be described by taking the phase expansion drive method as an example, but the operation is not limited to this, and for example, the electro-optical device 10 may adopt the demultiplex drive method. The operation of the switch circuit 51 and the output order of the gradation voltage from the display driver 12 may be changed according to the drive method.

The control circuit 21 outputs the first to nth display data to the D / A conversion circuits DAC1 to DACn. The display data output to each D / A conversion circuit is data in which a plurality of gradation values are multiplexed. Further, the control circuit 21 outputs a control signal for controlling the waveform forming circuits HSC1 to HSCn and the switch circuit 51 to the output terminal TS. In FIG. 4, the control circuit 21 outputs one control signal from one output terminal TS, but when the control circuit 21 outputs a plurality of control signals, the display driver 12 outputs a plurality of control signals. It may include a plurality of output terminals of. In this case, the circuit device 100 may include a plurality of input terminals into which a plurality of control signals are input.

The D / A conversion circuits DAC1 to DACn D / A convert the first to nth display data into the first to nth voltages. The amplifier circuits AM1 to AMn output the 1st to nth data voltage signals by buffering or amplifying the 1st to nth voltages. Each data voltage signal is a signal in which a plurality of gradation voltages are multiplexed, and the plurality of gradation voltages correspond to a plurality of multiple gradation values in the display data.

The output terminals TD1 to TDn are electrically connected to the input terminals TI1 to TI of the circuit device 100 via the substrate 16, the connector 13, and the flexible substrate 14. The first to nth data voltage signals input to the input terminals TI1 to TI are input to the waveform forming circuits HSC1 to HSCn. The waveform shaping circuits HSC1 to HSCn adjust the waveform distortion of the first to nth data voltage signals so as to approach the waveform of the original first to nth data voltage signals output by the amplifier circuits AM1 to AMn. Further, the waveform shaping circuits HSC1 to HSCn demultiplex the gradation voltage multiplexed in the adjusted first to nth data voltage signals, and output the gradation voltage after the demultiplexing. Taking the waveform shaping circuit HSC1 as an example, the first data voltage signal is a signal in which m gradation voltages are multiplexed, and the waveform shaping circuit HSC1 decodes the multiplexed m gradation voltages. Multiplexing is performed, and m gradation voltages after demultiplexing are output to the output terminals TQ11 to TQ1m.

The output terminal TS is electrically connected to the input terminal TIS of the circuit device 100 via the board 16, the connector 13, and the flexible board 14. The control signal input to the input terminal TIS is input to the timing signal output circuit 195. Based on the control signal, the timing signal output circuit 195 outputs a signal for timing control of the demultiplexing operation to the waveform shaping circuits HSC1 to HSCn. Further, the timing signal output circuit 195 level-shifts the control signal to the operating voltage of the TFTs constituting the switch circuit 51, and outputs the control signal after the level shift to the output terminal TQS.

The output terminals TQ11 to TQ1m, TQ21 to TQ2m, ..., TQn1 to TQnm, and TQS of the circuit device 100 are input terminals TP11 to TP1m, TP21 to TP2m, ..., Of the electro-optical panel 15 via the flexible substrate 14. TPn1 to TPnm, electrically connected to TPS. The first to nm data voltage signals input to the input terminals TP11 to TP1m, TP21 to TP2m, ..., TPn1 to TPnm, and the control signal input to the input terminal TPS are input to the switch circuit 51. The pixel array 52 has first to kth data lines, and the first to kth data lines are electrically connected to the switch circuit 51. k is an integer of 2 nm or more. The first to first k data lines shall be arranged in the horizontal scanning direction in that order. Hereinafter, the scanning line selected in a certain horizontal scanning period is referred to as a selective scanning line. The switch circuit 51 connects the input terminals TP11 to TP1m, TP21 to TP2m, ..., TPn1 to TPnm and the first to nmth data lines based on the control signal. At this time, the data voltage signal is written to the pixels connected to the selective scanning line and the first to nmth data lines. Next, the switch circuit 51 connects the input terminals TP11 to TP1m, TP21 to TP2m, ..., TPn1 to TPnm and the nm + 1 to 2 nm data lines based on the control signal. At this time, the data voltage signal is written to the pixels connected to the selective scanning line and the nm + 1 to 2 nm data lines. By repeating this up to the kth data line, the gradation voltage is written in the pixels of one scanning line.

FIG. 5 is a diagram illustrating the operation of the display driver 12, the circuit device 100, and the electro-optical panel 15 in the phase expansion drive system. Here, the case where n = 2 and m = 3 will be described as an example, but the numerical values of n and m are not limited to this. TH is the horizontal scanning period, and the horizontal scanning period TH includes periods P1, P2, ..., Px. x = k / nm.

In the period P1, the amplifier circuit AM1 sequentially outputs the gradation voltages V1, V2, and V3, and the amplifier circuit AM2 sequentially outputs the gradation voltages V4, V5, and V6. The waveform shaping circuit HSC1 demultiplexes the gradation voltages V1, V2, and V3 that are sequentially output, outputs the gradation voltage V1 to the output terminal TQ11, outputs the gradation voltage V2 to the output terminal TQ12, and outputs the gradation voltage V2. The gradation voltage V3 is output to the terminal TQ13. The waveform shaping circuit HSC2 demultiplexes the sequentially output gradation voltages V4, V5, and V6, outputs the gradation voltage V4 to the output terminal TQ21, outputs the gradation voltage V5 to the output terminal TQ22, and outputs the gradation voltage V5. The gradation voltage V6 is output to the terminal TQ23.

After the gradation voltages V3 and V6 are output and before the period P1 ends, the switch circuit 51 connects the input terminals TI11 to TI13, TI21 to TI23 and the first to sixth data lines. As a result, the gradation voltages V1 to V6 are written to the pixels connected to the selective scanning line and the first to sixth data lines. In the period P2, the gradation voltages V9 to V12 are written to the pixels connected to the selected scanning line and the 7th to 12th data lines by the same operation, and the same operation is repeated up to the kth data line. The gradation voltage is written in the pixels of one scanning line.

2. First Detailed Configuration Example of Circuit Device The details of the waveform forming circuits HSC1 to HSCn of the circuit device 100 will be described. Hereinafter, only the configuration related to HSCi will be illustrated and described. i is an arbitrary integer of 1 or more and n or less.

FIG. 6 is a first detailed configuration example of the circuit device 100. The circuit device 100 includes a waveform forming circuit HSCi, a storage unit 180, an input terminal TIi, and output terminals TQi1 to TQim. The waveform forming circuit HSSi includes a strain adjustment circuit 130, a first withstand voltage buffer circuit 110, first to first m analog latch circuits AL1 to ALm, first to first m second withstand voltage buffer circuits BF21 to BF2m, and a capacitance C3. include.

The capacitance C3 is the capacitance of the electrostatic protection circuit with respect to the input terminal TIi. One end of the capacitance C3 is connected to the data voltage signal input node NA, and the other end is connected to the ground node NG. The data voltage signal input node NA is connected to the input terminal TIi. The capacitance C3 is a capacitor included in the electrostatic protection circuit, a parasitic capacitance of the electrostatic protection circuit, or a combination thereof.

A data voltage signal DVS is input from the display driver to the distortion adjustment circuit 130 via wiring on the flexible substrate, and the waveform distortion of the data voltage signal DVS is adjusted to output the adjusted signal TGS. The strain adjusting circuit 130 includes a voltage dividing circuit 105, a first capacitor C1 and a second capacitor C2.

The voltage dividing circuit 105 is provided between the data voltage signal input node NA to which the data voltage signal DVS is input and the ground node NG. Specifically, the voltage dividing circuit 105 includes a first resistor R1 and a second resistor R2. The first resistor R1 is provided between the data voltage signal input node NA and the voltage dividing node NB. That is, one end of the first resistor R1 is connected to the data voltage signal input node NA, and the other end is connected to the voltage division node NB. The second resistor R2 is provided between the voltage dividing node NB and the ground node NG. That is, one end of the second resistor R2 is connected to the voltage dividing node NB, and the other end is connected to the ground node NG.

The first capacitor C1 is provided between the data voltage signal input node NA and the voltage division node NB. That is, one end of the first capacitor C1 is connected to the data voltage signal input node NA, and the other end is connected to the voltage division node NB. The capacitance value of the second capacitor C2 is variable, and the second capacitor C2 is provided between the voltage dividing node NB and the ground node NG. That is, one end of the second capacitor C2 is connected to the voltage dividing node NB, and the other end is connected to the ground node NG. The second capacitor C2 is, for example, a variable capacitance circuit in which the capacitance value is variably controlled based on the capacitance setting data. The variable capacitance circuit includes a capacitor array and a switch array. The switch array selects one or a plurality of capacitors indicated by the capacitance setting data from the plurality of capacitors constituting the capacitor array. As a result, one or more selected capacitors are connected in parallel between the voltage dividing node NB and the ground node NG.

The storage unit 180 stores the capacity setting data and outputs the capacity setting data to the second capacitor C2. The storage unit 180 is a register or a memory. The memory is RAM, non-volatile memory, or the like. The storage unit 180 may be configured to be accessible from an external device such as a display controller via an interface circuit (not shown). In this case, the capacity setting data is written from the external device to the storage unit 180. The storage unit 180 may be provided in each of the waveform forming circuits HSC1 to HSCn. Alternatively, the storage unit 180 may be provided in common for all the waveform forming circuits HSC1 to HSCn. In this case, the capacitance setting data may be individually set for each of the waveform forming circuits HSC1 to HSCn.

The voltage division node NB is connected to the first input node, which is the input node of the first withstand voltage buffer circuit 110. That is, the distortion adjustment circuit 130 outputs the signal of the voltage division node NB to the first withstand voltage buffer circuit 110 as the adjusted signal TGS. The adjusted signal TGS is a signal in which the waveform distortion of the data voltage signal DVS is adjusted. This point will be described below. In the following, the code NB is also used for the first input node.

FIG. 6 shows the parasitic resistance RP parasitizing the flexible substrate and the parasitic capacitances CP1 and CP2. RP1 and CP1 are parasitic resistors and capacitances generated between the output terminal TDi of the display driver 12 and the input terminal TIi of the circuit device 100. CP2 is a parasitic capacitance generated between the output terminal TDi and the ground.

FIG. 7 is an example of a signal waveform in the circuit device 100. Here, as an example, an example in which the amplifier circuit AMi outputs a rectangular wave data voltage signal is shown. The pulse width of the square wave corresponds to the period during which the gradation voltage for one pixel is output in the multiplexed data voltage signal.

As shown in the upper part of FIG. 7, the data voltage signal DVS input to the strain adjustment circuit 130 is distorted by the parasitic resistance RP and the parasitic capacitances CP1 and CP2 of the flexible substrate and the capacitance C3 of the electrostatic protection circuit. FIG. 7 shows, as an example, a waveform when the high frequency component of the square wave is reduced. As shown in the lower part of FIG. 7, the adjusted signal TGS output by the distortion adjustment circuit 130 has a smaller amplitude than the data voltage signal DVS and has less distortion than the data voltage signal DVS.

Specifically, the amplitude of the adjusted signal TGS is determined by the voltage division ratio of the voltage dividing circuit 105. Further, the frequency characteristic of the distortion adjustment circuit 130 is determined by the voltage division ratio of the voltage dividing circuit 105 and the capacitance ratio of the first capacitor C1 and the second capacitor C2, and the waveform distortion of the data voltage signal DVS is adjusted by the frequency characteristic. NS. By setting the capacitance value of the second capacitor C2 so that the voltage division ratio and the capacitance ratio are the same, a distortion-corrected adjusted signal TGS can be obtained.

More specifically, the distortion is corrected by setting the capacitance value of the second capacitor C2 so that the partial voltage ratio including the parasitic resistance and the parasitic capacitance of the flexible substrate and the capacitance ratio are the same. The back signal TGS is obtained. Here, the resistance values of RP, R1 and R2 are rp, r1 and r2, and the capacitance values of CP1, C1 and C2 are cp1, c1 and c2. The voltage division ratio including the parasitic resistance and the parasitic capacitance is rp + r1: r2, and the capacitance ratio is cp1 + c1: c2. The capacitance value of the second capacitor C2 is set so that these ratios are the same. Since rp and cp1 are unknown, the capacitance value of the second capacitor C2 may be determined based on, for example, the result of actually measuring the waveform or the result of circuit simulation. Alternatively, a monitor circuit (not shown) is built in the circuit device 100, the monitor circuit compares the first output signal QS1 with the reference signal, and the capacitance value of the second capacitor C2 is automatically set based on the comparison result. You may. The voltage division ratio and the volume ratio do not have to be exactly the same. That is, the voltage division ratio and the capacitance ratio may be different as long as the distortion of the data voltage signal DVS is adjusted appropriately.

According to the present embodiment, by providing the distortion adjustment circuit 130, it is possible to adjust the distortion of the data voltage signal DVS in which waveform distortion occurs due to transmission by a flexible substrate or the like. As a result, a high-speed data voltage signal that cannot be transmitted on a flexible substrate without the circuit device 100 can be transmitted by providing the circuit device 100, and it is possible to cope with an increase in the number of pixels of the electro-optical panel 15. Will be.

Further, according to the present embodiment, by providing the voltage dividing circuit 105, it is possible to make the coefficient of determination ratio rp + r1: r2 and the capacitance ratio cp1 + c1: c2 the same. Qualitatively, in the path from the output node of the amplifier circuit AMi to the voltage division node NB of the strain adjustment circuit 130, the gain in the low frequency band is determined by the voltage division ratio rp + r1: r2, and the gain in the high frequency band is determined by the capacitance ratio cp1 + c1: c2. The gain is determined. When the voltage division ratio and the capacitance value are the same, the gain in the low frequency band and the gain in the high frequency band are the same, and the frequency characteristics in the above path are close to flat. As a result, the adjusted signal TGS with less distortion can be obtained. When the capacitance value of the second capacitor C2 is increased, the high frequency component of the adjusted signal TGS is relatively decreased, and when the capacitance value of the second capacitor C2 is decreased, the high frequency component of the adjusted signal TGS is relatively increased. do.

In the present embodiment, the input impedance of the strain adjustment circuit 130 is lower than the input impedance of the input terminal TPj of the electro-optical panel 15 to which the second output signal QS2j from the second withstand voltage buffer circuit BF2j is input. j is an integer of 1 or more and m or less. The input impedance of the strain adjustment circuit 130 is the input impedance of the strain adjustment circuit 130 as seen from the input terminal TIi. In this way, the data voltage signal input to the electro-optical panel 15 when the circuit device 100 is provided is more than the waveform distortion of the data voltage signal input to the electro-optical panel 15 when the circuit device 100 is not provided. The waveform distortion of is smaller. In the present embodiment, since the data voltage signal is further strain-adjusted by the strain adjusting circuit 130, high-speed data voltage signal transmission is possible.

Next, the first withstand voltage buffer circuit 110 of FIG. 6 will be described. Taking the jth analog latch circuit ALj and the j second withstand voltage buffer circuit BF2j as examples, the first to mth analog latch circuits AL1 to ALm and the first to m second withstand voltage buffer circuits BF21 to BF2m Will be described.

A data voltage signal DVS in which the first to mth gradation voltages are multiplexed is input to the distortion adjustment circuit 130 via the input terminal TIi. For example, when i = 1 and m = 3, V1 to V3 and the like in FIG. 5 correspond to the first to mth gradation voltages. The adjusted signal TGS output by the distortion adjustment circuit 130 is a signal in which m voltages are multiplexed corresponding to the first to mth gradation voltages.

The first withstand voltage buffer circuit 110 is composed of a transistor with a first withstand voltage, buffers the adjusted signal TGS, and outputs the first output signal QS1.

FIG. 8 is a detailed configuration example of the first withstand voltage buffer circuit 110. The first withstand voltage buffer circuit 110 includes an operational amplifier ABF1 composed of a first withstand voltage transistor. The first withstand voltage buffer circuit 110 is a voltage follower circuit configured by the operational amplifier ABF1. That is, the non-inverting input node of the operational amplifier ABF1 is connected to the first input node NB. The inverting input node of the operational amplifier ABF1 is connected to the output node of the operational amplifier ABF1. The output node of the operational amplifier ABF1 is the output node of the first withstand voltage buffer circuit 110, and this is referred to as the first output node NC. The first output node NC is connected to the input node of the jth analog latch circuit ALj.

The first output signal QS1 is input to the jth analog latch circuit ALj. The first output signal QS1 is a signal in which m voltages are multiplexed corresponding to the first to mth gradation voltages. The j-th analog latch circuit ALj latches the voltage corresponding to the j-th gradation voltage in the first output signal QS1 based on the latch signal ENIj, and outputs the latched voltage to the output node NEj as the output signal ALQj. .. The latch signal ENIj is input from the timing signal output circuit 195 to the analog latch circuit ALj.

FIG. 9 is a detailed configuration example of the j-th analog latch circuit ALj. The j-th analog latch circuit ALj includes a switch SWA and a capacitor CA. The switch SWA is a transistor and is controlled on or off by the latch signal ENIj. One end of the switch SWA is connected to the first output node NC, and the other end is connected to the output node NEj. One end of the capacitor CA is connected to the output node NEj, and the other end is connected to the ground node. When the switch SWA is on, the first output signal QS1 is output as the output signal ALQj. When the switch SWA is turned from on to off, the voltage held in the capacitor CA is fixed and output as an output signal ALQj. The output node NEj is connected to a second input node which is an input node of the second withstand voltage buffer circuit BF2j of the jth. Hereinafter, the reference numeral NEj is also used for the second input node.

The second withstand voltage buffer circuit BF2j of the second j is composed of a transistor with a second withstand voltage higher than the first withstand voltage, amplifies the output signal ALQj of the analog latch circuit ALj of the jth, and outputs the second output signal QS2j to the electro-optical panel 15 Output to. The amplitude of the output signal ALQj is the same as the amplitude of the first output signal QS1 and is smaller than the amplitude of the data voltage signal DVS as described with reference to FIG. The second withstand voltage buffer circuit BF2j has a gain larger than 1, and increases the amplitude of the output signal ALQj to output as the second output signal QS2j. For example, the second withstand voltage buffer circuit BF2j has a gain such that the amplitude of the second output signal QS2j is about the same as the amplitude of the data voltage signal DVS. The gain of the second withstand voltage buffer circuit BF2j is about the reciprocal of the voltage division ratio of the voltage dividing circuit 105.

FIG. 10 is a detailed configuration example of the second withstand voltage buffer circuit BF2j of the jth. The second withstand voltage buffer circuit BF2j j includes an operational amplifier ABF2 composed of a second withstand voltage transistor, resistors RBF1 and RBF2. The second withstand voltage buffer circuit BF2j of the jth is a forward rotation amplifier circuit. That is, the non-inverting input node of the operational amplifier ABF2 is connected to the second input node NEj. The output node of the operational amplifier ABF2 is connected to one end of the resistor RBF1, and the inverting input node of the operational amplifier ABF2 is connected to the other end of the resistor RBF1 and one end of the resistor RBF2. The other end of the resistor RBF2 is connected to the ground node NG. The output node of the operational amplifier ABF2 is the output node of the second withstand voltage buffer circuit 120, and this is referred to as the second output node NDj. The second output node NDj is connected to the output terminal TQij.

The withstand voltage of a transistor is the maximum rated voltage that can be applied to the terminals of the transistor, and is defined by, for example, a semiconductor process. The withstand voltage of the transistor is determined by the thickness of the gate oxide film, the impurity concentration in the impurity region, and the electric field relaxation structure. That is, the transistor having the first withstand voltage and the transistor having the second withstand voltage differ in at least one of the thickness of the gate oxide film, the concentration of impurities in the impurity region, and the electric field relaxation structure. For example, when a process having two types of transistors, high withstand voltage and low withstand voltage, is used, the first withstand voltage corresponds to low withstand voltage and the second withstand voltage corresponds to high withstand voltage. Alternatively, when a process having three types of transistors, high withstand voltage, medium withstand voltage, and low withstand voltage, is used, the first withstand voltage corresponds to low withstand voltage and the second withstand voltage corresponds to medium withstand voltage or high withstand voltage. Alternatively, the first withstand voltage corresponds to a medium withstand voltage, and the second withstand voltage corresponds to a high withstand voltage.

According to this embodiment, the strain adjusting circuit 130 divides the voltage, so that the first withstand voltage buffer circuit 110 can be configured by a transistor having a first withstand voltage lower than the second withstand voltage. As the second withstand voltage, the withstand voltage required to drive the electro-optical panel 15 is required. By forming the first withstand voltage buffer circuit 110 with transistors having a first withstand voltage lower than the second withstand voltage, the first withstand voltage buffer circuit 110 can be made smaller, faster, and consume less power.

FIG. 11 is a waveform diagram illustrating the operation of the circuit device 100 in the first detailed configuration example. FIG. 11 is an example in the case where m = 3. The first withstand voltage buffer circuit 110 sequentially outputs a plurality of voltages VA1 to VA3 as the first output signal QS1. This corresponds to the display driver 12 sequentially outputting a plurality of gradation voltages as a data voltage signal DVS.

As shown in FIG. 11, the latch signals ENI1 to ENI3 are sequentially set to high levels in synchronization with the multiplexed data voltage signal DVS. Specifically, when the latch signal ENI1 becomes a high level when QS1 = VA1, and the latch signal ENI1 changes from a high level to a low level, the analog latch circuit AL1 holds the output signal ALQ1 = VA1. Similarly, when QS1 = VA2 and VA3, the latch signals ENI2 and ENI3 become high level, and when the latch signals ENI2 and ENI3 change from high level to low level, the analog latch circuits AL2 and AL3 output signals ALQ2 = VA2 and ALQ3. = Holds VA3.

The second withstand voltage buffer circuit BF21 amplifies the output signal ALQ1 of the analog latch circuit AL1 and outputs the output signal QS21. Similarly, the second withstand voltage buffer circuits BF22 and BF23 amplify the output signals ALQ2 and ALQ3 of the analog latch circuits AL2 and AL3 and output the output signal QS21.

According to this embodiment, the display driver 12 multiplexes a plurality of gradation voltages and outputs the data voltage signal DVS, and the analog latch circuits AL1 to ALm can demultiplex the multiplexed voltage. As a result, it is possible to increase the number of pixels or the frame rate of the electro-optical panel 15 while reducing the number of outputs of the display driver 12. That is, the number of outputs of the display driver 12 may be 1 / m with respect to the number of inputs of the electro-optical panel 15, but the transfer rate of the data voltage signal from the display driver 12 to the circuit device 100 is m times. As described above, in the present embodiment, since the waveform distortion can be adjusted by the distortion adjusting circuit 130, the data voltage signal can be transmitted with high accuracy and high speed even if the transfer rate is increased by m times.

3. 3. Second Detailed Configuration Example of Circuit Device FIG. 12 is a second detailed configuration example of the circuit device 100. In FIG. 12, the waveform shaping circuit HSSi further includes first to mth voltage shift circuits VSH1 to VSHm. The components already described are designated by the same reference numerals, and the description of the components will be omitted as appropriate. Although only the configuration related to the waveform forming circuit HSCi is shown in FIG. 12, the waveform forming circuits HSC1 to HSCn have the same configuration.

The second voltage shift circuit VSHj will be described as an example. The j-th voltage shift circuit VSHj voltage-shifts the input signal of the second withstand voltage buffer circuit BF2j of the jth based on the polarity signal POL. In FIG. 12, the input signal of the second withstand voltage buffer circuit BF2j of the jth is the output signal ALQj of the analog latch circuit ALj. The polarity signal POL is input from the timing signal output circuit 195 to the j-th voltage shift circuit VSHj.

The j-th voltage shift circuit VSHj includes a capacitor CSj and a buffer circuit BFSj. One end of the capacitor CSj is connected to the second input node NEj, and the other end is connected to the output node of the buffer circuit BFSj. The polarity signal POL is input to the input node of the buffer circuit BFSj. The buffer circuit BFSj buffers the polarity signal POL and outputs it to the other end of the capacitor CSj. When the signal level of the polar signal POL changes, the voltage of the second input node NEj changes due to the coupling of the capacitor CSj. This conversion controls the polarity of the panel drive.

For example, it is assumed that the negative electrode voltage for driving the pixels of the electro-optical panel 15 is 0 to 5 V, the positive electrode voltage is 5 to 10 V, and the gain of the second withstand voltage buffer circuit BF2j of the jth is 2. The display driver 12 outputs a data voltage signal in the negative electrode voltage range of 0 to 5 V even during the positive electrode drive period. In this case, the capacitance of the capacitor CSj is set so that the voltage of the second input node NEj shifts by 2.5V by changing the polarity signal POL from the low level to the high level. Then, the voltage of the second input node NEj is shifted from the range of 0 to 2.5V to the range of 2.5V to 5V, and is doubled by the second withstand voltage buffer circuit BF2j of the j, so that the positive electrode voltage is 5V. It becomes 10V.

FIG. 13 is a waveform diagram illustrating the operation of the circuit device 100 in the second detailed configuration example. The operation until the analog latch circuits AL1 to AL3 latch the voltages VA1 to VA3 by the latch signals ENI1 to ENI3 is the same as in FIG. In FIG. 13, the polarity signal POL becomes high level after the latch signal ENI3 changes from high level to low level and before the latch signal ENI1 changes from low level to high level. As a result, the voltages of AL1 to AL3 input to the second withstand voltage buffer circuits BF21 to BF23 are shifted in the positive direction. As a result, the negative electrode voltage is shifted to the positive electrode voltage. Writing is performed on the pixels of the electro-optical panel 15 when the polarity signal POL is at a high level.

Although the case of performing positive electrode drive is shown in FIG. 13, in the case of negative electrode drive, after the latch signal ENI3 changes from high level to low level and before the latch signal ENI1 changes from low level to high level. , The polarity signal POL is maintained at a low level.

According to the present embodiment, by providing the first to mth voltage shift circuits VSH1 to VSHm, it is possible to reduce the withstand voltage of the transistors constituting the display driver 12 and the first withstand voltage buffer circuit 110. That is, since the display driver 12 only needs to output the negative electrode voltage and does not need to output the positive electrode voltage, the circuit can be configured with a transistor having a withstand voltage lower than that of the conventional one. Further, since the voltage obtained by dividing the negative electrode voltage by the voltage dividing circuit 131 is input to the first withstand voltage buffer circuit 110, the input voltage is lower than that in the case where the voltage shift circuit is not provided. As a result, the first withstand voltage buffer circuit 110 can be configured with transistors having a lower withstand voltage as compared with the case where the voltage shift circuit is not provided. By using a transistor with a lower withstand voltage, it is possible to reduce the size of the circuit, reduce the power consumption of the circuit, or operate the circuit at high speed.

4. Third Detailed Configuration Example of Circuit Device In the above, an example in which one second withstand voltage buffer circuit is provided in one analog latch circuit has been described, but even if one second withstand voltage buffer circuit is provided in a plurality of analog latch circuits. good. Hereinafter, a configuration in which one second withstand voltage buffer circuit is provided in a plurality of analog latch circuits will be described. Such a configuration is applicable when the electro-optical panel is of the demultiplex drive system.

FIG. 14 is a diagram illustrating the operation of the display driver 12, the circuit device 100, and the electro-optic panel 15 of FIG. 4 in the demultiplex drive system. Here, the case where n = 3 and m = 2 and the number of demultis is 2 will be described as an example, but the numerical values of n and m and the number of demultis are not limited to this. TH corresponds to the horizontal scanning period when the display driver 12 outputs a data voltage signal, and TH'corresponds to the horizontal scanning period when the electro-optical panel 15 is driven.

In the horizontal scanning period TH, the amplifier circuit AM1 of the display driver 12 sequentially outputs the gradation voltages V1', V3', V2', and V4'. The waveform forming circuit HSC1 latches the voltage corresponding to the gradation voltage V1 and V3, outputs the voltage from the output terminals TQ11 and TQ12, and then latches the voltage corresponding to the gradation voltage V2 and V4, and outputs the output terminals TQ11 and TQ12. Output from. As a result, V1'and V2' are sequentially output from the output terminals TQ11 and V3'and V4' are sequentially output from the output terminals TQ12 during the horizontal scanning period TH'.

Similarly, during the horizontal scanning period TH, the amplifier circuit AM2 of the display driver 12 sequentially outputs the gradation voltages V5', V7', V6', and V8', and the amplifier circuit AM3 of the display driver 12 has the gradation voltage. V9', V11', V10', and V12' are output in sequence. In the horizontal scanning period TH', output terminals TQ21 to V5' and V6' are sequentially output, output terminals TQ22 to V7'and V8' are sequentially output, and output terminals TQ31 to V9'and V10' are sequentially output. Then, V11'and V12' are sequentially output from the output terminal TQ32.

The switch circuit 51 of the electro-optical panel 15 sequentially connects the first data line and the second data line to the input terminal TP11 during the horizontal scanning period TH'. As a result, the gradation voltage V1'is written to the pixels connected to the selective scanning line and the first data line, and the gradation voltage V2'is written to the pixels connected to the selective scanning line and the second data line. Similarly, in the horizontal scanning period TH', the switch circuit 51 sequentially connects the third data line and the fourth data line to the input terminal TP12, and sequentially connects the fifth data line and the sixth data line to the input terminal TP21. Connect, connect the 7th data line and 8th data line to the input terminal TP22 in sequence, connect the 9th data line and 10th data line to the input terminal TP31 in sequence, and connect the 11th data line to the input terminal TP32. The twelfth data line is connected in sequence. As a result, the gradation voltages V3'to V12' are written to the pixels connected to the selective scanning line and the third to twelfth data lines.

FIG. 15 is a third detailed configuration example of the circuit device 100. In FIG. 15, the waveform forming circuit HSSi further includes the analog latch circuits ALm + 1 to AL2m of the first m + 1 to 2 m, the selectors SEL1 to SELm of the first to m, and the initialization circuits SINT1 to SINTm of the first to m. .. The components already described are designated by the same reference numerals, and the description of the components will be omitted as appropriate. Although only the configuration related to the waveform forming circuit HSCi is shown in FIG. 12, the waveform forming circuits HSC1 to HSCn have the same configuration.

Note that FIG. 15 illustrates an example in which the number of demultis is 2, but the present invention is not limited to this, and when the number of demultis is p, p analog latch circuits ALj are used for one second withstand voltage buffer circuit BF2j. , ALm + j, ..., ALpm + j may be provided. p is an integer of 2 or more.

The j-th analog latch circuit ALj, the m + j analog latch circuit ALm + j, the j-th selector SELj, and the initialization circuit SINTj will be described as examples. The configuration of the analog latch circuit ALm + j of the m + j is the same as that in FIG.

The jth selector SELj includes switches SSj and SSm + j. The input node of the j-th analog latch circuit ALj and the analog latch circuit ALm + j of the m + j is commonly connected to the first output node NC, and the output node is connected to one end of the switches SSj and SSm + j. The other ends of the switches SSj and SSm + j are connected to the node NFj. NFj is an input node of the second withstand voltage buffer circuit BF2j of the jth. The initialization circuit SINTj is a switch, one end of which is connected to the node NFj and the other end of which is connected to the node of the reference voltage VR. The reference voltage VR is, for example, a ground voltage, but is not limited thereto.

A data voltage signal DVS in which the gradation voltage of the first to second m gradation voltages is multiplexed is input to the distortion adjustment circuit 130 via the input terminal TIi. For example, when i = 1 and m = 2, V1', V3', V2', and V4'in FIG. 14 correspond to the first to fourth gradation voltages. The first output signal QS1 output by the first withstand voltage buffer circuit 110 is a signal in which 2 m of voltages are multiplexed corresponding to the gradation voltages of the first to second m.

The j-th analog latch circuit ALj latches the voltage corresponding to the j-th gradation voltage in the first output signal QS1 based on the latch signal ENIj, and outputs the latched voltage as the output signal ALQj. The analog latch circuit ALm + j of the m + j latches the voltage corresponding to the gradation voltage of the m + j in the first output signal QS1 based on the latch signal ENIm + j, and outputs the latched voltage as the output signal ALQm + j. The latch signals ENIj and ENIm + j are input from the timing signal output circuit 195 to the analog latch circuits ALj and ALm + j.

The jth selector SELj selects the output signal ALQj or the output signal ALQm + j, and outputs the selected signal as the output signal SLQj. Specifically, the selection signals ENQj and ENQm + j are input to the switches SSj and SSm + j from the timing signal output circuit 195. The switch SSj or the switch SSm + j is turned on based on the selection signals ENQj and ENQm + j. When the switch SSj is on, the jth selector SELj outputs the output signal ALQj, and when the switch SSm + j is on, the jth selector SELj outputs the output signal ALQm + j. The second withstand voltage buffer circuit BF2j of the second buffers the output signal SLQj of the selector SELj of the jth and outputs the second output signal QS2j to the electro-optical panel 15.

The initialization circuit SINTj initializes the charge of the node NFj. The node NFj is a second input node, that is, an input node of the j second withstand voltage buffer circuit BF2j. Specifically, the initialization signal INIT is input from the timing signal output circuit 195 to the initialization circuit SINTj, and the switch of the initialization circuit SINTj is turned on or off based on the initialization signal INIT. When both the switches SSj and SSm + j of the second selector SELj are off, the switch of the initialization circuit SINTj is turned on, and the second input node NFj and the node of the reference voltage VR are connected. As a result, the electric charge of the second input node NFj is initialized.

Since the analog latch circuits ALj and ALm + j hold the electric charge by the capacitor, the voltage of the second input node NFj becomes inaccurate due to the influence of the electric charge remaining in the second input node NFj. In the present embodiment, the charge of the second input node NFj is initialized by the initialization circuit SINTj, so that the voltage of the second input node NFj becomes accurate.

FIG. 16 is a waveform diagram illustrating the operation of the circuit device 100 in the third detailed configuration example. FIG. 16 shows an example in which m = 2 and the number of demultis is 2. The first withstand voltage buffer circuit 110 sequentially outputs a plurality of voltages VB1, VB3, VB2, and VB4 as the first output signal QS1. This corresponds to the display driver 12 sequentially outputting a plurality of gradation voltages as a data voltage signal DVS.

The latch signals ENI1, ENI2, ENI3, and ENI4 become high levels in order in synchronization with the timing of the voltages VB1, VB3, VB2, and VB4. As a result, the voltages VB1, VB3, VB2, and VB4 are latched by the analog latch circuits AL1, AL2, AL3, and AL4.

The selection signal ENQ1 changes from low level to high level after the latch signal ENI2 changes from high level to low level and before the latch signal ENI3 changes from low level to high level. The selection signal ENQ1 changes from high level to low level after the latch signal ENI4 changes from high level to low level. During the period when the selection signal ENQ1 is at a high level, the second withstand voltage buffer circuit BF21 outputs the output signal QS21 = VB1, and the second withstand voltage buffer circuit BF22 outputs the output signal QS22 = VB3.

The selection signal ENQ2 changes from low level to high level after the selection signal ENQ1 changes from high level to low level and before the latch signal ENI1 changes from low level to high level. The selection signal ENQ2 changes from high level to low level after the latch signal ENI2 changes from high level to low level and before the selection signal ENQ1 changes from low level to high level. During the period when the selection signal ENQ2 is at a high level, the second withstand voltage buffer circuit BF21 outputs the output signal QS21 = VB2, and the second withstand voltage buffer circuit BF22 outputs the output signal QS22 = VB4.

The initialization signal INIT becomes a high level when both the selection signals ENQ1 and ENQ2 are at a low level. For example, if the reference voltage VR is the ground voltage, the input signals of the second withstand voltage buffer circuits BF21 and BF22 become the ground voltage when the initialization signal INIT becomes high level, and the second withstand voltage buffer circuits BF21 and BF22 become the ground voltage. Is output. After that, the input signals of the second withstand voltage buffer circuits BF21 and BF22 are maintained at the ground voltage until any of the selection signals ENQ1 and ENQ2 reaches a high level.

The voltage shift circuits VSH1 to VSHm of FIG. 12 may be combined with the configuration of FIG. In this case, the voltage shift circuit VSHj is connected to the second input node NFj in FIG. The polarity signal POL is maintained at a low level in the negative electrode drive. In the positive electrode drive, the polarity signal POL changes from low level to high level and from high level to low level during the period when the selection signal ENQ1 or ENQ2 is at a high level. During the period when the polarity signal POL is at a high level, writing to the pixels of the electro-optical panel 15 is performed.

5. Second Configuration Example of Electro-Optical Device FIG. 17 is a second configuration example of the electro-optical device 10. The electro-optical device 10 includes a display driver 12, a connector 13, an electro-optical panel 15, a substrate 16, a thin coaxial cable group 17, a connector 18, and a circuit device 100. The components already described are designated by the same reference numerals, and the description of the components will be omitted as appropriate.

The thin coaxial cable group 17 includes a plurality of thin coaxial cables, one end of which is connected to the connector 13 and the other end of which is connected to the connector 18. One thin coaxial cable is provided for one output of the display driver 12. The thin coaxial cable is a very thin coaxial cable, for example, a coaxial cable having a cable outer diameter of 1 mm or less.

The connector 18 is mounted on one end of the flexible substrate 19. The other end of the flexible substrate 19 is connected to the electro-optical panel 15, and the circuit device 100 is mounted on the flexible substrate 19. The data voltage signal and control signal output by the display driver 12 are input to the circuit device 100 via the thin coaxial cable group 17 and the flexible substrate 19. The configuration and operation of the circuit device 100 are as described above.

6. Electronic device FIG. 18 is a configuration example of an electronic device 300 including a circuit device 100. The electronic device 300 includes an electro-optical device 10, a processing device 310, a display controller 320, a storage unit 330, a communication unit 340, and an operation unit 360. The electro-optical device 10 includes a display driver 12, a circuit device 100, and an electro-optical panel 15.

As a specific example of the electronic device 300, various electronic devices equipped with a display device such as a projector, a head-mounted display, a portable information terminal, an in-vehicle device, a portable game terminal, and an information processing device can be assumed. The in-vehicle device is, for example, a meter panel, a car navigation system, or the like.

The operation unit 360 is a user interface that receives various operations from the user. For example, a button, a mouse, a keyboard, a touch panel attached to the electro-optical panel 15, and the like. The communication unit 340 is a data interface that inputs and outputs image data and control data. The communication unit 340 is, for example, a wireless communication interface such as a wireless LAN or short-range wireless communication, or a wired communication interface such as a wired LAN or USB. The storage unit 330 stores, for example, the data input from the communication unit 340, or functions as a working memory of the processing device 310. The storage unit 330 is, for example, a memory such as a RAM or ROM, a magnetic storage device such as an HDD, or an optical storage device such as a CD drive or a DVD drive. The display controller 320 processes the image data input from the communication unit 340 or stored in the storage unit 330 and transfers the image data to the display driver 12. The display driver 12 outputs a data voltage signal and a control signal based on the image data transferred from the display controller 320. The circuit device 100 adjusts the distortion of the data voltage signal and shifts the level of the control signal, and outputs them to the electro-optical panel 15. As a result, the image is displayed on the electro-optical panel 15. The processing device 310 performs control processing of the electronic device 300, various signal processing, and the like. The processing device 310 is, for example, a processor such as a CPU or MPU, or an ASIC or the like.

For example, when the electronic device 300 is a projector, the electronic device 300 further includes a light source and an optical system. The optical system is, for example, a lens, a prism, a mirror, or the like. When the electro-optical panel 15 is a transmission type, the optical device causes the light from the light source to enter the electro-optical panel 15 and projects the light transmitted through the electro-optical panel 15 onto the screen. When the electro-optical panel 15 is a reflection type, the optical device causes the light from the light source to enter the electro-optical panel 15 and projects the light reflected from the electro-optical panel 15 onto the screen.

The circuit device of the present embodiment described above includes a strain adjustment circuit, a first withstand voltage buffer circuit, first to first m analog latch circuits, and first to first m second withstand voltage buffer circuits. In the distortion adjustment circuit, a data voltage signal in which the first to mth gradation voltages are multiplexed is input from the display driver, the waveform distortion of the data voltage signal is adjusted, and the adjusted signal is output. The first withstand voltage buffer circuit is composed of transistors with a first withstand voltage, buffers the adjusted signal, and outputs the first output signal. The j-th analog latch circuit latches the voltage corresponding to the j-th gradation voltage in the first output signal. The second withstand voltage buffer circuit of j is composed of transistors having a second withstand voltage higher than that of the first withstand voltage, amplifies the output signal of the analog latch circuit of j, and outputs the second output signal to the electro-optical panel.

In this way, the distortion adjusting circuit can adjust the distortion of the data voltage signal caused by the waveform distortion caused by the transmission by the flexible substrate or the like. As a result, high-speed data voltage signals that cannot be transmitted on a flexible substrate without a circuit device can be transmitted by providing a circuit device. By enabling high-speed data voltage signals to be transmitted, it becomes possible to cope with an increase in the number of pixels of an electro-optical panel. Further, according to the present embodiment, the display driver multiplexes the first to mth gradation voltages and outputs them as a data voltage signal, and the first to mth analog latch circuits demultiply the multiplexed voltage. You can plex. As a result, it is possible to increase the number of pixels or the frame rate of the electro-optical panel 15 while reducing the number of outputs of the display driver. In the present embodiment, since the waveform distortion can be adjusted by the distortion adjustment circuit, the data voltage signal can be transmitted with high accuracy and high speed even if the transfer rate is increased by the demultiplexing.

Further, the circuit device of the present embodiment may include the first to third voltage shift circuits. The j-th voltage shift circuit may voltage-shift the input signal of the second withstand voltage buffer circuit of the jth based on the polarity signal.

In this way, the negative electrode voltage can be voltage-shifted to the positive electrode voltage by the voltage shift circuit, so that the display driver only needs to output the negative electrode voltage even in the positive electrode drive. This makes it possible to reduce the withstand voltage of the transistors that make up the display driver and the transistors that make up the first withstand voltage buffer circuit. By lowering the withstand voltage, it is possible to reduce the size of the circuit, reduce the power consumption of the circuit, or operate the circuit at high speed.

Further, in the present embodiment, the distortion adjusting circuit may have a voltage dividing circuit. The voltage dividing circuit may be provided between the data voltage signal input node into which the data voltage signal is input and the ground node. The voltage dividing node of the voltage dividing circuit may be connected to the first input node of the first withstand voltage buffer circuit.

In this way, it is possible to make the voltage division ratio and the capacitance ratio to the data voltage signal the same in the path from the output of the display driver to the voltage division node of the distortion adjustment circuit. When the voltage division ratio and the capacitance value are the same, the gain in the low frequency band and the gain in the high frequency band are the same, and the frequency characteristics in the above path are close to flat. As a result, an adjusted signal with less distortion can be obtained.

Further, in the present embodiment, the strain adjusting circuit may have a first capacitor and a second capacitor. The first capacitor may be provided between the data voltage signal input node and the voltage dividing node. The second capacitor may be provided between the voltage dividing node and the ground node, and the capacitance value may be variable.

By doing so, the above-mentioned capacitance ratio is adjusted by adjusting the capacitance value of the second capacitor. This makes it possible to make the voltage division ratio and the capacitance ratio to the data voltage signal the same in the path from the output of the display driver to the voltage division node of the distortion adjustment circuit.

Further, in the present embodiment, the voltage dividing circuit may have a first resistor and a second resistor. The first resistor may be provided between the data voltage signal input node and the voltage dividing node. The second resistor may be provided between the voltage dividing node and the ground node.

In this way, the data voltage signal can be divided by the first resistor and the second resistor. The above-mentioned voltage division ratio is determined by the parasitic resistance of the transmission path such as a flexible substrate, the first resistance, and the second resistance.

Further, in the present embodiment, the input impedance of the distortion adjustment circuit may be lower than the input impedance of the input terminal of the electro-optical panel to which the second output signal is input.

In this way, the waveform distortion of the data voltage signal input to the circuit device when the circuit device is provided is larger than the waveform distortion of the data voltage signal input to the electro-optical panel when the circuit device is not provided. However, it becomes smaller. In the present embodiment, since the data voltage signal is further strain-adjusted by the distortion adjusting circuit, high-speed data voltage signal transmission is possible.

Further, the circuit device of the present embodiment may include a first m + 1st and 2nd m analog latch circuit into which a first output signal is input, and a first to mth selector. A data voltage signal in which the first to mth gradation voltage and the first m + 1st to second m gradation voltage are multiplexed may be input to the distortion adjustment circuit from the display driver. The m + j analog latch circuit may latch a voltage corresponding to the gradation voltage of the m + j in the first output signal. The j-th selector may select and output the output signal of the j-th analog latch circuit or the output signal of the m + j analog circuit. The second withstand voltage buffer circuit of j may buffer the output signal of the selector of j and output the second output signal to the electro-optic panel.

In this way, the circuit device can be applied when the electro-optical panel is of the demultiplex drive system. That is, the j-th selector selects and outputs the output signal of the j-th analog latch circuit or the output signal of the m + j analog circuit, so that the output signal of the j-th analog latch circuit and the analog of the m + j The output signal of the circuit is multiplexed. The second withstand voltage buffer circuit of the jth amplifies and outputs the multiplexed signal, so that the multiplexed gradation voltage is input to the electro-optical panel. This multiplexed gradation voltage is demultiplexed by the switch circuit of the electro-optical panel.

Further, the circuit device of the present embodiment may include the first to first m initialization circuits. The initialization circuit of the jth may be connected to the second input node of the second withstand voltage buffer circuit of the jth, and may initialize the charge of the second input node.

Since the j-th analog latch circuit and the j + m analog latch circuit ALm + j hold the electric charge, the second input node, which is the input node of the second withstand voltage buffer circuit, is affected by the electric charge remaining on the second input node. The voltage at the input node becomes inaccurate. In the present embodiment, the charge of the second input node is initialized by the initialization circuit, so that the voltage of the second input node becomes accurate. As a result, the second withstand voltage buffer circuit of j can output an accurate gradation voltage.

Further, the electro-optical device of the present embodiment includes the circuit device according to any one of the above, a display driver, and an electro-optical panel.

Further, in the present embodiment, the electro-optical device may include a flexible substrate. A circuit device is provided on the flexible substrate, and the flexible substrate may be connected to an electro-optical panel.

Further, the electronic device of the present embodiment includes the circuit device according to any one of the above.

Although the present embodiment has been described in detail as described above, those skilled in the art will easily understand that many modifications that do not substantially deviate from the new matters and effects of the present disclosure are possible. Therefore, all such variations are included in the scope of the present disclosure. For example, a term described at least once in a specification or drawing with a different term in a broader or synonymous manner may be replaced by that different term anywhere in the specification or drawing. All combinations of the present embodiment and modifications are also included in the scope of the present disclosure. Further, the configuration and operation of the circuit device, the display driver, the electro-optical panel, the electro-optic device, the electronic device, and the like are not limited to those described in the present embodiment, and various modifications can be performed.

10 ... Electro-optical device, 12 ... Display driver, 13 ... Connector, 14 ... Flexible board, 15 ... Electro-optical panel, 16 ... Board, 17 ... Thin coaxial cable group, 18 ... Connector, 19 ... Flexible board, 21 ... Control circuit , 51 ... switch circuit, 52 ... pixel array, 100 ... circuit device, 105 ... voltage dividing circuit, 110 ... first withstand voltage buffer circuit, 130 ... distortion adjustment circuit, 131 ... voltage dividing circuit, 180 ... storage unit, 195 ... timing Signal output circuit, 300 ... Electronic equipment, 310 ... Processing device, 320 ... Display controller, 330 ... Storage unit, 340 ... Communication unit, 360 ... Operation unit, AL1 to ALm ... Analog latch circuit, BF21 to BF2m ... Second withstand voltage buffer Circuit, C1 ... 1st capacitor, C2 ... 2nd capacitor, DVS ... Data voltage signal, POL ... Polarity signal, QS1 ... 1st output signal, QS21 to QS2m ... 2nd output signal, SEL1 to SELm ... Selector, SINT1 to SINTm ... initialization circuit, TGS ... adjusted signal, VSH1 to VSHm ... voltage shift circuit

Claims (11)

A data voltage signal in which the first to mth gradation voltages (m is an integer of 2 or more) is multiplexed is input from the display driver, the waveform distortion of the data voltage signal is adjusted, and the adjusted signal is output. Distortion adjustment circuit and
A first withstand voltage buffer circuit composed of transistors with a first withstand voltage, buffering the adjusted signal and outputting a first output signal, and a first withstand voltage buffer circuit.
The first to mth analog latch circuits to which the first output signal is input, and
The first to second m second withstand voltage buffer circuits and
Including
The j-th analog latch circuit (j is an integer of 1 or more and m or less) is
The voltage corresponding to the j-th gradation voltage is latched in the first output signal, and the voltage corresponding to the j-th gradation voltage is latched.
The second withstand voltage buffer circuit of the jth is
A circuit device composed of transistors having a second withstand voltage higher than the first withstand voltage, amplifying the output signal of the j-th analog latch circuit, and outputting the second output signal to an electro-optical panel. In the circuit device according to claim 1,
Including the first to mth voltage shift circuits, including
The j-th voltage shift circuit is
A circuit device characterized in that the input signal of the second withstand voltage buffer circuit of the jth is voltage-shifted based on a polarity signal. In the circuit device according to claim 1 or 2.
The distortion adjustment circuit
It has a voltage dividing circuit provided between a data voltage signal input node into which the data voltage signal is input and a ground node.
A circuit device characterized in that a voltage dividing node of the voltage dividing circuit is connected to a first input node of the first withstand voltage buffer circuit. In the circuit device according to claim 3,
The distortion adjustment circuit
A first capacitor provided between the data voltage signal input node and the voltage dividing node,
A second capacitor provided between the voltage dividing node and the ground node and having a variable capacitance value,
A circuit device characterized by having. In the circuit device according to claim 3 or 4.
The voltage dividing circuit
A first resistor provided between the data voltage signal input node and the voltage dividing node,
A second resistor provided between the voltage dividing node and the ground node,
A circuit device characterized by having. In the circuit device according to any one of claims 1 to 5.
The input impedance of the distortion adjustment circuit is
A circuit device characterized in that the input impedance of the terminal of the electro-optical panel to which the second output signal is input is lower than the input impedance. In the circuit device according to any one of claims 1 to 6.
The m + 1 to 2 m analog latch circuits to which the first output signal is input, and
The first to mth selectors and
Including
The data voltage signal in which the first to mth gradation voltage and the m + 1st to second m gradation voltage are multiplexed is input to the distortion adjustment circuit from the display driver.
The m + j analog latch circuit (j is an integer of 1 or more and m or less) is
In the first output signal, the voltage corresponding to the gradation voltage of the m + j is latched, and the voltage corresponding to the gradation voltage is latched.
The jth selector is
The output signal of the j-th analog latch circuit or the output signal of the m + j analog circuit is selected and output.
The second withstand voltage buffer circuit of the jth is
A circuit device characterized in that the output signal of the j-th selector is buffered and the second output signal is output to the electro-optical panel. In the circuit device according to claim 7.
Including the first to mth initialization circuits
The j-th initialization circuit is
A circuit device that is connected to a second input node of the second withstand voltage buffer circuit of j and initializes the electric charge of the second input node. The circuit device according to any one of claims 1 to 8.
With the display driver
With the electro-optic panel
An electro-optic device comprising. In the electro-optical device according to claim 9.
An electro-optical device provided with the circuit device and including a flexible substrate connected to the electro-optical panel. An electronic device comprising the circuit device according to any one of claims 1 to 8.

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