JP6737256B2 - Display driver, electro-optical device and electronic device - Google Patents

Description

The present invention relates to a display driver, an electro-optical device, an electronic device and the like.

A display driver that drives an electro-optical panel includes a D/A conversion circuit that selects a grayscale voltage corresponding to display data from a plurality of voltages generated by a ladder resistance circuit, and amplifies or buffers the grayscale voltage. And an amplifier circuit for (impedance conversion) and outputting a data voltage. The amplifier circuit writes to the pixel by driving the data line of the electro-optical panel with the data voltage. Conventional techniques of such a display driver are disclosed in Patent Documents 1 to 3, for example. In Patent Document 1, the amplifier circuit is configured by a non-inverting amplifier circuit. Further, in Patent Documents 2 and 3, the amplifier circuit is configured by an inverting amplifier circuit.

In recent years, display drivers are required to drive pixels at high speed within a short drive time due to higher definition and higher frame rate of electro-optical panels. Therefore, the amplifier circuit is configured using an operational amplifier having a high-speed response (for example, a high slew rate or a high sensitivity) so that the amplifier circuit can change the data voltage at high speed. By increasing the speed of the amplifier circuit as described above, the writing time to the pixel is shortened.

JP, 2005-292856, A JP 2001-67047 A JP-A-10-260664

When the speed of the amplifier circuit as described above is increased, high-speed writing (high slew rate) to the pixel becomes possible, while the high-speed response of the amplifier circuit affects the stability of the data voltage, Convergence to the target voltage is lowered, or accuracy of the writing voltage to the pixel is lowered. For example, the display driver has a plurality of outputs (a plurality of data voltage output terminals), and an amplifier circuit is provided for each output. At this time, since the characteristics of the amplifier circuit vary, the error in the write voltage caused by the decrease in stability may vary from output to output, and the display quality may deteriorate (for example, display unevenness may occur). Therefore, in order to shorten the writing time to the pixel, both high speed writing (high slew rate) to the pixel and stability of the data voltage are required.

According to some aspects of the present invention, it is possible to provide a display driver, an electro-optical device, an electronic device, and the like that can realize both high-speed writing (high slew rate) to pixels and stability of data voltage.

One embodiment of the present invention includes a data voltage output terminal, an amplifier circuit for outputting a data voltage, and a variable resistance circuit provided between an output node of the amplifier circuit and the data voltage output terminal, A drive circuit that outputs the data voltage from the data voltage output terminal to drive the data line of the electro-optical panel, and a resistance value of the variable resistance circuit from the first resistance value to the first resistance value at the switching timing of the drive period. A resistance control circuit for performing control to switch to a second resistance value higher than the resistance value, wherein the drive circuit sets a first data voltage corresponding to first display data to the data in the first drive period. The voltage is output to the voltage output terminal, and the second data voltage corresponding to the second display data is output to the data voltage output terminal in the second driving period subsequent to the first driving period. In the second driving period, the resistance value of the variable resistance circuit is changed from the first resistance value to the resistance value of the variable resistance circuit at the switching timing which becomes slower as the difference between the first data voltage and the second data voltage becomes larger. Related to a display driver that switches to a second resistance value.

According to one aspect of the present invention, the resistance value of the variable resistance circuit is switched from the first resistance value to the second resistance value higher than that at the switching timing. Thus, in the period before the switching timing, electric charges can be supplied to the source line (pixel) of the electro-optical panel at high speed, and the voltage of the source line can be changed sharply. On the other hand, in the period after the switching timing, the resistance value between the capacitance of the data line and the source line of the electro-optical panel and the output node of the amplifier circuit becomes high, and the stability of the voltage (data voltage) output by the amplifier circuit is improved. Can be secured. Further, by delaying the switching timing as the difference between the first data voltage and the second data voltage becomes larger, the data voltage is stabilized at the earliest possible timing while maximizing the period for driving the pixels at high speed. Can be converted. As described above, both high-speed writing to the pixel and stability of the data voltage can be realized.

Further, in one aspect of the present invention, the resistance control circuit may perform control such that the switching timing is delayed as the difference value between the first display data and the second display data increases.

The larger the difference value between the first display data and the second display data, the larger the difference between the first data voltage and the second data voltage. That is, the switching timing is delayed as the difference value between the first display data and the second display data is larger, and thus the switching timing is delayed as the difference between the first data voltage and the second data voltage is larger. Can be realized.

Further, in the aspect of the invention, the resistance control circuit may set the switching timing corresponding to the difference value based on table data that associates the difference value with the switching timing.

The time from the start of the driving period until the voltage of the data voltage output terminal reaches the vicinity of the target voltage is not necessarily linear with respect to the difference value of display data (difference in data voltage). By using the table data, the switching timing of the non-linear characteristic with respect to the difference value of the display data can be set, so that the pixel can be driven at high speed (the resistance value of the variable resistance circuit is the first resistance value). Can be optimized.

Further, in one aspect of the present invention, the resistance control circuit sets the resistance value of the variable resistance circuit to the first resistance value at the switching timing before the voltage of the data voltage output terminal reaches the data voltage which is a target voltage. The resistance value may be switched to the second resistance value.

If the voltage of the data voltage output terminal overshoots the target voltage, it takes extra time for the amplifier circuit to converge the overshooted voltage to the target voltage. According to one aspect of the present invention, it is possible to prevent the voltage of the data voltage output terminal from overshooting the target voltage, so that the voltage can be converged to the target voltage in a short time.

Further, in one aspect of the present invention, the variable resistance circuit includes first to nth resistances (n is an integer of 2 or more) and a first resistance provided between an output node of the amplifier circuit and the data voltage output terminal. It may have an nth switch, and the resistance control circuit may control the resistance value of the variable resistance circuit by controlling each switch of the first to nth switches to be on or off.

In this way, the resistance control circuit controls each of the first to nth switches to be turned on or off, so that one or more of the first to nth resistors are connected to the output node of the amplifier circuit. Connected to the data voltage output terminal. As a result, the resistance value of the variable resistance circuit can be switched from the first resistance to the second resistance at the switching timing of the driving period.

Further, according to one aspect of the present invention, a noise compensation circuit that is connected to the data voltage output terminal and performs a noise compensation operation for reducing switching noise of the first to nth switches may be included.

The switching noise of the first to n-th switches becomes noise of the voltage of the data voltage output terminal, and thus the accuracy of the writing voltage to the pixel may be reduced. According to one embodiment of the present invention, since the noise compensation circuit reduces switching noise of the first to nth switches, noise in the voltage of the data voltage output terminal is reduced and the writing voltage to the pixel can be made highly accurate. ..

In one aspect of the present invention, the noise compensation circuit includes first to nth capacitors having one end connected to the data voltage output terminal and having capacitance values corresponding to sizes of the first to nth switches. The resistance control circuit has a voltage of the other end of each of the first to nth capacitors according to whether each of the first to nth switches is on or off. The switching noise may be compensated by controlling.

The larger the size of the first to nth switches, the larger the noise (charge) generated by the switching. According to one aspect of the present invention, one ends of the first to nth capacitors having capacitance values corresponding to the sizes of the first to nth switches are connected to the data voltage output terminal, and the first to nth capacitors are connected. The voltage at the other end of the capacitor is controlled. Accordingly, noise (charge) generated by switching the first to nth switches can be absorbed by the first to nth capacitors having a capacitance value corresponding to the size.

Further, in one aspect of the present invention, the variable resistance circuit includes a variable resistance element whose resistance value is variably controlled according to a control voltage, and the resistance control circuit changes the control voltage, The resistance value of the variable resistance circuit may be controlled.

With this configuration, the resistance control circuit changes the control voltage, so that the resistance value of the variable resistance element (variable resistance circuit) can be switched at the switching timing.

Further, according to one aspect of the present invention, a register that stores a first setting value for setting the first resistance value and a second setting value for setting the second resistance value is included, The resistance control circuit may switch the resistance value of the variable resistance circuit from the first resistance value to the second resistance value based on the first set value and the second set value.

With this configuration, the resistance value of the variable resistance circuit can be switched from the first resistance value to the second resistance value at the switching timing based on the first and second setting values set in the register. .. Moreover, since the first and second set values can be set in the register, the optimum first and second resistance values can be set according to the type (for example, model) of the electro-optical panel.

Further, in one aspect of the present invention, a ratio of the second resistance value to the first resistance value may be 2 or more.

The load viewed from the amplifier circuit is the resistance of the variable resistance circuit and the capacitance of the data line and the source line of the electro-optical panel. Assuming that the electrostatic protection resistance of the electro-optical panel is sufficiently smaller than the second resistance value, when the ratio of the second resistance value to the first resistance value is 2 or more, the frequency characteristic of the load is at the switching timing. It will be more than doubled. If the ratio of the frequency characteristics is about 2 to 4 times, it is considered that the stability of the feedback loop of the amplifier circuit can be ensured. Therefore, the ratio of the second resistance value to the first resistance value should be 2 or more. Can ensure stability.

In one aspect of the present invention, the amplifier circuit is provided between an operational amplifier having a non-inverting input terminal to which a reference voltage is input, and an input node of the amplifier circuit and an inverting input terminal of the operational amplifier. And a second resistor provided between the output terminal of the operational amplifier and the inverting input terminal.

This amplifier circuit is an inverting amplifier circuit. By adopting the inverting amplifier circuit, the operating point of the differential pair of the operational amplifier is limited to the reference voltage, so that the operational amplifier can be made highly sensitive (high gain). Further, in the inverting amplifier circuit, the output phase is rotated by 180 degrees with respect to the input, so that the band in which the phase margin can be secured is widened, and the frequency response characteristic can be improved. Such higher sensitivity and wider band are advantageous for high-speed writing, but the stability of the data voltage may be deteriorated due to noise from the electro-optical panel, for example. According to one aspect of the present invention, the stability of the data voltage can be improved by switching the resistance value of the variable resistance circuit to the high resistance value (second resistance value) at the switching timing.

Another aspect of the present invention is a drive having a data voltage output terminal, an amplifier circuit for outputting a data voltage, and a variable resistance circuit provided between an output node of the amplifier circuit and the data voltage output terminal. A circuit and a resistance control circuit that performs control to switch the resistance value of the variable resistance circuit from a first resistance value to a second resistance value higher than the first resistance value at a switching timing of a driving period, The resistance control circuit changes the resistance value of the variable resistance circuit from the first resistance value to the second resistance value at the switching timing before the voltage of the data voltage output terminal reaches the data voltage that is the target voltage. Related to the display driver that switches to resistance.

According to another aspect of the present invention, the resistance value of the variable resistance circuit is switched from the first resistance value to the second resistance value higher than that at the switching timing. Thus, in the period before the switching timing, electric charges can be supplied to the source line (pixel) of the electro-optical panel at high speed, and the voltage of the source line can be changed sharply. On the other hand, in the period after the switching timing, the resistance value between the capacitance of the data line and the source line of the electro-optical panel and the output node of the amplifier circuit becomes high, and the stability of the voltage (data voltage) output by the amplifier circuit is improved. Can be secured. Further, if the voltage of the data voltage output terminal overshoots the target voltage, it takes extra time for the amplifier circuit to converge the overshooted voltage to the target voltage. According to another aspect of the present invention, it is possible to prevent the voltage of the data voltage output terminal from overshooting the target voltage, so that the voltage can be converged to the target voltage in a short time. As described above, both high-speed writing to the pixel and stability of the data voltage can be realized.

Still another aspect of the present invention relates to an electro-optical device including the display driver according to any one of the above, and an electro-optical panel driven by the display driver.

Still another aspect of the present invention relates to an electronic device including the display driver according to any one of the above.

An example of the waveform of the voltage at the data voltage output terminal when a high slew rate amplifier circuit is used and the resistance from the output of the amplifier circuit to the pixel is low. An example of the waveform of the enable signal and the voltage of the data voltage output terminal when sampling the data voltage on the source line of the electro-optical panel. 6 is a configuration example of a display driver of the present embodiment. The figure explaining operation|movement of the display driver of this embodiment. Waveform example when the switching timing is set before the voltage of the data voltage output terminal reaches the target voltage. Waveform example when the switching timing is set after the voltage of the data voltage output terminal reaches the target voltage. The 1st detailed structural example of a variable resistance circuit and a resistance control circuit. A configuration example of a display driver including a noise compensation circuit. 6 is a timing chart illustrating the operation of a display driver including a noise compensation circuit. The 2nd detailed example of composition of a variable resistance circuit and a resistance control circuit. 6 is a configuration example of a variable resistance element in the case of an MR element. A detailed configuration example of a ladder resistance circuit, a D/A conversion circuit, and an amplification circuit. An example of composition of an electro-optical device. The structural example of an electronic device.

Hereinafter, preferred embodiments of the present invention will be described in detail. Note that the present embodiment described below does not unreasonably limit the content of the present invention described in the claims, and all the configurations described in the present embodiment are essential as a solution means of the present invention. Not necessarily.

1. Display Driver As described above, when the speed of the amplifier circuit is increased to enable high-speed writing to the pixel, the stability of the data voltage is affected by the high-speed response of the amplifier circuit. This point will be described with reference to FIGS. 1 and 2.

In order to enable high-speed writing to the pixel, it is necessary to increase the speed of the amplifier circuit and reduce the resistance value of the resistance from the output of the amplifier circuit to the pixel (source line) as much as possible. For example, a resistance provided between the output node of the amplifier circuit and the data voltage output terminal in the display driver, or a resistance for electrostatic protection provided in the data line (wiring connected to the data voltage input terminal) of the electro-optical panel. Is. By reducing the resistance value of these resistors, the charge transfer from the output of the amplifier circuit to the pixel is accelerated, and the writing to the pixel is accelerated.

FIG. 1 is a waveform example of the voltage of the data voltage output terminal when a high slew rate amplifier circuit is used and the resistance from the output of the amplifier circuit to the pixel is low. In FIG. 1, the amplifier circuit drives the voltage of the data voltage output terminal from the voltage VTA to the voltage VTB (target voltage) in the driving period TDR. The driving period TDR is a period in which the amplifier circuit drives one pixel.

As shown in FIG. 1, by using a high slew rate amplifier circuit and setting the resistance from the output of the amplifier circuit to the pixel to a low resistance value, the voltage of the data voltage output terminal sharply increases from VTA to VTB. Change. However, by overshooting the target voltage VTB and applying feedback to the overshot voltage, the voltage at the data voltage output terminal oscillates and gradually approaches the target voltage VTB. Such vibration occurs because the capacitance of the data line and the source line (wiring connected to the pixel) of the electro-optical panel is seen from the output of the amplifier circuit through the low resistance value resistor. This is probably because the stability of the feedback loop is reduced.

When the vibration as shown in FIG. 1 occurs, an error occurs between the voltage of the data voltage output terminal at the end of the driving period TDR and the target voltage VTB. Since the waveform of vibration depends on the characteristics of the amplifier circuit, the waveform of vibration also varies due to variations in the characteristics of the amplifier circuit. Therefore, the error of the write voltage is different in each of the plurality of amplifier circuits included in the display driver, and the display quality is deteriorated. For example, unevenness (belt unevenness) such as vertical stripes occurs in the display image.

FIG. 2 shows an example of the waveform of the enable signal and the waveform of the voltage of the data voltage output terminal when sampling the data voltage on the source line of the electro-optical panel. Similar to FIG. 1, an example of a waveform when a high slew rate amplifier circuit is used and the resistance from the output of the amplifier circuit to the pixel is made low is shown.

In the electro-optical panel, a switch for sampling the data voltage on the source line is provided between the data voltage input terminal (data line) and the source line. The enable signal is a signal for controlling the switch to be turned on or off. If the switch is an N-type transistor, the switch is turned off when the enable signal changes from the high level to the low level, and the voltage of the source line is fixed.

Since there is a parasitic capacitance between the gate of the N-type transistor of the switch and the data line, when the enable signal starts changing from the high level to the low level, the voltage of the data line drops due to the capacitive coupling. Then, due to this voltage drop, the voltage of the output node of the amplifier circuit drops. Since the amplifier circuit of the display driver tries to output a constant data voltage (target voltage), it tries to increase the voltage of the lowered output node. Such feedback causes oscillation (noise) in the voltage of the output node, which propagates to the source line. An example of the driving period of the pixel is 30 to 40 ns, while the transition time of the signal level of the enable signal is about 10 ns. Since a high-speed amplifier circuit capable of writing data to a pixel in a driving period of 30 to 40 ns is used, the amplifier circuit responds to the voltage change of the enable signal, and the above-mentioned voltage oscillation occurs. ..

The switch of the electro-optical panel is turned off when the voltage of the enable signal becomes lower than the threshold voltage Vth of the N-type transistor. Therefore, if the voltage of the source line at that moment deviates from the target voltage, the source line An error occurs in the voltage sampled at. Since the waveform of this vibration depends on the characteristics of the amplifier circuit, the waveform of the vibration also varies due to variations in the characteristics of the amplifier circuit. Therefore, the error of the write voltage is different in each of the plurality of amplifier circuits included in the display driver, and the display quality is deteriorated. For example, unevenness (belt unevenness) such as vertical stripes occurs in the display image.

As described above, by speeding up the writing of pixels, the stability of the voltage output from the amplifier circuit deteriorates, and the display quality deteriorates. In order to suppress this, a method of increasing the resistance value of a resistor provided between the output node of the amplifier circuit and the data voltage output terminal can be considered. However, since the charge transfer from the output of the amplifier circuit to the pixel is delayed, the writing to the pixel cannot be completed within the driving time.

FIG. 3 is a configuration example of the display driver 100 of the present embodiment that can solve the above problems. The display driver 100 includes a drive circuit 190, a resistance control circuit 194, and a data voltage output terminal TQ. Further, the display driver 100 can include a ladder resistance circuit 50 (gray scale voltage generation circuit in a broad sense), a D/A conversion circuit 10, and a memory 55 (storage unit). The display driver 100 is realized by, for example, an integrated circuit device (IC). Note that the present embodiment is not limited to the configuration of FIG. 3, and various modifications such as omission of a part of the components (for example, a ladder resistance circuit) or addition of other components are possible. is there.

The ladder resistance circuit 50 resistance-divides two voltages (for example, a high-potential-side power supply voltage and a low-potential-side power supply voltage) with a ladder resistance, and 128 pieces corresponding to the gradation value of the display data GRD [6:0]. To generate a voltage (a plurality of voltages) of.

The D/A conversion circuit 10 converts the display data GRD[6:0] into the gradation voltage VDA. That is, the D/A conversion circuit 10 selects a voltage corresponding to the display data GRD[6:0] from the 128 voltages generated by the ladder resistance circuit 50, and outputs the selected voltage as the gradation voltage VDA. .. For example, the gradation voltage VDA is a linear voltage with respect to the gradation value. Alternatively, the gradation voltage VDA may be a voltage having a given gamma characteristic with respect to the gradation value.

The drive circuit 190 outputs a data voltage from the data voltage output terminal TQ to drive the data line of the electro-optical panel. The drive circuit 190 includes an amplifier circuit 20 that outputs a data voltage, and a variable resistance circuit 192 that is provided between the output node NQ of the amplifier circuit 20 and the data voltage output terminal TQ.

Specifically, the variable resistance circuit 192 is a circuit whose resistance value is variably controlled. One end of the variable resistance circuit 192 is connected to the output node NQ of the amplifier circuit 20, and the other end is connected to the node NT connected to the data voltage output terminal TQ. The variable resistance circuit 192 includes switches SAA1 and SAA2 (for example, transistors) whose one ends are connected to the node NQ, switches SAB1 and SAB2 (for example, transistors) whose one ends are connected to the node NT, and resistors RA1 and RA2. One ends of the resistors RA1 and RA2 are connected to the other ends of the switches SAA1 and SAA2, respectively, and the other ends of the resistors RA1 and RA2 are connected to the other ends of the switches SAA1 and SAA2, respectively. The configuration of the variable resistance circuit 192 is not limited to this. For example, although the resistance value is discretely controlled in FIG. 3, the resistance value of the variable resistance circuit 192 may be continuously controlled.

The amplifier circuit 20 amplifies (or buffers) the gradation voltage VDA and outputs a voltage obtained by multiplying the gradation voltage VDA by a gain as a data voltage. The output voltage VQ of the amplifier circuit 20 and the voltage VT of the data voltage output terminal TQ (voltage of the node NT) are voltages that transiently change during the driving period, and VQ when the charge transfer through the variable resistance circuit 192 converges, VT becomes the same voltage, and VQ and VT become the target voltage. The target voltage is a data voltage corresponding to the display data GRD[6:0]. For example, when the amplifier circuit 20 is an inverting amplifier circuit with a gain of -1, the target voltage is -1xVDA with respect to the grayscale voltage VDA selected corresponding to the display data GRD[6:0].

The resistance control circuit 194 performs control to switch the resistance value of the variable resistance circuit 192 from the first resistance value to the second resistance value higher than the first resistance value at the drive timing switching timing. For example, the resistance control circuit 194 receives a signal or a clock signal that defines a drive period from the timing controller of the display driver 100 (for example, the control circuit 180 in FIG. 13). The resistance control circuit 194 controls the switching timing of the resistance value based on those signals, and controls the switches SAA1, SAB1, SAA2, SAB2 of the variable resistance circuit 192 to be turned on or off at the switching timing. The resistance control circuit 194 is realized by a logic circuit. The resistance control circuit 194 may be configured as an integrated logic circuit together with the timing controller.

The drive period is a period in which the drive circuit 190 (amplifier circuit 20) drives one pixel of the electro-optical panel. For example, it is a period in which the switch for sampling the data voltage on the source line connected to the pixel is on. Alternatively, the drive circuit 190 starts driving at the data voltage corresponding to the display data GRD[6:0] and then starts driving at the data voltage corresponding to the next display data GRD[6:0]. Until.

FIG. 4 is a diagram for explaining the operation of the display driver 100 of this embodiment. As shown in FIG. 4, in the driving period TDR1 (first driving period), the driving circuit 190 changes the data voltage VT1 (first data voltage) corresponding to the display data GRD1 (first display data) to the data voltage. Output to the output terminal TQ. In the driving period TDR2 (second driving period) next to the driving period TDR1, the data voltage VT2 (second data voltage) corresponding to the display data GRD2 (second display data) is output to the data voltage output terminal TQ. ..

Specifically, the D/A conversion circuit 80 latches the display data GRD[6:0]. For example, the driving period is defined by this latch timing. The display data GRD1 is latched at the start of the driving period TDR1 and the display data GRD2 is latched at the start of the driving period TDR2. The D/A conversion circuit 10 D/A converts the display data GRD1 in the driving period TDR1 and outputs the gradation voltage VDA1, and the amplification circuit 20 amplifies the gradation voltage VDA1 and outputs the data voltage VT1. Further, the D/A conversion circuit 10 D/A converts the display data GRD2 in the driving period TDR2 to output the gradation voltage VDA2, and the amplification circuit 20 amplifies the gradation voltage VDA2 and outputs the data voltage VT2. ..

In the driving period TDR2, the resistance control circuit 194 changes the resistance value of the variable resistance circuit 192 from the first resistance value at the switching timing ta2 that becomes slower as the difference DFB=|VT1-VT2| between the data voltage VT1 and the data voltage VT2 increases. Switch to the second resistance value.

For example, in the period TDA2 (first period) from the start of the driving period TDR2 to the switching timing ta2, the switches SAA1, SAB1, SAA2, SAB2 of the variable resistance circuit 192 are on, and the driving period TDR2 ends from the switching timing ta2. In the period TDB2 (second period) up to, the switches SAA1 and SAB1 are off, and the switches SAA2 and SAB2 are off. In this case, the first resistance value is RA1×RA2/(RA1+RA2), the second resistance value is RA2, and the second resistance value is higher than the first resistance value.

It is assumed that the data voltage is VT0 and DFA=|VT0−VTA1|<DFB in the drive period before the drive period TDR1. At this time, the period TDA2 of the driving period TDR2 is longer than the period TDA1 from the start of the driving period TDR1 to the switching timing ta1. As described above, the larger the voltage difference (change width) of the data voltage changed by the drive circuit 190 in the drive period, the later the switching timing becomes. Note that the switches SAA1, SAB1, SAA2, and SAB2 are on in the period TDA1, and the switches SAA1 and SAB1 are off and the switches SAA2 and SAB2 are off in the period TDB1 from the switching timing ta1 to the end of the driving period TDR1. ..

According to the above embodiment, the resistance value of the variable resistance circuit 192 is switched from the first resistance value to the second resistance value higher than the first resistance value at the switching timing ta2. As a result, the variable resistance circuit 192 is set to a relatively low first resistance value in the period TDA2 prior to the switching timing ta2, so that it is possible to rapidly supply charges to the source line (pixel) of the electro-optical panel. The voltage of the source line can be changed sharply. On the other hand, in the period TDB2 after the switching timing ta2, the variable resistance circuit 192 is set to the relatively high second resistance value. As a result, the resistance value between the capacitance of the data line and the source line of the electro-optical panel and the output node NQ of the amplifier circuit 20 becomes high, and the stability of the feedback loop of the amplifier circuit 20 can be secured. Further, even if the voltage VT of the data voltage output terminal TQ changes when the switch (switch for sampling the data voltage on the source line) of the electro-optical panel is turned off, the output node NQ of the amplifier circuit 20 and the data voltage Since the resistance value with the output terminal TQ is high, the change in the voltage VQ of the output node NQ is suppressed. As a result, even with the high slew rate amplifier circuit 20, it becomes difficult to respond to noise when the switch of the electro-optical panel is turned off, and the writing voltage to the pixel can be made highly accurate.

Also, by controlling the switching timing ta2 according to the difference between the data voltage VT1 in the driving period TDR1 and the data voltage VT2 in the driving period TDR2, the optimum switching timing can be realized. That is, at the start of the driving period, the difference between the output voltage VQ of the amplifier circuit 20 and the target voltage (VT2) is large, but the slope of the time change (time change rate) of the voltage VT at this time is It is determined by the slew rate. Therefore, the larger the data voltage difference DFB, the longer the time until the voltage VT becomes close to the target voltage. In the present embodiment, the larger the data voltage difference DFB, the later the timing ta2 at which the resistance value of the variable resistance circuit 192 is switched. As a result, the variable resistance circuit 192 can be switched to a high resistance value and the data voltage can be stabilized at the earliest possible timing while ensuring the maximum period TDA2 for driving the pixel at high speed.

Further, in the present embodiment, the resistance control circuit 194 performs control such that the switching timing ta2 in the drive period TDR2 is delayed as the magnitude of the difference value between the display data GRD1 and the display data GRD2 increases.

The difference value is a difference value between the gradation value of the display data GRD1 and the gradation value of the display data GRD2. That is, a large difference value means a large gradation difference. For example, the resistance control circuit 194 includes an arithmetic circuit that calculates the difference value between the display data GRD1 and GRD2. Alternatively, an arithmetic circuit (not shown) provided outside the resistance control circuit 194 may calculate a difference value between the display data GRD1 and GRD2, and the difference value may be input to the resistance control circuit 194.

The larger the difference value between the display data GRD1 and the display data GRD2, the larger the difference between the data voltage VT1 corresponding to the display data GRD1 and the data voltage VT2 corresponding to the display data GRD2. Therefore, the switching timing ta2 in the driving period TDR2 is delayed as the difference value between the display data GRD1 and the display data GRD2 is larger, so that the switching timing becomes slower as the difference DFB between the data voltage VT1 and the data voltage VT2 is larger. Ta2 can be realized. As described above, the larger the data voltage difference DFB, the longer the time until the voltage VT becomes close to the target voltage. However, according to the present embodiment, the time until the voltage VT becomes close to the target voltage becomes longer. Accordingly, the switching timing ta2 can be delayed.

Further, in the present embodiment, the resistance control circuit 194 sets the switching timing ta2 corresponding to the difference value based on the table data that associates the difference value with the switching timing.

As shown in FIG. 3, the memory 55 stores table data 56 that associates the difference value of the display data with the switching timing. Then, the resistance control circuit 194 refers to the table data 56, reads the switching timing corresponding to the difference value between the display data GRD1 and GRD2, and sets the switching timing ta2. The switching timing stored as the table data 56 becomes slower as the difference value of the display data increases (the length of the period from the start of the driving period to the switching timing increases monotonically with respect to the difference value). For example, when designing the display driver 100, table data is determined by circuit simulation or the like. Alternatively, the time change of the voltage VT of the data voltage output terminal TQ is measured, and the table data is determined based on the result. Then, when the display driver 100 is manufactured, the table data is written in the memory 55. The memory 55 is, for example, a non-volatile memory.

Thus, by setting the switching timing ta2 based on the table data 56 that associates the difference value of the display data with the switching timing, the switching timing ta2 can be delayed as the magnitude of the difference value of the display data increases, and the difference It becomes possible to set the optimum switching timing ta2 for the value. That is, the time from the start of the driving period until the voltage VT of the data voltage output terminal TQ reaches near the target voltage is not necessarily linear with respect to the difference value of display data (difference in data voltage). By using the table data, the switching timing of the non-linear characteristic with respect to the difference value of the display data can be set, so that the period in which the pixel can be driven at high speed (the period in which the variable resistance circuit 192 has the first resistance value) is optimal. Can be converted.

Further, in the present embodiment, the resistance control circuit 194 changes the resistance value of the variable resistance circuit 192 to the first value at the switching timing ta2 before the voltage VT of the data voltage output terminal TQ reaches the data voltage VT2 that is the target voltage. The resistance value is switched to the second resistance value.

Before the voltage VT reaches the target voltage is before the voltage VT first reaches the target voltage. Taking the drive period TDR2 of FIG. 4 as an example, the voltage VT changes from VT1 to VT2 which is the target voltage. For example, the switching timing is set so that the voltage VT at the switching timing is VT1+(VT2-VT1)/2≦VT<VT2. Desirably, the switching timing is set such that the voltage VT at the switching timing is VT1+(VT2-VT1)×3/4≦VT<VT2.

If the voltage VT of the data voltage output terminal TQ overshoots the target voltage, it takes extra time for the amplifier circuit 20 to converge the overshooted voltage to the target voltage. According to this embodiment, it is possible to prevent the voltage VT of the data voltage output terminal TQ from overshooting the target voltage, so that the voltage VT can be converged to the target voltage in a short time. This point will be described with reference to FIGS.

FIG. 5 is a waveform example when the voltage VT is changed from VTA to VTB in the driving period TDR and the switching timing ta is set before the voltage VT reaches the target voltage (VTB). As shown in FIG. 5, the voltage VT sharply changes until the switching timing ta. Since the variable resistance circuit 192 switches to a high resistance value at the switching timing ta, the voltage division ratio between the variable resistance circuit 192 and the electrostatic protection resistance of the electro-optical panel changes, and the voltage VT drops temporarily. However, since the amplifier circuit 20 tries to change the voltage VT in the same direction as before the switching timing ta, the voltage VT smoothly approaches the target voltage after the switching timing ta.

FIG. 6 is a waveform example when the voltage VT is changed from VTA to VTB in the driving period TDR and the switching timing ta′ is set after the voltage VT reaches the target voltage (VTB). In this case, the voltage VT overshoots the target voltage (VTB) at the switching timing ta'. Therefore, after the switching timing ta′ at which the variable resistance circuit 192 switches to a high resistance value, the amplifier circuit 20 tries to pull back the overshoot, so that the voltage VT falls below the target voltage again and the voltage gradually approaches the target voltage. It will be. Therefore, as compared with the case of FIG. 5, the time during which the voltage VT gradually approaches the target voltage is delayed, and there is a possibility that the error in the writing voltage to the pixel becomes large.

As described above, by setting the switching timing before the voltage VT of the data voltage output terminal TQ overshoots the target voltage, the voltage VT can be converged to the target voltage in a short time.

Further, in the present embodiment, the ratio of the second resistance value to the first resistance value is 2 or more. More preferably, the ratio of the second resistance value to the first resistance value is 4 or more.

The load viewed from the amplifier circuit 20 is the resistance of the variable resistance circuit 192 and the capacitance of the data line and the source line of the electro-optical panel. Assuming that the electrostatic protection resistance of the electro-optical panel is sufficiently smaller than the second resistance value, when the ratio of the second resistance value to the first resistance value is 2 or more, the frequency characteristic of the load is at the switching timing. It will be more than doubled. If the ratio of the frequency characteristics is about 2 to 4 times, it is considered that the stability of the feedback loop of the amplifier circuit 20 can be ensured, so the ratio of the second resistance value to the first resistance value is about 2 to 4. That would be fine.

2. First Detailed Configuration Example of Variable Resistance Circuit and Resistance Control Circuit FIG. 7 is a first detailed configuration example of the variable resistance circuit 192 and the resistance control circuit 194. The variable resistance circuit 192 has switches SBA1 to SBA4, SBB1 to SBB4, and resistors RB1 to RB4. The resistance control circuit 194 has a timing control circuit 196 and a register 198. In FIG. 7, the same components as those already described are designated by the same reference numerals, and the description of the components will be appropriately omitted. Note that the present invention is not limited to the configuration of FIG. 7, and various modifications such as omitting a part of the components (for example, the switches SBA1 to SBA4 or the switches SBB1 to SBB4) or adding other components. Is possible.

The resistors RB1 to RB4 and the switches SBA1 to SBA4 and SBB1 to SBB4 are provided between the output node NQ of the amplifier circuit 20 and the data voltage output terminal TQ. Specifically, one ends of the switches SBA1 to SBA4 are connected to the output node NQ, and the other ends of the switches SBA1 to SBA4 are connected to one ends of the resistors RB1 to RB4. The other ends of the resistors RB1 to RB4 are connected to one ends of the switches SBB1 to SBB4. The other ends of the switches SBB1 to SBB4 are connected to the data voltage output terminal TQ (node NT). The switches SBA1 to SBA4 and SBB1 to SBB4 are, for example, transistors.

The number of resistors and switches included in the variable resistance circuit 192 is not limited to the above. That is, the variable resistance circuit 192 may include the first to nth resistors (n is an integer of 2 or more) and the first to nth switches. The above is an example of n=4. The first to nth switches correspond to the switches SBA1 to SBA4 or the switches SBB1 to SBB4. Only one of the switches SBA1 to SBA4 and the switches SBB1 to SBB4 may be provided. In that case, one of the provided switches corresponds to the first to nth switches.

The resistance control circuit 194 controls the resistance value of the variable resistance circuit 192 by controlling each of the switches SBA1 to SBA4 and SBB1 to SBB4 to be turned on or off. Specifically, the resistance control circuit 194 controls the switch control signal SS1 that controls the switches SBA1 and SBB1 to turn on or off, the switch control signal SS2 that controls the switches SBA2 and SBB2 to turn on or off, and the switches SBA3 and SBB3. A switch control signal SS3 for controlling on or off and a switch control signal SS4 for controlling the switches SBA4 and SBB4 on or off are output.

By doing so, the resistance control circuit 194 controls each of the switches SBA1 to SBA4 and SBB1 to SBB4 to be turned on or off, so that one or more of the resistors RB1 to RB4 output the amplifier circuit 20. It is connected between node NQ and data voltage output terminal TQ. As a result, the resistance value of the variable resistance circuit 192 can be switched from the first resistance to the second resistance at the switching timing of the driving period.

Further, in the present embodiment, the register 198 stores the first set value for setting the first resistance value and the second set value for setting the second resistance value. The first and second set values are set values that specify which of the resistors RB1 to RB4 is selected (connected between the output node NQ and the data voltage output terminal TQ). That is, it is a set value that specifies the signal levels of the switch control signals SS1 to SS4. First and second set values are written in the register 198 from outside the display driver 100 via an interface circuit (for example, the interface circuit 170 in FIG. 13). Alternatively, the first and second setting values may be stored in the memory 55, and the first and second setting values may be loaded into the register 198.

The resistance control circuit 194 switches the resistance value of the variable resistance circuit 192 from the first resistance value to the second resistance value based on the first set value and the second set value. Specifically, the timing control circuit 196 sets the switching timing corresponding to the difference between the display data GRD[6:0] (the difference between GRD1 and GRD2 in FIG. 4) with reference to the memory 55 (table data). , And outputs a timing control signal for instructing the switching timing. The register 198 outputs the switch control signals SS1 to SS4 based on the timing control signal and based on the first set value in the first period before the switching timing. As a result, the resistor designated by the first set value is selected from the resistors RB1 to RB4. The register 198 outputs the switch control signals SS1 to SS4 based on the timing control signal and based on the second set value in the second period after the switching timing. As a result, the resistor designated by the second set value is selected from the resistors RB1 to RB4.

With this configuration, the resistance value of the variable resistance circuit 192 can be switched from the first resistance value to the second resistance value at the switching timing based on the first and second setting values set in the register 198. become. Further, since the capacitance values of the data line and the source line are different depending on the type (for example, model) of the electro-optical panel, the optimum resistance value of the variable resistance circuit 192 for the driving speed of the pixel and the stability of the data voltage is the electro-optical panel It depends on the type. In the present embodiment, the first and second set values can be set in the register 198, so that the optimum first and second resistance values can be set according to the type of the electro-optical panel.

3. Noise Compensation Circuit FIG. 8 is a configuration example of the display driver 100 including a noise compensation circuit. The display driver 100 includes a noise compensation circuit 195, a drive circuit (amplifier circuit 20, variable resistance circuit 192), a resistance control circuit 194, and a memory 55. In FIG. 8, the same components as those already described are designated by the same reference numerals, and the description of the components will be appropriately omitted. Note that illustration of the ladder resistance circuit 50 and the D/A conversion circuit 10 is omitted in FIG.

The noise compensation circuit 195 is a circuit that performs a noise compensation operation that reduces switching noise of the switches SBA1 to SBA4 and SBB1 to SBB4, and is connected to the data voltage output terminal TQ. Specifically, each of the switches SBA1 to SBA4 and SBB1 to SBB4 is a transfer gate in which a P-type transistor and an N-type transistor are combined. If the P-type transistor and the N-type transistor have the same on-resistance, the P-type transistor has a larger gate size. Therefore, due to the capacitive coupling between the gate and the source and between the gate and the drain, the voltage of the source and the drain rises when the transfer gate is turned on and off, and the source voltage increases when the transfer gate is turned off. And the drain voltage drops. The voltage change due to this switching becomes noise of the voltage VT of the data voltage output terminal TQ. The noise compensating circuit 195 compensates (reduces) noise due to switching of the transfer gate by taking in and out charges in accordance with switching of the transfer gate.

As described above, the switching noise of the switches SBA1 to SBA4 and SBB1 to SBB4 becomes the noise of the voltage VT of the data voltage output terminal TQ, and thus the accuracy of the writing voltage to the pixel may be reduced. According to the present embodiment, the noise compensation circuit 195 compensates the switching noise of the switches SBA1 to SBA4 and SBB1 to SBB4, so that the noise is reduced and the writing voltage to the pixel can be made highly accurate.

More specifically, the noise compensation circuit 195 includes capacitors CN1 to CN4 and buffer circuits BF1 to BF4. One ends of the capacitors CN1 to CN4 are connected to the data voltage output terminal TQ (node NT), and the capacitors CN1 to CN4 have capacitance values corresponding to the sizes of the switches SBA1 to SBA4 and SBB1 to SBB4. The transistor sizes of the transfer gates forming the switches SBA1 to SBA4 and SBB1 to SBB4 differ depending on the resistance values of the resistors RB1 to RB4. That is, the larger the resistance value of the resistor, the larger the transistor size of the transfer gate connected to the resistor. The capacitance value of the capacitor CN1 corresponds to the transistor size of the switches SBA1 and SBB1, and is a capacitance value that can absorb the switching noise (charge) of the switches SBA1 and SBB1. Similarly, the capacitance values of the capacitors CN2, CN3, CN4 correspond to the transistor sizes of the switches SBA2, SBB2, the switches SBA3, SBB3, the switches SBA4, SBB4, respectively. For example, the capacitance values of the capacitors CN1 to CN4 are set by circuit simulation or the like.

The resistance control circuit 194 controls the voltage at the other end of each of the capacitors CN1 to CN4 according to whether each of the switches SBA1 to SBA4 and SBB1 to SBB4 is ON or OFF, thereby switching noise. To compensate. Specifically, the timing control circuit 196 of the resistance control circuit 194 switches the signal levels of the control signals SNC1 to SNC4 at the switching timing. The buffer circuits BF1 to BF4 buffer the control signals SNC1 to SNC4 and output them to the other ends of the capacitors CN1 to CN4. When the signal levels of the control signals SNC1 to SNC4 change, the voltages at the other ends of the capacitors CN1 to CN4 change, so that the charges move between the capacitors CN1 to CN4 and the node NT. Switching noise is compensated by this charge transfer.

FIG. 9 is a timing chart explaining the operation of the display driver 100 of FIG. FIG. 9 illustrates a case where the switches are turned on and off when the switch control signals SS1 to SS4 are at high level (active) and low level (inactive), respectively.

As shown in FIG. 9, in the period TDA (first period) before the switching timing of the driving period TDR, all the switches SBA1 to SBA4 and SBB1 to SBB4 are turned on and all the resistors RB1 to RB4 are selected. It In the period TDB (second period) after the switching timing of the driving period TDR, the switches SBA2 and SBB2 are turned on, the other switches are turned off, and the resistor RB2 is selected. Note that the resistance selection method is not limited to this, and the resistance value in the period TDB may be higher than the resistance value in the period TDA.

As shown in FIG. 9, when the switch control signals SS1 to SS4 change from low level to high level (when the corresponding switch changes from off to on), the control signals SNC1 to SNC4 change from low level to high level, respectively. .. When the switch is turned from OFF to ON, the voltage VT of the data voltage output terminal TQ decreases, so that the electric charges are supplied by increasing the voltage of the other ends of the capacitors CN1 to CN4 to cancel the noise of the voltage VT. On the other hand, when the switch control signals SS1 to SS4 change from high level to low level (when the corresponding switch changes from on to off), the control signals SNC1 to SNC4 change from high level to low level, respectively. When the switch is turned off, the voltage VT of the data voltage output terminal TQ rises, so that the voltage at the other ends of the capacitors CN1 to CN4 is lowered to absorb the charge and cancel the noise of the voltage VT.

According to this embodiment, one ends of the capacitors CN1 to CN4 having capacitance values corresponding to the sizes of the switches SBA1 to SBA4 and SBB1 to SBB4 are connected to the data voltage output terminal TQ, and the voltage of the other ends of the capacitors CN1 to CN4. Is controlled, the switching noise of the switches SBA1 to SBA4 and SBB1 to SBB4 can be compensated (reduced). That is, the larger the size of the switches SBA1 to SBA4 and SBB1 to SBB4, the larger the noise (charge) generated by the switching, but the noise (charge) can be absorbed by the capacitors CN1 to CN4 having the capacitance value corresponding to the size.

8 and 9, the case where the noise compensation circuit 195 includes four capacitors has been described, but the number of capacitors is not limited to this. That is, the capacitor may be provided corresponding to the resistance included in the variable resistance circuit 192. For example, one capacitor (first to nth capacitor) is provided for each of the first to nth resistors included in the variable resistance circuit 192. The corresponding capacitors may be provided only for some of the resistors included in the variable resistance circuit 192. For example, a capacitor may not be provided for a resistor having a small switch transistor size.

4. Second Detailed Configuration Example of Variable Resistance Circuit and Resistance Control Circuit FIG. 10 is a second detailed configuration example of the variable resistance circuit 192 and the resistance control circuit 194. The variable resistance circuit 192 includes a variable resistance element VRG (variable resistance circuit element, variable resistor). The resistance control circuit 194 includes a voltage generation circuit 193, a register 191, and a timing control circuit 196. In FIG. 10, the same components as the components already described are designated by the same reference numerals, and the description of the components will be appropriately omitted.

The variable resistance element VRG is a resistance element whose resistance value is variably controlled according to the control voltage VCNT. Specifically, the first terminal of the variable resistance element VRG is connected to the output node NQ of the amplifier circuit 20, and the second terminal is connected to the data voltage output terminal TQ. Then, the resistance value between the first terminal and the second terminal is controlled by the control voltage VCNT input to the third terminal of the variable resistance element VRG. For example, the variable resistance element VRG is an MR element (Magneto Resistive element) whose resistance value is variably controlled by a magnetic field (magnetic field). The MR element will be described later with reference to FIG.

The resistance control circuit 194 controls the resistance value of the variable resistance circuit 192 by changing the control voltage VCNT. Specifically, the timing control circuit 196 sets the switching timing corresponding to the difference between the display data GRD[6:0] (the difference between GRD1 and GRD2 in FIG. 4) with reference to the memory 55 (table data). , And outputs a timing control signal for instructing the switching timing. The register 191 outputs the first voltage setting value based on the timing control signal and based on the first setting value indicating the first resistance value in the first period before the switching timing. The voltage generation circuit 193 outputs the control voltage VCNT corresponding to the first voltage setting value, and the variable resistance element VRG is set to the first resistance value. Based on the timing control signal, the register 191 outputs the second voltage setting value based on the second setting value indicating the second resistance value during the period after the switching timing (second period). The voltage generation circuit 193 outputs the control voltage VCNT corresponding to the second voltage setting value, and the variable resistance element VRG is set to the second resistance value. For example, the voltage generation circuit 193 is composed of a regulator and a D/A conversion circuit, and the first and second voltage setting values are setting values for setting the output voltage of the regulator or input data of the D/A conversion circuit. ..

FIG. 11 is a configuration example of the variable resistance element VRG in the case of an MR element. In FIG. 11, x, y, and z are directions orthogonal to each other. As shown in FIG. 11, the diffusion layer ADF is formed on the substrate (semiconductor substrate) of the display driver 100, the wiring LN1 (wiring of the metal wiring layer) is connected to one end of the diffusion layer ADF, and the wiring LN2 ( The wiring of the metal wiring layer) is connected. For example, the wiring LN1 corresponds to the output node NQ of the amplifier circuit 20, and the wiring LN2 corresponds to the node NT connected to the data voltage output terminal TQ. The coil CI is provided on the diffusion layer ADF. The coil CI is formed by wiring of a metal wiring layer, for example. The coil CI is connected to the output of the voltage generation circuit 193 via a resistor, the control voltage VCNT is voltage-current converted by the resistor, and a current corresponding to the control voltage VCNT flows through the coil CI. The current causes the coil CI to generate a magnetic field. For example, when the direction of the current flowing through the diffusion layer ADF is the x direction in FIG. 11 and the direction of the magnetic field generated by the coil CI is the z direction, the positive charge of the current receives a force in the y direction. This force increases as the magnetic field (control voltage VCNT) increases. When the positive charge of the current receives a force in the y direction, the length of the path through which the current flows through the diffusion layer ADF becomes longer, and the resistance value of the diffusion layer ADF appears to be substantially higher. In this way, the resistance value of the MR element is controlled by the control voltage VCNT.

According to the above embodiment, the resistance control circuit 194 changes the control voltage VCNT, so that the resistance value of the variable resistance element VRG (variable resistance circuit 192) can be controlled. By setting the control voltage VCNT to a voltage corresponding to the first and second resistance values, the resistance value of the variable resistance element VRG can be switched from the first resistance value to the second resistance value at the switching timing. ..

5. Ladder Resistance Circuit, D/A Conversion Circuit, Amplification Circuit FIG. 12 is a detailed configuration example of the ladder resistance circuit 50, the D/A conversion circuit 10, and the amplification circuit 20. Note that, although the case where the amplifier circuit 20 is an inverting amplifier circuit that performs feedback with a resistor is described as an example in FIG. 12, the configuration of the amplifier circuit 20 is not limited to this. For example, the amplifier circuit 20 may be an inverting amplifier circuit that performs feedback with a capacitor, or may be a voltage follower circuit or a normal amplifier circuit.

The ladder resistance circuit 50 includes resistors RV1 to RV129 connected in series. The high-potential-side power supply voltage VRH is input to one end of the resistors RV1 to RV129 connected in series on the resistance RV1 side, and the low-potential-side power supply voltage VRL is input to the other end of the resistance RV129 side. The voltages VP1 to VP64 and VM1 to VM64 are output from the nodes (tap) between the resistors of the ladder resistance circuit 50. For example, the resistors RV2 to RV128 have the same resistance value. Note that the present invention is not limited to this, and for example, the resistors RV2 to RV65 have a resistance value corresponding to the gamma characteristic of negative polarity driving, and the resistors RV66 to RV128 have a resistance value corresponding to the gamma characteristic of positive polarity driving. Good.

The D/A conversion circuit 10 converts the display data GRD[6:0] into the gradation voltage VDA. That is, the D/A conversion circuit 10 selects a voltage corresponding to the display data GRD [6:0] from the plurality of voltages VP1 to VP64 and VM1 to VM64, and outputs the selected voltage as the gradation voltage VDA. Specifically, when GRD[6:0]=0000000, 00000001,..., 0111111, the negative polarity driving voltages VM64, VM63,..., VM1 are output as the gradation voltage VDA, respectively. In the case of GRD[6:0]=1000000, 1000001,..., 1111111, the positive drive voltages VP1, VP2,..., VP64 are output as the grayscale voltage VDA, respectively. In addition, GRD [6:0] is represented here by a binary number. In polarity inversion drive in which the drive polarity is inverted for each pixel, line, or frame, voltages VP1 to VP64 for positive polarity drive are selected for positive polarity drive, and voltages VM1 to VM64 for negative polarity drive are selected for negative polarity drive. Is selected.

The amplifier circuit 20 has an operational amplifier OPA (op amp), a resistor R1 (input resistor, first resistor), and a resistor R2 (feedback resistor, second resistor). The reference voltage VC is input to the non-inverting input terminal (positive electrode terminal, non-inverting input node NIP) of the operational amplifier OPA. The resistor R1 is provided between the input node NIA to which the gray scale voltage VDA is input and the inverting input terminal (negative terminal, inverting input node NIM) of the operational amplifier OPA. The resistor R2 is provided between the output terminal of the operational amplifier OPA (the output node NQ of the amplifier circuit 20) and the inverting input terminal of the operational amplifier OPA. When the resistance values of the resistors R1 and R2 are r1 and r2, the amplifier circuit 20 inverts and amplifies the gradation voltage VDA with a gain (−r2/r1) and outputs an output voltage VQ (data voltage). For example, VP64<VP63<... <VP1=VC<VM1<VM2<... <VM64. The negative drive voltages VM1 to VM64 become negative data voltages lower than the reference voltage VC by inverting amplification, and the positive drive voltages VP1 to VP64 become positive data voltages higher than the reference voltage VC by inverting amplification. Becomes

According to the above-described embodiment, by adopting the inverting amplifier circuit, the operating point of the differential pair of the operational amplifier OPA is limited to the reference voltage VC (voltage near the reference voltage VC). As a result, it is not necessary to secure the sensitivity (gain) of the operational amplifier OPA in a wide range of input voltage, and the operational amplifier OPA can be made highly sensitive (gain). Further, in the inverting amplifier circuit, since the output phase is rotated by 180 degrees with respect to the input, the band in which the phase margin can be secured is widened, and the frequency response characteristic can be improved as compared with the case where the voltage follower circuit is used for the output of the data voltage. (Broadband can be widened). Such high sensitivity and wide band are advantageous for high-speed writing, but the response to noise as described in FIG. 2 becomes a problem. In this regard, according to the method of switching the resistance value of the variable resistance circuit 192 described with reference to FIG. 3 and the like, by switching the variable resistance circuit 192 to a high resistance value (second resistance value) after the switching timing, the response to noise is increased. Can be suppressed (writing error to pixels can be reduced).

6. Electro-Optical Device FIG. 13 is a configuration example of an electro-optical device 400 including the display driver 100 of this embodiment. The electro-optical device 400 (display device) includes a display driver 100 and an electro-optical panel 200 (display panel). Note that the case where the display driver 100 performs phase expansion drive will be described below as an example, but the application target of the present invention is not limited to this, and can be applied to, for example, multiplex drive (demultiplex drive).

The electro-optical panel 200 includes a pixel array 210 and a sample hold circuit 220 (switch circuit). The electro-optical panel 200 is, for example, a liquid crystal display panel, an EL (Electro Luminescence) display panel, or the like.

The pixel array 210 has a plurality of pixels arranged in an array (matrix). In the phase expansion driving, the source lines of the pixel array 210 are sequentially driven by eight lines (k lines in a broad sense, k is an integer of 2 or more). Specifically, the sample hold circuit 220 is a circuit that samples and holds the data voltages VT1 to VT8 from the display driver 100 on the source line of the pixel array 210. Specifically, the data voltages VT1 to VT8 are input to the first to eighth data lines of the electro-optical panel 200. It is assumed that the pixel array 210 has, for example, first to 640th source lines. The sample hold circuit 220 connects the first to eighth data lines and the first to eighth source lines in the first period, and in the next second period, the first to eighth data lines and the ninth line. To 16th source lines are connected, and in the same manner, the 1st to 8th data lines and the 633rd to 640th source lines are connected in the 80th period. Such an operation is performed in each horizontal scanning period.

The display driver 100 includes a ladder resistance circuit 50, a D/A conversion unit 110 (D/A conversion circuit), a drive unit 120 (drive circuit), a voltage generation circuit 150, a storage unit 160 (memory), an interface circuit 170, a control circuit. Includes 180 (controller).

The interface circuit 170 performs communication between the display driver 100 and an external processing device (for example, the processing unit 310 in FIG. 14). For example, a clock signal, a timing control signal, and display data are input to the control circuit 180 from an external processing device via the interface circuit 170.

The control circuit 180 controls each part of the display driver 100 and each part of the electro-optical panel 200 based on the clock signal, the timing control signal, and the display data input via the interface circuit 170. For example, the control circuit 180 controls display timing such as selection of horizontal scanning lines of the pixel array 210, vertical synchronization control, control of phase expansion drive (first to 80th periods described above), and D The A/A converter 110 and the driver 120 are controlled.

The voltage generation circuit 150 generates various voltages and outputs them to the drive unit 120 and the D/A conversion unit 110. For example, the voltage generation circuit 150 generates power for the D/A conversion unit 110 and the drive unit 120. The voltage generation circuit 150 is composed of, for example, a regulator.

The D/A conversion unit 110 includes D/A conversion circuits 11-18. Each of the D/A conversion circuits 11 to 18 has the same configuration as the D/A conversion circuit 10 described with reference to FIG. The drive unit 120 includes drive circuits 21 to 28 and resistance control circuits 31 to 38. Each of the drive circuits 21 to 28 has the same configuration as the drive circuit 190 described with reference to FIG. Each of the resistance control circuits 31 to 38 has the same configuration as the resistance control circuit 194 described with reference to FIG. The resistance control circuits 31 to 38 may be included in the control circuit 180. The D/A conversion circuits 11 to 18 D/A convert the display data from the control circuit 180 and output the D/A converted voltage to the drive circuits 21 to 28. The drive circuits 21 to 28 amplify the voltages from the D/A conversion circuits 11 to 18 and output the data voltages VT1 to VT8 to the electro-optical panel 200.

The storage unit 160 stores various data (for example, setting data) used for controlling the display driver 100. The memory 55 described with reference to FIG. 3 and the like may be included in the storage unit 160. For example, the storage unit 160 is composed of a non-volatile memory or a RAM (SRAM, DRAM, etc.).

7. Electronic Device FIG. 14 is a configuration example of an electronic device 300 including the display driver 100 of the present embodiment. Specific examples of the electronic device 300 include various types of display devices such as a projector, a head mounted display, a portable information terminal, an in-vehicle device (for example, a meter panel, a car navigation system, etc.), a portable game terminal, and an information processing device. Can be assumed to be electronic devices.

The electronic device 300 includes a processing unit 310 (for example, a processor such as a CPU, a display controller, or an ASIC), a storage unit 320 (for example, a memory, a hard disk, etc.), an operation unit 330 (an operation device), an interface unit 340 (an interface circuit, Interface device), a display driver 100, and an electro-optical panel 200.

The operation unit 330 is a user interface that receives various operations from the user. For example, a button, a mouse, a keyboard, a touch panel mounted on the electro-optical panel 200, or the like. The interface unit 340 is a data interface that inputs and outputs image data and control data. For example, it is a wired communication interface such as USB or a wireless communication interface such as a wireless LAN. The storage unit 320 stores the data input from the interface unit 340. Alternatively, the storage unit 320 functions as a working memory of the processing unit 310. The processing unit 310 processes the display data input from the interface unit 340 or stored in the storage unit 320 and transfers the display data to the display driver 100. The display driver 100 causes the electro-optical panel 200 to display an image based on the display data transferred from the processing unit 310.

For example, when the electronic device 300 is a projector, the electronic device 300 further includes a light source and an optical device (eg, lens, prism, mirror, etc.). When the electro-optical panel 200 is a transmissive type, the optical device causes the light from the light source to enter the electro-optical panel 200 and causes the light transmitted through the electro-optical panel 200 to be projected on the screen (display unit). When the electro-optical panel 200 is a reflection type, the optical device causes the light from the light source to enter the electro-optical panel 200 and causes the light reflected from the electro-optical panel 200 to be projected on the screen (display unit).

Although the present embodiment has been described in detail as described above, it will be easily understood by those skilled in the art that many modifications can be made without departing from the novel matters and effects of the present invention. Therefore, all such modifications are included in the scope of the present invention. For example, a term described in the specification or the drawings at least once together with a different term having a broader meaning or the same meaning can be replaced with the different term in any place in the specification or the drawing. Further, all combinations of the present embodiment and modifications are also included in the scope of the present invention. Further, the configurations and operations of the display driver, the electro-optical panel, the electro-optical device, and the electronic device are not limited to those described in this embodiment, and various modifications can be made.

10... D/A conversion circuit, 11-18... D/A conversion circuit, 20... Amplification circuit, 21-28... Drive circuit, 31-38... Resistance control circuit, 50... Ladder resistance circuit, 55... Memory, 56... Table data, 80... D/A conversion circuit, 100... Display driver, 110... D/A conversion unit, 120... Driving unit, 150... Voltage generation circuit, 160... Storage unit, 170... Interface circuit, 180... Control circuit, 190... Driving circuit, 191... Register, 192... Variable resistance circuit, 193... Voltage generating circuit, 194... Resistance control circuit, 195... Noise compensation circuit, 196... Timing control circuit, 198... Register, 200... Electro-optical panel, 210 ... Pixel array, 220... Sample and hold circuit, 300... Electronic equipment, 310... Processing section, 320... Storage section, 330... Operation section, 340... Interface section, 400... Electro-optical device, BF1 to BF4... Buffer circuit, CN1 to CN1. CN4... Capacitor, GRD[6:0]... Display data, GRD1, GRD2... Display data, OPA... Operational amplifier, R1, R2... Resistor, RA1, RA2... Resistor, RB1 to RB4... Resistor, SAA1, SAA2, SAB1, SAB2... switch, SBA1 to SBA4, SBB1 to SBB4... switch, SNC1 to SNC4... control signal, SS1 to SS4... switch control signal, TDA, TDB... period, TDR... drive period, TQ... data voltage output terminal, VC... reference Voltage, VCNT... Control voltage, VDA... Grayscale voltage, VRG... Variable resistance element, VT... Data voltage output terminal voltage, VTB... Voltage (target voltage), ta... Switching timing

Claims (10)

A data voltage output terminal,
An amplifier circuit that outputs a data voltage, and a variable resistance circuit that is provided between the output node of the amplifier circuit and the data voltage output terminal are provided, and the data voltage is output from the data voltage output terminal to generate an electric signal. A drive circuit for driving the data line of the optical panel,
A resistance control circuit that performs control to switch the resistance value of the variable resistance circuit from a first resistance value to a second resistance value higher than the first resistance value at a switching timing of a driving period;
A noise compensation circuit connected to the data voltage output terminal,
Including
The drive circuit is
In the first driving period, the first data voltage corresponding to the first display data is output to the data voltage output terminal,
In a second driving period subsequent to the first driving period, a second data voltage corresponding to second display data is output to the data voltage output terminal,
The resistance control circuit,
In the second driving period, the resistance value of the variable resistance circuit is changed from the first resistance value to the second resistance value at the switching timing which becomes slower as the difference between the first data voltage and the second data voltage becomes larger. switching of the resistance value,
The variable resistance circuit,
A first to nth resistor (n is an integer of 2 or more) and a first to nth switch provided between the output node of the amplifier circuit and the data voltage output terminal,
The noise compensation circuit is
One end is connected to the data voltage output terminal, and includes first to nth capacitors having capacitance values corresponding to sizes of the first to nth switches,
The resistance control circuit,
The resistance value of the variable resistance circuit is controlled by controlling each of the first to nth switches to be turned on or off,
By controlling the voltage of the other end of each capacitor of the first to nth capacitors according to whether each switch of the first to nth switches is on or off, the first to nth switches are controlled. A display driver, which compensates switching noise of the n-th switch . In claim 1,
The resistance control circuit,
A display driver, wherein control is performed such that the switching timing is delayed as the magnitude of the difference value between the first display data and the second display data increases. In claim 2,
The resistance control circuit,
A display driver, wherein the switching timing corresponding to the difference value is set based on table data that associates the difference value with the switching timing. In any one of Claim 1 thru|or 3,
The resistance control circuit,
Switching the resistance value of the variable resistance circuit from the first resistance value to the second resistance value at the switching timing before the voltage of the data voltage output terminal reaches the data voltage which is the target voltage. Characteristic display driver. In any one of Claim 1 thru|or 4,
The variable resistance circuit,
A variable resistance element whose resistance value is variably controlled according to a control voltage,
The resistance control circuit,
A display driver, wherein the resistance value of the variable resistance circuit is controlled by changing the control voltage. In any one of Claim 1 thru|or 5 ,
A register for storing a first set value for setting the first resistance value and a second set value for setting the second resistance value;
The resistance control circuit,
A display driver, wherein the resistance value of the variable resistance circuit is switched from the first resistance value to the second resistance value based on the first set value and the second set value. In any one of Claim 1 thru|or 6 ,
A display driver, wherein a ratio of the second resistance value to the first resistance value is 2 or more. In any one of Claim 1 thru|or 7 ,
The amplifier circuit is
An operational amplifier whose reference voltage is input to the non-inverting input terminal,
An input resistor provided between the input node of the amplifier circuit and the inverting input terminal of the operational amplifier;
A feedback resistor provided between the output terminal of the operational amplifier and the inverting input terminal;
Display driver characterized by having. A display driver according to any one of claims 1 to 8 ,
An electro-optical panel driven by the display driver,
An electro-optical device comprising: An electronic apparatus comprising the display driver according to any one of claims 1 to 8.

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