JP6390078B2 - Data line driver, semiconductor integrated circuit device, and electronic device - Google Patents

Description

  The present invention relates to a data line driver for driving data lines of a display panel such as an LCD (Liquid Crystal Display) panel. Furthermore, the present invention relates to a semiconductor integrated circuit device incorporating such a data line driver, an electronic device using a display panel driving circuit including the data line driver, and the like.

  For example, an LCD panel using TFTs (thin film transistors) made of HTPS (high temperature polysilicon) is required to drive a data line at a very high speed as well as having multiple gradations (high accuracy). In particular, when the pixels for one line of the LCD panel are sequentially driven by a limited number of gradation voltage generation circuits included in the data line driver, gradation voltage generation is performed in response to changes in image data. The gradation voltage output from the circuit must be raised or lowered in a short time.

  Therefore, conventionally, in the operational amplifiers used in the gradation voltage generation circuit, the operational amplifier capacity is increased by increasing the steady current flowing in the differential stage or increasing the output transistor capacity. ing. However, if the steady current is increased in the differential stage or the output stage, the power consumption increases.

  Alternatively, a data line can be driven at high speed by connecting in parallel a high-precision amplifier that determines the final gradation voltage and a high-drive amplifier that quickly changes the gradation voltage when the gradation changes. However, since the high drive amplifier has a high drive capability, there is a problem that it often oscillates due to a load.

  As a related technique, Patent Document 1 discloses an operational amplifier capable of increasing a slew rate without increasing a steady driving current, and a liquid crystal driving device using the operational amplifier. This operational amplifier uses at least one differential input unit that generates a voltage signal corresponding to a potential difference between a positive phase input signal and a negative phase input signal using a differential pair including a pair of transistors, and is generated by the differential input unit. An output unit that generates and outputs an output signal of a logic level corresponding to the voltage signal to be output, and at least one auxiliary that generates an auxiliary current by detecting that the positive phase input signal or the negative phase input signal has fluctuated sharply A current generation unit; and a drive current generation unit that generates a drive current of the differential input unit by adding a predetermined reference current and an auxiliary current.

  However, according to the operational amplifier of Patent Document 1, the slew rate is increased by increasing the drive current of the differential input unit after detecting that the positive phase input signal or the negative phase input signal fluctuates sharply. A time difference occurs between the fluctuation of the input signal and the increase in the slew rate, and the response is delayed.

JP 2011-172203 A (paragraphs 0011-0013, FIG. 1)

  Accordingly, in view of the above points, one of the objects of the present invention is to improve the rise and fall characteristics of the gradation voltage when the image data changes in the data line driver, thereby making the data lines of the display panel faster. It is to be able to drive with.

  In order to solve the above problems, a data line driver according to one aspect of the present invention is a data line driver that drives a data line of a display panel by generating a gradation voltage based on image data, The first and second data storage units connected in series for sequentially storing successively supplied image data, and the image data stored in the first data storage unit are D / A (digital DAC (digital / analog converter) that outputs an analog image signal after conversion, an image signal output from the DAC is amplified to generate an output signal, and the output signal is output to the gradation voltage output terminal. An amplifier to be supplied, a subtractor for calculating a difference value between image data stored in the first data storage unit and image data stored in the second data storage unit, and a subtractor Therefore comprising a timing pulse generator for generating timing pulses based on the difference value calculated, and a charge supply circuit supplies charges to the gradation voltage output terminal in accordance with a timing pulse timing pulse generator occurs.

  According to one aspect of the present invention, a difference value between two successive image data is digitally calculated, and the charge supply circuit supplies charges to the gradation voltage output terminal based on the difference value. In addition, a high-speed charge supply operation is possible. Therefore, the rising and falling characteristics of the gradation voltage when the image data changes can be improved, and the data lines of the display panel can be driven at high speed. On the other hand, the amplifier can maintain an accurate gradation voltage based on an analog image signal obtained by A / D converting image data.

  Here, the data line driver stores an operation table in which pulse width data representing the pulse width of the timing pulse is set corresponding to a plurality of difference values, and the pulse width corresponding to the difference value calculated by the subtractor An operation table storage unit for outputting data may be further provided, and the timing pulse generator may generate a timing pulse having a pulse width set based on the pulse width data output from the operation table storage unit. . Thereby, the timing pulse generator can generate a timing pulse having a pulse width corresponding to the difference value calculated by the subtractor.

  In that case, the charge supply circuit includes a plurality of P-channel transistors connected in parallel between the high-potential power supply potential and the grayscale voltage output terminal, and the grayscale voltage output terminal and the low-potential power supply potential. A plurality of N-channel transistors connected in parallel with each other, the data line driver corresponding to the plurality of difference values, and the selection information of the transistors selected when the charge supply circuit operates is set to the second And a second operation table storage unit for outputting a signal representing selection information corresponding to the difference value calculated by the subtractor, and a second operation according to the timing pulse generated by the timing pulse generator. And a transistor drive circuit for turning on at least one transistor selected by a signal output from the table storage unit. . As a result, at least one transistor having an appropriate driving capability is selected, so that the lack of accuracy of the pulse width of the timing pulse can be compensated.

  Further, the data line driver stores a third operation table in which selection information of transistors to be additionally selected when the charge supply circuit operates corresponding to a plurality of image data values is stored. A third operation table storage unit that outputs a signal representing selection information corresponding to image data stored in one data storage unit; and at least one transistor is configured by a signal output from the third operation table storage unit. An additional transistor driving circuit that turns on the at least one transistor according to a timing pulse generated by the timing pulse generator when selected may be further included. As a result, when the voltage between the source and drain of the transistor becomes small, it is possible to compensate for the lack of driving capability of the transistor.

  Alternatively, the data line driver further includes a pulse width setting unit that sets a pulse width of the timing pulse based on the difference value calculated by the subtractor, and the timing pulse generator is set by the pulse width setting unit. A timing pulse having a pulse width may be generated. Thereby, the timing pulse generator can generate a timing pulse having a pulse width corresponding to the difference value calculated by the subtractor.

  In that case, the charge supply circuit includes a plurality of P-channel transistors connected in parallel between the high-potential power supply potential and the grayscale voltage output terminal, and the grayscale voltage output terminal and the low-potential power supply potential. A plurality of N-channel transistors connected in parallel, and a signal representing selection information of transistors selected when the data line driver operates the charge supply circuit based on a difference value calculated by the subtractor And a transistor drive circuit that turns on at least one transistor selected by a signal output from the transistor setting unit in accordance with a timing pulse generated by the timing pulse generator. As a result, at least one transistor having an appropriate driving capability is selected, so that the lack of accuracy of the pulse width of the timing pulse can be compensated.

  In addition, the data line driver outputs a signal representing selection information of a transistor that is additionally selected when the charge supply circuit operates based on the image data stored in the first data storage unit. A setting unit and an additional transistor driving circuit that turns on the at least one transistor according to a timing pulse generated by a timing pulse generator when at least one transistor is selected by a signal output from the additional transistor setting unit. Furthermore, you may comprise. As a result, when the voltage between the source and drain of the transistor becomes small, it is possible to compensate for the lack of driving capability of the transistor.

  Alternatively, the charge supply circuit outputs a polarity pulse having a polarity corresponding to the polarity of the difference value calculated by the subtracter according to the timing pulse generated by the timing pulse generator, and the polarity pulse output unit. A differentiation circuit for differentiating the output polarity pulse, a second output signal generated by amplifying the polarity pulse differentiated by the differentiation circuit, and supplying the second output signal to the gradation voltage output terminal. These amplifiers may be included. In that case, by combining the output signal of the amplifier that amplifies the image signal and the output signal of the second amplifier that amplifies the differentiated polarity pulse, the rise of the gradation voltage when the image data changes In addition, the falling characteristic can be improved and the data line of the display panel can be driven at high speed.

  In the above, the data line driver may further include a switch circuit that opens and closes the connection between the output terminal of the amplifier and the gradation voltage output terminal. As a result, the influence of the amplifier on the operation of the charge supply circuit can be reduced by separating the output terminal of the amplifier from the gradation voltage output terminal while the charge supply circuit is operating.

  In that case, the data line driver turns off the switch circuit in synchronization with the timing at which the image data stored in the first and second data storage units changes, and turns on the switch circuit after the charge supply circuit operates. A control circuit may be further provided. As a result, when image data changes, the charge supply circuit supplies charge to the gradation voltage output terminal to improve the rising and falling characteristics of the gradation voltage, and then the amplifier fine-tunes the gradation voltage. In addition, an accurate gradation voltage can be maintained.

  A semiconductor integrated circuit device according to one aspect of the present invention includes any one of the data line drivers described above. Thereby, the circuit including the data line driver can be miniaturized and arranged in the vicinity of the display panel.

  An electronic apparatus according to one aspect of the present invention includes (i) a display panel, and (ii) a display panel driving circuit that includes any of the data line drivers described above and drives the display panel. Thereby, an electronic apparatus including a display panel in which data lines are driven at high speed can be provided.

The figure of the image display part containing the data line driver concerning one embodiment of the present invention. The figure which shows the 1st structural example of the data line driver shown in FIG. FIG. 3 is a diagram illustrating a configuration example of a charge supply circuit, a transistor drive circuit, and the like illustrated in FIG. 2. The figure which shows the synthesis | combination of the waveform of the gradation voltage by the amplifier and charge supply circuit which are shown in FIG. The figure which shows the 2nd structural example of the data line driver shown in FIG. The figure which shows the 3rd structural example of the data line driver shown in FIG. FIG. 7 is a circuit diagram showing a configuration example of an operational amplifier that can be used as each amplifier shown in FIG. 6. The block diagram which shows the main structures of a video projector. Schematic which shows the structural example of the optical system shown in FIG.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In addition, the same referential mark is attached | subjected to the same component and the overlapping description is abbreviate | omitted.
FIG. 1 is a block diagram illustrating a configuration example of an image display unit including a data line driver according to an embodiment of the present invention. As shown in FIG. 1, the image display unit includes a display control circuit 1, a display panel drive circuit 2, and a display panel 100, and displays an image based on image data supplied from the outside.

  The display panel 100 may be a color display panel having pixels of red color (R), green color (G), and blue color (B), or a single color having a single color pixel. The display panel may be used. In particular, in applications for video projectors, three types of display panels are provided to form images of red color (R), green color (G), and blue color (B). May be. In that case, three types of data line drivers may be provided corresponding to the three types of display panels.

  The display panel 100 may be an LCD panel, an organic EL (Electro-Luminescence) panel, or the like. In the present embodiment, as an example, a case where an active matrix transmissive LCD panel is used will be described.

  In an active matrix LCD panel, a first transparent substrate on which a plurality of individual electrodes and a plurality of TFTs (thin film transistors) connected thereto are formed, and a second transparent substrate on which one common electrode is formed Are arranged opposite to each other, and liquid crystal is sealed between the first transparent substrate and the second transparent substrate.

  In the display panel 100, for example, the same number of individual electrodes as those pixels are arranged in a two-dimensional matrix corresponding to 720 × 132 pixels. In FIG. 1, capacitors formed between the individual electrodes and the common electrode are represented as capacitors C11, C12, C13,..., C21, C22, C23,. Further, the same number of TFTs 111, 112, 113,..., 121, 122, 123,.

  The drains of the plurality of TFTs are connected to the plurality of individual electrodes, respectively. 1, the sources of TFTs in a plurality of columns in the vertical direction are connected to source lines S1, S2, S3,. Further, the gates of the TFTs in a plurality of horizontal lines (rows) in FIG. 1 are connected to gate lines (also called scanning lines) G1, G2,. When a high level scanning signal is applied to the gate and each TFT is turned on, each TFT outputs a gradation voltage supplied to the source from the drain and applies it to the corresponding individual electrode.

  In the display panel 100, if a direct current voltage is continuously applied between the individual electrode and the common electrode, the characteristics of the liquid crystal deteriorate. Therefore, the polarity of the voltage applied between the individual electrode and the common electrode has a predetermined cycle. Inverted. In this embodiment, a frame inversion method in which the polarity of the applied voltage is inverted every frame or a line inversion method in which the polarity of the applied voltage is inverted every line is used.

  The display control circuit 1 includes an image data processing circuit 10 and a display timing generation circuit 20. The display panel drive circuit 2 includes a data line driver 30, a gate line driver 40, and a common potential generation circuit 50.

  Here, the data line driver 30 may be incorporated in a semiconductor integrated circuit device (display driver IC) alone or together with the gate line driver 40 or the common potential generation circuit 50. Thereby, the circuit including the data line driver 30 can be reduced in size and disposed in the vicinity of the display panel 100. The display control circuit 1 may be incorporated in a semiconductor integrated circuit device (display controller IC) separate from the display driver IC, or may be incorporated in the display driver IC.

  The image data processing circuit 10 receives image data and a clock signal, and performs image processing on the image data as necessary. For example, the image data processing circuit 10 processes the image data so that the polarity of the gradation voltage is inverted for each frame or each line according to the polarity inversion signal. Specifically, when the common potential applied to the common electrode is constant at 7V, the gradation potential applied to the individual electrode is 12V for positive polarity and 2V for negative polarity when the gradation is 100%. Inverted between. Furthermore, the image data processing circuit 10 may perform general image processing such as edge enhancement.

  The display timing generation circuit 20 receives the horizontal synchronization signal, the vertical synchronization signal, and the clock signal, and generates various timing signals. As various timing signals, for example, a polarity inversion signal indicating inversion / non-inversion of the polarity of the gradation voltage, an output timing signal indicating the timing of outputting the gradation voltage, and a column for selecting a write column in the display panel 100 This corresponds to a selection signal, a scanning timing signal indicating a switching timing of a writing line in the display panel 100, and the like.

  The data line driver 30 drives the data lines of the display panel 100 by generating gradation voltages based on the image data supplied from the image data processing circuit 10 according to the clock signal and the output timing signal. The data line driver 30 outputs the generated plurality of gradation voltages to data lines (also called signal lines) D1, D2, D3,... Of the display panel 100, respectively.

  The multiplexer 60 provided in the display panel 100 is a group of sources in which the data lines D1, D2, D3,... Are selected from the source lines S1, S2, S3,. Connect to each line. Accordingly, the pixels for one line of the display panel 100 can be sequentially driven by a limited number of gradation voltage generation circuits included in the data line driver 30. When the data line driver 30 is provided with the same number of gradation voltage generation circuits as the number of pixels for one line of the display panel 100, the multiplexer 60 is not necessary, and the data lines D1, D2, D3, Are equal to the source lines S1, S2, S3,.

  The gradation voltage supplied to the source line S1 is applied to the sources of the TFTs 111, 121,. Further, the gradation voltage supplied to the source line S2 is applied to the sources of the TFTs 112, 122,. Further, the gradation voltage supplied to the source line S3 is applied to the sources of the third row TFTs 113, 123,..., And so on.

  The gate line driver 40 sequentially activates a plurality of scanning signals respectively supplied to the gate lines G1, G2,... To a high level (for example, 15V) according to the scanning timing signal. As a result, among the plurality of TFTs connected to each source line, the TFT whose gate line is at the high level is turned on, and the gradation voltage is applied to the individual electrode connected to the drain of the TFT. . The common potential generation circuit 50 generates a common potential COM and applies the common potential COM to the common electrode of the display panel 100. In this way, an image is displayed on the display panel 100.

Here, a first configuration example of the data line driver shown in FIG. 1 will be described.
FIG. 2 is a diagram showing a first configuration example of the data line driver shown in FIG. As shown in FIG. 2, the data line driver 30 includes a RAM (random access memory) 31 and a plurality of gradation voltage generation circuits 32. The RAM 31 temporarily stores image data supplied from the image data processing circuit 10 (FIG. 1), and outputs image data for a plurality of pixels in parallel according to an output timing signal.

  Each gradation voltage generation circuit 32 includes an image data input terminal 301, data latch circuits (data storage units) 302 and 303, a DAC (digital / analog converter) 304, an amplifier 305, a switch circuit 306, A control circuit 307, a subtractor 308, a timing pulse generator 309, a charge supply circuit 310, and a gradation voltage output terminal 316 are included.

  The grayscale voltage generation circuit 32 is supplied with image data for one pixel at a time from the RAM 31 in synchronization with the output timing signal. The data latch circuits 302 and 303 are connected in series, and sequentially store image data supplied continuously in synchronization with the output timing signal. FIG. 2 shows a state in which the data latch circuit 302 stores the i-th image data, and the data latch circuit 303 stores the (i−1) -th image data.

  The DAC 304 D / A (digital / analog) converts the image data stored in the data latch circuit 302 and outputs an analog image signal. When a resistance ladder type DAC is used as the DAC 304, the conversion characteristics of the DAC are determined by setting a resistance value in the ladder type resistance circuit. For example, the DAC 304 may D / A convert image data in accordance with conversion characteristics that correct the gamma characteristics of the display panel 100 (FIG. 1). However, if standard gamma correction has already been performed on the image data supplied to the RAM 31, only the gamma characteristic of the display panel 100 is different from the standard gamma characteristic. Just do it.

  The amplifier 305 amplifies the image signal output from the DAC 304 to generate an output signal, and supplies the output signal to the gradation voltage output terminal 316 via the switch circuit 306. The amplifier 305 has a large open loop gain, and is capable of amplifying an image signal with high accuracy by applying overall negative feedback (negative feedback from the output terminal to the inverting input terminal). However, a certain amount of delay occurs in the rise and fall of the output signal. In order to improve the rising and falling characteristics of the gradation voltage when the image data changes, a subtractor 308 to a charge supply circuit 310 are provided.

  The subtractor 308 calculates a difference value between the i-th image data stored in the data latch circuit 302 and the (i−1) -th image data stored in the data latch circuit 303. The timing pulse generator 309 generates a timing pulse for operating the charge supply circuit 310 based on the difference value calculated by the subtractor 308. For example, the timing pulse generator 309 may generate a timing pulse having a pulse width substantially proportional to the absolute value of the difference value calculated by the subtractor 308.

  The charge supply circuit 310 supplies charges to the gradation voltage output terminal 316 in accordance with the timing pulse generated by the timing pulse generator 309. Here, the charge supply circuit 310 supplies a positive charge to the gradation voltage output terminal 316 if the difference value calculated by the subtractor 308 is positive, and outputs a gradation voltage output if the difference value is negative. Negative charge is supplied to the terminal 316.

  According to the present embodiment, a difference value between two consecutive image data is digitally calculated, and the charge supply circuit 310 supplies charges to the gradation voltage output terminal 316 based on the difference value. In addition, a high-speed charge supply operation is possible. Accordingly, the rising and falling characteristics of the gradation voltage when the image data changes can be improved, and the data lines of the display panel 100 can be driven at high speed. On the other hand, the amplifier 305 can maintain an accurate gradation voltage based on an analog image signal obtained by A / D converting image data.

  In order to generate a timing pulse for operating the charge supply circuit 310, an operation table storage unit 311 shown in FIG. 2 may be provided. The operation table storage unit 311 includes, for example, a non-volatile memory and the like, and an operation in which pulse width data representing a pulse width of a timing pulse is set corresponding to a plurality of difference values (a range of a plurality of difference values may be used). Table A is stored. The operation table storage unit 311 refers to the operation table A, and outputs pulse width data corresponding to the difference value calculated by the subtractor 308.

  The timing pulse generator 309 is set based on the pulse width data by setting a start timing and an end timing for operating the charge supply circuit 310 based on the pulse width data output from the operation table storage unit 311. A timing pulse having a pulse width is generated.

  For example, the timing pulse generator 309 may set the start timing by latching the output timing signal in synchronization with the clock signal. The timing pulse generator 309 may set the end timing by delaying the start timing in synchronization with the clock signal according to the pulse width represented by the pulse width data.

  Thereby, the timing pulse generator 309 can generate a timing pulse having a pulse width set based on the difference value calculated by the subtractor 308. However, when the period of the clock signal is not so short, the accuracy of the pulse width of the timing pulse cannot be sufficiently increased.

  Therefore, in the charge supply circuit 310, a plurality of transistors connected in parallel are provided, and at least one transistor to be turned on is selected based on the difference value calculated by the subtractor 308, whereby the gradation voltage output terminal 316 is connected. The amount of charge supplied may be controlled with high accuracy. In that case, an operation table storage unit 312 and a transistor drive circuit 313 shown in FIG. 2 are provided.

  The operation table storage unit 312 includes a non-volatile memory, for example, and selects a transistor that is selected when the charge supply circuit 310 operates corresponding to a plurality of difference values (or a range of a plurality of difference values). The operation table B in which information is set is stored. The operation table storage unit 312 refers to the operation table B, and outputs an enable signal representing selection information corresponding to the difference value calculated by the subtractor 308.

  The transistor drive circuit 313 turns on at least one transistor selected by the enable signal output from the operation table storage unit 312 according to the timing pulse generated by the timing pulse generator 309.

  As a result, at least one transistor having an appropriate driving capability is selected, so that the lack of accuracy of the pulse width of the timing pulse can be compensated. However, depending on the value of the gradation voltage to be output, the voltage between the source and drain of the selected transistor becomes small, so that the driving capability of the transistor is lowered.

  Therefore, a plurality of transistors for correction are provided in the charge supply circuit 310, and at least one transistor to be turned on is additionally selected based on the value of the i-th image data stored in the data latch circuit 302. By doing so, the amount of charge supplied to the gradation voltage output terminal 316 may be corrected. In that case, an operation table storage unit 314 and an additional transistor drive circuit 315 shown in FIG. 2 are provided.

  The operation table storage unit 314 includes, for example, a non-volatile memory or the like, and is additionally provided when the charge supply circuit 310 operates corresponding to a plurality of image data values (or a range of a plurality of image data values). The operation table C in which selection information of transistors to be selected is set is stored. Further, the operation table storage unit 314 outputs an additional enable signal representing selection information corresponding to the i-th image data stored in the data latch circuit 302 by referring to the operation table C.

  The additional transistor drive circuit 315 turns on the at least one transistor according to the timing pulse generated by the timing pulse generator 309 when at least one transistor is selected by the additional enable signal output from the operation table storage unit 314. Let As a result, when the voltage between the source and drain of the transistor becomes small, it is possible to compensate for the lack of driving capability of the transistor.

  FIG. 3 is a diagram illustrating a configuration example of the charge supply circuit, the transistor drive circuit, and the additional transistor drive circuit illustrated in FIG. 3, the charge supply circuit 310 includes a first group of P-channel MOS transistors QP11, QP12,... Connected in parallel between the power supply potential VDD on the high potential side and the gradation voltage output terminal 316. And a second group of P-channel MOS transistors QP21, QP22,.

  The source of each transistor is connected to the wiring of the power supply potential VDD, and the drain is connected to the gradation voltage output terminal 316. The first group of P-channel MOS transistors QP11, QP12,... Preferably have different sizes (for example, channel widths) such as 1: 2:. Similarly, it is desirable that the second group of P-channel MOS transistors QP21, QP22,... Have different sizes.

  In addition, the charge supply circuit 310 includes a first group of N-channel MOS transistors QN11, QN12,... Connected in parallel between the gradation voltage output terminal 316 and the power supply potential VSS on the low potential side, and a second group. N channel MOS transistors QN21, QN22, and so on.

  The drain of each transistor is connected to the gradation voltage output terminal 316, and the source is connected to the wiring of the power supply potential VSS. The first group N-channel MOS transistors QN11, QN12,... Preferably have different sizes such as 1: 2:. Similarly, the second group N-channel MOS transistors QN21, QN22,... Desirably have different sizes.

  The transistor drive circuits 313a and 313b constitute the transistor drive circuit 313 shown in FIG. The transistor drive circuit 313a includes a plurality of logic circuits that calculate a logical product of the timing pulse and the enable signals EP11, EP12,... And output a low-level drive pulse. The output signals of these logic circuits are applied to the gates of the first group of P-channel MOS transistors QP11, QP12,.

  3, NAND circuits NA11, NA12,... Are shown as examples of a plurality of logic circuits included in the transistor drive circuit 313a. For example, when a high-level timing pulse having a set pulse width is supplied while the enable signal EP11 is activated to a high level, the NAND circuit NA11 has the same pulse width as the timing pulse. A low level driving pulse having the same value is output. The transistor QP11 to which the drive pulse is applied to the gate is turned on and supplies positive charges from the power supply potential VDD to the gradation voltage output terminal 316.

  The transistor drive circuit 313b includes a plurality of logic circuits that calculate a logical product of the timing pulse and the enable signals EN11, EN12,... And output a high-level drive pulse. The output signals of these logic circuits are applied to the gates of the first group of N-channel MOS transistors QN11, QN12,.

  In FIG. 3, AND circuits AN11, AN12,... Are shown as examples of a plurality of logic circuits included in the transistor drive circuit 313b. For example, when a high-level timing pulse having a set pulse width is supplied while the enable signal EN11 is activated to a high level, the AND circuit AN11 has the same pulse width as the timing pulse. A high-level drive pulse having the same is output. The transistor QN11 to which the drive pulse is applied to the gate is turned on to supply negative charge from the power supply potential VSS to the gradation voltage output terminal 316.

  The additional transistor drive circuits 315a and 315b constitute the additional transistor drive circuit 315 shown in FIG. The additional transistor drive circuit 315a includes a plurality of logic circuits that calculate a logical product of the timing pulse and the additional enable signals EP21, EP22,... And output a low level drive pulse. The output signals of these logic circuits are applied to the gates of the second group of P-channel MOS transistors QP21, QP22,.

  3, NAND circuits NA21, NA22,... Are shown as examples of a plurality of logic circuits included in the additional transistor drive circuit 315a. For example, when a high-level timing pulse having a set pulse width is supplied while the additional enable signal EP21 is activated to a high level, the NAND circuit NA21 has the same pulse width as the pulse width of the timing pulse. A low-level drive pulse having The transistor QP21 to which the drive pulse is applied to the gate is turned on to supply positive charges from the power supply potential VDD to the gradation voltage output terminal 316.

  The additional transistor drive circuit 315b includes a plurality of logic circuits that calculate a logical product of the timing pulse and the additional enable signals EN21, EN22,... And output a high level drive pulse. The output signals of these logic circuits are applied to the gates of the second group of N-channel MOS transistors QN21, QN22,.

  3, AND circuits AN21, AN22,... Are shown as examples of a plurality of logic circuits included in the additional transistor drive circuit 315b. For example, when a high-level timing pulse having a set pulse width is supplied while the additional enable signal EN21 is activated to a high level, the AND circuit AN21 has the same pulse width as the pulse width of the timing pulse. A high-level driving pulse having The transistor QN21 to which the drive pulse is applied to the gate is turned on to supply a negative charge from the power supply potential VSS to the gradation voltage output terminal 316.

  Referring to FIG. 2 again, the switch circuit 306 opens and closes the connection between the output terminal of the amplifier 305 and the grayscale voltage output terminal 316. Thus, while the charge supply circuit 310 is operating, the output terminal of the amplifier 305 can be disconnected from the gradation voltage output terminal 316, and the influence of the amplifier 305 on the operation of the charge supply circuit 310 can be reduced. Opening and closing of the switch circuit 306 is controlled by a control signal CS output from the control circuit 307.

  In accordance with the output timing signal, the control circuit 307 turns off the switch circuit 306 in synchronization with the timing at which the image data stored in the data latch circuits 302 and 303 changes. Further, the control circuit 307 turns on the switch circuit 306 after the charge supply circuit 310 is operated in accordance with the timing pulse generated by the timing pulse generator 309. As a result, when the image data changes, the charge supply circuit 310 supplies charges to the gradation voltage output terminal 316 to improve the rising and falling characteristics of the gradation voltage. Can be finely adjusted to maintain an accurate gradation voltage.

  FIG. 4 is a diagram showing the synthesis of the gradation voltage waveform by the amplifier and the charge supply circuit shown in FIG. As shown in FIG. 4A, the output signal v1 of the amplifier 305 to which the image signal is input rises slowly, but after rising, an accurate voltage is maintained by negative feedback. On the other hand, as shown in FIG. 4B, the charge Q supplied by the charge supply circuit 310 has a pulse waveform corresponding to the change of the image signal.

  As shown in FIG. 4B, the control signal CS output from the control circuit 307 is synchronized with the timing at which the image data stored in the data latch circuit 302 changes from D (i−1) to D (i). Thus, the switch circuit 306 is turned off by being deactivated to a low level. While the switch circuit 306 is off, the output terminal of the amplifier 305 is disconnected from the gradation voltage output terminal 316. Thereafter, the charge supply circuit 310 supplies the charge Q to the gradation voltage output terminal 316.

  The load of the charge supply circuit 310 is a capacitance and a wiring capacitance formed between the individual electrode and the common electrode of the display panel. The charge supply circuit 310 supplies the charge Q to these capacitors, and thereafter has little influence on the gradation voltage due to the high output impedance. When the charge supply operation of the charge supply circuit 310 is completed, the control signal CS is activated to a high level, and the switch circuit 306 is turned on. While the switch circuit 306 is on, the output terminal of the amplifier 305 is connected to the gradation voltage output terminal 316.

  By synthesizing the output signal v1 of the amplifier 305 and the charge Q supplied by the charge supply circuit 310, a gradation voltage v2 having a waveform as shown in FIG. 4C is obtained. In the waveform of the gradation voltage v2 (solid line), the rising characteristic is improved as compared with the waveform of the output signal v1 of the amplifier 305 (broken line). The waveform of the gradation voltage v2 can be optimized by adjusting the pulse width data and selection information set in the operation tables A to C.

Next, a second configuration example of the data line driver shown in FIG. 1 will be described.
FIG. 5 is a diagram showing a second configuration example of the data line driver shown in FIG. In the second configuration example shown in FIG. 5, instead of the operation table storage units 311, 312, and 314 in the first configuration example shown in FIG. 2, a pulse width setting unit 317, a transistor setting unit 318, and An additional transistor setting unit 319 is provided. The other points are the same as in the first configuration example.

  The pulse width setting unit 317 is configured by a logic circuit, for example, and sets the pulse width of the timing pulse based on the difference value calculated by the subtractor 308. For example, the pulse width setting unit 317 may set a pulse width substantially proportional to the absolute value of the difference value calculated by the subtractor 308 and output pulse width data representing the pulse width.

  The timing pulse generator 309 generates a timing pulse having a pulse width set by the pulse width setting unit 317. For example, the timing pulse generator 309 determines the start timing and end timing by setting the start timing and end timing for operating the charge supply circuit 310 based on the pulse width data output from the pulse width setting unit 317. A timing pulse having a pulse width may be generated.

  In that case, the timing pulse generator 309 may set the start timing by latching the output timing signal in synchronization with the clock signal. The timing pulse generator 309 may set the end timing by delaying the start timing in synchronization with the clock signal according to the pulse width represented by the pulse width data.

  Thereby, the timing pulse generator 309 can generate a timing pulse having a pulse width set based on the difference value calculated by the subtractor 308. However, when the period of the clock signal is not so short, the accuracy of the pulse width of the timing pulse cannot be sufficiently increased.

  Therefore, in the charge supply circuit 310, a plurality of transistors connected in parallel are provided, and at least one transistor to be turned on is selected based on the difference value calculated by the subtractor 308, whereby the gradation voltage output terminal 316 is connected. The amount of charge supplied may be controlled with high accuracy. In that case, a transistor setting unit 318 and a transistor driving circuit 313 shown in FIG. 5 are provided.

  The transistor setting unit 318 is configured by a logic circuit, for example, and outputs an enable signal indicating selection information of a transistor selected when the charge supply circuit 310 operates based on a difference value calculated by the subtractor 308. .

  The transistor drive circuit 313 turns on at least one transistor selected by the enable signal output from the transistor setting unit 318 according to the timing pulse generated by the timing pulse generator 309.

  As a result, at least one transistor having an appropriate driving capability is selected, so that the lack of accuracy of the pulse width of the timing pulse can be compensated. However, depending on the value of the gradation voltage to be output, the voltage between the source and the drain of the transistor of the charge supply circuit 310 becomes small, so that the driving capability of the transistor is lowered.

  Therefore, a plurality of transistors for correction are provided in the charge supply circuit 310, and at least one transistor to be turned on is additionally selected based on the value of the i-th image data stored in the data latch circuit 302. By doing so, the amount of charge supplied to the gradation voltage output terminal 316 may be corrected. In that case, an additional transistor setting unit 319 and an additional transistor driving circuit 315 shown in FIG. 5 are provided.

  The additional transistor setting unit 319 includes, for example, a logic circuit, and is a transistor that is additionally selected when the charge supply circuit 310 operates based on the i-th image data stored in the data latch circuit 302. An additional enable signal representing the selection information is output.

  The additional transistor driving circuit 315 turns on the at least one transistor according to the timing pulse generated by the timing pulse generator 309 when at least one transistor is selected by the additional enable signal output from the additional transistor setting unit 319. Let As a result, when the voltage between the source and drain of the transistor becomes small, it is possible to compensate for the lack of driving capability of the transistor.

Next, a third configuration example of the data line driver shown in FIG. 1 will be described.
FIG. 6 is a diagram showing a third configuration example of the data line driver shown in FIG. In the third configuration example shown in FIG. 6, instead of the operation table storage units 312 and 314, the transistor drive circuit 313, and the additional transistor drive circuit 315 in the first configuration example shown in FIG. 320, a differentiating circuit 321 and an amplifier 322 are provided. The other points are the same as in the first configuration example. Instead of the operation table storage unit 311, a pulse width setting unit 317 in the second configuration example shown in FIG. 5 may be provided.

  The polarity pulse output unit 320, the differentiation circuit 321, and the amplifier 322 constitute a charge supply circuit that supplies charges to the gradation voltage output terminal 316 in accordance with the timing pulse generated by the timing pulse generator 309. The polarity pulse output unit 320 outputs a polarity pulse having a polarity corresponding to the sign of the difference value calculated by the subtractor 308 according to the timing pulse generated by the timing pulse generator 309.

  For example, the polarity pulse output unit 320 includes a P-channel MOS transistor connected between the power supply potential VDD on the high potential side and the output terminal, and an N connected between the output terminal and the power supply potential VSS on the low potential side. It includes channel MOS transistors and logic circuits that drive the transistors.

  When the difference value calculated by the subtractor 308 is positive, the logic circuit outputs a low-level drive pulse having the same pulse width as the timing pulse generated by the timing pulse generator 309 to the P-channel MOS transistor. Apply to the gate. As a result, a positive polarity pulse is output from the output terminal.

  On the other hand, when the difference value calculated by the subtractor 308 is negative, the logic circuit outputs a high-level drive pulse having the same pulse width as the timing pulse generated by the timing pulse generator 309 to the N-channel MOS. Applied to the gate of the transistor. As a result, a negative polarity pulse is output from the output terminal.

Differentiating circuit 321 includes a capacitor C1 and a resistor R1. The first terminal of the capacitor C1 is connected to the output terminal of the polarity pulse output unit 320, and the second terminal of the capacitor C1 is connected to the first terminal of the resistor R1. A reference potential V _{REF that} is supplied to the inverting input terminal of the amplifier 322 and serves as a reference for the amplification operation is supplied to the second terminal of the resistor R1. In addition, a coupling capacitor C2 is connected between the second terminal of the capacitor C1 and the non-inverting input terminal of the amplifier 322.

  The differentiation circuit 321 differentiates the polarity pulse output from the polarity pulse output unit 320. The amplifier 322 is an operational amplifier having high driving capability, amplifies the polarity pulse differentiated by the differentiating circuit 321, generates an output signal, and supplies the output signal to the gradation voltage output terminal 316. As a result, the output signal of the amplifier 305 and the output signal of the amplifier 322 are combined at the gradation voltage output terminal 316 to generate a gradation voltage.

  According to the above configuration, by combining the output signal of the amplifier 305 that amplifies the image signal and the output signal of the amplifier 322 that amplifies the differentiated polarity pulse, the gradation voltage when the image data changes is obtained. The data line of the display panel 100 (FIG. 1) can be driven at high speed by improving the rising and falling characteristics.

  Here, the amplifier 305 amplifies the image signal output from the DAC 304 in a DC manner with overall negative feedback. The amplifier 305 has a large open loop gain, and is capable of amplifying an image signal with high accuracy by being subjected to overall negative feedback. On the other hand, the amplifier 322 amplifies the polarity pulse differentiated by the differentiating circuit 321 in an AC manner without overall negative feedback. By not applying overall negative feedback to the amplifier 322, it is difficult for ringing or the like to occur, and the output impedance becomes high, so the influence on the operation of the amplifier 305 is reduced.

  FIG. 7 is a circuit diagram showing a configuration example of an operational amplifier that can be used as each amplifier shown in FIG. In FIG. 7, a P channel MOS transistor QP1 and an N channel MOS transistor QN1 constitute a first inverter. The source of the transistor QP1 is connected to the wiring of the power supply potential VDD on the high potential side. The drain of the transistor QN1 is connected to the drain of the transistor QP1, and the source of the transistor QN1 is connected to the wiring of the power supply potential VSS on the low potential side. The gates of the transistors QP1 and QN1 are connected to the input terminal of the enable signal ENB. The first inverter inverts the input enable signal ENB and outputs a first control signal PS.

  P channel MOS transistor QP2 and N channel MOS transistor QN2 constitute a second inverter. The source of the transistor QP2 is connected to the wiring of the power supply potential VDD. The drain of the transistor QN2 is connected to the drain of the transistor QP2, and the source of the transistor QN2 is connected to the wiring of the power supply potential VSS. The first control signal PS is input to the gates of the transistors QP2 and QN2. The second inverter inverts the input first control signal PS and outputs a second control signal XPS.

  P channel MOS transistors QP3 to QP4 and N channel MOS transistors QN3 to QN6 form a first differential stage. The sources of the transistors QP3 and QP4 are connected to the wiring of the power supply potential VDD, and the gates of the transistors QP3 and QP4 are connected to the drain of the transistor QP4.

  The drain of the transistor QN3 is connected to the drain of the transistor QP3, and the gate of the transistor QN3 is connected to the non-inverting input terminal of the operational amplifier. The drain of the transistor QN4 is connected to the drain of the transistor QP4, and the gate of the transistor QN4 is connected to the inverting input terminal of the operational amplifier.

  The drain of the transistor QN5 is connected to the sources of the transistors QN3 and QN4, and the second control signal XPS is supplied to the gate of the transistor QN5. The drain of the transistor QN6 is connected to the source of the transistor QN5, and the source of the transistor QN6 is connected to the wiring of the power supply potential VSS. The first bias potential VRN is supplied to the gate of the transistor QN6.

  When the enable signal ENB is activated to a high level, the second control signal XPS also becomes a high level, the transistor QN5 is turned on, and the first differential stage operates. The first differential stage inverts and amplifies the difference between the signal input to the non-inverting input terminal of the operational amplifier and the signal input to the inverting input terminal, and applies the first amplified signal to the drains of the transistors QP3 and QN3. Generate.

  P channel MOS transistors QP5 to QP8 and N channel MOS transistors QN7 to QN8 form a second differential stage. The source of the transistor QP5 is connected to the wiring of the power supply potential VDD, and the second bias potential VRP is supplied to the gate of the transistor QP5. The source of the transistor QP6 is connected to the drain of the transistor QP5, and the first control signal PS is supplied to the gate of the transistor QP6.

  The sources of the transistors QP7 and QP8 are connected to the drain of the transistor QP6. The gate of the transistor QP7 is connected to the non-inverting input terminal of the operational amplifier. The gate of the transistor QP8 is connected to the inverting input terminal of the operational amplifier.

  The drain of the transistor QN7 is connected to the drain of the transistor QP7, and the source of the transistor QN7 is connected to the wiring of the power supply potential VSS. The drain of the transistor QN8 is connected to the drain of the transistor QP8, and the source of the transistor QN8 is connected to the wiring of the power supply potential VSS. The gates of the transistors QN7 and QN8 are connected to the drain of the transistor QN8.

  When the enable signal ENB is activated to a high level, the first control signal PS becomes a low level, the transistor QP6 is turned on, and the second differential stage operates. The second differential stage inverts and amplifies the difference between the signal input to the non-inverting input terminal of the operational amplifier and the signal input to the inverting input terminal, and supplies the second amplified signal to the drains of the transistors QP7 and QN7. Generate.

  P-channel MOS transistor QP9 and N-channel MOS transistor QN9 constitute an output stage. The source of the transistor QP9 is connected to the power supply potential VDD, the drain of the transistor QP9 is connected to the output terminal, and the first amplified signal is supplied to the gate of the transistor QP9. The source of the transistor QN9 is connected to the power supply potential VSS, the drain of the transistor QN9 is connected to the output terminal, and the second amplified signal is supplied to the gate of the transistor QN9. The transistor QP9 inverts and amplifies the first amplified signal applied to the gate and supplies it to the output terminal, and the transistor QN9 inverts and amplifies the second amplified signal applied to the gate and supplies it to the output terminal.

  When the operational amplifier shown in FIG. 7 is used as the amplifier 322 shown in FIG. 6, in the transistors QN3 and QN4 constituting the differential pair of the first differential stage, the channel width W and the channel length L of the transistor QN3 The ratio W / L may be made smaller than the ratio W / L between the channel width W and the channel length L of the transistor QN4 at a predetermined rate. In that case, the output transistor QP9 does not turn on unless the balance point in the first differential stage is shifted and the potential of the non-inverting input terminal becomes higher than the potential of the inverting input terminal to some extent.

  Further, in the transistors QP7 and QP8 constituting the differential pair of the second differential stage, the ratio W / L between the channel width W and the channel length L of the transistor QP7 is set to be equal to the channel width W and the channel length L of the transistor QP8. The ratio W / L may be reduced at a predetermined rate. In that case, the output transistor QN9 does not turn on unless the balance point in the second differential stage is shifted and the potential of the non-inverting input terminal becomes lower than the potential of the inverting input terminal to some extent.

  As a result, when the potential of the non-inverting input terminal is within a predetermined range with respect to the potential of the inverting input terminal, the operational amplifier does not perform an amplification operation, and the output impedance of the operational amplifier increases. In other words, this operational amplifier has a dead zone for an input voltage within a predetermined range.

  As a result, the amplifier 322 operates when the level of the polarity pulse output from the polarity pulse output unit 320 changes greatly, but does not operate for a slight level fluctuation of the polarity pulse. The influence on the operation of converging the voltage can be further reduced. In addition, power loss when the output terminal of the amplifier 305 and the output terminal of the amplifier 322 are connected can be further reduced.

  The operational amplifier illustrated in FIG. 7 can also be used as the amplifier 305 illustrated in FIGS. 2, 5, and 6. However, it is desirable that the slew rate of the amplifier 322 is larger than the slew rate of the amplifier 305. In this case, the effect of improving the waveform of the gradation voltage by the amplifier 322 is increased.

  In addition, it is desirable that the size (eg, channel width) and / or drive current of the output transistor of the amplifier 322 be larger than the size and / or drive current of the output transistor of the amplifier 305. In that case, the amplifier 322 can drive the data line with high driving capability.

Next, an electronic apparatus according to an embodiment of the present invention will be described.
The present invention can be applied to electronic devices such as a video projector, an electronic viewfinder, a display device, and a mobile phone. In the following, an embodiment in which the present invention is applied to a video projector will be described.

  FIG. 8 is a block diagram showing the main configuration of a video projector as an electronic apparatus according to an embodiment of the invention. As shown in FIG. 8, the video projector includes a display control circuit 1, a display panel drive circuit 2, an optical system 3, a control unit 4, and a power supply unit 5. This video projector can project an image corresponding to image data input from an external device onto the screen 6 or the like.

  The display control circuit 1 and the display panel drive circuit 2 are the same as those already described. The optical system 3 includes a lamp 3a, an image forming unit 3b, and a projection lens unit 3c. The lamp 3a is, for example, a high-pressure mercury lamp or a metal halide lamp, and generates light emitted toward the screen 6 through the image forming unit 3b and the projection lens unit 3c.

  The image forming unit 3b includes at least one display panel. In the case of a color method, the image forming unit 3b may include three display panels. The display panel is a transmissive image forming panel, and forms an image by changing the transmittance of each pixel in accordance with the gradation voltage and the scanning signal supplied from the display panel driving circuit 2.

  Since the image forming unit 3b is irradiated with light generated from the lamp 3a, the image formed on the display panel is projected onto the projection lens unit 3c. The projection lens unit 3 c refracts incident light and emits projection light 7. Therefore, the image formed on the display panel is enlarged and projected onto the screen 6.

  The control unit 4 is composed of, for example, a microcomputer, and includes a CPU (Central Processing Unit) 4a and a memory 4b. The CPU 4a controls operations of the display control circuit 1, the display panel drive circuit 2, and the like according to a control program stored in the memory 4b. The power supply unit 5 supplies power to each unit of the video projector based on an AC or DC power supply voltage supplied from the outside.

Here, a configuration example of the image forming unit of the optical system shown in FIG. 8 will be described in detail.
FIG. 9 is a schematic diagram showing a configuration example of the optical system shown in FIG. As shown in FIG. 9, the image forming unit 3b includes a spectroscopic unit 90, three display panels 100R, 100G, and 100B, and a cross dichroic prism 110.

  The spectroscopic unit 90 includes dichroic mirrors 91 and 92 and reflection mirrors 93 to 95. Light 8 generated from the lamp 3a enters the spectroscopic unit 90 along the optical axis 9a. The spectroscopic unit 90 separates, for example, red light 8R, green light 8G, and blue light 8B from incident light 8 (substantially white light).

  The dichroic mirror 91 is disposed at a position intersecting with the optical axis 9a and inclined by approximately 45 ° with respect to the optical axis 9a. Of the incident light 8, the dichroic mirror 91 transmits the red color light 8 </ b> R and reflects the green color light 8 </ b> G and the blue color light 8 </ b> B. The light 8R transmitted through the dichroic mirror 91 is guided to the reflection mirror 93 along the optical axis 9a. The reflection mirror 93 is disposed at a position intersecting with the optical axis 9a and inclined by approximately 45 ° with respect to the optical axis 9a. The light 8R is reflected by the reflecting mirror 93 and enters the display panel 100R along the optical axis 9b.

  On the other hand, the light reflected by the dichroic mirror 91 is guided to the dichroic mirror 92 along the optical axis 9c. The dichroic mirror 92 is disposed at a position intersecting with the optical axis 9c and inclined by approximately 45 ° with respect to the optical axis 9c. Of the light reflected by the dichroic mirror 91, the dichroic mirror 92 reflects the green light 8G and transmits the blue light 8B. The light 8G reflected by the dichroic mirror 92 enters the display panel 100G along the optical axis 9d.

  On the other hand, the light 8B transmitted through the dichroic mirror 92 is guided to the reflection mirror 94 along the optical axis 9c. The reflection mirror 94 is disposed at a position intersecting with the optical axis 9c and inclined by approximately 45 ° with respect to the optical axis 9c. The light 8B is reflected by the reflecting mirror 94 and guided to the reflecting mirror 95 along the optical axis 9e. The reflection mirror 95 is disposed at a position intersecting with the optical axis 9e and inclined by approximately 45 ° with respect to the direction of the optical axis 9e. The light 8B is reflected by the reflection mirror 95 and enters the display panel 100B along the optical axis 9f.

  A polarizing plate (not shown) is provided between the spectroscopic unit 90 and each display panel. A polarizing plate (not shown) is also provided between each display panel and the cross dichroic prism 110. Each of these polarizing plates has a transmission axis, and can transmit light having a polarization axis in the direction of the transmission axis. A pair of polarizing plates facing each other across the display panel is provided in a state where the transmission axes cross each other.

  The cross dichroic prism 110 is provided at a position overlapping the intersection of the optical axes 9b, 9d, and 9f, and has four surfaces 110a to 110d. The light 8R transmitted through the display panel 100R enters the cross dichroic prism 110 from the surface 110a. The light 8G transmitted through the display panel 100G enters the cross dichroic prism 110 from the surface 110b. The light 8B transmitted through the display panel 100B enters the cross dichroic prism 110 from the surface 110c. As a result, a red color image is projected onto the surface 110a, a green color image is projected onto the surface 110b, and a blue color image is projected onto the surface 110c.

  The red color light 8 </ b> R, the green color light 8 </ b> G, and the blue color light 8 </ b> B incident on the cross dichroic prism 110 are combined by the cross dichroic prism 110. That is, the cross dichroic prism 110 synthesizes a red color image, a green color image, and a blue color image.

  The synthesized light is emitted as color image light 8C from the surface 110d of the cross dichroic prism 110 and enters the projection lens unit 3c. As shown in FIG. 8, the color image light 8 </ b> C incident on the projection lens unit 3 c is projected onto the screen 6 or the like as the projection light 7. As described above, by using the display panel driving circuit including the data line driver according to the present invention, an electronic apparatus including a display panel in which data lines are driven at high speed can be provided.

  The present invention is not limited to the embodiments described above, and many modifications can be made within the technical idea of the present invention by those having ordinary knowledge in the technical field.

  DESCRIPTION OF SYMBOLS 1 ... Display control circuit, 2 ... Display panel drive circuit, 3 ... Optical system, 3a ... Lamp, 3b ... Image formation part, 3c ... Projection lens part, 4 ... Control part, 4a ... CPU, 4b ... Memory, 5 ... Power supply , 6 ... screen, 10 ... image data processing circuit, 20 ... display timing generation circuit, 30 ... data line driver, 31 ... RAM, 32 ... gradation voltage generation circuit, 301 ... image data input terminal, 302, 303 ... data Latch circuit, 304 ... DAC, 305 ... Amplifier, 306 ... Switch circuit, 307 ... Control circuit, 308 ... Subtractor, 309 ... Timing pulse generator, 310 ... Charge supply circuit, 311, 312, 314 ... Operation table storage unit, 313, 313a, 313b ... transistor drive circuit, 315, 315a, 315b ... additional transistor drive circuit, 316 ... gradation Pressure output terminal, 317 ... Pulse width setting unit, 318 ... Transistor setting unit, 319 ... Additional transistor setting unit, 320 ... Polarity pulse output unit, 321 ... Differentiation circuit, 322 ... Amplifier, 40 ... Gate line driver, 50 ... Common potential Generating circuit, 60: multiplexer, 90: spectroscopic unit, 91, 92 ... dichroic mirror, 93-95 ... reflecting mirror, 100, 100R, 100G, 100B ... display panel, 110 ... cross dichroic prism, 111-123 ... TFT, C11 to C23: Capacitance, D1, D2, D3 ... Data line, S1, S2, S3 ... Source line, G1, G2 ... Gate line, C1, C2 ... Capacitor, R1 ... Resistance, QP1 to QP24 ... P channel MOS transistor, QN1 to QN24: N channel MOS transistor, NA1 ~NA24 ... NAND circuit, AN11~AN24 ... AND circuit

Claims (5)

A data line driver that drives a data line of a display panel by generating a gradation voltage based on image data,
A first data storage unit and a second data storage unit for sequentially storing successively supplied image data;
A DAC (digital / analog converter) that D / A (digital / analog) converts the image data stored in the first data storage unit and outputs an analog image signal;
An amplifier that amplifies an image signal output from the DAC to generate an output signal, and supplies the output signal to a gradation voltage output terminal;
A polarity pulse output unit for outputting a polarity pulse having a polarity corresponding to the positive / negative of the difference value between the image data stored in the first data storage unit and the image data stored in the second data storage unit And a differentiation circuit for differentiating the polarity pulse output from the polarity pulse output unit, a polarity pulse differentiated by the differentiation circuit is amplified to generate a second output signal, and the second output signal is A charge supply circuit for supplying charge to the gradation voltage output terminal, comprising: a second amplifier for supplying to the gradation voltage output terminal;
A data line driver comprising: The data line driver according to claim 1, further comprising a switch circuit that opens and closes a connection between an output terminal of the amplifier and the gradation voltage output terminal. And a control circuit that turns off the switch circuit in synchronization with a timing at which image data stored in the first and second data storage units changes, and turns on the switch circuit after the charge supply circuit operates. The data line driver according to claim 2 . The semiconductor integrated circuit device having a data line driver according to any one of claims 1-3. A display panel;
Includes data lines driver according to any one of claims 1 to 3, the display panel drive circuit for driving the display panel,
An electronic device comprising:

Images