JP2021111897A - Frame period error detector and inter-base station synchronization system - Google Patents

Abstract

To provide a frame period error detector that implements cost reduction.SOLUTION: A frame period error detector detects a frame period error corresponding to a difference between reception timings of a plurality of signals individually transmitted from a plurality of base stations. The frame period error detector includes a receiver and an error detector. The receiver is shared by the plurality of base stations, and receives the plurality of signals and generates demodulation data corresponding to each of the plurality of signals. The error detector detects the frame period error between the plurality of signals on the basis of detection timing of a synchronization word included in the demodulation data. The error detector includes a storage unit and an error calculation unit. The storage unit stores information on detection timing of the synchronization word for each base station. The error calculation unit detects the frame period error on the basis of the information on detection timing for each base station.SELECTED DRAWING: Figure 1

Description

The present disclosure relates to a frame period error detection device and an inter-base station synchronization system.

If a mobile station straddles the zone boundary and enters the adjacent zone with two or more signals having a frame timing error at the zone boundary, the mobile station will wait until the frame resynchronization is completed. Communication is cut off. In order to avoid such interruption of communication, it is necessary to match the frame timing at the zone boundary. The inter-base station synchronization system detects an error in the frame period and shifts the transmission timing of the signal transmitted from the base station. As a result, the error of the frame period is corrected, and the frame timing at the zone boundary is matched. In a conventional inter-base station synchronization system, two demodulation units and a synchronization detection unit corresponding to each of the two base stations are provided in order to detect an error in the frame period between adjacent base stations (for example,). See Patent Document 1).

Japanese Unexamined Patent Publication No. 2001-268628

As described above, when the device that detects the error of the frame period requires a plurality of demodulation units and synchronization detection units corresponding to a plurality of base stations, the number of demodulation units and synchronization detection units is the number of base stations. The cost increases because it increases accordingly.

The present disclosure has been made in order to solve the above-mentioned problems, and an object of the present disclosure is to provide a frame period error detection device that realizes cost reduction.

The frame period error detection device according to the present disclosure detects a frame period error corresponding to a difference in reception timing of a plurality of signals transmitted from a plurality of base stations. The frame period error detector includes a receiver and an error detector. The receiver is provided in common for a plurality of base stations, receives a plurality of signals, and generates demodulation data corresponding to each of the plurality of signals. The error detector detects an error in the frame period of a plurality of signals based on the detection timing of the synchronous word included in the demodulated data. The error detector includes a storage unit and an error calculation unit. The storage unit stores information on the detection timing of synchronous words for each base station. The error calculation unit detects an error in the frame period based on the detection timing information for each base station.

According to the present disclosure, it is possible to provide a frame period error detection device that realizes cost reduction.

The purposes, features, aspects, and advantages of the present disclosure will be made clear by the following detailed description and accompanying drawings.

It is a block diagram which shows the structure of the frame period error detection apparatus and the synchronization system between base stations in Embodiment 1. FIG. It is a block diagram which shows the structure of the error detector in Embodiment 1. FIG. It is a timing chart which shows the operation of the frame period error detection apparatus in Embodiment 1. FIG. It is a figure which shows an example of the structure of the processing circuit included in the frame period error detection apparatus. It is a figure which shows another example of the structure of the processing circuit included in the frame period error detection apparatus. It is a flowchart which shows the synchronization method between base stations in Embodiment 1. FIG. It is a block diagram which shows the structure of the frame period error detection apparatus and the synchronization system between base stations in Embodiment 2. FIG. It is a figure which shows typically the frequency response of the signal processed by each functional part. It is a block diagram which shows the structure of the frame period error detection apparatus and the synchronization system between base stations in Embodiment 3. FIG.

<Embodiment 1>
FIG. 1 is a block diagram showing a configuration of a frame period error detection device 100 and an inter-base station synchronization system 200 according to the first embodiment.

The inter-base station synchronization system 200 includes a frame period error detection device 100, two base stations (first base station 110 and second base station 120), and two leakage coaxial cables (first leakage coaxial cable 130 and second leakage coaxial cable). Cable 140) is included. The first leakage coaxial cable 130 connects the first base station 110 and the frame period error detection device 100. The second leakage coaxial cable 140 connects the second base station 120 and the frame period error detection device 100. The communicable zone provided by the first leaky coaxial cable 130 and the communicable zone provided by the second leaky coaxial cable 140 are adjacent to each other. The first leaky coaxial cable 130 and the second leaky coaxial cable 140 are provided, for example, along a railroad track or a road. Further, in the first embodiment, the carrier frequency of the signal output from the first base station 110 to the first leakage coaxial cable 130 is the carrier wave of the signal output from the second base station 120 to the second leakage coaxial cable 140. It may be the same as or different from the frequency.

The frame period error detection device 100 is provided at the zone boundary of the first leakage coaxial cable 130 and the second leakage coaxial cable 140. The frame period error detection device 100 detects an error in the frame period of two signals transmitted from the first base station 110 and the second base station 120, respectively. The frame period error corresponds to the difference between the reception timings of the two signals at the zone boundary. The frame period error detection device 100 includes a receiver 10 and an error detector 20.

The receiver 10 is commonly provided for the first base station 110 and the second base station 120. In other words, one receiver 10 is provided for the first base station 110 and the second base station 120. The receiver 10 receives two signals and generates demodulation data corresponding to each signal. The receiver 10 includes a selection unit 11, a demodulation unit 12, and a synchronization detection unit 13. The error detector 20 detects the error of the frame period of the two signals based on the detection timing within one frame of the synchronous word included in the demodulated data. FIG. 2 is a block diagram showing the configuration of the error detector 20 according to the first embodiment. The error detector 20 includes a counter unit 21, a storage unit 22, and an error calculation unit 23.

The selection unit 11 switches the input source to the demodulation unit 12 at a predetermined time so that the signal transmitted from one of the two signals is input to the demodulation unit 12. The selection unit 11 in the first embodiment switches between the first leakage coaxial cable 130 and the second leakage coaxial cable 140 connected to the demodulation unit 12 at regular time intervals. The fixed time interval may be, for example, a frame period, as long as it is a time during which the synchronization detection unit 13 can detect the synchronization word. However, when the synchronization detection unit 13 generates a synchronization detection pulse based on protection conditions for preventing false detection, such as generating a synchronization detection pulse when the synchronization word is detected a plurality of times in succession, the selection unit 11 may generate a synchronization detection pulse. , The frame cycle time may be switched based on the protection condition.

The selection unit 11 has, for example, a mechanical switch for switching between the first leakage coaxial cable 130 and the second leakage coaxial cable 140 connected to the demodulation unit 12. Alternatively, the selection unit 11 may have a semiconductor switch such as a PIN diode or a FET (Field Effect Transistor). In that case, the selection unit 11 converts the signal input from one of the leaky coaxial cables into a digital value by the analog-digital conversion circuit, and outputs the signal to the demodulation unit 12. Alternatively, the selection unit 11 may select one of the two digital values converted by the analog-digital conversion circuit provided for each leakage coaxial cable and output it to the demodulation unit 12.

The demodulation unit 12 receives a signal propagating from one of the leaky coaxial cables switched by the selection unit 11, that is, a signal transmitted from one of the base stations, and generates demodulation data. After a lapse of a certain period of time, the demodulation unit 12 receives a signal propagating from the other leaky coaxial cable, that is, a signal transmitted from the other base station, and generates demodulation data. FIG. 3 is a timing chart showing the operation of the frame period error detection device 100 according to the first embodiment. The demodulated data shown at the timing on the left side of FIG. 3 corresponds to the signal transmitted from the first base station 110 via the first leakage coaxial cable 130. The demodulated data shown at the timing on the right side of FIG. 3 corresponds to the signal transmitted from the second base station 120 via the second leakage coaxial cable 140. Only the signal transmitted from one of the base stations is selectively demodulated by the demodulation unit 12. The demodulated data includes the synchronous word data SW and the signal data SD. Here, the synchronous word data SW is included at the beginning of the demodulated data in one frame. The demodulated data for each frame may be continuously generated or discontinuously generated between the timing on the left side and the timing on the right side. In any case, the timing on the left side and the timing on the right side correspond to an integral multiple of the frame period, and correspond to the clear interval of the counter described later.

The synchronization detection unit 13 detects the synchronization word data SW included in the demodulation data of one frame. The synchronization detection unit 13 outputs a synchronization detection pulse corresponding to the detection timing of the synchronization word to the error detector 20.

The counter unit 21 includes a counter that is reset every frame. In other words, the counter clears the counter value at the frame cycle and counts up again. The frame period used for the clear operation may be the frame period of any of the first base station 110 and the second base station 120. This is because all base stations use the same clock source due to GPS (Global Positioning System) synchronization and the like. When the first base station 110 and the second base station 120 cannot use the same clock source due to a failure or the like, that is, when the clock sources are not common, the counter unit 21 uses the frame of the base station for which GPS synchronization has been established. You may choose the period. The reason why the counter unit 21 clears the counter in the frame cycle is that the synchronous word included in the demodulated data is included for each frame. For example, when the counter unit 21 clears the counter at a cycle exceeding two frames, two synchronous words are detected. As a result, the frame period error detecting device 100 includes the possibility of erroneously detecting the error of the frame period.

The storage unit 22 stores information on the detection timing of synchronous words for each base station. Here, the storage unit 22 stores the counter value corresponding to the timing of the synchronization detection pulse as the information of the detection timing of the synchronization word. For example, as shown in FIG. 3, the counter value when the counter unit 21 receives the synchronous detection pulse for the demodulated data of the first base station 110 is “3”. The first storage unit 22A stores the counter value “3” as detection timing information. On the other hand, the counter value when the counter unit 21 receives the synchronous detection pulse for the demodulated data of the second base station 120 is “4”. The second storage unit 22B stores the counter value “4” as detection timing information. The first storage unit 22A and the second storage unit 22B may be the same storage device or may be separate storage devices.

The error calculation unit 23 detects an error in the frame period based on the detection timing information for each base station. Specifically, the error calculation unit 23 calculates the difference between the two counter values stored in the first storage unit 22A and the second storage unit 22B, respectively. Then, the error calculation unit 23 detects the error of the frame period based on the difference and the information of the clock period when the counter unit 21 counts up. In the example of FIG. 3, the difference between the two counter values is "1". When the clock period is 2 kHz, the error of the frame period of the two signals is 1/2000 × 1 = 0.0005 s. However, if the clock frequencies used for counting up are unified in advance in the entire base station synchronization system 200 and are self-evident, the error calculation unit 23 can detect the error of the frame period only by the difference of the counter values. ..

At least one of the first base station 110 and the second base station 120 transmits a signal whose transmission timing is corrected to the leakage coaxial cable based on the frame cycle error detected by the frame cycle error detection device 100. Output. The correction of the transmission timing is performed, for example, by cutting off an extra wiring length provided in advance in the leaky coaxial cable on the base station side. Alternatively, the base station may acquire information on the error of the frame period and shift the transmission timing of the signal output to the leaky coaxial cable according to the information.

FIG. 4 is a diagram showing an example of the configuration of the processing circuit 90 included in the frame period error detection device 100. Each function of the demodulation unit 12, the synchronization detection unit 13, the counter unit 21, the storage unit 22, and the error calculation unit 23 is realized by, for example, the processing circuit 90. In that case, the processing circuit 90 includes a demodulation unit 12, a synchronization detection unit 13, a counter unit 21, a storage unit 22, and an error calculation unit 23.

When the processing circuit 90 is dedicated hardware, the processing circuit 90 may be, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), or an FPGA (Field). -Programmable Gate Array), or a circuit that combines these. The functions of the demodulation unit 12, the synchronization detection unit 13, the counter unit 21, the storage unit 22, and the error calculation unit 23 may be individually realized by a plurality of processing circuits, or may be collectively realized by one processing circuit. May be good.

FIG. 5 is a diagram showing another example of the configuration of the processing circuit included in the frame period error detection device 100. The processing circuit includes a processor 91 and a memory 92. By executing the program stored in the memory 92 by the processor 91, the functions of the demodulation unit 12, the synchronization detection unit 13, the counter unit 21, the storage unit 22, and the error calculation unit 23 are realized. For example, each function is realized by executing software or firmware described as a program by the processor 91. As described above, the frame period error detection device 100 has a memory 92 for storing the program and a processor 91 for executing the program.

In the program, the frame period error detection device 100 switches the input source at a predetermined time so that the signal transmitted from one of the plurality of signals is input, and is transmitted from one base station. The demodulation data corresponding to the signal is generated, the synchronization detection pulse corresponding to the detection timing within one frame of the synchronization word included in the demodulation data is output, and the counter value is reset every frame and is the synchronization detection pulse. The function of storing the counter value corresponding to the timing of is stored for each base station as the information of the detection timing of the synchronous word and detecting the error of the frame period based on the information of the detection timing for each base station is described. Further, the program causes the computer to execute the procedure or method of the demodulation unit 12, the synchronization detection unit 13, the counter unit 21, the storage unit 22, and the error calculation unit 23.

The processor 91 is, for example, a CPU (Central Processing Unit), an arithmetic unit, a microprocessor, a microcomputer, a DSP (Digital Signal Processor), or the like. The memory 92 is a non-volatile or volatile memory such as a RAM (Random Access Memory), a ROM (Read Only Memory), a flash memory, an EPROM (Erasable Programmable Read Only Memory), or an EEPROM (Electrically Erasable Programmable Read Only Memory). It is a semiconductor memory. Alternatively, the memory 92 may be any storage medium used in the future, such as a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, or a DVD.

Some of the functions of the demodulation unit 12, the synchronization detection unit 13, the counter unit 21, the storage unit 22, and the error calculation unit 23 described above are realized by dedicated hardware, and some of them are realized by software or firmware. You may. In this way, the processing circuit realizes each of the above-mentioned functions by hardware, software, firmware, or a combination thereof.

Next, the operations of the frame period error detection device 100 and the inter-base station synchronization system 200 will be described. FIG. 6 is a flowchart showing a synchronization method between base stations according to the first embodiment.

In step S11, the selection unit 11 switches to the connection with the first leakage coaxial cable 130. That is, the selection unit 11 switches the input source so that the signal transmitted from the first base station 110 is input.

In step S12, the demodulation unit 12 generates demodulation data corresponding to the signal transmitted from the first base station 110.

In step S13, the synchronization detection unit 13 detects the synchronization word included in the demodulated data in one frame. The synchronization detection unit 13 outputs a synchronization detection pulse corresponding to the detection timing of the synchronization word.

In step S14, the first storage unit 22A stores the counter value corresponding to the timing of the synchronization detection pulse.

In step S15, the selection unit 11 switches to the connection with the second leakage coaxial cable 140. That is, the selection unit 11 switches the input source so that the signal transmitted from the second base station 120 is input.

In step S16, the demodulation unit 12 generates demodulation data corresponding to the signal transmitted from the second base station 120.

In step S17, the synchronization detection unit 13 detects the synchronization word included in the demodulated data in one frame. The synchronization detection unit 13 outputs a synchronization detection pulse corresponding to the detection timing of the synchronization word.

In step S18, the second storage unit 22B stores the counter value corresponding to the timing of the synchronization detection pulse.

In step S19, the error calculation unit 23 obtains the difference between the counter value of the first storage unit 22A and the counter value of the second storage unit 22B. The error calculation unit 23 detects the error of the frame period based on the difference and the information of the clock period.

In step S20, the first base station 110 or the second base station 120 outputs a signal whose transmission timing has been corrected based on the frame cycle error detected by the frame cycle error detection device 100 to the leaky coaxial cable. ..

This completes the inter-base station synchronization method.

The frame period error detection device 100 described above switches between the two leakage coaxial cables that are the input sources to the demodulation unit 12 by the selection unit 11. However, the configuration of the frame period error detection device 100 is not limited to this. The frame period error detection device 100 may detect an error in the frame period while switching three or more leaky coaxial cables in order by the selection unit 11. In this case, the frame period error detection device 100 may have the same number of storage units as the number of connected leakage coaxial cables, and each of these storage units may store information on the detection timing of the synchronous word.

Alternatively, the frame period error detection device 100 may have two storage units, and one storage unit may store the synchronous word detection timing in the signal received from one leakage coaxial cable as a reference. Then, the other storage unit may sequentially store the detection timings of the synchronous words in the signals received from the remaining two or more leaky coaxial cables by the switching operation of the selection unit 11. The frame cycle error detection device 100 may obtain the error of the frame cycle based on one detection timing which is a reference and the other detection timing which is stored in order.

Specifically, the first storage unit 22A stores the counter value when the synchronous detection pulse of the signal received from the reference leakage coaxial cable arrives. The second storage unit 22B stores the counter value when the synchronous detection pulse of the signal received from one of the leakage coaxial cables selected by the selection unit 11 among the other plurality of leakage coaxial cables arrives. The error calculation unit 23 obtains the difference between the value stored in the first storage unit 22A and the value stored in the second storage unit 22B. The error calculation unit 23 calculates the error of the frame period based on the difference and the clock frequency of the counter. Then, the selection unit 11 switches to the next leaky coaxial cable among the plurality of other leaky coaxial cables that are not the reference. The second storage unit 22B stores the counter value when the synchronous detection pulse arrives, and the error calculation unit 23 calculates the error of the frame period. This operation may be repeated.

Summarizing the above, the frame period error detection device 100 according to the first embodiment detects a frame period error corresponding to a difference in reception timing of a plurality of signals transmitted from a plurality of base stations. The frame period error detection device 100 includes a receiver 10 and an error detector 20. The receiver 10 is provided in common for a plurality of base stations, receives a plurality of signals, and generates demodulation data corresponding to each of the plurality of signals. The error detector 20 detects an error in the frame period of a plurality of signals based on the detection timing of the synchronous word included in the demodulated data. The error detector 20 includes a storage unit 22 and an error calculation unit 23. The storage unit 22 stores information on the detection timing of synchronous words for each base station. The error calculation unit 23 detects an error in the frame period based on the detection timing information for each base station.

In such a configuration, the receiver 10 is commonly provided for a plurality of base stations. Therefore, the cost of the frame period error detection device 100 can be reduced. Specifically, it has the effects of lowering the price, downsizing, power saving, and heat generation of the device. It also has the effect of reducing maintenance costs.

Further, the receiver 10 of the frame period error detection device 100 according to the first embodiment includes a demodulation unit 12 and a selection unit 11. The demodulation unit 12 generates demodulation data. The selection unit 11 switches the input source to the demodulation unit 12 at a predetermined time so that the signal transmitted from one of the plurality of signals is input to the demodulation unit 12.

With such a configuration, the frame period error detection device 100 does not require a plurality of receivers 10 corresponding to a plurality of base stations. Therefore, the cost of the frame period error detection device 100 can be reduced.

Further, the receiver 10 of the frame period error detection device 100 in the first embodiment includes a synchronization detection unit 13. The synchronization detection unit 13 outputs a synchronization detection pulse corresponding to the detection timing within one frame of the synchronization word. The error detector 20 includes a counter unit 21. The counter unit 21 includes a counter that is reset every frame. The storage unit 22 stores the value of the counter based on the synchronization detection pulse as the information of the detection timing of the synchronization word.

With such a configuration, the frame period error detecting device 100 can accurately or easily detect the error of the frame period.

Further, the inter-base station synchronization system 200 according to the first embodiment includes the above-mentioned frame period error detection device 100, a plurality of base stations, and a leakage coaxial cable. The leaky coaxial cable connects each of the plurality of base stations to the frame period error detection device 100. At least one of the plurality of base stations outputs a signal whose transmission timing is corrected based on the frame cycle error detected by the frame cycle error detection device 100 to the leakage coaxial cable.

With such a configuration, the cost of the inter-base station synchronization system 200 can be reduced.

<Embodiment 2>
The frame period error detection device 101 and the inter-base station synchronization system 201 according to the second embodiment will be described. The same configuration and operation as in the first embodiment will not be described.

FIG. 7 is a block diagram showing the configuration of the frame period error detection device 101 and the inter-base station synchronization system 201 according to the second embodiment. FIG. 8 is a diagram schematically showing the frequency response of the signal processed by each functional unit.

In the second embodiment, the carrier frequency of the signal output from the first base station 110 to the first leakage coaxial cable 130 is the carrier frequency of the signal output from the second base station 120 to the second leakage coaxial cable 140. Is different. However, the content of the signal (baseband signal) in the baseband before frequency conversion into the band of each carrier frequency is the same.

The frame period error detection device 101 includes a receiver 10A and an error detector 20. The receiver 10A includes a synthesis unit 14, a filter unit 15, a demodulation unit 12, and a synchronization detection unit 13. The configuration of the demodulation unit 12, the synchronization detection unit 13, and the error detector 20 is the same as that of the first embodiment.

The synthesis unit 14 collectively receives two signals transmitted from the first base station 110 and the second base station 120 at different carrier frequencies. The synthesis unit 14 adds these two signals to generate a synthesis signal. The synthesis unit 14 performs analog-to-digital conversion processing on the composite signal.

The filter unit 15 separates signals having two carrier frequencies from the synthesized signal by performing digital frequency conversion processing on the synthesized signal subjected to analog-digital conversion processing, and further, a signal having one carrier frequency among them. Is extracted. Further, in the digital frequency conversion process, the filter unit 15 switches the frequency band to be extracted at a predetermined time. As a result, signals having two carrier frequencies, that is, a signal transmitted from the first base station 110 and a signal transmitted from the second base station 120, are alternately extracted at regular time intervals. The fixed time interval is the same as in the first embodiment.

The demodulation unit 12 receives a signal of one carrier frequency extracted by the filter unit 15 and generates demodulation data. After a lapse of a certain period of time, the demodulation unit 12 receives a signal of the other carrier frequency and generates demodulation data.

The synchronization detection unit 13 detects synchronous words included in the demodulated data in one frame. The synchronization detection unit 13 outputs a synchronization detection pulse corresponding to the detection timing of the synchronization word to the error detector 20.

The error detector 20 includes the same configuration as that of the first embodiment. The error detector 20 detects an error in the frame period of the two signals based on the detection timing of the synchronous word.

At least one of the first base station 110 and the second base station 120 transmits a signal whose transmission timing is corrected to the leakage coaxial cable based on the frame cycle error detected by the frame cycle error detection device 101. Output.

The functions of the synthesis unit 14, the filter unit 15, the demodulation unit 12, and the synchronization detection unit 13 of the receiver 10A are realized by, for example, the processing circuit shown in FIG. 4 or FIG.

Summarizing the above, the receiver 10A of the frame period error detection device 101 according to the second embodiment includes a synthesis unit 14, a filter unit 15, and a demodulation unit 12. The synthesis unit 14 collectively receives a plurality of signals transmitted from a plurality of base stations at different carrier frequencies to generate a synthesis signal. The filter unit 15 performs frequency conversion processing on the composite signal and extracts a signal having one carrier frequency from the composite signal. The demodulation unit 12 generates demodulation data corresponding to the signal of the one carrier frequency. The filter unit 15 switches the frequency band to be extracted in the frequency conversion process at a predetermined time.

With such a configuration, the cost of the frame period error detection device 101 can be reduced. Further, the frame period error detection device 101 can detect the frame period error even when the carrier frequencies of the signals transmitted from the base station are different. Such a frame period error detection device 101 can also be applied to a redundant system in which the carrier frequency bands are separated.

Further, the frame period error detection device 101 according to the second embodiment has the same effect as described above even if it is connected to three or more base stations.

<Embodiment 3>
The frame period error detection device 102 and the inter-base station synchronization system 202 according to the third embodiment will be described. The description of the configuration and operation similar to those of the first or second embodiment will be omitted.

FIG. 9 is a block diagram showing the configuration of the frame period error detection device 102 and the inter-base station synchronization system 202 according to the third embodiment.

In the third embodiment, the carrier frequency of the signal output from the first base station 110 to the first leakage coaxial cable 130 is the carrier frequency of the signal output from the second base station 120 to the second leakage coaxial cable 140. It is the same. Further, the modulation method of these two signals is frequency modulation.

The frame period error detection device 102 includes a multiplier 31, a filter unit 32, a storage unit 33, and an error time calculation unit 34.

The multiplier 31 generates a multiplication signal by collectively receiving and multiplying two signals transmitted from the first base station 110 and the second base station 120 at the same carrier frequency. The multiplied signal includes a frequency component of the modulated signal that is close to the DC component and a frequency component that is twice the sum of the carrier frequency and the frequency of the modulated signal.

The filter unit 32 removes a frequency component twice the sum of the carrier frequency and the frequency of the modulated signal from the multiplication signal by a low-pass filter, and extracts only a frequency component close to the DC component. That is, the filter unit 32 extracts the beat pattern of the multiplication signal.

Both the synchronous word contained in the signal transmitted from the first base station 110 and the synchronous word included in the signal transmitted from the second base station 120 have a known signal pattern. Therefore, a unique beat pattern is formed in the multiplication signal according to the degree of error in the frame period of the two signals. The beat pattern is obtained by the following equation (1). In the formula (1), Bp represents a signal obtained by removing a signal having a frequency component twice the sum of the carrier frequency and the frequency of the modulated signal from the multiplication signal, that is, a beat pattern. f _Lo represents the carrier frequency, f _fm represents the frequency of the signal (modulated signal) whose synchronous word is frequency-modulated, t represents the time, and t _gosa represents the difference in reception timing, that is, the error in the frame period.

In equation (1), "+ (1/2) x {cos (2π (f _Lo + f _fm ) t + (f _Lo + f _fm ) (t + t _gosa )}" is the carrier frequency and the frequency of the modulated signal. It is shown that the frequency component twice the sum of and is removed by the low-pass filter _{. The value of Bp} changes according to the value of t gosa as shown in the equation (1). The beat pattern changes according to the degree of error in the frame period. For example, when t _gosa is 0, Bp = 0.5.

The storage unit 33 stores in advance a plurality of beat patterns corresponding to a plurality of errors in the frame periods of the two signals. For example, the storage unit 33 stores the above equation (1). _{Alternatively} , for example, the storage unit 33 stores a plurality of beat patterns according to t gosa obtained from the equation (1) as a table.

The error time calculation unit 34 detects an error in the frame period of the two signals based on the beat pattern extracted by the filter unit 32 and the plurality of beat patterns stored in advance in the storage unit 33. When the storage unit 33 stores the equation (1), the error time calculation unit 34 _{compares the} beat pattern obtained by performing the calculation while changing t gosa with the beat pattern extracted by the filter unit 32. do. Alternatively, when the storage unit 33 stores a plurality of beat patterns according to the degree of error in the frame period as a table, the error time calculation unit 34 uses the beat patterns stored in the table and the filter unit 32. Compare with the extracted beat pattern. The error time calculation unit 34 _{detects t gosa} when both match as an error of the frame period.

At least one of the first base station 110 and the second base station 120 transmits a signal whose transmission timing is corrected to the leakage coaxial cable based on the frame cycle error detected by the frame cycle error detection device 102. Output.

The functions of the multiplier 31, the filter unit 32, the storage unit 33, and the error time calculation unit 34 are realized by, for example, the processing circuit shown in FIG. 4 or FIG.

Summarizing the above, the frame period error detection device 102 according to the third embodiment detects the frame period error corresponding to the difference in reception timing of the two signals transmitted from the two base stations. The frame period error detection device 102 includes a multiplier 31, a filter unit 32, a storage unit 33, and an error time calculation unit 34. The multiplier 31 generates a multiplication signal by collectively receiving and multiplying two signals transmitted from two base stations at the same carrier frequency. The filter unit 32 extracts a beat pattern by removing a frequency component twice the sum of the carrier frequency and the frequency of the modulated signal from the multiplication signal. The storage unit 33 stores in advance a plurality of beat patterns corresponding to a plurality of errors in the frame periods of the two signals. The error time calculation unit 34 detects an error in the frame period of the two signals based on the beat pattern extracted by the filter unit 32 and the plurality of beat patterns stored in advance in the storage unit 33.

With such a configuration, the cost of the frame period error detection device 102 can be reduced. Further, the frame period error detection device 102 can detect the error of the frame period by using the multiplication signal. As shown in the first or second embodiment, the circuit configuration is simplified because the receiver 10 or the receiver 10A does not need to demodulate the signal to find the synchronous word. This is for the purpose of detecting the error of the frame period which is the difference of the reception timing, and in the above-mentioned frame period error detection device 102, the demodulated synchronous word data and other data are detected. This is because it is not used.

In the present disclosure, each embodiment can be freely combined, and each embodiment can be appropriately modified or omitted.

Although the present disclosure has been described in detail, the above description is exemplary in all embodiments and the present disclosure is not limited thereto. It is understood that a myriad of variants not illustrated can be envisioned without departing from the scope of the present disclosure.

10 receiver, 10A receiver, 11 selection section, 12 demodulation section, 13 synchronization detection section, 14 synthesis section, 15 filter section, 20 error detector, 21 counter section, 22 storage section, 22A first storage section, 22B first storage section. 2 storage unit, 23 error calculation unit, 31 multiplier, 32 filter unit, 33 storage unit, 34 error time calculation unit, 100 frame period error detection device, 101 frame period error detection device, 102 frame period error detection device, 110th 1 base station, 120 2nd base station, 130 1st leak coaxial cable, 140 2nd leak coaxial cable, 200 inter-base station synchronization system, 201 inter-base station synchronization system, 202 inter-base station synchronization system, SD signal data, SW Synchronous word data.

Claims (7)

A frame cycle error detection device that detects a frame cycle error corresponding to a difference in reception timing of a plurality of signals transmitted from a plurality of base stations.
A receiver that is commonly provided for the plurality of base stations, receives the plurality of signals, and generates demodulation data corresponding to each of the plurality of signals.
An error detector that detects the error of the frame period of the plurality of signals based on the detection timing of the synchronous word included in the demodulated data is provided.
The error detector
A storage unit that stores information on the detection timing of the synchronous word for each base station, and
A frame cycle error detection device including an error calculation unit that detects the error of the frame cycle based on the information of the detection timing for each base station. The receiver
The demodulation unit that generates the demodulation data and
1. The first aspect of the present invention includes a selection unit that switches an input source to the demodulation unit at a predetermined time so that a signal transmitted from one of the plurality of signals is input to the demodulation unit. The frame period error detection device according to. The receiver
A compositing unit that collectively receives the plurality of signals transmitted from the plurality of base stations at different carrier frequencies and generates a composite signal, and a compositing unit.
A filter unit that performs frequency conversion processing on the composite signal and extracts a signal having one carrier frequency from the composite signal.
A demodulation unit that generates the demodulation data corresponding to the signal of the one carrier frequency is included.
The frame period error detection device according to claim 1, wherein the filter unit switches the frequency band to be extracted in the frequency conversion process at a predetermined time. The receiver
Further including a synchronization detection unit that outputs a synchronization detection pulse corresponding to the detection timing within one frame of the synchronization word.
The error detector
A counter unit including a counter that is reset every frame is further included.
The storage unit
The frame period error detection device according to any one of claims 1 to 3, which stores the value of the counter based on the synchronization detection pulse as the information of the detection timing of the synchronization word. The frame period error detection device according to any one of claims 1 to 4.
With the plurality of base stations
A leaky coaxial cable for connecting each of the plurality of base stations and the frame period error detection device is provided.
At least one of the plurality of base stations outputs a signal whose transmission timing is corrected based on the error of the frame period detected by the frame period error detection device to the leaky coaxial cable. , Base station synchronization system. It is a frame cycle error detection device that detects a frame cycle error corresponding to the difference in reception timing of two signals transmitted from two base stations, respectively.
A multiplier that generates a multiplication signal by collectively receiving and multiplying the two signals transmitted from the two base stations at the same carrier frequency.
A filter unit that extracts a beat pattern by removing a frequency component that is twice the sum of the carrier frequency and the frequency of the modulated signal from the multiplication signal.
A storage unit that stores a plurality of beat patterns corresponding to a plurality of errors in the frame period of the two signals in advance, and a storage unit.
An error time calculation unit that detects the error of the frame period of the two signals based on the beat pattern extracted by the filter unit and the plurality of beat patterns stored in advance in the storage unit. A frame period error detector comprising. The frame period error detection device according to claim 6 and
The two base stations and
A leaky coaxial cable for connecting each of the two base stations and the frame period error detection device is provided.
At least one of the two base stations outputs a signal whose transmission timing is corrected based on the error of the frame period detected by the frame period error detection device to the leakage coaxial cable. , Base station synchronization system.

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