JP2002185373A - Receiver having antenna selecting diversity function for spectrum spread communication - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a reproduction of data in a short time in a spectrum spread communication utilizing a selecting diversity. SOLUTION: A selector 11 selectively outputs a signal received by an antenna 1 or 2 according to a designation from a diversity circuit 21. A correlation circuit 12 reversely spreads a signal selected by the selector 11. A synchronizing circuit 13 establishes a sign synchronization based on an output of the circuit 12. An AFC circuit 16 corrects phase information. A decoding circuit 17 reproduces data from the corrected phase information. During a period in which the one antenna is selected, information detected or generated from the signal received via another antenna is held in a register 22. When the other antenna is selected, synchronization establishment is executed by utilizing the information held in the register 22.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a receiver having an antenna selection diversity function in spread spectrum communication, and more particularly to a technique for establishing synchronization when switching antennas.

[0002]

2. Description of the Related Art Spread spectrum communication is known as one of wireless communication systems. In spread spectrum communication, data is spread using a spreading code and transmitted. Then, the receiver reproduces data by despreading the received signal using the same code as the spreading code used in the transmitter. The spread spectrum communication method is a fundamental technology for realizing CDMA (Code Division Multiple Access).

[0003] In spread spectrum communication, a diversity technique is known as a method for reproducing a signal in a poor radio environment. Selection diversity and maximum ratio combining are known as diversity techniques. Hereinafter, selection diversity that is directly related to the present invention will be briefly described.

[0004] Selection diversity is usually realized by providing a plurality of antennas in a receiving apparatus and selecting the most reliable signal among signals received via each antenna. In this case, for example, an optimum antenna can be selected by multiplying a signal received via each antenna by a spreading code and comparing the respective correlation values.

However, in mobile communication systems and the like, since there is a strong demand for miniaturization of each mobile station and reduction in power consumption, it is not preferable to configure redundant circuits for selection diversity. That is, it is not preferable to provide a plurality of reception demodulation circuits for selection diversity. For this reason, in a receiving apparatus employing selection diversity, one receiving demodulation circuit is usually provided for a plurality of antennas, and a signal received via an appropriately selected antenna is demodulated by the receiving modulation circuit. It has become. In this receiving apparatus, when signal reception is started, an antenna to be used is switched at predetermined time intervals, so that an optimal antenna is selected.

[0006]

In spread spectrum communication, a receiving demodulation circuit needs to perform processing for establishing synchronization of spread codes at the start of signal reception. Further, when the transmitting apparatus and the receiving apparatus transmit and receive signals using oscillators independent of each other, the reception demodulation circuit uses an AFC (Auto Frequency Control) to correct an error in the oscillation frequency of the oscillators.
matic FrequencyControl). Each of these processes requires a relatively long time (for example, about several μ to several tens μ seconds).

[0007] For this reason, in a receiving apparatus employing selection diversity, it takes a long time to reproduce correct data at the start of signal reception. In particular,
Whenever the antenna to be used for determining the optimum antenna is switched, the above-described synchronization establishment processing and AFC processing are executed each time, so that it takes a long time.

FIG. 14 is a diagram for explaining the above problem. Here, the receiving device has two antennas. Also, this figure shows a state in which the optimum antenna is searched for while switching the antenna to be used every period T at the start of signal reception.

[0009] Between times T1 and T2, synchronization establishment processing and AFC processing are performed on the signal received via the antenna 1. Then, a correlation value or the like of the signal received via the antenna 1 is calculated. Subsequently, at times T2 to T
In 3, synchronization establishment processing and AFC processing are performed on a signal received via the antenna 2, and similarly, a correlation value and the like for the signal are calculated. Thereafter, the same processing is repeated for antennas 1 and 2 in order to increase reliability. For example, between times T3 and T4, the signal received via the antenna 1 is again subjected to synchronization establishment processing and A
The FC process is executed to calculate a correlation value and the like. However,
The processing for each cycle is executed independently of each other.

As described above, in the existing receiving apparatus,
Each time the antenna is switched, the synchronization establishment process and the AFC process are executed independently. Therefore, in order to complete the synchronization establishment processing and the AFC processing within each cycle, the cycle T needs to be lengthened, and the throughput decreases. That is, it takes a long time to reproduce correct data.

Note that this problem may occur not only at the start of signal reception, but also with respect to synchronization establishment and AFC after the antenna to be used is determined. An object of the present invention is to make it possible to reproduce data in a short time in spread spectrum communication using selection diversity.

[0012]

A receiving apparatus according to the present invention has an antenna selection diversity function in spread spectrum communication, a plurality of antennas for receiving signals, a selector for selecting one antenna from the plurality of antennas,
Reproducing means for reproducing data from a signal received via the antenna selected by the selector; holding means for holding information detected or generated from the signal by the reproducing means; and From the state in which the first antenna is selected, the second
When the antenna is switched to the selected state, the information detected or reproduced by the reproducing means from the signal received through the first antenna is written into the holding means, and the information is transmitted through the second antenna. Control means for reading, from the holding means, information detected or reproduced in the past by the reproducing means from the received signal.
Then, the reproducing means reproduces data using the information read from the holding means by the control means.

According to the above configuration, when data is reproduced from a signal received via a certain antenna, information previously detected or generated from a signal received via the antenna can be taken over and used. Can play data. According to another aspect of the present invention, there is provided a receiving apparatus comprising:
A reproducing unit for reproducing data from a signal received through the antenna, and a period in which the reproducing unit reproduces data from the signal received through the first antenna, via the second antenna. Holding information used by the reproducing means when reproducing data from the received signal,
The period during which the reproducing means reproduces data from the signal received via the second antenna is used by the reproducing means when reproducing data from the signal received via the first antenna. Holding means for holding information. Then, the reproducing means reproduces the data using the information held by the holding means. Also in this configuration, as in the above-described configuration, the information held in the past for the same antenna can be effectively used, so that data can be reproduced in a short time.

[0014]

Embodiments of the present invention will be described below with reference to the drawings. The receiving device according to the present embodiment is used in a communication system in which data is transmitted using spread spectrum. Here, the data is transmitted using the spreading code after being multiplied by the spreading code in the transmission device. On the other hand, the receiving apparatus reproduces data by despreading a signal (spread data) transmitted using a spreading code. When extracting a signal from a received wave in the receiving apparatus, it is necessary to remove a carrier component from the received wave. Then, in order to remove the carrier component from the received wave, it is necessary to multiply the received wave by a periodic wave having the same frequency as the carrier.

As a method of preparing a periodic wave having the same frequency as a carrier in a receiving apparatus, a method of reproducing a carrier from a received wave is known. However, when this method is performed, the circuit scale of the receiving device becomes large. Therefore, in the communication system of this embodiment, FIG.
As shown in (1), the transmitting device and the receiving device each include an oscillator that operates independently of each other. Here, the oscillation frequencies of these oscillators are basically the same.

However, the oscillation frequency of the oscillator has manufacturing variations. That is, it is rare that the oscillation frequencies of the oscillators provided in the transmission device and the reception device completely match each other. Therefore, the receiving device has a function for correcting a difference between the oscillation frequencies of the oscillators of the transmitting device and the receiving device. Note that the difference between these oscillation frequencies may be referred to as “offset frequency”, and the phase shift caused by the offset frequency may be referred to as “offset” or “carrier offset”.

Also, in the communication system of this embodiment,
Data is QPSK (QuadriphasePhase Shift Keyin
g) It is assumed that two bits are transmitted in parallel using modulation. In QPSK, 2-bit data is represented by the carrier phase (0 phase, π / 2 phase, π phase, or 3π phase).
/ 2 phase). At this time, the phase of the carrier may be fixedly associated with the 2-bit data, or the shift amount of the phase of the carrier may be associated. Note that the latter method is often called "differential code".

The phase of the carrier is IQ as shown in FIG.
It can be represented as a signal point on a plane. That is, 2
In QPSK, the bit data is converted into information representing a corresponding signal point on the IQ plane. Specifically, the 2-bit data is converted into I component data and Q component data of coordinates representing the corresponding signal point on the IQ plane. Hereinafter, a method of converting 2-bit data into information representing a corresponding signal point on the IQ plane in the operation code will be briefly described. Here, it is assumed that the relationship between each 2-bit data and the corresponding phase shift amount is as follows. 2-bit data (0,0): phase shift amount 0 (0,1): + 3π / 2 (1,0): + π / 2 (1,1): + π Under the above correspondence, for example, n−1 If the n-th 2-bit data is transmitted using the signal point A and the n-th 2-bit data is (0, 1), the n-th 2-bit data sets the phase of the signal point A to “+ 3π / 2”. Is transmitted using the signal point obtained by shifting the signal point (i.e., the signal point D). In this case, the n-th 2-bit data is converted to a point (+1, -1) on the IQ plane.

FIG. 3 is a diagram showing an example of a carrier modulated based on signal points on the IQ plane. The carrier is modulated by data (I component data, Q component data) representing the coordinates of the signal point on the IQ plane obtained based on the 2-bit data. As a result, in FIG. 3, for example, the phase of the carrier wave during the period when the n-th 2-bit data is transmitted is n
It is advanced by “+ 3π / 2” compared to that during the period in which the −1st 2-bit data is transmitted. Therefore, the receiving device can reproduce the 2-bit data transmitted from the transmitting device by detecting the shift amount of the phase of the carrier.

In the above description, the data to be transmitted from the transmitting device to the receiving device is arranged at the corresponding signal point. However, the signal point corresponding to each chip obtained by spreading the data is defined as the corresponding signal point. It may be arranged. In this case, the receiving device recognizes the spread signal by detecting the shift amount of the phase of the carrier wave, and reproduces the data by despreading the spread signal.

FIG. 4 is a block diagram of the receiving apparatus of the present embodiment. This receiver has an antenna selection diversity function and reproduces data from a received radio signal.
The antennas 1 and 2 are independent receiving antennas, and each receive a radio signal. Selector 11
According to an instruction from the diversity circuit 21, one of the signals received via the antennas 1 and 2 is
Lead to 2. Note that the signal selected by the selector 11 is actually removed from the carrier component, decomposed into an I component and a Q component, further converted to a digital signal by an A / D converter, and then sent to the correlation circuit 12. . At this time, the received signal is multiplied by a periodic wave having substantially the same frequency as the carrier used for transmitting the signal and a periodic wave orthogonal to the periodic wave.

The correlation circuit 12 multiplies each of the I-component data sequence and the Q-component data sequence of the received signal by a spreading code. This spreading code is the same as the spreading code used in the transmitting device. FIG. 5 is a circuit diagram of an example of the correlation circuit 12. The circuit for processing the I component data sequence and the circuit for processing the Q component data sequence have basically the same configuration as each other.

The correlation circuit 12 has shift registers 31 of the same number of stages as the number of chips of the spreading code, and stores the input data sequence in order. In the case where the above-mentioned A / D converter (not shown) performs n-times oversampling, the number of stages of the shift register 31 is n times the number of chips of the spread code. The spreading code storage register 34 stores a spreading code. The multiplication circuit 32 has the same number of exclusive NOR circuits as the number of stages of the shift register 31. Each time a new data element is input to the shift register 31, the multiplication circuit 32 spreads the data sequence held in the shift register 31 The multiplication by the spread code stored in the code storage register 34 is performed. Then, the adding unit 33 calculates each exclusive N
The sum of the operation results of the OR circuit is output as correlation value data. Thus, the correlation circuit 12 sequentially outputs correlation value data every time a new data element is input.

The synchronization circuit 13 includes a synchronization detection circuit 14 for establishing code synchronization and a phase detection circuit 15 for detecting the phase of a received signal. FIG. 6 is a schematic flowchart showing the operation of the synchronization detection circuit 14. In step S1, the maximum value of the correlation value data output from the correlation circuit 12 is detected for each symbol period, and the timing at which the maximum value is obtained is detected. Note that this timing is represented by a count value of a timing counter that operates according to a clock. Here, the timing counter, for example, according to the clock of the chip period of the spreading code (1/2 cycle of the number of chips in the case of double oversampling), the number of chips (in the case of double oversampling, the number of chips). The counting operation is cyclically repeated with a cycle of (2 times). In the example shown in FIG. 7, the timing counter can take a value from “0” to “21”. Further, in the example shown in FIG. 7, the maximum value of the correlation value data is obtained at “timing counter = 7”.

In step S2, it is checked whether or not the timing at which the maximum value was obtained in the previous symbol period coincides with the timing at which the maximum value was obtained in the current symbol period. In this determination, the count value of the timing counter is compared. If they match each other, the count value of the synchronization counter is incremented in step S3. On the other hand, if the timings do not match, the synchronization counter is reset in step S4.

In step S5, it is determined whether or not the count value of the synchronous counter is a predetermined value set in advance. If the count value is a predetermined value, it is regarded that code synchronization has been established, and a synchronization establishment flag is set in step S6. On the other hand, if the count value has not reached the predetermined value, the process returns to step S1 to execute the processing of steps S1 to S4 for the next symbol.

As described above, when the maximum value of the correlation value data is repeatedly detected a predetermined number of times at a predetermined timing, the synchronization detection circuit 14 regards that code synchronization has been established.
The phase detection circuit 15 detects a phase for each symbol. Specifically, for example, the phase is detected based on the I component and the Q component at the timing when the maximum value of the correlation value data is obtained. However, the phase detected by the phase detection circuit 15 includes the influence of the carrier offset. The effect of this carrier offset is caused by the AFC circuit 1
6 is corrected.

FIG. 8 is a block diagram of the AFC circuit 16. After the code synchronization is established, the AFC circuit 16 removes the influence of the carrier offset from the phase data detected by the phase detection circuit 15. The comparator 41
The phase data detected by the phase detection circuit 15 and NC
The phase correction data generated by the O (numerically controlled oscillator) 43 is calculated, and the error is output. Loop filter 4
2 outputs a signal corresponding to the carrier offset based on the error. The NCO 43 calculates the output of the loop filter 42 and outputs phase correction data. In the above configuration, the correct phase (the phase from which the influence of the carrier offset has been removed) can be obtained by subtracting the phase correction data from the phase data detected by the phase detection circuit 15. Then, this phase is given to the decoding circuit 17.

FIG. 9 is a schematic flowchart showing the operation of the AFC circuit 16. In step S11, an error between the input phase and the correction phase is calculated. The method of calculating the error is as described with reference to FIG.
In step S12, it is checked whether the error calculated in step S11 is smaller than a predetermined value set in advance. If the error is smaller than the predetermined value, in step S13, the count value of the AFC lock counter is incremented. On the other hand, if the error is larger than the predetermined value, the AFC
Reset the lock counter.

In step S15, it is determined whether the count value of the AFC lock counter is a predetermined value set in advance. If the count value is a predetermined value, it is considered that the operation of the AFC circuit 16 has sufficiently converged, and the AFC lock flag is set in step S16. On the other hand, if the count value has not reached the predetermined value, the process returns to step S11. In the data reception mode, that is, after the operation of the AFC circuit 16 has sufficiently converged,
The gain of the loop filter 42 is reduced. This is to reduce the influence of noise and the like.

As described above, the AFC circuit 16 determines that the AFC operation has been locked when the state in which the error output from the comparator 41 converges to a certain value or less is repeatedly detected a predetermined number of times. The decoding circuit 17 reproduces the transmission data based on the phase data obtained by the AFC circuit 16. In this embodiment, since QPSK is employed as the modulation method, the decoding device 17 reproduces 2-bit transmission data based on the applied phase data. Note that a method of converting phase data to 2-bit data corresponds to a method of converting 2-bit data to phase data in a transmission device.

The diversity circuit 21 determines an antenna to be used and gives a switching instruction to the selector 11. The diversity circuit 21 includes a register 22 and temporarily stores information used when reproducing data from a received signal. Specifically, the register 22 includes:
While the signal is being received via the antenna 1, various information detected in the code synchronization operation and the AFC operation during the period when the signal is being received via the antenna 2 is held, and the signal is received via the antenna 2. During the receiving period, various information detected in the code synchronization operation and the AFC operation during the period when the signal is being received via the antenna 1 is held.

FIG. 10 is a diagram for explaining the operation of the diversity circuit 21. Diversity circuit 21 alternately designates antennas 1 and 2 in a sequence for determining an antenna to be used. In the example shown in FIG.
The antenna 1 is selected between the time T2 and the time T3 to the time T3, and the antenna 2 is selected from the time T2 to the time T3. Then, for each period, the correlation circuit 12 to the AFC circuit 16 detect the maximum value (or the average value) of the correlation value data, and perform the code synchronization operation and the AFC.
The operation is performed. In the example shown in FIG.
2 and at times T3 to T4, the above operation is performed on the signal received via the antenna 1, and at times T2 to T4.
At T3, the above operation is performed on the signal received via the antenna 2.

In the above sequence, when the antenna is switched, the diversity circuit 21 writes various information detected or generated before the switching into the register 22 and writes the various information held in the register 22 into the synchronization circuit 13. And to the AFC circuit 16 and the like. For example, at time T2, the antenna 1
The various information detected or generated based on the signal received through the register 22 is written into the register 22, and the various information held in the register 22 is stored in the synchronous circuit 13 and A
It is provided to the FC circuit 16 and the like.

As a result, the synchronization circuit 13 and the AFC circuit 16 and the like can effectively use the information detected or generated by taking over the information, thereby achieving synchronization establishment and convergence of the AFC operation in a short time. For example, at time T2, as described above, various information detected or generated based on the signal received via antenna 1 from time T1 to T2 is written to register 22. Subsequently, at time T3, the information is read from the register 22 and provided to the synchronization circuit 13, the AFC circuit 16, and the like. Therefore, when the synchronization circuit 13 and the AFC circuit 16 and the like perform the synchronization operation and the AFC operation on the signal received via the antenna 1 during the time T3 to T4, the synchronization circuit 13 and the AFC circuit 16 extract various information detected or generated during the time T1 to T2. Can be used to take over.

Thereafter, the diversity circuit 21 determines an antenna to be actually used. Specifically, for example,
The average value of the correlation value for the signal received via antenna 1 is compared with the average value of the correlation value for the signal received via antenna 2 and the antenna with the larger value is selected. In the example shown in FIG. 10, the antenna 2 is selected.

Next, a specific example of information to be stored in the register 22 and effects of the present embodiment will be described. Among the information detected or generated by the synchronization detection circuit 14, the following information is held in the register 22. (1) Maximum correlation value timing information: The count value of the timing counter indicating the timing at which the maximum value of the correlation value data is obtained. For example, in the example shown in FIG. 7, "7" is obtained. (2) Synchronization count information: Information indicating the number of times the maximum correlation value timing information repeatedly matches. It is counted by a synchronous counter. (3) Synchronization establishment flag: 1-bit information indicating whether code synchronization has been established. This is set in step S6 of the flowchart shown in FIG. (4) Switching timing information: the count value of the timing counter indicating the timing at which the antenna is switched. This information is used to correlate the timing of switching the antenna with the operation of the timing counter. When this value is given to the synchronization detection circuit 14, "1" is added to the value written in the register 22.
For example, when the count value of the timing counter is “8” when switching from the antenna 1 to the antenna 2, the value is written to the register 22. Then, when the antenna 1 is selected next time, “9” is given to the synchronization circuit 13. This ensures continuity of operation. (5) Synchronization timing information: a count value of a timing counter indicating the timing at which the maximum value of the correlation value data is obtained when code synchronization is established.

When executing the processing of the flowchart shown in FIG. 6, the synchronization detecting circuit 14 reads the above information from the register 22 and uses it. For example, when step S2 is performed immediately after the antenna is switched, the timing at which the maximum value of the correlation value data detected first after the switching is obtained and the maximum correlation value timing information read from the register 22 Is compared with If they match each other, the synchronization counter is incremented in step S3. At this time, the synchronization counter information read from the register 22 is used as the count value of the synchronization counter.

FIG. 11 shows a specific example of the above operation. FIG.
1, in period 1, antenna 1 is selected;
Synchronization processing is performed on a signal received via the antenna 1. Then, in this period 1, it is assumed that the synchronization counter has counted up from “1” to “5”. In the period 2, the antenna 2 is selected, and a synchronization process is performed on a signal received via the antenna 2. During this period, the value of the synchronization counter for the signal received via the antenna 1 (that is, the synchronization number information =
5) is held in the register 22. Subsequently, at the start of the period 3, the information held in the register 22 is passed to the synchronization detection circuit 14. Then, when the synchronization process is performed on the signal received via the antenna 1 in the period 3, the count value of the synchronization counter is counted up from the value received from the register 22.

As described above, in the period 3, the synchronization operation is continued by inheriting the information obtained in the period 1. Therefore, in the flowchart shown in FIG.
The time required to reach the predetermined value in step S5 is reduced. That is, the time required for establishing synchronization is reduced.

Further, the synchronization detecting circuit 14 is provided with the register 2
Based on the synchronization establishment flag read from Step 2, it is determined whether code synchronization has already been established. If the code synchronization has already been established, the apparatus operates in the data reception mode without executing steps S1 to S6 shown in FIG. That is, it can be considered that the synchronization establishment process has been completed, and the process can proceed to the next operation. Therefore,
This also shortens the time until the correct data can be reproduced.

The following information among the information detected or generated in the AFC circuit 16 is held in the register 22. (1) Offset information: an output of the loop filter 42, which represents a carrier offset. (2) Phase correction information: output from the NCO 43 and represents phase correction data. (3) AFC lock count information: indicates the number of times the error output from the comparator 41 has become equal to or less than a predetermined value. It is counted by the AFC lock counter. (4) AFC lock flag: 1-bit information indicating whether or not AFC operation has converged. This is set in step S16 of the flowchart shown in FIG.

The AFC circuit 16 reads out the above information from the register 22 and uses it when executing the processing of the flowchart shown in FIG. The method of reading and using these pieces of information is basically the same as the operation of the synchronization detection circuit 14. Therefore, the description is omitted here.

However, the phase correction information requires a predetermined operation when the information written in the register 22 is given to the AFC circuit 16. Hereinafter, the operation regarding the phase correction information will be described with reference to FIG. AFC circuit 16
Calculates the phase correction amount based on the carrier offset as described with reference to FIG. However, within one symbol time, the phase correction data advances by the amount of the offset data. Therefore, in a sequence in which the antennas are switched alternately, when a plurality of symbols are transmitted during a period in which each antenna is selected, it is necessary to consider that fact. For example, in FIG.
At T2, the offset data due to the carrier offset is "α", and the phase correction data at time T2 is "β".
It is assumed that It is also assumed that k symbols are transmitted during a period in which each antenna is selected. In this case, at time T 2, “α” as offset information and “β” as phase correction information are written in the register 22. Then, at time T3, A
“Β + k · α” is given to the phase correction data of the FC circuit 16. In this case, the comparator 41 of the AFC circuit 16
Corrects the phase using “β + k · α” for the first phase data after antenna switching, and
43, the phase data is corrected.

The receiving apparatus of the present embodiment stores various information in the register 2 in addition to the information taken in the above-described embodiment.
2 and can be used. An example will be described below. (1) Maximum correlation value phase information: information indicating the phase at the timing when the maximum value of the correlation value data is obtained. This information
Obtained by the phase detection circuit 15. (2) Maximum correlation value amplitude information: information indicating the amplitude at the timing when the maximum value of the correlation value data is obtained. This information also
Obtained by the phase detection circuit 15. (3) Data clock information: information indicating whether the data clock is "H" or "L". Note that this information may be modified based on the above-described switching timing information under specific conditions. Hereinafter, the data clock will be described with reference to FIG.

In FIG. 13, it is assumed that the data clock is generated based on the count value of the timing counter. In this embodiment, the data clock is generated such that its logic is inverted at the timing when the count value of the timing counter changes from "10" to "11" and when the count value returns from "21" to "0".

As shown in FIG. 13A, when the antenna is switched at time T1, the logic of the data clock at that timing is written in the register 22 as data clock information. Here, “H” is written in the register 22. Then, when the antenna 1 is selected again at time T2, the logic of the data clock is generated according to the data clock information held in the register 22. That is, the logic of the data clock at time T2 is "H".

In the example shown in FIG. 13B, when the antenna is switched at time T3, the count value of the timing clock is "21". In this case, when the antenna 1 is selected again at time T4, the count value of the timing clock starts from "0". Here, at the timing when the count value of the timing counter changes from “21” to “0”, it is necessary to invert the logic of the data clock. Therefore, in this case, when "L" is written to the register 22 as data clock information at time T3, "H" is output as data clock information at time T4. This processing is executed when the count value of the timing clock at the time of antenna switching is “10” or “21”.

Although the above embodiment has described the case where the receiving apparatus has two antennas, the present invention is also applicable to a case where three or more antennas are provided. In this case, information obtained in the synchronization establishment processing or the like is held in the register 22 for each antenna, and when a certain antenna is selected, information corresponding to that antenna is read from the register 22 and used.

[0050]

According to the present invention, in a receiving apparatus having an antenna selection diversity function in spread spectrum communication, the time required for code synchronization and automatic frequency control is reduced, so that correct data can be reproduced in a short time. Therefore, the throughput is improved.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a communication system in which a receiving device according to an embodiment is used.

FIG. 2 is a diagram illustrating an IQ plane.

FIG. 3 is a diagram illustrating an example of a carrier modulated based on a signal point on an IQ plane.

FIG. 4 is a block diagram of a receiving device of the present embodiment.

FIG. 5 is a circuit diagram of an example of a correlation circuit;

FIG. 6 is a schematic flowchart showing the operation of the synchronization detection circuit.

FIG. 7 is a diagram illustrating the operation of the synchronization detection circuit.

FIG. 8 is a block diagram of an AFC circuit.

FIG. 9 is a schematic flowchart showing the operation of the AFC circuit.

FIG. 10 is a diagram illustrating the operation of the diversity circuit.

FIG. 11 is a diagram illustrating a process of counting the number of times of synchronization.

FIG. 12 is a diagram illustrating a process of calculating phase correction data.

FIG. 13 is a diagram illustrating a process of generating a data clock.

FIG. 14 is a diagram illustrating a problem of existing diversity selection.

[Explanation of symbols]

 1, 2 Antenna 11 Selector 12 Correlation Circuit 13 Synchronization Circuit 14 Synchronization Detection Circuit 15 Phase Detection Circuit 16 AFC Circuit 17 Decoding Circuit 21 Diversity Circuit 22 Register

Claims (5)

[Claims] 1. A receiving apparatus having an antenna selection diversity function in spread spectrum communication, comprising: a plurality of antennas for receiving a signal; a selector for selecting one antenna from the plurality of antennas; Reproducing means for reproducing data from a signal received via an antenna; holding means for holding information detected or generated from the signal by the reproducing means; a first antenna among the plurality of antennas by the selector When information is switched from the state where is selected to the state where the second antenna is selected, information detected or reproduced by the reproducing means from a signal received via the first antenna is written into the holding means, and The signal received via the second antenna is detected in the past by the reproducing means. Or reproducing information and a control means for reading from said holding means, said reproducing means, receiving apparatus for reproducing data by using the information read out from the holding means by the control means. 2. A receiving apparatus having an antenna selection diversity function in spread spectrum communication, comprising: reproducing means for reproducing data from a signal received via a first or second antenna; During a period in which data is reproduced from a signal received through the antenna, the information used by the reproducing means when reproducing data from the signal received through the second antenna is held. During the period when the means is reproducing data from the signal received via the second antenna, information used by the reproducing means when reproducing data from the signal received via the first antenna is used. Holding means for holding, wherein the reproducing means reproduces data using information held by the holding means. 3. The receiving device according to claim 1, wherein the information held in the holding unit is information used for establishing code synchronization. 4. The receiving device according to claim 1, wherein the information held in the holding unit is information used for converging an automatic frequency control operation. 5. A receiving apparatus having an antenna selection diversity function in spread spectrum communication, comprising: a plurality of antennas for receiving a signal; a selector for selecting one antenna from the plurality of antennas; Synchronizing means for establishing code synchronization for a signal received via an antenna, holding means for holding information detected or generated from the signal by the synchronizing means, and a first of the plurality of antennas by the selector. When switching from the state where the antenna is selected to the state where the second antenna is selected, the information detected or reproduced by the synchronizing means from the signal received via the first antenna is written to the holding means. At the same time, the signal received through the second antenna Control means for reading out the information detected or reproduced from the holding means, wherein the synchronization means establishes code synchronization by using the information read from the holding means by the control means. .