JP2021057892A5 - - Google Patents

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Publication number
JP2021057892A5
JP2021057892A5 JP2020149113A JP2020149113A JP2021057892A5 JP 2021057892 A5 JP2021057892 A5 JP 2021057892A5 JP 2020149113 A JP2020149113 A JP 2020149113A JP 2020149113 A JP2020149113 A JP 2020149113A JP 2021057892 A5 JP2021057892 A5 JP 2021057892A5
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JP
Japan
Prior art keywords
physical layer
input
communication protocol
bus
marshalling
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JP2020149113A
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English (en)
Japanese (ja)
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JP2021057892A (ja
JP7792193B2 (ja
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Priority claimed from US16/573,380 external-priority patent/US11734213B2/en
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JP2020149113A 2019-09-17 2020-09-04 プロセス制御入力／出力デバイスにおける多数の通信物理層およびプロトコルの統合 Active JP7792193B2 (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US16/573,380 2019-09-17
US16/573,380 US11734213B2 (en) 2019-09-17 2019-09-17 Integration of multiple communication physical layers and protocols in a process control input/output device

Publications (3)

Publication Number Publication Date
JP2021057892A JP2021057892A (ja) 2021-04-08
JP2021057892A5 true JP2021057892A5 (enExample) 2023-05-22
JP7792193B2 JP7792193B2 (ja) 2025-12-25

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