JP2021040049A - Manufacturing method for semiconductor module - Google Patents

Abstract

To provide a technique for suppressing a void generated inside a semiconductor module.SOLUTION: A manufacturing method for a semiconductor module includes the steps of: preparing a semi-product in which a semiconductor element is bonded to an internal conductive layer of an insulating substrate including an external conductive layer and the internal conductive layer on both surfaces of an insulating layer; disposing the semi-product inside a mold so that the external conductive layer of the insulating substrate is in contact with the mold; and filling the mold, where the semi-product is disposed, with a sealing material from a gate provided to the mold. The external conductive layer of the insulating substrate includes a first part and a second part that is provided with a space from the first part. In the disposing step, the semi-product is disposed so that the gate comes on an extension line of the space extending between the first part and the second part in a plan view.SELECTED DRAWING: Figure 4

Description

The techniques disclosed herein relate to methods of manufacturing semiconductor modules.

Patent Document 1 discloses a method for manufacturing a semiconductor module. The molding apparatus used in the manufacturing method of Patent Document 1 includes a product section and a resin reservoir provided on the downstream side of the product section. The resin pool portion communicates with the inside of the product portion and has an internal space for storing the resin poured from the product portion. In this manufacturing method, after injecting resin into the mold of the product part and holding the pressure, the volume of the closed space is increased by increasing the internal space of the resin pool part, and the flow of the stopped resin is restarted. .. It is described that this allows the voids remaining in the mold to be moved together with the resin to the internal space of the resin reservoir.

Japanese Unexamined Patent Publication No. 2019-009184

The manufacturing method of Patent Document 1 has a problem that the apparatus is complicated and the amount of resin used is large. The present specification provides a technique for suppressing voids generated inside a semiconductor module by a configuration different from that of Patent Document 1.

The method for manufacturing a semiconductor module disclosed in the present specification includes a step of preparing a semi-finished product in which a semiconductor element is bonded to the inner conductor layer of an insulating substrate having an inner conductor layer and an outer conductor layer on both sides of the insulating layer. The step of arranging the semi-finished product in the mold and the step of arranging the semi-finished product in the mold so that the outer conductor layer of the insulating substrate comes into contact with the mold are provided in the mold. It includes a step of filling the sealing material from the gate. The outer conductor layer of the insulating substrate has a first portion and a second portion provided at a distance from the first portion. In the arranging step, the semi-finished product is arranged so that the gate is located on an extension of the space extending between the first portion and the second portion in a plan view.

In the above manufacturing method, the semi-finished product is arranged in the mold so that the outer conductor layer of the insulating substrate comes into contact with the mold. As a result, the semi-finished product is positioned with respect to the semiconductor module. The outer conductor layer has a first portion and a second portion provided at a distance from the first portion. Therefore, when the semi-finished product is arranged in the mold, a relatively narrow space is formed by the first portion, the second portion, the insulating layer, and the mold. In this step of placing the semi-finished product, the semi-finished product is placed so that the gate for filling the sealing material is located on the extension of the space extending between the first portion and the second portion in a plan view. Will be done. Therefore, in this manufacturing method, the sealing material filled in the mold easily flows into the above-mentioned space in one direction. As described above, according to the above-mentioned manufacturing method, since the sealing material is suppressed from flowing into the space from different directions, the sealing material can be filled in the entire space. Therefore, in this manufacturing method, voids are unlikely to occur inside the semiconductor module to be manufactured.

The plan view of the semiconductor module of Example 1. FIG. FIG. 2 is a cross-sectional view taken along the line II-II of FIG. The figure for demonstrating the manufacturing process of the semiconductor module of Example 1. FIG. The figure for demonstrating the manufacturing process of the semiconductor module of Example 1 (cross-sectional view taken along line IV-IV of FIG. 3). The figure for demonstrating the manufacturing process of the semiconductor module of Example 1 (top view of FIG. 3). The figure for demonstrating the manufacturing process of the semiconductor module of Example 1. FIG. The figure which shows the state which the sealing material is injected into the mold. FIG. 5 is a cross-sectional view of the semiconductor module of the second embodiment. The figure which looked at the 1st insulation substrate of Example 2 from the 1st inner conductor layer side (lower side). The figure for demonstrating the manufacturing process of the semiconductor module of Example 2. FIG. The figure for demonstrating the manufacturing process of the semiconductor module of Example 2. FIG. The figure for demonstrating the manufacturing process of the semiconductor module of Example 2. FIG. The figure for demonstrating the modification of the manufacturing process of the semiconductor module of Example 2. FIG.

In one embodiment of the present technology, in the arranging step, the semi-finished product may be arranged so that the gate is located on the extension of the space extending between the first portion and the second portion in the side view.

In such a configuration, the space and the gate are in a positional relationship so as to face each other. Therefore, the sealing material can more easily flow in one direction into the space formed by the first portion, the second portion, the insulating layer, and the mold. Therefore, voids are less likely to occur inside the manufactured semiconductor module.

In one embodiment of the present technology, a step of forming recesses or through holes on one side or both sides of the insulating substrate at positions away from the inner conductor layer and the outer conductor layer may be further provided.

When a semiconductor module is used, each member repeatedly expands and contracts due to repeated heat generation. Since the coefficient of linear expansion of each member is different, thermal stress is generated in each member. As a result, the insulating substrate and the sealing material may be peeled off. However, in the above configuration, the sealing material functions as an anchor by entering the recess or the through hole. Therefore, peeling between the sealing material and the insulating substrate due to thermal stress can be suppressed.

(Example 1)
The semiconductor module 10 of the first embodiment will be described with reference to the drawings. The semiconductor module 10 is adopted in, for example, a power control device for an electric vehicle, and can form at least a part of a power conversion circuit such as a converter or an inverter. The term "electric vehicle" as used herein broadly means a vehicle having a motor for driving wheels, and for example, an electric vehicle charged by external electric power, a hybrid vehicle having an engine in addition to the motor, and a fuel powered by a fuel cell. Including battery cars, etc.

As shown in FIGS. 1 and 2, the semiconductor module 10 includes a first semiconductor element 12, a second semiconductor element 14, and a sealant 52. The first semiconductor element 12 and the second semiconductor element 14 are sealed inside the sealing body 52. The sealing body 52 is made of an insulating material. Although not particularly limited, the sealing body 52 in this embodiment is made of a thermosetting resin such as an epoxy resin. The sealing body 52 generally has a plate shape, and has an upper surface 52a and a lower surface 52b located on the opposite side of the upper surface 52a.

As shown in FIG. 2, the first semiconductor element 12 has a semiconductor substrate 12a, an upper surface electrode 12b, a lower surface electrode 12c, and a plurality of signal electrodes (not shown). The upper surface electrode 12b and the plurality of signal electrodes are located on the upper surface of the semiconductor substrate 12a, and the lower surface electrode 12c is located on the lower surface of the semiconductor substrate 12a. Although not particularly limited, the first semiconductor element 12 is a switching element that conducts and cuts off between the upper surface electrode 12b and the lower surface electrode 12c, and is specifically an RC-IGBT (Reverse Conducting-Insulated Gate Bipolar Transistor). That is, the first semiconductor element 12 has a built-in freewheeling diode in addition to the IGBT. As another embodiment, the first semiconductor element 12 may be a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor).

Similarly, the second semiconductor element 14 has a semiconductor substrate 14a, an upper surface electrode 14b, a lower surface electrode 14c, and a plurality of signal electrodes (not shown). The upper surface electrode 14b and the plurality of signal electrodes are located on the upper surface of the semiconductor substrate 14a, and the lower surface electrode 14c is located on the lower surface of the semiconductor substrate 14a. Although not particularly limited, the second semiconductor element 14 is also a switching element that conducts and cuts off between the upper surface electrode 14b and the lower surface electrode 14c, and is specifically an RC-IGBT. That is, the second semiconductor element 14 also has a built-in freewheeling diode in addition to the IGBT. As another embodiment, the second semiconductor element 14 may be a MOSFET.

Although not particularly limited, semiconductor elements having the same structure are adopted in the first semiconductor element 12 and the second semiconductor element 14. However, as another embodiment, semiconductor elements having different structures may be adopted for the first semiconductor element 12 and the second semiconductor element 14. For example, switching elements having different structures can be adopted for the first semiconductor element 12 and the second semiconductor element 14. Alternatively, the first semiconductor element 12 may be a switching element and the second semiconductor element 14 may be a diode element. The first semiconductor element 12 and the second semiconductor element 14 are not limited to switching elements, and various types of power semiconductor elements can be adopted. The semiconductor substrates 12a and 14a of the first semiconductor element 12 and the second semiconductor element 14 are not particularly limited, but may be, for example, a silicon substrate, a silicon carbide substrate, or a nitride semiconductor substrate.

The semiconductor module 10 further includes a first insulating substrate 20 and a second insulating substrate 30. The first insulating substrate 20 faces the second insulating substrate 30 via the first semiconductor element 12 and the second semiconductor element 14. The first insulating substrate 20 and the second insulating substrate 30 are integrally held by the sealing body 52, and the space between the first insulating substrate 20 and the second insulating substrate 30 is filled with the sealing body 52. There is.

The first insulating substrate 20 includes a first insulating layer 22, a first inner conductor layer 24 provided on one surface (that is, a lower surface) of the first insulating layer 22, and the other surface of the first insulating layer 22 (that is, a lower surface). That is, it has a first outer conductor layer 26 provided on the upper surface). The first inner conductor layer 24 is electrically connected to the first semiconductor element 12 and the second semiconductor element 14 inside the sealing body 52. On the other hand, the first outer conductor layer 26 is exposed to the outside on the upper surface 52a of the sealing body 52. As a result, the first insulating substrate 20 not only constitutes a part of the electric circuit, but also functions as a heat radiating plate that releases the heat of the first semiconductor element 12 and the second semiconductor element 14 to the outside.

The first inner conductor layer 24 has a first portion 24X and a second portion 24Y. The first portion 24X and the second portion 24Y are separated from each other and are electrically insulated on the first insulating layer 22. The first portion 24X is electrically connected to the upper surface electrode 12b of the first semiconductor element 12 via the first conductor spacer 16. Specifically, the first portion 24X is bonded to the first conductor spacer 16 via the bonding layer 60A, and the first conductor spacer 16 is bonded to the upper surface electrode 12b of the first semiconductor element 12 via the bonding layer 60B. Has been done. On the other hand, the second portion 24Y is electrically connected to the upper surface electrode 14b of the second semiconductor element 14 via the second conductor spacer 18. Specifically, the second portion 24Y is bonded to the second conductor spacer 18 via the bonding layer 60D, and the second conductor spacer 18 is bonded to the upper surface electrode 14b of the second semiconductor element 14 via the bonding layer 60E. Has been done. The bonding layers 60A, 60B, 60D, and 60E are not particularly limited, but are made of, for example, a solder material.

The first outer conductor layer 26 also has a first portion 26X and a second portion 26Y. The first portion 26X has substantially the same shape as the first portion 24X of the first inner conductor layer 24, and the first portion 24X and the first portion 26X face each other via the first insulating layer 22. There is. Similarly, the second portion 26Y has substantially the same shape as the second portion 24Y of the first inner conductor layer 24, and the second portion 24Y and the second portion 26Y each other via the first insulating layer 22. Facing each other. As described above, when the first insulating substrate 20 has a symmetrical structure on both sides of the first insulating layer 22, the warp of the first insulating substrate 20 due to thermal deformation is effectively suppressed.

The second insulating substrate 30 includes a second insulating layer 32, a second inner conductor layer 34 provided on one surface (that is, an upper surface) of the second insulating layer 32, and the other surface of the second insulating layer 32 (that is, the upper surface). That is, it has a second outer conductor layer 36 provided on the lower surface). The second inner conductor layer 34 is electrically connected to the first semiconductor element 12 and the second semiconductor element 14 inside the sealing body 52. On the other hand, the second outer conductor layer 36 is exposed to the outside on the lower surface 52b of the sealing body 52. As a result, the second insulating substrate 30 not only constitutes a part of the electric circuit, but also functions as a heat radiating plate that releases the heat of the first semiconductor element 12 and the second semiconductor element 14 to the outside.

The second inner conductor layer 34 has a first portion 34X and a second portion 34Y. The first portion 34X and the second portion 34Y are separated from each other and are electrically insulated on the second insulating layer 32. The first portion 34X is bonded to the lower surface electrode 12c of the first semiconductor element 12 via the bonding layer 60C, and is electrically connected to the lower surface electrode 12c. On the other hand, the second portion 34Y is bonded to the lower surface electrode 14c of the second semiconductor element 14 via the bonding layer 60F, and is electrically connected to the lower surface electrode 14c. The bonding layers 60C and 60F are not particularly limited, but are made of, for example, a solder material.

The second outer conductor layer 36 also has a first portion 36X and a second portion 36Y. The first portion 36X has substantially the same shape as the first portion 34X of the second inner conductor layer 34, and the first portion 34X and the first portion 36X face each other via the second insulating layer 32. There is. Similarly, the second portion 36Y has substantially the same shape as the second portion 34Y of the second inner conductor layer 34, and the second portion 34Y and the second portion 36Y each other via the second insulating layer 32. Facing each other. As described above, when the second insulating substrate 30 has a symmetrical structure on both sides of the second insulating layer 32, the warp of the second insulating substrate 30 due to thermal deformation is effectively suppressed.

As an example, the first insulating substrate 20 and the second insulating substrate 30 in this embodiment are DBC (Direct Bonded Copper) substrates. The insulating layers 22 and 32 are made of ceramic such as aluminum oxide, silicon nitride, and aluminum nitride. On the other hand, the inner conductor layers 24 and 34 and the outer conductor layers 26 and 36 are made of copper. The surfaces of the inner conductor layers 24 and 34 are nickel-plated and gold-plated. However, each of the two insulating substrates 20 and 30 is not limited to the DBC substrate, and may be, for example, an AMC (Active Metal brazed Copper) substrate or a DBA (Direct Bonded Aluminum) substrate.

The first portion 24X of the first inner conductor layer 24 and the second portion 34Y of the second inner conductor layer 34 are electrically formed in a region between the first semiconductor element 12 and the second semiconductor element 14 in a cross section (not shown). It is connected. As a result, the first semiconductor element 12 and the second semiconductor element 14 are electrically connected in series inside the sealing body 52.

As shown in FIG. 1, the semiconductor module 10 further includes a first power terminal 42, a second power terminal 44, and a third power terminal 46. These three power terminals 42, 44, and 46 project from the encapsulant 52 in the same direction and extend in parallel with each other. The three power terminals 42, 44, 46 are made of a conductor such as copper or other metal.

Although not shown, the first power terminal 42 is joined to the second insulating substrate 30 inside the sealing body 52. Specifically, the first power terminal 42 is joined to the first portion 34X of the second inner conductor layer 34. As a result, the first power terminal 42 is electrically connected to the lower surface electrode 12c of the first semiconductor element 12. Further, the second power terminal 44 is joined to the first insulating substrate 20 inside the sealing body 52. Specifically, the second power terminal 44 is joined to the second portion 24Y of the first inner conductor layer 24. As a result, the second power terminal 44 is electrically connected to the upper surface electrode 12b of the second semiconductor element 14. Further, the third power terminal 46 is joined to the second insulating substrate 30 inside the sealing body 52. Specifically, the third power terminal 46 is joined to the second portion 34Y of the second inner conductor layer 34. As a result, the third power terminal 46 is electrically connected to the upper surface electrode 12b of the first semiconductor element 12 and the lower surface electrode 14c of the second semiconductor element 14.

The semiconductor module 10 further includes a plurality of first signal terminals 48 and a plurality of second signal terminals 50. These signal terminals 48 and 50 project from the sealing body 52 in the same direction and extend in parallel with each other. The plurality of signal terminals 48, 50 are made of a conductor such as copper or other metal. Although not shown, the plurality of first signal terminals 48 are electrically connected to each of the plurality of signal electrodes of the first semiconductor element 12 inside the sealing body 52. The plurality of second signal terminals 50 are electrically connected to each of the plurality of signal electrodes of the second semiconductor element 14 inside the sealing body 52. Although not particularly limited, each signal terminal 48, 50 in this embodiment is connected to a corresponding signal electrode via a bonding wire made of a metal such as aluminum or copper. However, the connection between the signal terminals 48 and 50 and the signal electrodes is not limited to the bonding wire, and may be made by using, for example, the inner conductor layers 24 and 34 of the first insulating substrate 20 or the second insulating substrate 30. Good.

Next, a method of manufacturing the semiconductor module 10 will be described. However, in this embodiment, in particular, the periphery of the semi-finished product 100 in which the first insulating substrate 20, the conductor spacers 16 and 18, the semiconductor elements 12 and 14, the second insulating substrate 30, and the like are laminated is sealed by the sealing body 52. The process to be performed will be described. Since the step of manufacturing the semi-finished product 100 can be carried out by appropriately using various conventionally known methods, the description of the step is omitted here.

First, as shown in FIG. 3, a semi-finished product 100 in which the first insulating substrate 20, the conductor spacers 16 and 18, the semiconductor elements 12 and 14, and the second insulating substrate 30 are laminated is prepared. Then, the semi-finished product 100 is placed in the mold 90. Here, the semi-finished product 100 is arranged so that the surface of the outer conductor layer 36 of the second insulating substrate 30 comes into contact with the inner surface of the mold 90. Although not shown, some of the power terminals 42, 44, 46 and the signal terminals 48, 50 are semi-finished products so as to project to the outside of the mold 90 (that is, not to be sealed later). 100 is placed. At this time, as shown in FIGS. 3 to 5, the space between the first portion 36X and the second portion 36Y is provided by the inner surfaces of the first portion 36X, the second portion 36Y, the second insulating layer 32, and the mold 90. An extending space S1 is formed. In this step, as shown in FIGS. 3 to 5, a semi-finished product is provided so that the gate 90a of the mold 90 is located on the extension of the space S1 extending between the first portion 36X and the second portion 36Y. 100 is placed. That is, the semi-finished product 100 is arranged so that the gate 90a is located on the extension of the space S1 in both the plan view and the side view. In other words, the semi-finished product 100 is arranged so that the end portion where the space S1 is opened faces the gate 90a. In FIG. 5, the inner surface of the mold is also shown by a solid line for easy understanding of the figure.

Next, as shown in FIG. 6, the sealing material 152 is filled from the gate 90a into the mold 90 in which the semi-finished product 100 is arranged. The sealing material 152 is a thermosetting resin such as an epoxy resin. Specifically, the molten sealing material 152 is injected from the gate 90a of the mold 90, and the inside of the mold 90 is filled with the sealing material 152. After that, by cooling the mold 90, the sealing material 152 in the mold 90 is cured, and the molded body 110 is formed.

After that, the mold body 110 is taken out from the mold 90, the portion of the first insulating substrate 20 covering the outer conductor layer 26 (the portion shown by the broken line 110a in FIG. 6) is polished, and the outer conductor layer 26 is removed from the mold body 110. Expose. As a result, the semiconductor module 10 shown in FIGS. 1 and 2 is completed.

In the manufacturing method of this embodiment, when the semi-finished product 100 is arranged in the mold 90, the semi-finished product 100 is positioned so that the gate 90a of the mold 90 is located on the extension of the space S1. Therefore, when the sealing material 152 is injected into the mold 90, the sealing material 152 flows in one direction in the relatively narrow space S1 as shown by the arrow 80 in FIG. Therefore, it is possible to suppress the formation of voids due to the inflow of the sealing material 152 into the space S1 from different directions. As described above, in the manufacturing method of this embodiment, the entire space S1 can be easily filled with the sealing material 152, and it is possible to suppress the formation of voids inside the semiconductor module 10 to be manufactured.

In this embodiment, the gate 90a of the mold 90 is located on the extension of the space S1 in both the plan view and the side view. However, in the side view, the gate 90a does not have to be located on the extension of the space S1. That is, in the side view, the position of the gate 90a and the position of the space S1 may be displaced in the vertical direction. That is, the gate 90a may be located on an extension of the space S1 at least in a plan view.

Further, in this embodiment, the space S1 formed by the first portion 36X, the second portion 36Y, the second insulating layer 32, and the inner surface of the mold 90 is a space extending linearly. However, the shape of the space is not particularly limited. When arranging the semi-finished product in the mold 90, one end of the space to be opened and the gate 90a of the mold 90 may face each other in a plan view.

Further, in this embodiment, the outer conductor layer 36 of the second insulating substrate 30 is arranged so as to be in contact with the inner surface of the mold. However, the semi-finished product 100 may be arranged so that the outer conductor layer 26 of the first insulating substrate 20 is in contact with the inner surface of the mold 90. Further, the semi-finished product 100 may be arranged so that both the outer conductor layer 26 and the outer conductor layer 36 are in contact with the inner surface of the mold 90.

Further, the semiconductor module 10 manufactured by the manufacturing method of this embodiment has a so-called double-sided cooling structure in which the outer conductor layers 26 and 36 are exposed on both sides of the sealing body 52, respectively. However, for example, the technique disclosed in the present specification can be applied to a semiconductor module having a single-sided cooling structure to which the first insulating substrate 20 is not provided.

(Example 2)
In the semiconductor module 210 of the second embodiment shown in FIG. 8, the configurations of the first insulating layer 222 of the first insulating substrate 220 and the second insulating layer 232 of the second insulating substrate 230 are different from those of the first insulating substrate 230. .. As shown in FIGS. 8 and 9, the first insulating layer 222 is provided with a plurality of recesses 222a on the surface (that is, the lower surface) on which the first inner conductor layer 24 is arranged. Each recess 222a is provided in a range of the surface of the first insulating layer 222 that is not covered by the first inner conductor layer 24. Each recess 222a has a circular shape when viewed in a plan view. The shape of each recess 222a is not particularly limited, and may have a polygonal shape, for example. The depth of each recess 222a is not particularly limited, but is, for example, 100 μm to 200 μm. The distance between the two adjacent recesses 222a (specifically, the shortest distance between the recesses 222a in a plan view) is not particularly limited, but is, for example, 200 μm to 1000 μm. Further, each recess 222a is provided at a position separated from the outer peripheral end of the first inner conductor layer 24 by 100 μm or more. The second insulating layer 232 is provided with a plurality of recesses 232a on the surface (that is, the upper surface) on which the second inner conductor layer 34 is arranged. The configuration of each recess 232a is the same as the configuration of each recess 222a. The inside of each of the recesses 222a and 232a is filled with a sealing body 52.

When the semiconductor module 210 is used, each member (semiconductor elements 12, 14, insulating substrates 220, 230, sealant 52, etc.) repeatedly expands and contracts due to repeated heat generation. Since the coefficient of linear expansion of each member is different, thermal stress is generated in each member. As a result, peeling may occur between the insulating layers 222 and 232 and the sealing body 52. However, in the semiconductor module 210 of this embodiment, recesses 222a and 232a are provided on the respective surfaces of the insulating layers 222 and 232. The inside of each of these recesses 222a and 232a is filled with a sealing body 52. Therefore, the sealing body 52 arranged in the recesses 222a and 232a functions as an anchor, and it is possible to prevent peeling from occurring between the insulating layers 222 and 232 and the sealing body 52. Therefore, the semiconductor module 210 is highly reliable.

Next, a method of manufacturing the semiconductor module 210 of the second embodiment will be described. In the method for manufacturing the semiconductor module 210 of the second embodiment, in addition to the manufacturing method of the first embodiment, a step of forming recesses 222a and 232a in the insulating layers 222 and 232 is further provided.

The step of forming the recesses 222a and 232a is carried out before the semi-finished product is manufactured. 10 to 12 show a process of manufacturing the second insulating substrate 230 of this embodiment. When manufacturing the second insulating substrate 230, first, as shown in FIG. 10, conductor layers 234 and 236 made of copper are bonded to the upper surface and the lower surface of the sintered insulating layer 232, respectively. Next, as shown in FIG. 11, a part of the surface of the insulating layer 232 is exposed by selectively etching the conductor layers 234 and 236. As a result, the inner conductor layer 34 (first portion 34X and second portion 34Y) is formed on the upper surface of the insulating layer 232, and the outer conductor layer 36 (first portion 36X and second portion 36Y) is formed on the lower surface of the insulating layer 232. It is formed.

Next, as shown in FIG. 12, a plurality of recesses 232a are formed on the upper surface of the insulating layer 232 by spot-irradiating the surface (that is, the upper surface) of the insulating layer 232 on the inner conductor layer 34 side with laser light. Form. Here, the laser beam is selectively irradiated to the range of the upper surface of the insulating layer 232 that is not covered by the inner conductor layer 34. As a result, the second insulating substrate 230 can be formed. The first insulating substrate 220 can be manufactured by going through the same steps as the second insulating substrate 230.

Then, using the insulating substrates 220 and 230 obtained through the above-mentioned steps, semi-finished products similar to those in Example 1 are manufactured, and various steps (FIGS. 3 to 6) described in Example 1 are carried out. By doing so, the semiconductor module 210 shown in FIG. 8 is completed.

When manufacturing the insulating substrate 230, the insulating substrate 330 having a plurality of conductor layer 334 patterns formed on the surface of one insulating layer 332 as shown in FIG. 13 is used, and the insulating substrate 330 is used. By dividing, a plurality of (two in FIG. 13) insulating substrates 230 may be manufactured from one insulating substrate 330. In this case, the mechanical intensity is lowered by irradiating the laser beam along the line (indicated by the broken line 330a) to cut the insulating layer 332, and a load is applied to the line 330a to apply a load to the plurality of insulating substrates. Divide into 230. At this time, in addition to the spot irradiation of the laser light along the line 330a, as shown in FIG. 13, the spot irradiation of the laser light for forming the recess 232a may be performed at the same time. In such a manufacturing method, the recess 232a can be formed at the same time when the insulating substrate 330 is divided by laser processing. Therefore, the recess 232a can be formed without increasing the number of steps as compared with the conventional manufacturing method.

Further, in this embodiment, the recesses 222a and 232a are formed on the inner conductor layers 24 and 34 side surfaces (that is, the inner side surfaces of the semiconductor module 210) of the insulating layers 222 and 232. However, the surface forming each recess 222a and 232a is not particularly limited. It may be formed on the outer conductor layers 26 and 36 side surfaces of the insulating layers 222 and 232 (that is, the outer surface side of the semiconductor module 210), or may be formed on both surfaces of the insulating layers 222 and 232. Further, the recess may be formed only in either the first insulating layer 222 or the second insulating layer 232. Further, instead of the recesses 222a and 232a, a through hole may be provided so as to penetrate from the upper surface to the lower surface of the insulating layers 222 and 232.

Further, the method of forming the recesses 222a and 232a in the insulating layers 222 and 232 is not limited to the above method. For example, the insulating layer 222, in which the recesses 222a and 232a are formed in advance by molding the concave portions 222a and 232a with respect to the insulating layer 222 and 232 before sintering (that is, the raw material powder) and then sintering. 232 may be prepared. After that, the insulating substrates 220 and 230 may be obtained by forming the inner conductor layers 24 and 34 and the outer conductor layers 26 and 36.

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples illustrated above. The technical elements described herein or in the drawings exhibit their technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques illustrated in this specification or drawings achieve a plurality of objectives at the same time, and achieving one of the objectives itself has technical usefulness.

10: Semiconductor module, 12: First semiconductor element, 12a: Semiconductor substrate, 12b: Top electrode, 12c: Bottom electrode, 14: Second semiconductor element, 14a: Semiconductor substrate, 14b: Top electrode, 14c: Bottom electrode, 16 : 1st conductor spacer, 18: 2nd conductor spacer, 20: 1st insulating substrate, 22: 1st insulating layer, 24: 1st inner conductor layer, 24X: 1st part, 24Y: 2nd part, 26: 1st 1 outer conductor layer, 26X: first part, 26Y: second part, 30: second insulating substrate, 32: second insulating layer, 34: second inner conductor layer, 34X: first part, 34Y: second part , 36: 2nd outer conductor layer, 36X: 1st part, 36Y: 2nd part, 42: 1st power terminal, 44: 2nd power terminal, 46: 3rd power terminal, 48: 1st signal terminal, 50 : 2nd signal terminal, 52: Encapsulant, 90: Mold, 90a: Gate, 100: Semi-finished product

Claims (3)

It is a manufacturing method of semiconductor modules.
A step of preparing a semi-finished product in which a semiconductor element is bonded to the inner conductor layer of an insulating substrate having an inner conductor layer and an outer conductor layer on both sides of the insulating layer.
A step of arranging the semi-finished product in the mold so that the outer conductor layer of the insulating substrate comes into contact with the mold.
A step of filling the mold in which the semi-finished product is placed with a sealing material from a gate provided in the mold, and a step of filling the mold.
Is equipped with
The outer conductor layer of the insulating substrate has a first portion and a second portion provided at a distance from the first portion.
In the arranging step, the semi-finished product is arranged so that the gate is located on an extension of the space extending between the first portion and the second portion in a plan view.
Production method. In the step of arranging, the semi-finished product is arranged so that the gate is located on an extension of the space extending between the first portion and the second portion in a side view. The manufacturing method described. The manufacturing method according to claim 1 or 2, further comprising a step of forming a recess or a through hole on one side or both sides of the insulating substrate at a position away from the inner conductor layer and the outer conductor layer.

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