JP2019068110A - Power module - Google Patents

Abstract

To provide a power module and a method of manufacturing the same capable of achieving miniaturization, increase in current capacity, and reduction in cost by a lead frame structure, and of suppressing variation of welding without damaging a semiconductor device to improve a yield.SOLUTION: A power module 20 comprises: a first metal circuit pattern 3; a semiconductor device 1 disposed on the first metal circuit pattern 3; a lead frame 15 electrically connected with the semiconductor device 1; and a stress buffer layer 14 disposed on an upper surface of the semiconductor device 1, and capable of absorbing thermal expansion coefficient difference between the semiconductor device 1 and the lead frame 15. The lead frame 15 is connected with the semiconductor device 1 via the stress buffer layer 14, and a thermal expansion coefficient of the stress buffer layer 14 is equal to or less than that of the lead frame 15, and a cross-sectional shape of the stress buffer layer 14 is in an L-shape.SELECTED DRAWING: Figure 12

Description

  The present invention relates to a power module, and more particularly to a power module having a lead frame wiring structure.

  At present, research and development of silicon carbide (SiC: Silicon Carbide) devices is being conducted in many research institutes. SiC power devices have better low on resistance, faster switching and higher temperature operating characteristics than Si power devices.

  In the SiC power module, the loss of the SiC device is relatively small, so that a large current can be conducted and the high temperature operation is facilitated, but the design of the power module to allow this is essential.

  The case type is adopted as a package of a SiC power device.

  On the other hand, a semiconductor device sealed with a resin by transfer molding is also disclosed (for example, see Patent Document 1).

  In the conventional power module, in the connection structure of the heat spreader and the metal plate and the connection structure of the electrode wiring, an example is also disclosed in which the laser welding technology is applied without using a bonding material for bonding between the stress buffer layer and the lead frame. (See, for example, Patent Literature 2 and Patent Literature 3).

Unexamined-Japanese-Patent No. 2005-183463 Unexamined-Japanese-Patent No. 2007-165690 JP 2008-98586 A

  There is a limit to the need for smaller size and higher current of power modules in conventional aluminum wire wiring. To address this issue, for example, thicken the wire to make the aluminum wire of φ400 μm into aluminum wire such as φ500 μm, lower resistance and high conductivity to make it copper wire, for example, aluminum ribbon about 12 mm wide × 0.5 mm thick Measures such as low resistance and high conductivity have been taken, but higher current density is required for electric vehicles and hybrid vehicles. Furthermore, there is a need for downsizing and simplification of the cooling device and reduction of the mounting volume by elimination of the cooling device.

  For these, wire-thickening, copper wire-making, and aluminum ribbon-making are insufficient. Taking the aluminum wire as a specific example, the current which can be conducted to the 15 mm long aluminum wire of φ 400 μm is about 20 A in general. If the amount of current more than this is conducted steadily, melting of the wiring will occur. Even when wire thickening, copper wire making, or aluminum ribboning is performed, for example, it is difficult to conduct only about 1.5 times, that is, about 30 A.

  An object of the present invention is to provide a power module which can be reduced in size and increased in current capacity and reduced in cost by a lead frame structure and which suppresses variations in welding without damaging semiconductor devices and improves yield. .

  According to one aspect of the present invention, a first metal pattern, a first wide band gap semiconductor device disposed on the first metal pattern, and a lead frame electrically connected to the semiconductor device And a stress buffer layer disposed on the top surface of the semiconductor device and capable of buffering a difference in thermal expansion coefficient between the semiconductor device and the lead frame, the lead frame including the stress buffer layer. There is provided a power module connected to the semiconductor device and having a CTE of the stress buffer layer equal to or less than a thermal expansion coefficient of the lead frame.

  According to the present invention, it is possible to provide a power module which can be reduced in size, increased in current capacity, and reduced in cost by lead frame structure, and can suppress variations in welding without damaging semiconductor devices and can improve yield. .

The power module which concerns on a comparative example WHEREIN: Typical explanatory drawing of laser beam irradiation. The power module which concerns on a comparative example WHEREIN: Schematic explanatory drawing at the time of irradiating a laser beam to CuMo. The power module which concerns on a comparative example WHEREIN: The schematic explanatory drawing at the time of irradiating a laser beam to Cu / CuMo clad | crud. FIG. 2 is a schematic cross-sectional view of a power module according to Comparative Example 1; FIG. 5 is a schematic cross-sectional view of a power module according to Comparative Example 2; FIG. 10 is a schematic cross-sectional view of a power module according to Comparative Example 3; FIG. 7 is a diagram showing the relationship between the reflectance R of laser light emitted to a metal material and the laser wavelength λ. In a power module concerning a 1st embodiment, principle explanatory drawing of laser beam irradiation. The typical plane pattern block diagram of the power module concerning a 1st embodiment. The side view observed from the IA-IA direction in FIG. FIG. 10 is another side view observed from the IA-IA direction in FIG. 9; (A) A schematic cross-sectional structure view taken along line II in FIG. (B) A schematic cross-sectional structure view taken along line II-II in FIG. (A) In the power module according to the first modification of the first embodiment, a laminated structure of ceramic substrate / first metal circuit pattern / lower chip bonding layer / semiconductor device / upper chip bonding layer / L-shaped stress buffer layer (B) In the power module concerning modification 1 of a 1st embodiment, the typical cross section diagram of the part from which the thickness of the above-mentioned layered structure differs. (A) In the power module according to the second modification of the first embodiment, a laminated structure of ceramic substrate / first metal circuit pattern / lower chip bonding layer / semiconductor device / upper bonding layer on chip / L-shaped stress buffer layer (B) Typical cross-section figure of the part from which the thickness of the thickness of said laminated structure differs in the power module concerning the modification 2 of (b) 1st embodiment. (A) In the power module according to the second embodiment, a schematic cross section of a laminated structure of ceramic substrate / first metal circuit pattern / junction layer under chip / semiconductor device / junction layer on chip / U-shaped stress buffer layer (B) A schematic cross-sectional view of a portion of the power module according to the second embodiment in which the thickness of the laminated structure is different. It is a power module concerning a 3rd embodiment, and is a typical plane pattern lineblock diagram before forming a mold resin layer in a two-in-one module (2 in 1 Module) (half bridge built-in module). It is a power module which concerns on 3rd Embodiment, Comprising: The circuit block diagram of the two-in-one module (half bridge built-in module) which applied SiC insulated-gate field effect transistor (MISFET: Metal Oxide Semiconductor Field Effect Transistor) as a semiconductor device. The side view observed from the IIA-IIA direction in FIG. It is a power module concerning the modification of a 3rd embodiment, and is a side view observed from the IIA-IIA direction in FIG. The enlarged view of A part of FIG. It is a power module concerning a 3rd embodiment, and is a typical bird's-eye view block diagram after forming a mold resin layer in a half bridge built-in module. It is a power module concerning a 4th embodiment, and is a typical bird's-eye view block diagram before forming a mold resin layer in a two-in-one module (half bridge built-in module). It is a power module concerning the modification of a 4th embodiment, and is a typical bird's-eye view block diagram before forming a mold resin layer in a two-in-one module (half bridge built-in module). It is a power module concerning a 5th embodiment, and is a typical plane pattern lineblock diagram before forming a mold resin layer in a two-in-one module (half bridge built-in module). (A) The side view observed from IIIA-IIIA direction in FIG. 24, (b) The enlarged view of the B section of FIG. 25 (a). It is a power module which concerns on embodiment, Comprising: The typical circuit expression figure of SiC MISFET of a one in one module (1 in 1 Module), (b) The typical circuit expression figure of IGBT of a one in one module. It is a power module which concerns on embodiment, Comprising: The detailed circuit circuit diagram of SiC MISFET of a one-in-one module. It is a power module concerning an embodiment, and is a schematic circuit expression figure of SiC MISFET of (a) two-in-one module, (b) schematic circuit expression figure of the insulated gate bipolar transistor (IGBT: Insulated Gate Bipolar Transistor) of two-in-one module . It is an example of the semiconductor device applied to the power module which concerns on embodiment, Comprising: (a) Typical cross-section figure of SiC MISFET, (b) Typical cross-section figure of IGBT. It is an example of the semiconductor device applied to the power module which concerns on embodiment, Comprising: The typical cross-section figure of SiC MISFET containing source pad electrode SP and gate pad electrode GP. It is an example of the semiconductor device applied to the power module which concerns on embodiment, Comprising: The typical cross-section figure of IGBT containing emitter pad electrode EP and gate pad electrode GP. It is an example of the semiconductor device applicable to the power module which concerns on embodiment, Comprising: The typical cross-section figure of a SiC DI (Double Implanted) MISFET. It is an example of the semiconductor device applicable to the power module which concerns on embodiment, Comprising: The typical cross-section figure of a SiC trench (T: Trench) MISFET. In a schematic circuit configuration of a three-phase AC inverter configured using the power module according to the embodiment, (a) a circuit in which a SiC MISFET is applied as a semiconductor device and a snubber capacitor is connected between the power supply terminal PL and the ground terminal NL Configuration example, (b) A circuit configuration example in which an IGBT is applied as a semiconductor device and a snubber capacitor is connected between the power supply terminal PL and the ground terminal NL. The schematic circuit block diagram of the 3-phase alternating current inverter comprised using the power module which concerns on embodiment which applied SiC MISFET as a semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS The typical circuit block diagram of the 3-phase alternating current inverter comprised using the power module which concerns on embodiment which applied IGBT as a semiconductor device.

  Next, embodiments of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between the thickness of each component and the planar dimension etc. is different from the actual one. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that parts having different dimensional relationships and ratios among the drawings are included.

  Further, the embodiments described below illustrate apparatuses and methods for embodying the technical idea of the present invention, and the embodiments of the present invention are the materials, shapes, and structures of respective components. , Arrangement, etc. are not specified to the following. Various modifications can be made to the embodiments of the present invention within the scope of the claims.

[Comparative example]
In the power module according to the comparative example, laser welding is performed by irradiating the laser beam hv in an electrode connection structure that connects the stress buffer layer (CuMo electrode) 254 disposed on the semiconductor device 1 and the lead frame (Cu) 250. A schematic cross-sectional structure for explaining the formation of the portion 160 is represented as shown in FIG.

  As the stress buffer layer, Cu / CuMo clad or Cu / CuW clad is applicable. CuMo and CuW are sintered bodies of Cu and Mo or Cu and W and are expensive. It is necessary to form a clad layer structure in which Cu is attached to at least one side of these materials, which is an expensive material.

  In the power module according to the comparative example, a state where the stress buffer layer (CuMo electrode) 254 is irradiated with the laser light hv is represented as shown in FIG.

  Although CuMo and CuW are effective as the stress buffer layer 254, when trying to weld them to the lead frame (Cu) 250 using, for example, a YAG laser, there arises a disadvantage of sputtering of Cu. That is, when the stress buffer layer (CuMo electrode) 254 is irradiated with the laser light hv, the melting point of Cu is 1083 ° C., but the melting point of Mo is 2620 ° C., as schematically shown in FIG. To melt with YAG laser light, it must be heated to at least 2620.degree. However, since the boiling point of Cu is 2570 ° C., when it is melted to Mo of CuMo, the boiling point of Cu is exceeded, and as a result, the portion melted by the laser beam is spattered and scattered. In the case of CuW, since the melting point of W is 3400 ° C., the same result is obtained.

  In order to avoid this, it is possible to use a Cu / CuMo clad in which Cu is laminated on the upper surface of a CuMo material. In the case of CuW, it is Cu / CuW clad.

  In the power module according to the comparative example, in the structure in which the lead frame 250 is disposed on the Cu clad layer 252 / CuMo stress buffer layer 254, laser light hv is irradiated through the lead frame 250 to lead the lead frame 250 and the Cu clad layer 252. The laser-welded state of and is represented as shown in FIG. As shown in FIG. 3, the laser beam hv is scattered in the welding portion 160 and melting of the welding portion 160 proceeds. When the melting of the weld 160 proceeds to the bottom of the Cu clad layer 252 and reaches the surface 254 S of the CuMo stress buffer layer 254, a cavity 254 A is easily formed in the CuMo stress buffer layer 254. Also, assuming that these clad structures are used as the stress buffer layer 254, the lead frame 250 is stacked directly on the semiconductor device 1, and when irradiated with YAG laser light hν from above, the semiconductor is caused by welding variation. Laser light may reach the surface of the device.

  The schematic cross-sectional structure of the power module 20A according to the comparative example 1 is represented as shown in FIG. 4, and the schematic cross-sectional structure of the power module 20A according to the comparative example 2 is represented as shown in FIG. A schematic cross-sectional structure of the power module 20A according to No. 3 is represented as shown in FIG.

  The power module 20A according to the comparative example 1 has a wiring structure by wire wiring as shown in FIG. Further, as shown in FIGS. 5 and 6, the power modules according to Comparative Examples 2 and 3 have a wiring structure by lead frame wiring.

As shown in FIG. 4, the power module 20A according to the comparative example 1 includes the semiconductor device 1 disposed on the insulating circuit substrate 8 via the lower chip bonding layer 2 and the bonding wire 51 for connecting the semiconductor device 1 to _{each other.} When, and a bonding wire 5 ₂ for connecting the semiconductor device 1 and the surface copper foil 6. Insulated circuit board 8 includes ceramic substrate 4, front surface copper foils 3 and 6 disposed on the front surface of ceramic substrate 4, and back surface copper foil 7 disposed on the back surface of ceramic substrate 4.

  The power modules 20A according to Comparative Examples 2 and 3 are disposed on the semiconductor device 1 and the semiconductor device 1 disposed on the insulating circuit substrate 8 via the lower chip bonding layer 2 as shown in FIGS. The on-chip bonding layer 9, the stress buffer layer 10 disposed on the on-chip bonding layer 9, the stress buffer layer bonding layer 11 disposed on the stress buffer layer 10, and the stress buffer layer bonding layer 11 And a lead frame 12 disposed on the Further, the lead frame 12 is connected to the surface copper foil 6 disposed on the surface of the ceramic substrate 4 via the lower lead frame bonding layer 13.

When a copper or aluminum lead frame 12 is bonded to the upper surface of the semiconductor device 1, stress is generated in the bonding surface and cracks occur in the bonding material or the semiconductor chip when exposed to a cold thermal environment due to the difference in thermal expansion coefficient. Resulting in. In order to avoid this, the lead frame 12 of copper or aluminum is not directly bonded to the top surface of the semiconductor device 1, and as shown in FIGS. 5 and 6, between the top surface of the semiconductor device 1 and the lead frame 12 It is possible to sandwich a material close to the thermal expansion coefficient of the semiconductor device (Si or SiC) 1. That is, the value of the thermal expansion coefficient of Si or SiC is about 3 × 10 ⁻⁶ / K, the value of the thermal expansion coefficient of the lead frame is about 17 × 10 ⁻⁶ / K in the case of copper, in the case of aluminum ^Is about 24 × 10 ⁻⁶ / K. Therefore, as shown in FIGS. 5 and 6, the thermal expansion coefficient of a molybdenum plate, a tungsten plate, a CuMo sintered body, a CuW sintered body, or the like between the upper surface of the semiconductor device (Si or SiC) 1 and the lead frame 12 is low. Insert the material (stress buffer layer 10). Here, the thermal expansion coefficient of CuMo is, for example, about 8 ppm / K to about 10 ppm / K.

  If the semiconductor device 1 is a single chip in the laminated structure of the semiconductor device 1 / the bonding layer 9 on the chip / the bonding layer 10 on the chip / the bonding layer 11 on the stress buffer layer / the lead frame 12, the variation in height is a problem. Although this is not the case, in practice, the semiconductor devices 1 are arranged in parallel in a plurality of chips to secure the current capacity, so that variations in thickness occur as shown in FIG. 6 and wiring using the lead frame 12 is difficult.

First Embodiment
The laser applicable as the manufacturing technology of the power module according to the first embodiment is, for example, a YAG laser or a second harmonic of a YAG laser, YLF (YLiF ₄ : Yuttrium Lithium Fluoride) laser, YVO ₄ (YVO ₄ : Yuttrium Vanadium Qxide laser, KrF laser, CO ₂ laser, or CO laser.

  The relationship between the reflectance R (%) of the laser beam to the metal material (Ag, Cu, Al, Ni, Fe) and the laser wavelength λ (μm) is expressed as shown in FIG.

  In the power module 20 according to the first embodiment, the principle of the laser light irradiation is expressed as shown in FIG.

  The power module 20 according to the first embodiment, as shown in FIG. 8, is a power module in which the semiconductor device 1 is mounted on the substrate surface and the lead frame 15 is joined to the upper surface of the semiconductor device 1. The stress buffer layer 14 having a thermal expansion coefficient difference between the lead frame 15 and the lead frame 15 has a structure in which a material having a low thermal expansion coefficient is sandwiched between the semiconductor device 1 and the lead frame 15. Here, the thermal expansion coefficient of the stress buffer layer 14 is equal to or less than the thermal expansion coefficient of the lead frame 15, and the shape of the stress buffer layer 14 is L-shaped.

  The stress buffer layer 14 and the lead frame 15 are connected by laser welding on the L-shaped side surface of the stress buffer layer 14 in the direction perpendicular to the top surface of the semiconductor device 1 as shown in FIG. The laser beam hv is not irradiated to the surface of the stress buffer layer 14 in focus as shown by a broken line in FIG. 8, but is defocused on the surface of the stress buffer layer 14 as shown by a solid line. The irradiation is desirable because the area of the laser weld 160 can be expanded.

  A schematic plane pattern configuration of the power module 20 according to the first embodiment is represented as shown in FIG. 9, and a side view observed from the IA-IA direction is represented as shown in FIG. 10. Moreover, another side view observed from the IA-IA direction is represented as shown in FIG. Furthermore, a schematic cross-sectional structure taken along the line II is represented as shown in FIG. 12 (a), and a schematic cross-sectional structure taken along the line II-II is represented as shown in FIG. 12 (b) .

  The power module 20 according to the first embodiment includes a first metal circuit pattern 3, a semiconductor device 1 disposed on the first metal circuit pattern 3, and a semiconductor device 1 as shown in FIGS. 9 to 12. And a stress buffer layer 14 disposed on the top surface of the semiconductor device 1 and capable of buffering a thermal expansion coefficient difference between the semiconductor device 1 and the lead frame 15. Here, the lead frame 15 is connected to the semiconductor device 1 through the stress buffer layer 14, and the thermal expansion coefficient of the stress buffer layer 14 is equal to or less than the thermal expansion coefficient of the lead frame 15 and of the stress buffer layer 14. The cross-sectional shape is L-shaped.

  Here, the first metal circuit pattern 3 is formed of a surface copper foil disposed on the ceramic substrate 4. In addition, a back surface copper foil 7 is formed on the back surface of the ceramic substrate 4. An insulating circuit board 8 formed of a DBC (Direct Bonding Copper) board is constituted by the front side copper foil 3 · 6 / ceramic substrate 4 / back side copper foil 7. Further, as the insulating circuit board 8, a direct brazed aluminum (DBA) board or an active metal brazed (AMB) board may be used.

  Further, as shown in FIG. 12, the lead frame 15 and the stress buffer layer 14 are connected at the L-shaped side surface of the stress buffer layer 14 in the direction perpendicular to the top surface of the semiconductor device 1.

  Further, as shown in FIGS. 9 to 12, the stress buffer layer 14 and the lead frame 15 are joined at the weld portion 16 by laser welding. Moreover, you may join by spot welding.

  The semiconductor device 1 is connected to the first metal circuit pattern 3 via the lower chip bonding layer 2 disposed on the first metal circuit pattern 3. The lower chip bonding layer 2 may be, for example, a lower chip solder layer. In addition, electrical connection between the surface of the first metal circuit pattern 3 and the semiconductor device 1 may be performed using baked silver. That is, baked silver such as an Ag particle layer or an Ag nanoparticle layer formed in advance on the back electrode of the semiconductor device 1 may be applied as the lower chip bonding layer 2 as it is.

  The semiconductor device 1 is also connected to the stress buffer layer 14 via the on-chip bonding layer 9. The on-chip bonding layer 9 may be, for example, a on-chip solder layer. Further, the electrical connection between the semiconductor device 1 and the stress buffer layer 14 may be performed using baked silver. That is, baked silver such as an Ag particle layer or an Ag nanoparticle layer formed in advance on the surface electrode of the semiconductor device 1 may be applied as the on-chip bonding layer 9 as it is.

  The stress buffer layer 14 may be formed of kovar or invar.

The stress buffer layer 14 may be formed of an Fe-Ni-based alloy or a Ni-Mo-Fe-based alloy. That is, in the power module 20 according to the first embodiment, the stress buffer layer 14 does not use an expensive material such as Cu / CuMo clad or Cu / CuW clad, and the thermal expansion coefficient is relatively large. Kovar (thermal expansion coefficient is 5 × 10 ^-6 / K, melting point is 1450 ° C.), invar (thermal expansion coefficient is 0.5) as a low cost material having a relatively low melting point and being cheaper than these clad materials. ^{× 10 -6 / K~2 × 10 -6} / K, a melting point of 1425 ℃) Fe-Ni based alloys such as Hastelloy B2 (thermal expansion coefficient of 10.8 × 10 ^-6 / K, a melting point of 1302 ° C. ~ You may use Ni-Mo-Fe type | system | group alloys, such as 1368 degreeC.

  Moreover, the power module 20 which concerns on 1st Embodiment may be equipped with the 2nd metal circuit pattern 6 connected with the lead frame 15, as shown to FIGS.

  Here, as shown in FIGS. 9 to 10, the lead frame 15 and the second metal circuit pattern 6 are joined by laser welding at the welding portion 17. Moreover, you may join by spot welding.

The laser applicable as a manufacturing technique of the power module according to the first embodiment is, for example, YAG laser or second harmonic of YAG laser, YLF laser, YVO ₄ laser, KrF laser, CO ₂ laser, CO laser It is either. At the wavelength (1064 nm) of the YAG laser, the reflectance R is as high as about 90% when applied directly to the welding of the Cu surface, so the YAG laser (wavelength In the case of using 1064 nm), for example, Ni plating is performed on the Cu surface. Also, the Cu surface may be oxidized.

  The power module 20 according to the first embodiment may include the ceramic substrate 4 as shown in FIGS. 9 to 10, and the first metal circuit pattern 3 may be disposed on the ceramic substrate 4. That is, the first metal circuit pattern 3 is formed of a front surface copper foil disposed on the ceramic substrate 4, and the rear surface copper foil 9 is formed on the rear surface of the ceramic substrate 4. The front surface copper foil 3 / ceramic substrate 4 / back surface copper foil 7 constitute an insulating circuit substrate 8 of a DBC substrate. Further, the second metal circuit pattern 6 is disposed on the ceramic substrate 4 in the same manner as the first metal circuit pattern 3.

  Further, as shown in FIGS. 9 and 11, the power module 20 according to the first embodiment includes the insulating layer substrate 40, and the first metal circuit pattern 3 is disposed on the insulating layer substrate 40. Also good. Also, the second metal circuit pattern 6 may be disposed on the insulating layer substrate 40 in the same manner as the first metal circuit pattern 3. Here, the insulating layer substrate 40 may be formed of, for example, an organic insulating resin layer.

  The laser applicable as the manufacturing technology of the power module 20 according to the first embodiment is irradiated with the welding portion 16 through the laser irradiation window (34: see, for example, FIGS. 18 and 19). The window 34 for laser irradiation should just be a spatial space which can irradiate laser-beam h (nu) to the welding part 16. FIG. The irradiation direction of the laser light hv is, for example, a direction perpendicular to the surface of the lead frame 15 disposed on the side surface of the L-shaped stress buffer layer 14 in FIGS. 12 (a) and 12 (b).

  As shown in FIG. 12 (a) and FIG. 12 (b), the rising height of the L-shaped stress buffer layer 14 is represented by D1 in the inner part, while it is arranged on the side of the stress buffer layer 14 The width (length in the height direction) of the lead frame 15 is represented by T3. In the structural example of FIG. 12A, the width T3 of the lead frame 15 is included in the range of the rising height D1 of the stress buffer layer 14. On the other hand, in the structural example of FIG. 12B, the width T3 of the lead frame 15 is only partially included in the range of the rising height D1 of the stress buffer layer 14. However, since the rising portions of the lead frame 15 and the stress buffer layer 14 in the example of FIG. 12B overlap the portions of D1-T2, the laser light is shown in FIG. 12B on this overlapping portion. By irradiating hv, laser welding of the lead frame 15 and the stress buffer layer 14 can be performed.

  As described above, in the power module 20 according to the first embodiment, when the semiconductor devices 1 are arranged in parallel in a plurality of chips, the first metal circuit pattern 3 / the under-chip bonding layer 2 / the semiconductor device 1 / on the chip Even if thickness variations occur in the laminated structure of the stress buffer layer 14 having the bonding layer 9 / L-shaped structure, as shown in FIGS. 12 (a) and 12 (b), the variations in the thickness of the laminated portion described above It can be absorbed at the overlapping portion of the side surface of the L-shaped structure of the stress buffer layer 14 and the lead frame 15.

  Further, in the power module 20 according to the first embodiment, as shown in FIGS. 12A and 12B, the junction between the stress buffer layer 14 and the lead frame 15 is directly on the semiconductor device 1. For example, the L-shaped metal fitting is taken out in the side direction of the semiconductor device 1, and the lead frame 15 is laser welded there. As a result, even if there is variation in laser welding (variation in penetration amount), the semiconductor device 1 is not damaged, and the yield can be improved.

  The power module 20 according to the first embodiment differs from the power module 20A according to the comparative example in bonding the stress buffer layer 14 on the semiconductor device 1, but the shape is not flat. , L-shaped. Further, a lead frame 15 made of Cu, Cu alloy, aluminum or aluminum alloy is welded to the L-shaped stress buffer layer 14. Since the weld portion 16 is not disposed immediately above the semiconductor device 1, it is possible to avoid tip damage due to welding variations in the formation of a junction by laser welding. Moreover, spot welding is also applicable instead of laser welding.

  Furthermore, according to the power module of the first embodiment, since a bonding wire is not used for the main wiring, an Ag sintered material can be used as a bonding material. For example, high temperature operation of SiC semiconductor devices at around 300 ° C. It is possible to

(Production method)
The method of manufacturing the power module 20 according to the first embodiment includes the steps of forming the first metal circuit pattern 3, forming the semiconductor device 1 on the first metal circuit pattern 3, and the upper surface of the semiconductor device 1. Forming the stress buffer layer 14 having an L-shaped cross section, and connecting the lead frame 15 and the stress buffer layer 14 on the L-shaped side surface of the stress buffer layer 14 in the direction perpendicular to the top surface of the semiconductor device 1. And a process. Here, the thermal expansion coefficient of the stress buffer layer 14 is equal to or less than the thermal expansion coefficient of the lead frame 15, and the stress buffer layer 14 can buffer the thermal expansion coefficient difference between the semiconductor device 1 and the lead frame 15.

  Further, the step of connecting the lead frame 15 and the stress buffer layer 14 is performed by laser welding. Moreover, you may implement by spot welding.

  Furthermore, a step of forming the second metal circuit pattern 6 and a step of connecting the second metal circuit pattern 6 and the lead frame 15 may be included.

  Here, the step of connecting the second metal circuit pattern 6 and the lead frame 15 is performed by laser welding. Moreover, you may implement by spot welding.

  In addition, the method of manufacturing the power module 20 according to the first embodiment may include the steps of preparing a substrate and disposing the first metal circuit pattern 3 on the substrate. Furthermore, the method may have the step of arranging the second metal circuit pattern 6 on the substrate.

  The method of manufacturing the power module 20 according to the first embodiment includes the steps of preparing the insulating layer substrate 40 and disposing the first metal circuit pattern 3 on the insulating layer substrate 40. Also good. Furthermore, the process of disposing the second metal circuit pattern 6 on the insulating layer substrate 40 may be included.

(Modification 1)
In the power module 20 according to the first modification of the first embodiment, the stress buffer of the ceramic substrate 4 / first metal circuit pattern 3 / under-chip bonding layer 2 / semiconductor device 1 / upper-chip bonding layer 9 / L-shaped structure A schematic cross-sectional structure of the layered structure of the layer 14 is represented as shown in FIG. 13A, and a schematic cross-sectional structure of a portion having a different thickness of the above-described layered structure is as shown in FIG. expressed. Here, FIG. 13 (a) corresponds to a schematic cross sectional structure along FIG. 12 (a) showing a schematic cross sectional structure along line II in FIG. 9, and FIG. 13 (b) corresponds to FIG. Corresponds to a schematic cross-sectional structure along FIG. 12 (b) showing a schematic cross-sectional structure along the II-II line.

  In the power module 20 according to the first modification of the first embodiment, as shown in FIGS. 13 (a) and 13 (b), the lead frame 15 is formed inside the L-shaped structure of the stress buffer layer 14. It is disposed on the rising side and is joined by laser welding at the welding portion 16.

  That is, in the first embodiment, the weld portion 16 is extended in the side direction of the semiconductor device 1 using the L-shaped stress buffer layer 14, and the lead frame 15 is laser welded there. On the other hand, in the power module 20 according to the first modification of the first embodiment, the lead frame 15 is laser welded to the inner side rising side surface of the L-shaped structure of the stress buffer layer 14.

  The laser beam applicable as a manufacturing technique of power module 20 concerning modification 1 of a 1st embodiment is irradiated with welding part 16 via a window for laser irradiation. The window for laser irradiation may be a spatial space where the laser light hv can be irradiated to the welding portion 16. The irradiation direction of the laser light hv is, for example, in a direction perpendicular to the surface of the lead frame 15 disposed on the rising side on the inner side of the L-shaped stress buffer layer 14 in FIGS. 13 (a) and 13 (b). is there.

(Modification 2)
In the power module 20 according to the second modification of the first embodiment, stress buffer of ceramic substrate 4 / first metal circuit pattern 3 / under-chip bonding layer 2 / semiconductor device 1 / upper-chip bonding layer 9 / L-shaped structure A schematic cross-sectional structure of the layered structure of the layer 14 is represented as shown in FIG. 14 (a), and a schematic cross-sectional structure of a portion of the layered structure different in thickness as shown in FIG. 14 (b). expressed. Here, FIG. 14 (a) corresponds to a schematic sectional structure along FIG. 12 (a) showing a schematic sectional structure along line II in FIG. 9, and FIG. 14 (b) corresponds to FIG. Corresponds to a schematic cross-sectional structure along FIG. 12 (b) showing a schematic cross-sectional structure along the II-II line.

  In the power module 20 according to the second modification of the first embodiment, as shown in FIGS. 14 (a) and 14 (b), the lead frame 15 is formed inside the L-shaped structure of the stress buffer layer 14. It is disposed on the rising side and is joined by laser welding at the welding portion 16.

  In the power module 20 according to the first modification of the first embodiment, the lead frame 15 is laser welded to the inner side rising side of the L-shaped structure of the stress buffer layer 14. In the second modification of the first embodiment, the lead frame 15 laser-welded to the inner side surface of the L-shaped stress buffer layer 14 is a semiconductor compared to the first modification of the first embodiment. It is disposed further inside in the side direction of the device 1.

  According to the first embodiment and its modification, the lead frame structure enables downsizing, large current capacity, and cost reduction, and suppresses variations in welding without damaging semiconductor devices and improves yield. A power module and a method of manufacturing the same can be provided.

Second Embodiment
The power module 20 according to the second embodiment, as shown in FIG. 15, is a power module in which the semiconductor device 1 is mounted on the surface and the lead frame 15 is joined to the upper surface of the semiconductor device 1. The stress buffer layer 14 has a thermal expansion coefficient difference between the lead frame 15 and the lead frame 15 and a structure in which a material having a low thermal expansion coefficient is sandwiched between the semiconductor device 1 and the lead frame 15. Here, the thermal expansion coefficient of the stress buffer layer 14 is equal to or less than the thermal expansion coefficient of the lead frame 15, and the shape of the stress buffer layer 14 is U-shaped.

  In the power module 20 according to the second embodiment, a laminate of ceramic substrate 4 / first metal circuit pattern 3 / lower chip bonding layer 2 / semiconductor device 1 / upper bonding layer 9 / U-shaped stress buffer layer 14R A schematic cross-sectional structure of the structure is represented as shown in FIG. 15 (a), and a schematic cross-sectional structure of the portion with a different thickness of the above laminated structure is represented as shown in FIG. 15 (b). Here, FIG. 15 (a) shows a schematic cross-sectional structure along FIG. 12 (a) showing a schematic cross-sectional structure along the line II in the power module 20 (FIG. 9) according to the first embodiment. 15B corresponds to a schematic cross-sectional structure along FIG. 12B that represents a schematic cross-sectional structure along line II-II in FIG.

  In the power module 20 according to the second embodiment, as shown in FIGS. 15A and 15B, the lead frame 15 is separated from the upper surface of the semiconductor device 1 and the upper surface of the semiconductor device 1 Are disposed on the U-shaped side surface of the stress buffer layer 14R in the direction parallel to the direction.

  The laser applicable as the manufacturing technology of the power module 20 according to the second embodiment is irradiated with the welding portion 16 through the laser irradiation window. The window for laser irradiation may be a spatial space where the laser light hv can be irradiated to the welding portion 16. The irradiation direction of the laser light hv is, for example, a direction perpendicular to the surface of the lead frame 15 disposed outside the U-shaped side surface of the U-shaped stress buffer layer 14R in FIGS. 15 (a) and 15b).

  The power module 20 according to the second embodiment includes a first metal circuit pattern 3 and a semiconductor device disposed on the first metal circuit pattern 3 as shown in FIGS. 15 (a) and 15 (b). 1, a lead frame 15 electrically connected to the semiconductor device 1, and a stress buffer layer disposed on the top surface of the semiconductor device 1 and capable of buffering a thermal expansion coefficient difference between the semiconductor device 1 and the lead frame 15 And 14R. Here, the lead frame 15 is connected to the semiconductor device 1 through the stress buffer layer 14R, and the thermal expansion coefficient of the stress buffer layer 14R is equal to or less than the thermal expansion coefficient of the lead frame 15 and of the stress buffer layer 14R. The cross-sectional shape has a U-shape.

  Further, the lead frame 15 and the stress buffer layer 14R are separated from the upper surface of the semiconductor device 1 and connected at the U-shaped side surface of the stress buffer layer 14R in a direction parallel to the upper surface of the semiconductor device 1.

  Further, as shown in FIGS. 15A and 15B, the stress buffer layer 14R and the lead frame 15 are joined by laser welding at the weld portion 16. Moreover, you may join by spot welding.

In the power module 20 according to the second embodiment, as the stress buffer layer 14R, the thermal expansion coefficient is relatively low and the melting point is relatively low. (coefficient of thermal expansion 5 × 10 ^-6 / K, a melting point of 1450 ° C.), Invar (thermal expansion coefficient of ^{0.5 × 10 -6 / K~2 × 10} -6 / K, a melting point of 1425 ° C.), such as You may use Ni-Mo-Fe type alloys, such as Fe-Ni type alloy and hastelloy B2 (The thermal expansion coefficient is 10.8 * 10 < ^-6 > / K, melting | fusing point is 1302 degreeC-1368 degreeC).

The laser applicable as a manufacturing technology of the power module according to the second embodiment is, for example, YAG laser or second harmonic of YAG laser, YLF laser, YVO ₄ laser, KrF laser, CO ₂ laser, CO laser It is either.

  Further, in the power module 20 according to the second embodiment, as shown in FIGS. 15 (a) and 15 (b), the junction between the stress buffer layer 14 and the lead frame 15 is directly above the semiconductor device 1. Laser welding to the surface of the lead frame 15 disposed outside the U-shaped side surface of the U-shaped stress buffer layer 14R. As a result, even if there is variation in laser welding (variation in penetration amount), the semiconductor device 1 is not damaged, and the yield can be improved. Further, by using the stress buffer layer 14R having a U-shaped structure, it is possible to achieve high strength by the spring effect of the U-shaped structure.

  The power module 20 according to the second embodiment differs from the power module 20A according to the comparative example in bonding the stress buffer layer 14 on the semiconductor device 1, but the shape is not flat. , U-shaped. Further, a lead frame 15 made of Cu, Cu alloy, aluminum or aluminum alloy is welded to the U-shaped stress buffer layer 14. Since the weld portion 16 is not disposed immediately above the semiconductor device 1, it is possible to avoid tip damage due to welding variations in the formation of a junction by laser welding. Moreover, spot welding is also applicable instead of laser welding.

  Furthermore, according to the power module of the second embodiment, since a bonding wire is not used for the main wiring, an Ag sintered material can be used as a bonding material. For example, high temperature operation of SiC semiconductor devices at around 300 ° C. It is possible to

  According to the power module of the second embodiment, cost reduction of the module can be reduced because expensive stress cushioning material is not used.

  According to the power module of the second embodiment, the yield can be improved because the laser welding is not performed directly on the semiconductor device.

(Production method)
The method of manufacturing the power module 20 according to the second embodiment includes the steps of forming the first metal circuit pattern 3, forming the semiconductor device 1 on the first metal circuit pattern 3, and the upper surface of the semiconductor device 1. Forming a stress buffer layer 14R having a U-shaped cross section, and a lead at a U-shaped side surface of the stress buffer layer 14R which is separated from the upper surface of the semiconductor device 1 and parallel to the upper surface of the semiconductor device 1; Connecting the frame 15 and the stress buffer layer 14R. The thermal expansion coefficient of the stress buffer layer 14R is equal to or less than the thermal expansion coefficient of the lead frame 15, and the stress buffer layer 14R can buffer the thermal expansion coefficient difference between the semiconductor device 1 and the lead frame 15.

  The step of connecting the lead frame 15 and the stress buffer layer 14R is performed by laser welding. Moreover, you may implement by spot welding.

  Moreover, the manufacturing method of the power module 20 which concerns on 2nd Embodiment may have the process of preparing a board | substrate, and the process of arrange | positioning the 1st metal circuit pattern 3 on a board | substrate.

  The method of manufacturing the power module 20 according to the second embodiment includes the steps of preparing the insulating layer substrate 40 and disposing the first metal circuit pattern 3 on the insulating layer substrate 40. Also good.

  According to the second embodiment, it is possible to reduce the size and increase the current capacity and reduce the cost by the lead frame structure, and to suppress the variation of welding without damaging the semiconductor device and improve the yield, and the power module A manufacturing method can be provided.

Third Embodiment
A power module 200 according to a third embodiment, which is a two-in-one module (2 in 1 Module: module including a half bridge), and a schematic plane pattern configuration before forming the mold resin layer 33 is as shown in FIG. expressed. Here, in FIG. 16, the substrate 4 corresponds to the ceramic substrate, and the substrate 40 corresponds to the insulating layer substrate (FIG. 19) as a modification.

  The circuit configuration of a two-in-one module (half-bridge built-in module) corresponding to FIG. 16 which is a power module according to the third embodiment and to which a SiC MISFET is applied as a semiconductor device is represented as shown in FIG. Ru. In FIG. 16, a side view observed from the IIA-IIA direction is represented as shown in FIG. 18.

  In the power module 200 according to the third embodiment, in the half bridge built-in module, a schematic birdcage configuration after forming the mold resin layer 33 is represented as shown in FIG. In the power module 200 according to the third embodiment, the mold resin layer 33 may be provided, and the power module may be transfer molded by the mold resin layer 33.

  The power module 200 according to the third embodiment has a configuration of a half bridge built-in module in which two MISFETs Q1 and Q4 are incorporated in one module. As shown in FIG. 16, the MISFETs Q1 and Q4 are arranged in two chips in parallel, and the diodes DI1 and DI4 are also arranged in two chips in parallel. The diodes DI1 and DI4 are connected in antiparallel between D1 and S1 and between D4 and S4 of the MISFETs Q1 and Q4.

  In the power module 200 according to the third embodiment, as shown in FIGS. 16 and 21, the positive side power terminal P disposed on the first side of the substrate 4 (40) coated with the mold resin layer 33. And the negative power terminal N, the gate terminal GT1 arranged on the second side adjacent to the first side, and the source sense terminal SST1, and the output terminal arranged on the third side opposed to the first side O, and a gate terminal GT4 and a source sense terminal SST4 arranged on the fourth side opposite to the second side. Here, as shown in FIG. 16, the gate terminal GT1 · source sense terminal SST1 is connected to the gate signal wiring pattern GL1 · source signal wiring pattern SL1 of the MISFET Q1, and the gate terminal GT4 · source sense terminal SST4 is the MISFET Q4. The gate signal wiring pattern GL4 and the source signal wiring pattern SL4 are connected.

  A gate wire and a source sensing wire are connected from the MISFETs Q1 and Q4 toward the gate signal wiring patterns GL1 and GL4 and the source sensing signal wiring patterns SL1 and SL4. Further, gate terminals GT1 and GT4 for external extraction and SST1 and SST4 are connected to the gate signal wiring patterns GL1 and GL4 and the source sensing signal wiring patterns SL1 and SL4 by soldering or the like.

  The positive side power terminal P and the negative side power terminal N, and the gate terminals GT1 and GT4 and SST1 and SST4 for external extraction can be formed of, for example, Cu.

The ceramic substrate 4 may be made of, for example, Al ₂ O ₃ , AlN, SiN, AlSiC, or SiC having an insulating surface.

  The first metal circuit pattern 3 and the second metal circuit pattern 6 can be formed of, for example, Cu, Al or the like. The gate wire and the source sense wire can be made of, for example, Al, AlCu or the like.

  As the MISFETs Q1 and Q4, a SiC-based power device such as a SiC DIMISFET or a SiC TMISFET, or a GaN-based power device such as a GaN-based high electron mobility transistor (HEMT) can be applied. Further, depending on the case, power devices such as Si-based MISFETs and IGBTs are also applicable.

  As the diodes D1 and D4, a Schottky barrier diode (SBD: Schottky Barrier Diode) or the like can be applied.

  The power module 200 according to the third embodiment, as shown in FIGS. 16 and 18, includes a first metal circuit pattern 3, semiconductor devices Q1 and DI1 disposed on the first metal circuit pattern 3, and a semiconductor The lead frame 15-1 electrically connected to the device Q1 · DI1 is disposed on the top surface of the semiconductor device Q1 · DI1 to buffer the thermal expansion coefficient difference between the semiconductor device Q1 · DI1 and the lead frame 15-1. And a stress buffer layer 14-1 that is possible. Here, the lead frame 15-1 is connected to the semiconductor devices Q1 and DI1 through the stress buffer layer 14-1, and the thermal expansion coefficient of the stress buffer layer 14-1 is the thermal expansion coefficient of the lead frame 15-1. The cross-sectional shape of the stress buffer layer 14-1 is L-shaped.

  Further, as shown in FIGS. 16 and 18, the lead frame 15-1 and the stress buffer layer 14-1 are connected at the L-shaped side surface of the stress buffer layer 14-1 in the direction perpendicular to the upper surface of the semiconductor device Q1 · DI1. Be done.

  Further, as shown in FIGS. 16 and 18, the stress buffer layer 14-1 and the lead frame 15-1 are joined by laser welding at the welding portion 16. Moreover, you may join by spot welding.

  The semiconductor devices Q 1 and DI 1 are connected to the first metal circuit pattern 3 via the lower chip bonding layer 2 disposed on the first metal circuit pattern 3. The lower chip bonding layer 2 may be, for example, a lower chip solder layer. Further, the electrical connection between the surface of the first metal circuit pattern 3 and the semiconductor devices Q1 and DI1 may be implemented using baked silver. That is, baked silver such as an Ag particle layer or an Ag nanoparticle layer formed in advance on the back electrode of the semiconductor device 1 may be applied as the lower chip bonding layer 2 as it is.

  The semiconductor devices Q1 and DI1 are connected to the stress buffer layer 14-1 via the on-chip bonding layer 9. The on-chip bonding layer 9 may be, for example, a on-chip solder layer. Further, the electrical connection between the semiconductor devices Q1 and DI1 and the stress buffer layer 14-1 may be implemented using calcined silver. That is, baked silver such as an Ag particle layer or an Ag nanoparticle layer formed in advance on the surface electrode of the semiconductor device Q1 · DI1 may be applied as it is as the bonding layer 9 on the chip.

  The stress buffer layer 14-1 may be formed of kovar or invar. The stress buffer layer 14-1 may be formed of an Fe-Ni-based alloy or a Ni-Mo-Fe-based alloy.

  Further, as shown in FIG. 16, the power module 200 according to the third embodiment may include the second metal circuit pattern 6 connected to the lead frame 15-1. Here, as shown in FIG. 16, the lead frame 15-1 and the second metal circuit pattern 6 are joined by laser welding at the welding portion 17. Moreover, you may join by spot welding.

  Further, in the power module 200 according to the third embodiment, the positive side power terminal P (D1), the negative side power terminal N (S4), the output terminal O (D4), O (S1) are shown in FIG. As described above, in the welding portion 17, welding is performed by laser welding. Moreover, you may join by spot welding.

  Furthermore, as shown in FIG. 16, the power module 200 according to the third embodiment is electrically connected to the semiconductor devices Q4 and DI4 disposed on the second metal circuit pattern 6 and the semiconductor devices Q4 and DI4. Buffer layer 14-4 disposed on the top surface of the lead frame 15-4 and the semiconductor devices Q1 and DI4 and capable of buffering the thermal expansion coefficient difference between the semiconductor devices Q4 and DI4 and the lead frame 15-4. And Here, the lead frame 15-4 is connected to the semiconductor devices Q4 and DI4 through the stress buffer layer 14-4, and the thermal expansion coefficient of the stress buffer layer 14-4 is the thermal expansion coefficient of the lead frame 15-4. The cross-sectional shape of the stress buffer layer 14 is L-shaped. The other configuration is the same as that of the semiconductor devices Q1 and DI1.

The laser applicable as a manufacturing technique of the power module according to the third embodiment is, for example, YAG laser or second harmonic of YAG laser, YLF laser, YVO ₄ laser, KrF laser, CO ₂ laser, CO laser It is either.

  The power module 200 according to the third embodiment may include the ceramic substrate 4 as shown in FIGS. 16 and 18 and the first metal circuit pattern 3 may be disposed on the ceramic substrate 4. The second metal circuit pattern 6 may also be disposed on the ceramic substrate 4 in the same manner as the first metal circuit pattern 3.

(Window for laser irradiation)
The laser applicable as the manufacturing technology of the power module 200 according to the third embodiment is irradiated with the welding portion 16 through the laser irradiation window. The window for laser irradiation may be a spatial space where the laser light hν can be irradiated to the welding portion 16. The irradiation direction of the laser beam hv is a direction perpendicular to the inner surface of the L-shape of the stress buffer layer 14-1 bonded to the lead frame 15-1 in FIGS. On the other hand, the laser beam hv may be irradiated from the back surface direction perpendicular to the lead frame 15-1 bonded to the outer surface of the L-shaped stress buffer layer 14-1.

  The laser irradiation window 34 shown in FIG. 18 is opened in the lead frame 15-1. The laser light hv may be irradiated from the direction perpendicular to the lead frame 15-4 bonded to the L-shaped outer surface of the stress buffer layer 14-4 through the laser irradiation window 34.

  In the power module 200 according to the third embodiment, by providing the window 34 for laser irradiation on the lead frames 15-1 and 15-4, the arm welding on the opposite side can be performed. Further, as shown in FIG. 16, the lead frame 15-1 on the upper arm side and the lead frame 15-4 on the lower arm side are opposed to each other, and the opposing distance is arranged as close as the insulation withstand voltage can be secured. Parasitic inductance can be reduced, and the surge voltage generated at the time of switching can be reduced.

  In the power module 200 according to the third embodiment, in the case where the semiconductor devices 1 are arranged in parallel in a plurality of chips, the first metal circuit pattern 3 / lower chip junction layer 2 / semiconductor devices Q 1 · DI 1 · Q 4 · DI 4 / Even if thickness variations occur in the laminated structure of the on-chip bonding layer 9 / L-shaped stress buffer layers 14-1 and 14-4, the thickness variations of the laminated portion can be reduced to the stress buffer layers 14-1 and 14-4. The side portions of the L-shaped structure and the lead frames 15-1 and 15-4 can be absorbed at the overlapping portions.

  Further, in the power module 200 according to the third embodiment, as shown in FIG. 16 and FIG. 18, the junction between the stress buffer layers 14-1 and 14-4 and the lead frames 15-1 and 15-4. Are not provided directly on the semiconductor devices Q1, DI1, Q4, DI4, and the L-shaped metal fitting is used to extend the side direction of the semiconductor devices Q1, DI1, Q4, DI4, and the lead frames 15-1, 15-4 are placed here. Since the laser welding is performed, the semiconductor devices Q1, DI1, Q4, and DI4 are not damaged even if there is variation in laser welding (variation in penetration amount), and yield can be improved.

(Modification)
In addition, a side view of a power module 200 according to a modification of the third embodiment, which is observed from the IIA-IIA direction in FIG. 16, is represented as shown in FIG. Further, an enlarged view of a portion A of FIG. 19 is represented as shown in FIG. Moreover, the typical bird's-eye view structure after forming the mold resin layer 33 is represented similarly to FIG.

  In the power module 200 according to the modification of the third embodiment, the insulating layer substrate 40 is applied instead of the ceramic substrate 4 to realize cost reduction and further thinning. The insulating layer substrate 40 can be formed of, for example, an organic insulating resin substrate or the like.

  Further, as shown in FIGS. 16 and 19, the power module 200 according to the third embodiment includes the insulating layer substrate 40, and the first metal circuit pattern 3 is disposed on the insulating layer substrate 40. . The second metal circuit pattern 6 is disposed on the insulating layer substrate 40 in the same manner as the first metal circuit pattern 3. The other configuration is the same as that of the power module according to the third embodiment. Further, a method of manufacturing a power module according to the third embodiment and the modification thereof is the same as that of the first embodiment and the modification thereof.

  According to the third embodiment and its modification, the lead frame structure enables downsizing, large current capacity, and cost reduction, and suppresses variations in welding without damaging the semiconductor device and improves yield. A power module can be provided and a method of manufacturing the same can be provided.

Fourth Embodiment
It is a power module 200 according to the fourth embodiment, and in a two-in-one module (half bridge built-in module), a schematic bird's-eye view configuration before forming a mold resin layer is represented as shown in FIG. In the power module 200 according to the fourth embodiment, as shown in FIG. 22, a metal foil or a metal plate corresponding to the drain D4, the source S1, the source S4, the drain D1, etc. Using metal frame).

  The power module 200 according to the fourth embodiment can constitute, for example, a 1200 V / 150 A power module. The semiconductor devices Q1 and Q4 are formed of, for example, SiC TMOSFETs, and the semiconductor devices DI1 and DI4 are formed of, for example, SBDs. Two semiconductor devices Q1 and Q4 are arranged in parallel, respectively. Two semiconductor devices DI1 and DI4 are also arranged in parallel. The chip size of one SiC TMOSFET is about 3.1 mm × about 4.4 mm, and the chip size of one SBD is about 5.14 mm × about 5.14 mm. Bonding layer under chip · Bonding layer on chip: Ag paste, Ag particle layer, Ag nanoparticle layer, etc., which is formed in advance on the front surface electrode and back surface electrode of semiconductor devices Q1, Q4, DI1, DI4 You may. The thickness of baked silver is, for example, about 20 μm.

  The metal frames corresponding to the lead frames 15-1 and 15-4, the drain D4, the source S1, the source S4 and the drain D1 are made of, for example, pure copper (C1020), and the stress buffer layers 14-1 and 14- are used. 4 is formed of, for example, Kovar (Fe-29Ni-17Co).

  Further, in the power module 200 according to the fourth embodiment, the positive side power terminal P (D1), the negative side power terminal N (S4), the output terminal O (D4), O (S1) are shown in FIG. Thus, they are connected to the metal frame by a columnar electrode structure or the like.

  Further, as shown in FIG. 22, gate terminals GT1 and GT4 for external extraction and SST1 and SST4 are connected to the gate signal wiring patterns GL1 and GL4 and the source sensing signal wiring patterns SL1 and SL4 by soldering or the like. Ru. The gate wires and source sensing wires connected from the MISFETs Q1 and Q4 to the gate signal wiring patterns GL1 and GL4 and the source sensing signal wiring patterns SL1 and SL4 are not shown.

  The power module 200 according to the fourth embodiment may be configured to be able to perform arm welding on the opposite side by providing the window 34 for laser irradiation on the lead frames 15-1 and 15-4. Further, as shown in FIG. 22, the lead frame 15-1 on the upper arm side and the lead frame 15-4 on the lower arm side are opposed to each other, and the opposing distance is arranged close to the extent that withstand voltage can be secured. Parasitic inductance can be reduced, and the surge voltage generated at the time of switching can be reduced. The other configuration is the same as that of the power module 200 according to the third embodiment. Further, a method of manufacturing a power module according to the fourth embodiment is the same as that of the first embodiment.

(Modification)
A power module 200 according to a modification of the fourth embodiment, in a two-in-one module (half-bridge built-in module), a schematic bird's-eye configuration before forming a mold resin layer is represented as shown in FIG. . The power module 200 according to the modification of the fourth embodiment changes the arrangement configuration of the power module 200 according to the fourth embodiment and the semiconductor devices Q1, DI1, Q4, DI4. The other configuration is the same as that of the fourth embodiment. Further, a method of manufacturing a power module according to a modification of the fourth embodiment is the same as that of the first embodiment.

  According to the fourth embodiment and its modification, the lead frame structure enables downsizing, large current capacity, and cost reduction, and suppresses variation in welding without damaging the semiconductor device and improves yield. A power module and a method of manufacturing the same can be provided.

Fifth Embodiment
A power module 200 according to a fifth embodiment, which is a two-in-one module (half-bridge built-in module), a schematic planar pattern configuration before forming the mold resin layer 33 is represented as shown in FIG. A schematic bird's-eye view configuration after forming the resin layer 33 is expressed in the same manner as FIG. In FIG. 24, the side view observed from the direction of IIIA-IIIA is represented as shown in FIG. 25 (a), and the enlarged view of the B portion in FIG. 25 (a) is a table as shown in FIG. Be done. The fifth embodiment differs from the fourth embodiment in that a stress buffer layer is bonded onto semiconductor devices Q1, DI1, Q4, DI4, but the shape is not L-shaped. , U-shaped.

  In the power module 200 according to the fifth embodiment, the stress buffer layers 14R-1 and 14R-4 have a U-shaped structure, and as in FIGS. 15 (a) and 15 (b), the lead frame 15-. 1-15-4 are separated from the top surface of the semiconductor devices Q1 DI1 Q4 DI4, and in a direction parallel to the top surfaces of the semiconductor devices Q1 DI1 Q4 DI4 of the stress buffer layers 14R-1 14R-4. It is arranged at the U-shaped side and joined at the weld 16 by laser welding. As a result, even if there is variation in laser welding (variation in penetration amount), the semiconductor devices Q1, DI1, Q4, DI4 are not damaged, and the yield can be improved. Further, by using the stress buffer layers 14R-1 and 14R-4 having a U-shaped structure, it is possible to achieve high strength by the spring effect of the U-shaped structure.

  The laser applicable as the manufacturing technology of the power module 200 according to the fifth embodiment is irradiated with the welding portion 16 through the window for laser irradiation. The window for laser irradiation may be a spatial space where the laser light hv can be irradiated to the welding portion 16. The irradiation direction of the laser light hv is, for example, a direction perpendicular to the surfaces of the lead frames 15-1 and 15-4 disposed outside the U-shaped side surfaces of the stress buffer layers 14R-1 and 14R-4 in FIG. .

  The power module 200 according to the fifth embodiment, as shown in FIGS. 24 and 25, includes an insulating layer substrate 40, and has a metal circuit pattern (a metal (corresponding to metal) corresponding to the drain D4, source S1, source S4, drain D1 and the like. Frames 3 and 6 are disposed on the insulating layer substrate 40. By applying the insulating layer substrate 40, cost reduction and thinning can be realized. The insulating layer substrate 40 can be formed of, for example, an organic insulating resin substrate or the like. In the power module according to the fifth embodiment, the ceramic substrate 4 may be applied instead of the insulating layer substrate 40.

  Also in the power module 200 according to the fifth embodiment, the lead frame 15-1 on the upper arm side and the lead frame 15-4 on the lower arm side are opposed to each other, and the opposing distance is arranged as close as the insulation withstand voltage can be secured. Thus, the parasitic inductance of the wiring can be reduced, and the surge voltage generated at the time of switching can be reduced. The other configuration is the same as that of the second embodiment and the third embodiment. The method of manufacturing the power module 200 according to the fifth embodiment is also the same as in the second and third embodiments.

  According to the fifth embodiment, it is possible to reduce the size and increase the current capacity and reduce the cost by the lead frame structure, and to suppress the variation of welding without damaging the semiconductor device and improve the yield, and the power module A manufacturing method can be provided.

(Specific example of power module)
Hereinafter, specific examples of the power module according to the embodiment will be described. Of course, also in the power module described below, in a power module in which a semiconductor device is mounted on the surface and a lead frame is bonded to the upper surface of the semiconductor device, a stress buffer layer of the thermal expansion coefficient difference between the semiconductor device and the lead frame As a structure in which a material having a low thermal expansion coefficient is sandwiched between the semiconductor device and the lead frame, the thermal expansion coefficient of the stress buffer layer is equal to or less than the thermal expansion coefficient of the lead frame, and the shape of the stress buffer layer is L-shaped or The point provided with the U-shape is the same as the above embodiment. It is also possible to provide a power module that can be reduced in size, increased in current capacity, reduced in cost, reduced in welding variations without damaging semiconductor devices, and a method of manufacturing the same by the lead frame structure. , The same as the above embodiment.

  A schematic circuit representation of the SiC MISFET of the one-in-one module according to the embodiment is represented as shown in FIG. 26A, and a schematic circuit representation of the IGBT of the one-in-one module is a diagram of FIG. It is expressed as shown in 26 (b).

FIG. 26A shows a diode DI connected in antiparallel to the MISFET Q. The main electrode of the MISFET Q is represented by the drain terminal DT and the source terminal ST. Similarly, FIG. 26 (b) shows a diode DI connected in anti-parallel to the IGBT Q. The main electrode of IGBTQ is represented by collector terminal CT and emitter terminal ET.
In addition, a detailed circuit representation of the SiC MISFET in the power module 20 according to the embodiment, which is a one-in-one module, is represented as shown in FIG.

  The power module 20 according to the embodiment has, for example, a configuration of a one-in-one module. That is, one MISFET Q is incorporated in one module. As an example, five chips (MISFET × 5) can be mounted, and up to five MISFETs Q can be connected in parallel. It is also possible to mount a part of the five chips for the diode DI.

  More specifically, as shown in FIG. 27, the sense MISFET Qs is connected in parallel to the MISFET Q. The sense MISFET Qs is formed as a fine transistor in the same chip as the MISFET Q. In FIG. 27, SS denotes a source sense terminal, CS denotes a current sense terminal, and G denotes a gate signal terminal. Also in the embodiment, in the semiconductor device Q, the sense MISFETs Qs are formed as fine transistors in the same chip.

  In addition, a schematic circuit representation of the SiC MISFET of the two-in-one module in the power module 20T according to the embodiment is represented as shown in FIG.

  As shown in FIG. 28A, two MISFETs Q1 and Q4 and diodes DI1 and DI4 connected in anti-parallel to the MISFETs Q1 and Q4 are incorporated in one module. G1 is a gate signal terminal of the MISFET Q1, and S1 is a source terminal of the MISFET Q1. G4 is a gate signal terminal of the MISFET Q4, and S4 is a source terminal of the MISFET Q4. P is a positive side power supply input terminal, N is a negative side power supply input terminal, and O is an output terminal.

  Moreover, it is power module 20T which concerns on embodiment, Comprising: The typical circuit representation of IGBT of a two-in-one module is represented as shown in FIG.28 (b). As shown in FIG. 28B, two IGBTs Q1 and Q4 and diodes DI1 and DI4 connected in anti-parallel to the IGBTs Q1 and Q4 are incorporated in one module. G1 is a gate signal terminal of the IGBT Q1, and E1 is an emitter terminal of the IGBT Q1. G4 is a gate signal terminal of the IGBT Q4, and E4 is an emitter terminal of the IGBT Q4. P is a positive side power supply input terminal, N is a negative side power supply input terminal, and O is an output terminal.

(Structural example of semiconductor device)
It is an example of the semiconductor device applicable to the power module which concerns on embodiment, Comprising: The typical cross-section of SiC MISFET is expressed as shown to Fig.29 (a), The schematic cross-section of IGBT is FIG. It is expressed as shown in (b).

As an example of the semiconductor device 110 (Q) applicable to the power module according to the embodiment, as shown in FIG. 29A, a schematic cross-sectional structure of the SiC MISFET is a semiconductor substrate 126 made of an n ⁻ high resistance layer. And p body region 128 formed on the surface side of semiconductor substrate 126, source region 130 formed on the surface of p body region 128, and a gate disposed on the surface of semiconductor substrate 126 between p body region 128. The insulating film 132, the gate electrode 138 disposed on the gate insulating film 132, the source electrode 134 connected to the source region 130 and the p body region 128, and the back surface opposite to the surface of the semiconductor substrate 126 An n ⁺ drain region 124 and a drain electrode 136 connected to the n ⁺ drain region 124 are provided.

  In FIG. 29A, the semiconductor device 110 is formed of a planar gate n-channel vertical SiC MISFET, but may be formed of an n-channel vertical SiC TMISFET or the like as shown in FIG. 33 described later. good.

  In addition, a GaN-based FET or the like can be adopted as the semiconductor device 110 (Q) applicable to the power module according to the embodiment instead of the SiC MISFET.

  As a semiconductor device 110 applicable to the power module according to the embodiment, either a SiC-based or a GaN-based power device can be adopted.

  Furthermore, for the semiconductor device 110 applicable to the power module according to the embodiment, a semiconductor having a band gap energy of, for example, 1.1 eV to 8 eV can be used.

Examples of applicable semiconductor device 110A (Q) Similarly, the power module according to the embodiment, IGBT, as shown in FIG. 29 (b), n ^- semiconductor substrate 126 made of a high-resistance layer, a semiconductor P body region 128 formed on the surface side of substrate 126, emitter region 130E formed on the surface of p body region 128, and gate insulating film 132 disposed on the surface of semiconductor substrate 126 between p body region 128 , A gate electrode 138 disposed on the gate insulating film 132, an emitter electrode 134E connected to the emitter region 130E and the p body region 128, and ap ⁺ collector disposed on the back surface opposite to the surface of the semiconductor substrate 126. A region 124P and a collector electrode 136C connected to the p ⁺ collector region 124P are provided.

  In FIG. 29B, the semiconductor device 110A is formed of a planar gate n-channel vertical IGBT, but may be formed of a trench gate n-channel vertical IGBT or the like.

  It is an example of the semiconductor device 110 applicable to the power module which concerns on embodiment, Comprising: The typical cross-section of SiC MISFET containing source pad electrode SP and gate pad electrode GP is expressed as shown in FIG. Gate pad electrode GP is connected to gate electrode 138 disposed on gate insulating film 132, and source pad electrode SP is connected to source electrode 134 connected to source region 130 and p body region 128.

  In addition, gate pad electrode GP and source pad electrode SP are disposed on interlayer insulating film 144 for passivation covering the surface of semiconductor device 110, as shown in FIG. In the semiconductor substrate 126 below the gate pad electrode GP and the source pad electrode SP, a transistor structure with a fine structure may be formed as in the central part of FIG. 29A or FIG.

  Furthermore, as shown in FIG. 30, also in the transistor structure in the central portion, the source pad electrode SP may be extended and disposed on the interlayer insulating film 144 for passivation.

  A schematic cross-sectional structure of an IGBT including a source pad electrode SP and a gate pad electrode GP, which is an example of the semiconductor device 110A applied to the power modules 20 and 20T according to the embodiment, is represented as shown in FIG. . Gate pad electrode GP is connected to gate electrode 138 disposed on gate insulating film 132, and emitter pad electrode EP is connected to emitter electrode 134E connected to emitter region 130E and p body region 128.

  Further, as shown in FIG. 31, the gate pad electrode GP and the emitter pad electrode EP are disposed on a passivation interlayer insulating film 144 covering the surface of the semiconductor device 110A. In the semiconductor substrate 126 below the gate pad electrode GP and the emitter pad electrode EP, an IGBT structure having a fine structure may be formed as in the central portion of FIG. 29 (b) or FIG.

  Furthermore, as shown in FIG. 31, also in the IGBT structure in the central portion, emitter pad electrode EP may be extended and disposed on interlayer insulating film 144 for passivation.

-SiC DIMISFET-
It is an example of the semiconductor device 110 applicable to the power module which concerns on embodiment, Comprising: The typical cross-section of SiC DIMISFET is expressed as shown in FIG.

As shown in FIG. 32, the SiC DIMISFET applicable to the power module according to the embodiment includes a semiconductor substrate 126 formed of an n ⁻ high resistance layer, and a p body region 128 formed on the surface side of the semiconductor substrate 126. An n ⁺ source region 130 formed on the surface of p body region 128, a gate insulating film 132 disposed on the surface of semiconductor substrate 126 between p body regions 128, and a gate electrode disposed on gate insulating film 132 138, source electrode 134 connected to source region 130 and p body region 128, n ⁺ drain region 124 disposed on the back surface opposite to the surface of semiconductor substrate 126, and n ⁺ drain region 124 And a drain electrode 136.

In FIG. 32, in the semiconductor device 110, the p body region 128 and the n ⁺ source region 130 formed on the surface of the p body region 128 are formed by double ion implantation (DI), and the source pad electrode SP is the source region It is connected to source electrode 134 connected to 130 and p body region 128. The gate pad electrode GP (not shown) is connected to the gate electrode 138 disposed on the gate insulating film 132. The source pad electrode SP and the gate pad electrode GP (not shown) are disposed on a passivation interlayer insulating film 144 covering the surface of the semiconductor device 110, as shown in FIG.

SiC DIMISFET, as shown in FIG. 32, n sandwiched p-body region 128 ^- in the semiconductor substrate 126 made of a high-resistance layer, a depletion layer as shown by a broken line is formed, a junction FET ( The channel resistance _RJFET associated with the JFET) effect is formed. Further, as shown in FIG. 32, a body diode BD is formed between the p body region 128 and the semiconductor substrate 126.

-SiC TMISFET-
It is an example of the semiconductor device 110 applicable to the power module which concerns on embodiment, Comprising: The typical cross-section of SiC TMISFET is expressed as shown in FIG.

As shown in FIG. 33, the SiC TMISFET applicable to the power module according to the embodiment includes a semiconductor substrate 126N formed of n layers, a p body region 128 formed on the surface side of the semiconductor substrate 126N, and a p body region. The gate insulating layer 132 and the interlayer insulating films 144U and 144B are formed in the trench formed through the n ⁺ source region 130 formed on the surface of 128 and the p body region 128 to the semiconductor substrate 126N. Trench gate electrode 138TG, source electrode 134 connected to source region 130 and p body region 128, n + drain region 124 disposed on the back surface opposite to the surface of semiconductor substrate 126N, and n ⁺ drain region 124 And a drain electrode 136 connected thereto.

  33, in the semiconductor device 110, the trench gate electrode 138TG formed through the gate insulating layer 132 and the interlayer insulating films 144U and 144B is formed in the trench which penetrates the p body region 128 and extends to the semiconductor substrate 126N. Source pad electrode SP is connected to source electrode 134 connected to source region 130 and p body region 28. The gate pad electrode GP (not shown) is connected to the gate electrode 138 disposed on the gate insulating film 132. The source pad electrode SP and the gate pad electrode GP (not shown) are disposed on a passivation interlayer insulating film 144U covering the surface of the semiconductor device 110, as shown in FIG.

In SiC TMISFET, channel resistance R _JFET associated with junction FET (JFET) effect, such as SiC DIMISFET is not formed. Further, a body diode BD is formed between the p body region 128 and the semiconductor substrate 126N, as in FIG.

  In a schematic circuit configuration of a three-phase alternating current inverter 140 configured using a power module according to the embodiment, a circuit configuration in which a SiC MISFET is applied as a semiconductor device and a snubber capacitor C is connected between a power supply terminal PL and a ground terminal NL An example is represented as shown in FIG. 34 (a). Similarly, in the schematic circuit configuration of the three-phase AC inverter 140A configured using the power module according to the embodiment, an IGBT is applied as a semiconductor device, and a snubber capacitor C is connected between the power supply terminal PL and the ground terminal NL. The circuit configuration example is represented as shown in FIG.

When the power module according to the embodiment is connected to the power supply E, a large surge voltage Ldi / dt is generated because the switching speed of the SiC MISFET or IGBT is fast due to the inductance L of the connection line. For example, assuming that the current change di = 300 A and the time change dt = 100 nsec accompanying switching, di / dt = 3 × 10 ⁹ (A / s). Although the value of the surge voltage Ldi / dt changes depending on the value of the inductance L, the surge voltage Ldi / dt is superimposed on the power supply V. The surge voltage Ldi / dt can be absorbed by the snubber capacitor C connected between the power supply terminal PL and the ground terminal NL.

(Application example applying power module)
Next, with reference to FIG. 35, a three-phase alternating current inverter 140 configured using the power module according to the embodiment to which the SiC MISFET is applied as the semiconductor device will be described.

  As shown in FIG. 35, the three-phase alternating current inverter 140 includes a gate drive unit 150, a power module unit 152 connected to the gate drive unit 150, and a three-phase alternating current motor unit 154. The power module unit 152 is connected to U-phase, V-phase, and W-phase inverters corresponding to the U-phase, V-phase, and W-phase of the three-phase AC motor unit 154. Here, the gate drive unit 150 is connected to the SiC MISFETs Q1 and Q4, the SiC MISFETs Q2 and Q5, and the SiC MISFETs Q3 and Q6.

  The power module unit 152 is connected between the positive terminal (+) and the negative terminal (-) of the converter 148 to which the storage battery (E) 146 is connected, and has inverter-structured SiC MISFETs Q1 and Q4, Q2 and Q5, and Q3 and Q6. Equipped with In addition, free wheel diodes DI1 to DI6 are connected in antiparallel in parallel between the source and drain of the SiC MISFETs Q1 to Q6.

  Next, with reference to FIG. 36, a three-phase AC inverter 140A configured using a power module 20T according to an embodiment to which an IGBT is applied as a semiconductor device will be described.

  As shown in FIG. 36, the three-phase alternating current inverter 140A includes a gate drive unit 150A, a power module unit 152A connected to the gate drive unit 150A, and a three-phase alternating current motor unit 154A. In the power module unit 152A, U-phase, V-phase, and W-phase inverters are connected to the U-phase, V-phase, and W-phase of the three-phase AC motor unit 154A. Here, the gate drive unit 150A is connected to the IGBTs Q1 and Q4, the IGBTs Q2 and Q5, and the IGBTs Q3 and Q6.

  Power module unit 152A is connected between the positive terminal (+) and the negative terminal (-) of converter 148A to which storage battery (E) 146A is connected, and has IGBTs Q1 and Q4, Q2 and Q5, and Q3 and Q6 in an inverter configuration. Prepare. Furthermore, free wheel diodes DI1 to DI6 are connected in anti-parallel, respectively, between the emitters and the collectors of IGBTs Q1 to Q6.

  The power module according to the present embodiment can be formed into any one-in-one, two-in-one, four-in-one, six-in-one or seven-in-one type.

  For example, semiconductor devices such as IGBTs, diodes, Si-based MISFETs, SiC-based MISFETs, and GaN FETs are applicable to the power module according to the present embodiment.

  As described above, according to the present invention, a power module that can be reduced in size, increased in current capacity, and reduced in cost by the lead frame structure, and suppresses variations in welding without damaging the semiconductor device and improves yield. Can be provided.

[Other Embodiments]
As described above, although the present invention has been described by the embodiments, the descriptions and the drawings that form a part of this disclosure are illustrative and should not be understood as limiting the present invention. Various alternative embodiments, examples and operation techniques will be apparent to those skilled in the art from this disclosure.

  Thus, the present invention includes various embodiments that are not described herein.

  The power module according to the present invention can be used for semiconductor modules such as IGBT modules, diode modules, MOS modules (Si, SiC, GaN), and structures that do not use an insulating substrate such as DBC in case type modules, HEV It can be applied to a wide range of application fields such as inverters for / EV, inverters for industry, and converters.

1, 110, 110A, Q, Q1 to Q6 ... semiconductor devices (semiconductor chips, MISFETs, IGBTs)
2 ... lower chip bonding layer (lower chip solder layer, Ag)
3 ... 1st metal circuit pattern (surface copper foil, metal frame)
4 ... Insulating substrate (ceramic substrate)
5 ₁ , 5 ₂ ... bonding wire 6 ... second metal circuit pattern (surface copper foil, metal frame)
7: Back surface copper foil 8: Insulated circuit board 9: Bonding layer on chip (solder layer on chip)
DESCRIPTION OF SYMBOLS 10 ... Stress buffer layer 11 ... Stress bonding layer upper joining layer 12, 15, 15-1, 15-4 ... Lead frame 13 ... Lead frame lower joining layer 14, 14-1, 14-4 ... Stress buffer layer (L shape Hardware)
14R, 14R-1, 14R-4 ... Stress buffer layer (U-shaped fitting)
16, 17 ... Welds (laser welds, spot welds)
20, 20A, 20T, 200 Power module 33 Mold resin layer 34 Laser irradiation window 40 Insulating layer substrate (organic insulating resin layer)

Claims (30)

A first metal pattern,
A first wide band gap semiconductor device disposed on the first metal pattern;
A lead frame electrically connected to the semiconductor device;
A stress buffer layer disposed on the top surface of the semiconductor device and capable of buffering a thermal expansion coefficient difference between the semiconductor device and the lead frame;
The power module, wherein the lead frame is connected to the semiconductor device via the stress buffer layer, and the thermal expansion coefficient of the stress buffer layer is equal to or less than the thermal expansion coefficient of the lead frame. The semiconductor device further has a second surface opposite to the top surface,
The power module according to claim 1, wherein the first metal pattern is disposed on the second surface.   The power module according to claim 1, wherein a first welded portion is formed in a direction parallel to the upper surface at a connection portion between the stress buffer layer and the lead frame.   The power module according to claim 2, further comprising an electrical bonding layer bonding the first metal pattern and the semiconductor device, wherein the electric bonding layer comprises fired silver.   The power module according to claim 2, further comprising: an electrical bonding layer bonding the semiconductor device and the stress buffer layer, wherein the electrical bonding layer comprises calcined silver.   The power module according to claim 1, wherein the stress buffer layer comprises Kovar or Invar.   The power module according to claim 1, wherein the stress buffer layer comprises at least one of an Fe—Ni based alloy or a Ni—Mo—Fe based alloy.   The power module according to claim 1, further comprising a second metal pattern connected to the lead frame.   The power module according to claim 8, wherein a welded portion is formed at a connection portion between the lead frame and the second metal pattern. Further equipped with a substrate,
The power module according to claim 2, wherein the first metal pattern is disposed on the substrate.   The power module according to claim 10, wherein the substrate comprises any of a DBC substrate, a DBA substrate or an AMB substrate. Further comprising an insulating layer substrate,
The power module according to claim 2, wherein the first metal pattern is disposed on the insulating layer substrate.   The power module according to claim 12, wherein the insulating layer substrate comprises an organic insulating resin layer.   The difference between the thermal expansion coefficient of the semiconductor device and the thermal expansion coefficient of the stress relieving layer is smaller than the difference between the thermal expansion coefficient of the semiconductor device and the thermal expansion coefficient of the lead frame. Power module.   The power module according to claim 3, wherein the first welding portion is disposed outside the side surface on the short side of the semiconductor device.   The power module according to claim 1, wherein the lead frame extends in a direction orthogonal to the extending direction of the stress buffer layer.   The power module according to claim 1, wherein the stress buffer layer has a first joint surface joined to the top surface of the semiconductor device.   The power module according to claim 17, further comprising a first bonding layer disposed between the first bonding surface of the stress buffer layer and the top surface of the semiconductor device.   The power module according to claim 1, wherein the stress buffer layer has a bonding surface to which the lead frame is bonded.   The power module according to claim 19, wherein the bonding surface is perpendicular to the top surface. It further has a resin layer,
The power module according to claim 1, which is transfer molded by the resin layer.   The power module according to claim 1, wherein the power module comprises one of one-in-one, two-in-one, four-in-one, six-in-one or seven-in-one.   The power module according to claim 1, wherein the semiconductor device comprises one of an IGBT, a diode, a Si-based MISFET, a SiC-based MISFET, and a GaNFET.   The power module according to claim 1, wherein the stress buffer layer is connected to the semiconductor device through a conductive material.   The power module according to claim 24, wherein the stress buffer layer is connected to the lead frame through a conductive material.   26. The power module of claim 25, wherein a gate controlled conductive material is connected to the semiconductor device.   27. The power module of claim 26, wherein the gate controlled conductive material is connected to a second metal pattern.   The power module according to claim 27, wherein the lead frame is connected to a source terminal of the power module.   The power module according to claim 28, further comprising a second wide band gap semiconductor device, wherein the second wide band gap semiconductor device is disposed on the second metal pattern.   30. The power module of claim 29, wherein both the first and second wide band gap semiconductor devices are controlled by applying the same potential to the gate electrode.

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