JP2021040012A - Manufacturing method for semiconductor device - Google Patents

Abstract

To provide a manufacturing method for a semiconductor device by which a failure due to short-circuiting between adjacent metal bumps between a plurality of stacked semiconductor chips can be suppressed.SOLUTION: In a manufacturing method for a semiconductor device according to the embodiment, first and second semiconductor chips are stacked so that a plurality of first metal terminals provided to the first semiconductor chip and a plurality of second metal terminals provided to the second semiconductor chip and coated with an oxide film are brought into contact with each other. A first step of heating the first and second semiconductor chips at first temperature higher than or equal to the melting point of the second metal terminals is performed without introducing reducing gas that reduces the oxide film. A second step of heating the first and second semiconductor chips at second temperature higher than or equal to the temperature that activates the reducing gas and lower than or equal to the melting point of the second metal terminals is performed by introducing the reducing gas. A third step of heating the first and second semiconductor chips at third temperature higher than or equal to the melting point of the second metal terminals is performed.SELECTED DRAWING: Figure 6

Description

The present embodiment relates to a method for manufacturing a semiconductor device.

In semiconductor devices, a SiP (System in Package) structure has been developed in which a plurality of semiconductor chips are laminated in one package in order to reduce the size and enhance the functionality. In the SiP structure, when a plurality of semiconductor chips are laminated and flip-chip connected, the solder bumps of a plurality of semiconductor chips adjacent to each other may be melted and connected to each other by using the formic acid reflow method. In the formic acid reflow method, the oxide film formed on the surface of the solder bumps is reduced and removed with formic acid gas, and the solder bumps are melted and connected.

However, when the formic acid gas reduces and removes only a part of the oxide film, the solder bumps start to melt from the portion without the oxide film and flow out in a specific direction. If the solder bumps flow out in a specific direction, they may come into contact with other solder bumps adjacent in that direction, causing a short circuit defect.

Japanese Patent No. 5378078 Japanese Patent No. 5732623 U.S. Pat. No. 8,757,474

Provided is a method for manufacturing a semiconductor device capable of suppressing short-circuit defects between adjacent metal bumps between a plurality of stacked semiconductor chips.

In the method for manufacturing a semiconductor device according to the present embodiment, a plurality of first metal terminals provided on the first semiconductor chip and a plurality of second metal terminals provided on the second semiconductor chip and coated with an oxide film are brought into contact with each other. The first and second semiconductor chips are laminated as described above. The first step of heat-treating the first and second semiconductor chips at a first temperature equal to or higher than the melting point of the second metal terminal is executed without introducing a reducing gas that reduces the oxide film. The second step of introducing the reducing gas and heat-treating the first and second semiconductor chips at a second temperature equal to or higher than the temperature at which the reducing gas is activated and lower than the melting point of the second metal terminal is executed. The third step of heat-treating the first and second semiconductor chips at a third temperature equal to or higher than the melting point of the second metal terminal is executed.

The cross-sectional view which shows an example of the manufacturing method of the semiconductor device by 1st Embodiment. FIG. 1 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device, following FIG. FIG. 2 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device, following FIG. The block diagram which shows the structural example of the heat treatment apparatus used for a reflow process. The cross-sectional view which shows an example of the reflow process of a bump electrode. FIG. 5 is a cross-sectional view showing an example of a reflow process following FIG. FIG. 6 is a cross-sectional view showing an example of a reflow process following FIG. The graph which shows the temperature and the air pressure in a chamber in a reflow process. Sectional drawing which shows an example of a semiconductor package.

Hereinafter, embodiments according to the present invention will be described with reference to the drawings. The present embodiment is not limited to the present invention. The drawings are schematic or conceptual, and the ratio of each part is not always the same as the actual one. In the specification and the drawings, the same elements as those described above with respect to the existing drawings are designated by the same reference numerals, and detailed description thereof will be omitted as appropriate.

(First Embodiment)
1 to 3 are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to the first embodiment. First, the semiconductor element 20 is formed on the first surface F1 of the semiconductor substrate 10. The semiconductor substrate 10 may be, for example, a silicon substrate or the like. The semiconductor element 20 may be, for example, a three-dimensional memory cell array in which a plurality of memory cells are three-dimensionally arranged, and a CMOS (Complementary Metal-Oxide-Semiconductor) circuit that controls the memory cell array. That is, the semiconductor device may be a semiconductor chip of a NAND flash memory. The semiconductor element 20 may be another LSI (Large-Scale Integration). Further, the semiconductor element 20 may be formed on the second surface F2.

Next, a through electrode 30 such as a TSV (Through-Silicon Via) is formed on the semiconductor substrate 10. The through electrode 30 is provided between the first surface F1 and the second surface F2 on the opposite side thereof, and is formed by embedding a metal material in a through hole 40 penetrating the semiconductor substrate 10. For the through electrode 30, for example, a low resistance metal such as copper, nickel, or tungsten is used.

A bump electrode 50 as a first electrode terminal connected to the through electrode 30 is formed on the first surface F1. For the bump electrode 50, for example, a low resistance metal such as copper, nickel, or tungsten is used.

A bump electrode 60 as a second electrode terminal connected to the through electrode 30 is formed on the second surface F2. For the bump electrode 60, for example, a low resistance metal such as solder (tin) is used. The width of the bump electrode 60 is 5 μm to 50 μm. The distance between the adjacent bump electrodes 60 is 10 μm to 100 μm.

Further, an adhesive 70 is formed on the second surface F2 of the semiconductor substrate 10. As the adhesive 70, for example, a resin such as an epoxy resin, a phenol resin, or a polyimide, or a mixed resin thereof is used.

The above semiconductor wafers or semiconductor chips are flip-chip connected. The plurality of semiconductor wafers may be laminated in the wafer state and then diced. Alternatively, the semiconductor wafers may be individually diced into chips and then laminated. Hereinafter, the semiconductor wafer will be described as being diced and laminated on the semiconductor chip.

Next, as shown in FIG. 2, a plurality of semiconductor chips are laminated on the wiring board 120. The semiconductor wafer is separated into semiconductor chips by dicing. The wiring board 120 is adhered onto the lead frame 100 with an adhesive 110. After that, a plurality of semiconductor chips are laminated on the wiring board 120. That is, the plurality of semiconductor chips are flip-chip connected.

Instead of the wiring board 120, a plurality of semiconductor chips may be laminated on a semiconductor chip on which the through electrode 30 is not formed. In this case, the semiconductor chip instead of the wiring board 120 has a circuit configuration substantially equivalent to that of the semiconductor chip laminated on the semiconductor chip, but is different from other semiconductor chips in that the through electrode 30 is not formed.

FIG. 3 is a cross-sectional view showing a configuration when a plurality of semiconductor chips C1 to C4 are laminated on the wiring board 120. The semiconductor chips C1 to C3 are, for example, NAND memory chips, and the semiconductor chip C4 is, for example, a controller chip. A plurality of semiconductor chips C1 to C4 adjacent to each other in the stacking direction (D1 direction) are adhered to each other with an adhesive 70 to form a laminated body ST, and are electrically connected by a bump electrode 60 and a through electrode 30. In this embodiment, only the semiconductor chips C1 to C4 are shown, but the number of semiconductor chips may be 3 or less or 5 or more.

Here, the reflow process when laminating the semiconductor chips C1 to C4 from FIGS. 2 to 3 will be described in more detail.

FIG. 4 is a block diagram showing a configuration example of the heat treatment apparatus 200 used in the reflow process. The heat treatment apparatus 200 includes a chamber 201, a heater 202, a stage 203, a chemical liquid tank 204, an inert gas supply unit 205, pipes 206 and 207, a mass flow controller MFC, a vacuum pump 208, and an abatement apparatus 209. And have.

Chamber 201 houses the heater 202 and stage 203. The stage 203 can mount a plurality of laminated bodies ST carried into the chamber 201. The heater 202 can heat a plurality of laminated bodies ST. As a result, the bump electrodes 60 between the semiconductor chips can be reflowed inside the chamber 201.

The chemical solution tank 204 can accommodate the chemical solution C and is connected to the chamber 201 and the inert gas supply unit 205 via the pipe 206. The chemical solution C contains, for example, formic acid (HCOOH) as a reducing agent. Formic acid is used, for example, as a reducing agent for reducing oxidized solder (tin oxide (SnO, SnO _2)). The chemical solution C is vaporized in the chemical solution tank 204 and introduced into the chamber 201 via the pipe 206 as a reducing gas for reducing _{tin oxide (SnO, SnO 2).}

The inert gas supply unit 205 supplies the inert gas into the chemical solution tank 204 or the chamber 201 via the pipe 206. The inert gas may be, for example, nitrogen, a rare gas or the like. In the chemical solution tank 204, the inert gas is used for vaporizing the chemical solution C. The inert gas is also used for adjusting the concentration of the reducing gas and for cleaning the inside of the chamber 201. Hereinafter, the description will proceed assuming that the chemical solution C is a formic acid solution and the reducing gas contains formic acid gas as a main component.

The vacuum pump 208 is connected to the chamber 201 via a pipe 207, and can reduce the pressure inside the chamber 201 and control the air pressure inside the chamber 201. The abatement device 209 detoxifies the gas exhausted by the vacuum pump 208.

The laminated body ST is heat-treated by the heat treatment apparatus 200 having such a configuration.

5 (A) to 7 are cross-sectional views showing an example of a reflow process of the bump electrode 60.
5A to 7 show a state in which the semiconductor chip C2 as the second semiconductor chip is laminated on the first surface F1 of the semiconductor chip C1 as the first semiconductor chip.

First, as shown in FIG. 5A, the first surface F1 of the semiconductor chip C1 as the first semiconductor chip and the second surface F2 of the semiconductor chip C2 as the second semiconductor chip are opposed to each other, and the semiconductor chip C1 The bump electrode (first bump electrode) 50 on the side and the bump electrode (second bump electrode) 60 on the semiconductor chip C2 side are aligned so as to be in contact with each other.

In the semiconductor chip C1, an oxide film 51 is formed on the side surface of the bump electrode 50. For example, nickel is used for the bump electrode 50. The oxide film 51 is a natural oxide film of the bump electrode 50, for example, a nickel oxide film. Gold plating 80 is formed on the surface of the bump electrode 50. A polyimide film 90 is provided on the first surface F1 around the bump electrode 50, and electrically insulates the adjacent bump electrodes 50 from each other. For example, nickel is used for the through electrode 30. The through electrode 30 is electrically connected to the bump electrode 50 via the conductor 52.

On the other hand, in the semiconductor chip C2, an oxide film 61 is formed around the bump electrode 60. The oxide film 61 is a natural oxide film of the bump electrode 60, and is _{composed of, for example, a tin oxide (SnO, SnO 2} ) film. For example, a nickel oxide film is formed on the side surface of the through electrode 30. A copper film 31 is provided between the through electrode 30 and the bump electrode 60, and the through electrode 30 and the bump electrode 60 are well connected.

While heating such semiconductor chips C1 and C2, they are brought close to each other in the D1 direction and pressure-welded. At this time, the temperatures of the semiconductor chips C1 and C2 are lower than the melting point of the bump electrode 60. For example, when the bump electrode 60 is a solder bump, the temperature may be around 150 ° C. As a result, the bump electrode 50 and the bump electrode 60 are temporarily fixed. Temporary fixing refers to connecting the semiconductor chips C1 and C2 to the extent that they do not come off when the semiconductor chips C1 and C2 are carried into the heat treatment apparatus 200 during the reflow process. Therefore, the temporary fixing is a weaker connection than the connection of the semiconductor chips C1 and C2 after the reflow process. Further, for temporary fixing, the bump electrode 50 and the bump electrode 60 may be physically connected, and may not be electrically connected at this stage. For temporary fixing of the bump electrode 50 and the bump electrode 60, for example, a pulse heater heating type bonder is used to heat the bump electrode 60 (for example, solder) below its melting point while pressing the semiconductor chips C1 and C2 against each other. This is achieved by pressure contacting the bump electrode 50 and the bump electrode 60. Further, the temporary fixing may be realized by adhering the semiconductor chip C1 and the semiconductor chip C2 with a photosensitive adhesive or a non-conductive adhesive (not shown).

In the temporary fixing, as shown in FIG. 5B, the bump electrode 60 is crushed and deformed to some extent between the semiconductor chip C1 and the semiconductor chip C2 to form a substantially elliptical shape. Therefore, the distance (gap) DST between the adjacent bump electrodes 60 becomes narrower.

At this time, the oxide film 61 is deformed following the bump electrode 60 while covering the bump electrode 60. Therefore, the bump electrode 50 and the bump electrode 60 are connected via the oxide film 61, and are not yet electrically connected. In this way, the semiconductor chip C1 and the semiconductor chip C2 are laminated so that the bump electrode 50 and the bump electrode 60 are brought into contact with each other and temporarily fixed. Similarly, the semiconductor chip C1 is temporarily fixed on the wiring board 120, and the other semiconductor chips C3 and C4 are also temporarily fixed on the semiconductor chips C1 and C2. The laminated wiring board 120 and semiconductor chips C1 to C4 are also hereinafter referred to as a laminated body ST.

Next, the temporarily fixed laminated body ST is carried into the chamber 201 of the heat treatment apparatus 200 shown in FIG. The laminated body ST is placed on the stage 203. The reflow step is executed under the conditions shown in FIG.

FIG. 8 is a graph showing the temperature and air pressure in the chamber 201 in the reflow process. The horizontal axis shows the time of the reflow process. The left vertical axis shows the temperature of the stage 203 or the bump electrode 60, and the right vertical axis shows the air pressure in the chamber 201. Th1 is a threshold temperature at which formic acid gas as a reducing gas exhibits (activates) reducibility. If it is less than Th1, the formic acid gas is in an inactive state and cannot exert much reducing property. When Th1 or more, the formic acid gas becomes an active state and can exhibit reducing property. Th1 is, for example, 150 ° C to 180 ° C. Th2 is the melting point of solder as a material for the bump electrode 60, for example, about 232 ° C. _{Further, Th3 is the melting point of tin oxide (SnO, SnO 2} ) as a material of the oxide film 61, for example, about 840 ° C. The line Lt indicates the temperature of the stage 203 or the temperature actually applied to the bump electrode 60, and the line Lp indicates the air pressure in the chamber 201. Here, the temperature of the stage 203 and the temperature of the uppermost stage (farthest from the stage 203) of the laminated body ST may differ from each other by, for example, about 10 ° C. Therefore, for example, when the temperature of the bump electrode 60 of the uppermost semiconductor chip of the laminated body ST is to be set to the threshold temperature Th1 in which the reducing property of formic acid gas is desired to be exhibited, the temperature of the stage 203 is slightly higher than the threshold temperature Th1. There is. Therefore, when there is a difference between the temperature of the stage 203 and the actual temperature of the bump electrode 60, the temperature of the stage 203 is set in consideration of the actual temperature of the bump electrode 60. The temperature of the stage 203 set in consideration of the actual temperature of the bump electrode 60 in this way is referred to here as the “temperature of the bump electrode 60”.

After the laminated body ST is carried into the chamber 201, the pressure inside the chamber 201 is reduced at t0 to t1. When the inside of the chamber 201 is sufficiently depressurized, at t1 to t2, the heater 202 raises the temperature of the stage 203 or the temperature of the bump electrode 60 to the first temperature T1 which is Th2 or more and less than Th3.

At t2 to t3, the laminate ST is heat-treated at the first temperature T1 without introducing formic acid gas (first step). At this time, the heat treatment apparatus 200 does not introduce the formic acid gas into the chamber 201, but introduces the inert gas (for example, nitrogen) from the inert gas supply unit 205 into the chamber 201. As a result, the oxide film (tin oxide) 61 is not reduced and remains covered around the bump electrode 60.

On the other hand, as shown in FIG. 6A, the bump electrode (solder) 60 inside the oxide film 61 melts and approaches a sphere due to interfacial tension and becomes round. At this time, although the bump electrode 60 melts, it does not flow out from the oxide film 61 because it is covered with the oxide film 61. Further, the oxide film 61 is sufficiently thin and is similarly deformed according to the deformation of the bump electrode 60. Therefore, the oxide film 61 follows the deformation of the bump electrode 60 while suppressing the outflow of the bump electrode 60. As described above, the bump electrodes 60 are adjacent to each other as shown in FIGS. 5 (B) and 6 (A) by being deformed so as to approach a spherical shape from a crushed ellipse without flowing out from the oxide film 61. The distance DST between the bump electrodes 60 increases.

Next, before and after t3 in FIG. 8, the heater 202 lowers the temperature of the stage 203 or the temperature of the bump electrode 60 to a second temperature T2 which is Th1 or more and less than Th2. At t3 to t4, the laminate ST is heat-treated at the second temperature T2 while introducing formic acid gas (second step). At this time, since the heat treatment apparatus 200 introduces the formic acid gas into the chamber 201, the oxide film (tin oxide) 61 is reduced and removed as shown in FIG. 6 (B). However, since the second temperature T2 is lower than the melting point of the bump electrode 60, the bump electrode 60 in the oxide film 61 is solidified and does not flow out. That is, the distance DST between the adjacent bump electrodes 60 is the same as that in FIG. 6A, or the oxide film 61 can be removed while expanding by the amount of the oxide film 61.

Next, before and after t4 in FIG. 8, the heater 202 raises the temperature of the stage 203 or the temperature of the bump electrode 60 to a third temperature T3 which is Th2 or more and less than Th3. The third temperature T3 may be the same temperature as the first temperature T1 or may be a different temperature. At t4 to t5, the laminate ST is heat-treated at the third temperature T3 while introducing formic acid gas (third step). At this time, although the bump electrode 60 melts, as shown in FIGS. 6B and 7, since the oxide film 61 has already been removed, a part of the bump electrode 60 may flow out in a specific direction. It is suppressed. Further, since the oxide film 61 has been removed, the bump electrode 60 melts and becomes more spherical due to interfacial tension, and is electrically connected to the bump electrode 50 of the semiconductor chip C1. In the third step, formic acid gas is introduced into the chamber 201 to prevent the formation of an oxide film on the surface of the bump electrode 60.

Next, as shown in FIG. 8, after t5, the heater 202 lowers the temperature of the stage 203 or the temperature of the bump electrode 60 to Th1 or less so that the laminated body ST can be taken out from the chamber 201 (for example, 50 ° C.). .. At the same time, the supply of formic acid gas is stopped and the pressure inside the chamber 201 is reduced. After sufficiently depressurizing the inside of the chamber 201, an inert gas is supplied to the chamber 201 to bring the pressure inside the chamber 201 close to the atmospheric pressure.

After that, the laminated body ST is carried out from the chamber 201 and assembled as a semiconductor package. For example, FIG. 9 is a cross-sectional view showing an example of a semiconductor package. The laminate ST is adhered onto the mounting substrate 300 with a thermosetting resin 330, and the laminate ST and the mounting substrate are connected by wire bonding (not shown), bump electrodes 340, or the like. After that, the laminate ST on the mounting board is sealed with the resin 310, and the external connection terminal 320 is formed on the bottom surface of the mounting board. As a result, the semiconductor package (SiP) is completed. In FIG. 9, the number of semiconductor chips Cn (n is an integer) included in the laminated body ST is larger than that of the laminated body ST shown in FIG. Further, in the laminated body ST, the semiconductor chip Cn is mounted toward the mounting substrate 300. The wiring board 120 on the uppermost layer of the laminated body ST may be a semiconductor chip on which the through electrodes 30 are not formed.

As described above, in the method for manufacturing a semiconductor device according to the present embodiment, after a plurality of semiconductor chips C1 to C4 are laminated and temporarily fixed, in the reflow step, first, the melting point of the bump electrode 60 is obtained without introducing formic acid gas. The laminated body ST is heat-treated at the above first temperature T1 (first step). By adding such a first step, the shape of the bump electrode 60 can be brought closer to a spherical shape by interfacial tension before the second step of removing the oxide film 61, and the distance DST between the adjacent bump electrodes 60 can be set. Can be expanded. This makes it possible to suppress an unintended short-circuit defect between adjacent bump electrodes 60.

For example, when a plurality of semiconductor chips are temporarily fixed as shown in FIG. 5B, and then formic acid gas is introduced into the chamber 201 and heat-treated at a temperature of Th2 or higher at the same time, the bump electrode 60 has an oxide film 61. It melts and flows out from the removed part. That is, the oxide film 61 is not removed from the entire periphery of the bump electrode 60 at the same time, but the film thickness gradually decreases and is removed from a part of the periphery of the bump electrode 60. Therefore, the molten bump electrode 60 tends to flow out in the specific direction in which the oxide film 61 is first removed. At this time, if the bump electrode 60 flows out in the direction of another adjacent bump electrode, the bump electrode 60 may be short-circuited with another adjacent bump electrode. Further, when a plurality of semiconductor chips are temporarily fixed, the distance DST between the adjacent bump electrodes 60 is very short, as shown in FIG. 5 (B). Therefore, when the bump electrode 60 flows out toward the other adjacent bump electrode, the bump electrode 60 is more likely to be short-circuited with the other adjacent bump electrode.

On the other hand, in the reflow step according to the present embodiment, in the first step, the shape of the bump electrode 60 is brought closer to a spherical shape by interfacial tension while the bump electrode 60 is covered with the oxide film 61, and the distance DST between the adjacent bump electrodes 60 is set. It is expanded (see FIGS. 6 (A) and 6 (B)). This makes it possible to suppress an unintended short-circuit defect between adjacent bump electrodes 60. That is, the oxide film 61 is originally unnecessary, but according to the present embodiment, the oxide film 61 is used to make the shape of the bump electrode 60 closer to a sphere while suppressing the outflow of the bump electrode 60.

Further, in the second step, formic acid gas is introduced into the chamber 201, and the laminate ST is heat-treated at the second temperature T2. The second temperature T2 is a temperature equal to or higher than the temperature at which the reducing property of the formic acid gas is exhibited and lower than the melting point of the bump electrode 60. Therefore, the bump electrode 60 does not flow while being solidified, and the oxide film 61 can be removed. Then, in the third step, the bump electrode 60 is reflowed at a third temperature T3 equal to or higher than the melting point of the bump electrode 60. At this time, the oxide film 61 has already been removed, and the bump electrode 60 further approaches a spherical shape due to interfacial tension without flowing out in a specific direction. Therefore, the distance DST between the bump electrodes 60 is further increased. Therefore, it is possible to prevent the bump electrode 60 from being unintentionally short-circuited with another bump electrode. Further, since there is no oxide film 61, the bump electrode 60 can be electrically connected to the bump electrode 50 of another semiconductor chip. As a result, it is possible to suppress an unintended short circuit while reliably connecting the bump electrode 60 and the bump electrode 50, and it is possible to improve reliability.
(Modification example)
In the first step shown in FIG. 6A, the inert gas supply unit 205 may dare to introduce the oxidizing gas into the chamber 201. In this case, the bump electrode 60 shown in FIG. 6A is oxidized, and the oxide film 61 is formed to be thicker than the natural oxide film. As a result, the oxide film 61 can be prevented from being torn during the first step, and the internal bump electrode 60 can be suppressed from flowing out.

Although some embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the gist of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, as well as in the scope of the invention described in the claims and the equivalent scope thereof.

10 Semiconductor Substrates, 20 Semiconductor Devices, 30 Through Electrodes, 40 Through Holes, 50 Bump Electrodes, 61 Oxide Films, 70 Adhesives, 100 Lead Frames, 110 Adhesives, 120 Wiring Substrates, C1-C4 Semiconductor Chips, ST Laminates, 200 heat treatment equipment

Claims (7)

The first and second semiconductor chips are provided so that the plurality of first metal terminals provided on the first semiconductor chip and the plurality of second metal terminals provided on the second semiconductor chip and coated with the oxide film are in contact with each other. Laminate,
The first step of heat-treating the first and second semiconductor chips at a first temperature equal to or higher than the melting point of the second metal terminal is executed without introducing a reducing gas that reduces the oxide film.
The second step of introducing the reducing gas and heat-treating the first and second semiconductor chips at a second temperature equal to or higher than the temperature at which the reducing gas is activated and lower than the melting point of the second metal terminal is executed.
A method for manufacturing a semiconductor device, comprising performing a third step of heat-treating the first and second semiconductor chips at a third temperature equal to or higher than the melting point of the second metal terminal. The reducing gas is a gas containing at least formic acid.
The method for manufacturing a semiconductor device according to claim 1. The method for manufacturing a semiconductor device according to claim 1 or 2, wherein in the first step, an oxidizing gas is introduced to heat-treat the first and second semiconductor chips. Any of claims 1 to 3, wherein when the first and second semiconductor chips are laminated, the first and second semiconductor chips are pressed against each other and heat-treated at a temperature lower than the melting point of the second metal terminal. The method for manufacturing a semiconductor device according to item 1. The second metal terminal contains tin (Sn) and contains tin (Sn).
The method for manufacturing a semiconductor device according to any one of claims 1 to 4, wherein the oxide film contains tin oxide (SnO, SnO _2). The method for manufacturing a semiconductor device according to any one of claims 1 to 5, wherein in the second step, the oxide film is removed by the reducing gas. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein the first temperature is equal to or higher than the melting point of the second metal terminal and lower than the melting point of the oxide film.

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