CN112447607B - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
CN112447607B
CN112447607B CN202010709013.1A CN202010709013A CN112447607B CN 112447607 B CN112447607 B CN 112447607B CN 202010709013 A CN202010709013 A CN 202010709013A CN 112447607 B CN112447607 B CN 112447607B
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temperature
semiconductor chips
semiconductor
bump electrode
melting point
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CN112447607A (en
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赤羽隆章
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Kioxia Corp
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Kioxia Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053—Bonding environment
    • H01L2224/81054—Composition of the atmosphere
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81053—Bonding environment
    • H01L2224/81095—Temperature settings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909—Post-treatment of the bump connector or bonding area
    • H01L2224/8192—Applying permanent coating, e.g. protective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909—Post-treatment of the bump connector or bonding area
    • H01L2224/8193—Reshaping
    • H01L2224/81935—Reshaping by heating means, e.g. reflowing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909—Post-treatment of the bump connector or bonding area
    • H01L2224/81948—Thermal treatments, e.g. annealing, controlled cooling

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Wire Bonding (AREA)

Abstract

In the method for manufacturing a semiconductor device according to the present embodiment, the 1 st and 2 nd semiconductor chips are stacked so that the 1 st metal terminals provided on the 1 st semiconductor chip and the 2 nd metal terminals provided on the 2 nd semiconductor chip and covered with the oxide film are in contact with each other. The following step 1 is performed: the 1 st and 2 nd semiconductor chips are heat-treated at a 1 st temperature higher than the melting point of the 2 nd metal terminal without introducing a reducing gas for reducing the oxide film. The following step 2 is performed: introducing a reducing gas to heat-treat the 1 st and 2 nd semiconductor chips at a 2 nd temperature higher than a temperature at which the reducing gas activates and lower than a melting point of the 2 nd metal terminal. The following step 3 is performed: the 1 st and 2 nd semiconductor chips are heat-treated at a 3 rd temperature which is higher than the melting point of the 2 nd metal terminal.

Description

Method for manufacturing semiconductor device
Citation of related applications
The present application is based on and claims priority from prior japanese patent application No. 2019-159839, filed on date 2 of 2019, the contents of which are incorporated herein by reference in their entirety.
Technical Field
The present embodiment relates to a method for manufacturing a semiconductor device.
Background
In a semiconductor device, a SiP (System in Package ) structure in which a plurality of semiconductor chips are stacked in 1 package has been developed for miniaturization and high functionality. In the SiP structure, when a plurality of semiconductor chips are stacked and flip-chip connected, solder bumps of the plurality of semiconductor chips adjacent to each other up and down are sometimes melted and connected to each other by using a formic acid reflow method. In the formic acid reflow method, an oxide film formed on the surface of a solder bump is reduced and removed by a formic acid gas, and the solder bump is melted and connected.
However, if the formic acid gas reduces and removes only a part of the oxide film, the solder bump melts from the portion where the oxide film is not present and flows out in a specific direction. If the solder bump flows out in a specific direction, the solder bump may contact another solder bump adjacent to the solder bump in the specific direction, and may cause a short-circuit failure.
Disclosure of Invention
Provided is a method for manufacturing a semiconductor device capable of suppressing short-circuit failure between adjacent metal bumps between a plurality of stacked semiconductor chips.
In the method for manufacturing a semiconductor device according to the present embodiment, the 1 st and 2 nd semiconductor chips are stacked so that the 1 st metal terminals provided on the 1 st semiconductor chip and the 2 nd metal terminals provided on the 2 nd semiconductor chip and covered with the oxide film are in contact with each other. The following step 1 is performed: the 1 st and 2 nd semiconductor chips are heat-treated at a 1 st temperature higher than the melting point of the 2 nd metal terminal without introducing a reducing gas for reducing the oxide film. The following step 2 is performed: introducing a reducing gas to heat-treat the 1 st and 2 nd semiconductor chips at a 2 nd temperature higher than a temperature at which the reducing gas activates and lower than a melting point of the 2 nd metal terminal. The following step 3 is performed: the 1 st and 2 nd semiconductor chips are heat-treated at a 3 rd temperature which is higher than the melting point of the 2 nd metal terminal.
According to the above configuration, a method for manufacturing a semiconductor device can be provided in which short-circuit failure between adjacent metal bumps can be suppressed between a plurality of stacked semiconductor chips.
Drawings
Fig. 1 is a cross-sectional view showing an example of a method for manufacturing a semiconductor device according to embodiment 1.
Fig. 2 is a cross-sectional view showing an example of a method for manufacturing the semiconductor device next to fig. 1.
Fig. 3 is a cross-sectional view showing an example of a method for manufacturing the semiconductor device next to fig. 2.
Fig. 4 is a block diagram showing a configuration example of a heat treatment apparatus used in the reflow process.
Fig. 5 is a cross-sectional view showing an example of a reflow process of the bump electrode.
Fig. 6 is a cross-sectional view showing an example of the reflow process subsequent to fig. 5.
Fig. 7 is a cross-sectional view showing an example of the reflow process subsequent to fig. 6.
Fig. 8 is a graph showing the temperature and the air pressure in the chamber in the reflow process.
Fig. 9 is a cross-sectional view showing an example of a semiconductor package.
Detailed Description
Embodiments according to the present invention will be described below with reference to the drawings. The present embodiment is not limited to the present invention. The drawings are schematic diagrams or conceptual diagrams, and ratios of the respective portions and the like are not necessarily the same as those in the actual case. In the description and drawings, elements similar to those described above with respect to the drawings appearing thereon are denoted by the same reference numerals, and detailed description thereof is appropriately omitted.
(embodiment 1)
Fig. 1 to 3 are cross-sectional views showing an example of a method for manufacturing a semiconductor device according to embodiment 1. First, the semiconductor element 20 is formed on the 1 st surface F1 of the semiconductor substrate 10. The semiconductor substrate 10 is preferably a silicon substrate, for example. The Semiconductor device 20 is preferably a solid-state memory cell array in which a plurality of memory cells are arranged three-dimensionally, or a CMOS (Complementary Metal-Oxide-Semiconductor) circuit for controlling the memory cell array. That is, the semiconductor device may be a semiconductor chip of a NAND-type flash memory. The semiconductor element 20 may be another LSI (Large scale integrated circuit) as well. The semiconductor element 20 may be formed on the 2 nd surface F2.
Next, a Through-electrode 30 such as a TSV (Through-Silicon Via) is formed on the semiconductor substrate 10. The through electrode 30 is provided between the 1 st surface F1 and the 2 nd surface F2 located on the opposite side thereof, and is formed by embedding a metal material in the through hole 40 penetrating the semiconductor substrate 10. For the through electrode 30, a low-resistance metal such as copper, nickel, or tungsten is used.
On the 1 st surface F1, bump electrodes 50 as 1 st electrode terminals connected to the through electrodes 30 are formed. For the bump electrode 50, for example, a low-resistance metal such as copper, nickel, tungsten, or the like is used.
On the 2 nd surface F2, bump electrodes 60 as 2 nd electrode terminals connected to the through electrodes 30 are formed. For the bump electrode 60, a low-resistance metal such as solder (tin) is used. The bump electrode 60 has a width of 5 μm to 50 μm. The distance between adjacent bump electrodes 60 is 10 μm to 100 μm.
An adhesive 70 is formed on the 2 nd surface F2 of the semiconductor substrate 10. As the adhesive 70, for example, a resin such as an epoxy resin, a phenolic resin, and a polyimide, or a mixed resin thereof is used.
The above semiconductor wafer or semiconductor chip is flip-chip connected. The plurality of semiconductor wafers may be stacked in a wafer state and then diced. Alternatively, the semiconductor wafers may be singulated by dicing into chips and stacked. Hereinafter, a case where a semiconductor wafer is diced into semiconductor chips and stacked will be described.
Next, as shown in fig. 2, a plurality of semiconductor chips are stacked on the wiring substrate 120. The semiconductor wafer is singulated by dicing into semiconductor chips. The wiring board 120 is bonded to the lead frame 100 with the adhesive 110. Thereafter, a plurality of semiconductor chips are stacked on the wiring substrate 120. That is, a plurality of semiconductor chips are flip-chip connected.
Instead of the wiring board 120, a plurality of semiconductor chips may be stacked on a semiconductor chip on which the through electrode 30 is not formed. In this case, the semiconductor chip that replaces the wiring board 120 has a circuit configuration substantially equivalent to that of the semiconductor chip stacked thereon, but is different from other semiconductor chips in that the through electrode 30 is not formed.
Fig. 3 is a cross-sectional view showing a configuration in which a plurality of semiconductor chips C1 to C4 are stacked on the wiring board 120. The semiconductor chips C1 to C3 are NAND memory chips, for example, and the semiconductor chip C4 is a controller chip, for example. The plurality of semiconductor chips C1 to C4 adjacent to each other in the stacking direction (D1 direction) are bonded to each other with an adhesive 70 to form a stacked body ST, and are electrically connected to each other through the bump electrode 60 and the through electrode 30. In the present embodiment, only the semiconductor chips C1 to C4 are shown, but the number of semiconductor chips may be 3 or less or 5 or more.
Here, a reflow process when the semiconductor chips C1 to C4 are stacked on fig. 2 to 3 will be described in more detail.
Fig. 4 is a block diagram showing a configuration example of the heat treatment apparatus 200 used in the reflow process. The heat treatment apparatus 200 includes a chamber 201, a heater 202, a stage 203, a liquid chemical tank 204, an inert gas supply unit 205, pipes 206 and 207, a mass flow controller MFC, a vacuum pump 208, and a pest control device 209.
The chamber 201 accommodates a heater 202 and a stage 203. The stage 203 can mount a plurality of stacked bodies ST carried into the chamber 201. The heater 202 may heat the plurality of stacked bodies ST. Thus, the bump electrodes 60 between the semiconductor chips can be reflowed in the chamber 201.
The chemical liquid tank 204 can hold the chemical liquid C, and is connected to the chamber 201 and the inert gas supply unit 205 via a pipe 206. The chemical solution C contains formic acid (HCOOH) as a reducing agent, for example. Formic acid is used as, for example, solder (tin oxide (SnO, snO) 2 ) A reducing agent for reduction. The chemical solution C is gasified in the chemical solution tank 204 to form tin oxide (SnO, snO 2 ) The reduced reducing gas is introduced into the chamber 201 through the pipe 206.
The inert gas supply unit 205 supplies inert gas into the chemical tank 204 or the chamber 201 via the pipe 206. The inert gas is preferably nitrogen, a rare gas, or the like. In the chemical tank 204, an inert gas is used for vaporization of the chemical C. The inert gas is used for adjusting the concentration of the reducing gas or for cleaning the inside of the chamber 201. Hereinafter, the case where the chemical solution C is a formic acid solution and the reducing gas is a gas containing formic acid gas as a main component will be described.
The vacuum pump 208 is connected to the chamber 201 via a pipe 207, and can depressurize the chamber 201 or control the air pressure inside the chamber 201. The abatement device 209 abates the gas exhausted by the vacuum pump 208.
With the heat treatment apparatus 200 having such a configuration, the laminate ST is heat-treated.
Fig. 5 (a) to 7 are cross-sectional views showing an example of the reflow process of the bump electrode 60. Fig. 5 (a) to 7 show a case where the semiconductor chip C2 as the 2 nd semiconductor chip is stacked on the 1 st surface F1 of the semiconductor chip C1 as the 1 st semiconductor chip.
First, as shown in fig. 5 (a), the 1 st surface F1 of the semiconductor chip C1, which is the 1 st semiconductor chip, and the 2 nd surface F2 of the semiconductor chip C2, which is the 2 nd semiconductor chip, are aligned so that the bump electrode (1 st bump electrode) 50 on the semiconductor chip C1 side and the bump electrode (2 nd bump electrode) 60 on the semiconductor chip C2 side can be brought into contact with each other.
In the semiconductor chip C1, an oxide film 51 is formed on the side surface of the bump electrode 50. For the bump electrode 50, nickel is used, for example. The oxide film 51 is a natural oxide film of the bump electrode 50, for example, a nickel oxide film. A gold plating layer 80 is formed on the surface of the bump electrode 50. A polyimide film 90 is provided on the 1 st surface F1 of the periphery of the bump electrode 50 to electrically insulate adjacent bump electrodes 50 from each other. For example, nickel is used for the through electrode 30. The through electrode 30 is electrically connected to the bump electrode 50 via the conductor 52.
On the other hand, in the semiconductor chip C2, the oxide film 61 is formed around the bump electrode 60. The oxide film 61 is a natural oxide film of the bump electrode 60, for example, tin oxide (SnO ) 2 ) A membrane. On the side surface of the through electrode 30, for example, a nickel oxide film is formed. A copper film 31 is provided between the through electrode 30 and the bump electrode 60, and the through electrode 30 and the bump electrode 60 are well connected.
The semiconductor chips C1 and C2 are heated and brought close to each other in the D1 direction to be pressure-bonded. At this time, the temperature of the semiconductor chips C1, C2 is lower than the melting point of the bump electrode 60. For example, in the case where the bump electrode 60 is a solder bump, it is preferably around 150 ℃. Thereby, the bump electrode 50 and the bump electrode 60 are temporarily fixed. The temporary fixation means that the semiconductor chips C1 and C2 are connected to each other so as not to come off when the semiconductor chips C1 and C2 are carried into the heat treatment apparatus 200 in the reflow process. Therefore, the temporary fixation is weaker than the connection of the semiconductor chips C1, C2 after the reflow process. The temporary fixation may be performed by physically connecting the bump electrode 50 and the bump electrode 60, and electrical connection may not be performed at this stage. Temporary fixation of the bump electrode 50 and the bump electrode 60 is achieved by, for example, heating the bump electrode 60 (e.g., solder) below its melting point using a pulse heater heating type bonder, and pressing the semiconductor chips C1, C2 against each other to press-bond the bump electrode 50 and the bump electrode 60. The temporary fixation may be achieved by bonding the semiconductor chip C1 and the semiconductor chip C2 to each other with a photosensitive adhesive or a nonconductive adhesive, not shown.
In the temporary fixation, as shown in fig. 5 (B), the bump electrode 60 is deformed to be substantially elliptical by being crushed to some extent between the semiconductor chip C1 and the semiconductor chip C2. Therefore, the distance (gap) DST between adjacent bump electrodes 60 becomes narrow.
At this time, the oxide film 61 deforms to follow the bump electrode 60 in a state of covering the bump electrode 60. Therefore, the bump electrode 50 and the bump electrode 60 are connected via the oxide film 61, and are not yet electrically connected. In this way, the semiconductor chip C1 and the semiconductor chip C2 are stacked so that the bump electrode 50 and the bump electrode 60 are brought into contact with each other and temporarily fixed. Similarly, the semiconductor chip C1 is temporarily fixed to the wiring board 120, and the other semiconductor chips C3 and C4 are also temporarily fixed to the semiconductor chips C1 and C2. The stacked wiring board 120 and the semiconductor chips C1 to C4 are also referred to as a stack ST hereinafter.
Next, the temporarily fixed laminate ST is carried into the chamber 201 of the heat treatment apparatus 200 shown in fig. 4. The laminate ST is mounted on the stage 203. The reflow process is performed under the conditions shown in fig. 8.
Fig. 8 is a graph showing the temperature and the air pressure in the chamber 201 in the reflow process. The horizontal axis represents the time of the reflow process. The left vertical axis represents the temperature of the stage 203 or the bump electrode 60, and the right vertical axis represents the air pressure in the chamber 201. Th1 is a threshold temperature at which formic acid gas as a reducing gas exhibits reducibility (is activated). If the ratio is less than Th1, the formic acid gas is inactive and does not exhibit much reducibility. In the case of Th1 or more, the formic acid gas becomes active, and can exhibit reducibility. Th1 is, for example, 150℃to 180 ℃. Th2 is the melting point of solder, which is the material of the bump electrode 60, and is, for example, about 232 ℃. Further, the processing unit is used for processing the data,th3 is tin oxide (SnO ) as a material of the oxide film 61 2 ) For example, about 840 ℃. The line Lt represents the temperature of the stage 203 or the temperature actually applied to the bump electrode 60, and the line Lp represents the air pressure in the chamber 201. The temperature of the stage 203 may be different from the temperature of the uppermost stage (farthest from the stage 203) of the laminate ST by, for example, about 10 ℃. Therefore, for example, when the temperature of the bump electrode 60 of the semiconductor chip at the uppermost stage of the stacked body ST is to be set to the threshold temperature Th1 at which the reduction of the formic acid gas is to be exhibited, the temperature of the stage 203 may slightly rise from the threshold temperature Th 1. Therefore, when the temperature of the stage 203 differs from the actual temperature of the bump electrode 60, the temperature of the stage 203 is set in consideration of the actual temperature of the bump electrode 60. As described above, the temperature of the stage 203 set in consideration of the actual temperature of the bump electrode 60 is referred to as "the temperature of the bump electrode 60" herein.
After the stack ST is carried into the chamber 201, the chamber 201 is depressurized at t0 to t1. When the pressure in the chamber 201 is sufficiently reduced, the heater 202 increases the temperature of the stage 203 or the bump electrode 60 to a 1 st temperature T1 equal to or higher than Th2 and lower than Th3 at times T1 to T2.
At T2 to T3, the laminate ST is heat-treated at a 1 ST temperature T1 without introducing formic acid gas (1 ST step). At this time, the heat treatment apparatus 200 does not introduce the formic acid gas into the chamber 201, but introduces an inert gas (for example, nitrogen) from the inert gas supply unit 205 into the chamber 201. Thereby, the oxide film (tin oxide) 61 is not reduced, and remains in a state of covering the periphery of the bump electrode 60.
On the other hand, the bump electrode (solder) 60 inside the oxide film 61 melts as shown in fig. 6 (a) and becomes rounded by the interfacial tension approaching a sphere. At this time, although the bump electrode 60 is melted, it is covered with the oxide film 61, and therefore, does not flow out from the oxide film 61. The oxide film 61 is sufficiently thin, and is similarly deformed in accordance with the deformation of the bump electrode 60. Therefore, the oxide film 61 suppresses the outflow of the bump electrode 60 and follows the deformation of the bump electrode 60. As described above, the bump electrodes 60 deform so as to be approximately spherical by flattened ellipses without flowing out from the oxide film 61, and the distance DST between adjacent bump electrodes 60 expands as shown in fig. 5 (B) and 6 (a).
Next, before and after T3 in fig. 8, the heater 202 reduces the temperature of the stage 203 or the bump electrode 60 to a 2 nd temperature T2 which is equal to or higher than Th1 and lower than Th 2. At T3 to T4, formic acid gas is introduced, and the laminate ST is heat-treated at a 2 nd temperature T2 (2 nd step). At this time, since the heat treatment apparatus 200 introduces formic acid gas into the chamber 201, as shown in fig. 6 (B), the oxide film (tin oxide) 61 is reduced and removed. However, since the temperature T2 is lower than the melting point of the bump electrode 60, the bump electrode 60 in the oxide film 61 solidifies and does not flow out. That is, the distance DST between adjacent bump electrodes 60 is the same as that of fig. 6 (a), or extends only in a portion of the oxide film 61 and can remove the oxide film 61.
Next, before and after T4 in fig. 8, the heater 202 increases the temperature of the stage 203 or the bump electrode 60 to a 3 rd temperature T3 which is equal to or higher than Th2 and lower than Th 3. The 3 rd temperature T3 may be the same temperature as the 1 st temperature T1, or may be a different temperature. At T4 to T5, formic acid gas is introduced, and the laminate ST is heat-treated at a 3 rd temperature T3 (3 rd step). At this time, although the bump electrode 60 is melted, as shown in fig. 6 (B) and 7, since the oxide film 61 is removed, it is possible to suppress a part of the bump electrode 60 from flowing out in a specific direction. In addition, since the oxide film 61 is removed, the bump electrode 60 is melted and further approaches a spherical shape by interfacial tension, and is electrically connected to the bump electrode 50 of the semiconductor chip C1. In step 3, formic acid gas is introduced into the chamber 201, thereby suppressing formation of an oxide film on the surface of the bump electrode 60.
Next, as shown in fig. 8, after t5, the heater 202 lowers the temperature of the stage 203 or the bump electrode 60 to a temperature of Th1 or lower, and sets the temperature at which the laminate ST is taken out of the chamber 201 (for example, 50 ℃). At the same time, the supply of formic acid gas is stopped, and the pressure in the chamber 201 is reduced. After the inside of the chamber 201 is sufficiently depressurized, an inert gas is supplied to the chamber 201, and the pressure in the chamber 201 is brought close to the atmospheric pressure.
After that, the stack ST is carried out of the chamber 201 and assembled as a semiconductor package. For example, fig. 9 is a cross-sectional view showing an example of a semiconductor package. The laminate ST is bonded to the mounting board 300 with a thermosetting resin 330, and the laminate ST and the mounting board are connected by wire bonding (not shown) or bump electrodes 340. Thereafter, the laminate ST on the mounting board is sealed with a resin 310, and external connection terminals 320 are formed on the bottom surface of the mounting board. Thereby, a semiconductor package (SiP) is completed. In fig. 9, the stacked body ST includes more semiconductor chips Cn (n is an integer) than the stacked body ST shown in fig. 3. The stacked body ST mounts the semiconductor chip Cn on the mounting board 300. The uppermost wiring board 120 of the laminate ST may be a semiconductor chip on which the through electrode 30 is not formed.
As described above, in the method for manufacturing a semiconductor device according to the present embodiment, after a plurality of semiconductor chips C1 to C4 are stacked and temporarily fixed, in the reflow step, first, the stacked body ST is heat-treated at the 1 ST temperature T1 equal to or higher than the melting point of the bump electrode 60 without introducing formic acid gas (the 1 ST step). By adding step 1 as described above, the shape of the bump electrode 60 can be made nearly spherical by the interfacial tension before step 2 of removing the oxide film 61, and the distance DST between adjacent bump electrodes 60 can be extended. This can suppress unintended short-circuit failure between adjacent bump electrodes 60.
For example, as shown in fig. 5 (B), after a plurality of semiconductor chips are temporarily fixed, formic acid gas is introduced into the chamber 201, and at the same time, heat treatment is performed at a temperature of Th2 or higher, the bump electrode 60 is melted and flows out from the portion from which the oxide film 61 is removed. That is, the oxide film 61 is not removed from the entire periphery of the bump electrode 60 at one time, but gradually becomes thin in thickness, and is removed from a part of the periphery of the bump electrode 60. Therefore, the melted bump electrode 60 easily flows out in a specific direction from which the oxide film 61 was originally removed. In this case, if the bump electrode 60 flows out in the direction of the adjacent other bump electrode, the bump electrode 60 may be short-circuited with the adjacent other bump electrode. Further, in the case where a plurality of semiconductor chips are temporarily fixed, as shown in fig. 5 (B), the distance DST between adjacent bump electrodes 60 becomes extremely short. Therefore, when the bump electrode 60 flows out in the direction of the adjacent other bump electrode, the possibility of the bump electrode 60 being short-circuited with the adjacent other bump electrode is further increased.
On the other hand, in the reflow step according to the present embodiment, in step 1, the bump electrode 60 is kept covered with the oxide film 61, the shape of the bump electrode 60 is made nearly spherical by the interfacial tension, and the distance DST between adjacent bump electrodes 60 is extended (see fig. 6 (a) and 6 (B)). This can suppress unintended short-circuit failure between adjacent bump electrodes 60. That is, the oxide film 61 is not necessary, but according to the present embodiment, the oxide film 61 is used to suppress the outflow of the bump electrode 60 and to make the shape thereof nearly spherical.
Further, in step 2, formic acid gas is introduced into the chamber 201, and the laminate ST is heat-treated at a 2 nd temperature T2. The 2 nd temperature T2 is a temperature higher than the temperature at which the reducing property of the formic acid gas is exhibited and lower than the melting point of the bump electrode 60. Accordingly, the bump electrode 60 is kept in a solidified state without flowing, and the oxide film 61 can be removed. Then, in step 3, the bump electrode 60 is reflowed at a 3 rd temperature T3 equal to or higher than the melting point of the bump electrode 60. At this time, the oxide film 61 has been removed, and the bump electrode 60 does not flow out in a specific direction, but further approaches a sphere shape by interfacial tension. Thus, the distance DST between the bump electrodes 60 further expands. Therefore, the bump electrode 60 and other bump electrodes can be suppressed from being unintentionally shorted. In addition, since the oxide film 61 is not provided, the bump electrode 60 can be electrically connected to the bump electrode 50 of another semiconductor chip. As a result, the bump electrode 60 and the bump electrode 50 can be reliably connected, and an unintended short circuit can be suppressed, thereby improving reliability.
(modification)
In step 1 shown in fig. 6 (a), the inert gas supply unit 205 may forcibly introduce the oxidizing gas into the chamber 201. In this case, the bump electrode 60 shown in fig. 6 (a) is oxidized, and the oxide film 61 is formed further thick than the natural oxide film. This can suppress the oxide film 61 from being broken in step 1 and the bump electrode 60 inside from flowing out.
While several embodiments of the present invention have been described, these embodiments are presented as examples and are not intended to limit the scope of the invention. These embodiments may be implemented in various other modes, and various omissions, substitutions, and changes may be made without departing from the spirit of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are also included in the invention described in the claims and their equivalents.

Claims (10)

1. A method for manufacturing a semiconductor device includes the steps of:
the 1 st and 2 nd semiconductor chips are stacked so that a plurality of 1 st metal terminals provided on the 1 st semiconductor chip and a plurality of 2 nd metal terminals provided on the 2 nd semiconductor chip and covered with an oxide film are brought into contact with each other,
the following step 1 is performed: heat-treating the 1 st and 2 nd semiconductor chips at a 1 st temperature equal to or higher than the melting point of the 2 nd metal terminal without introducing a reducing gas for reducing the oxide film,
after the 1 st step, the temperature of the 1 st and 2 nd semiconductor chips is lowered to a temperature lower than the melting point of the 2 nd metal terminal without introducing the reducing gas,
the following step 2 is performed: introducing the reducing gas to heat-treat the 1 st and 2 nd semiconductor chips at a temperature higher than a temperature at which the reducing gas is activated and lower than a melting point of the 2 nd metal terminal,
the following step 3 is performed: and heat-treating the 1 st and 2 nd semiconductor chips at a 3 rd temperature higher than the melting point of the 2 nd metal terminal.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the reducing gas is a gas containing at least formic acid.
3. The method for manufacturing a semiconductor device according to claim 1, wherein an oxidizing gas is introduced in the step 1, and the 1 st and 2 nd semiconductor chips are subjected to a heat treatment.
4. The method for manufacturing a semiconductor device according to claim 1, wherein when stacking the 1 st and 2 nd semiconductor chips, the 1 st and 2 nd semiconductor chips are pressed against each other and heat-treated at a temperature lower than a melting point of the 2 nd metal terminal.
5. The method for manufacturing a semiconductor device according to claim 1, wherein the 2 nd metal terminal contains tin (Sn), the oxide film contains tin oxide, and the tin oxide is SnO or SnO 2 。
6. The method for manufacturing a semiconductor device according to claim 1, wherein in the step 2, the oxide film is removed by the reducing gas.
7. The method for manufacturing a semiconductor device according to claim 1, wherein in the step 1, a distance between adjacent 2 nd metal terminals is set apart by heat treatment.
8. The method for manufacturing a semiconductor device according to claim 1, wherein in the step 1, an oxide film formed on the metal 2 terminal is not removed.
9. The method for manufacturing a semiconductor device according to any one of claims 1 to 8, wherein the 1 st temperature is a melting point of the 2 nd metal terminal or higher and a melting point of the oxide film or lower.
10. A method for manufacturing a semiconductor device includes the steps of:
the 1 st and 2 nd semiconductor chips are stacked such that a plurality of 1 st metal terminals provided on the 1 st semiconductor chip and a plurality of 2 nd metal terminals provided on the 2 nd semiconductor chip containing tin (Sn) and covered with a film containing tin oxide are brought into contact with each other,
the following step 1 is performed: when a gas containing at least formic acid for reducing the tin oxide-containing film is not introduced, the 1 st and 2 nd semiconductor chips are heat-treated at a 1 st temperature equal to or higher than the melting point of the 2 nd metal terminals, and the distance between the adjacent 2 nd metal terminals is increased,
after the 1 st step, the temperature of the 1 st and 2 nd semiconductor chips is lowered to a temperature lower than the melting point of the 2 nd metal terminal without introducing the gas containing at least formic acid,
the following step 2 is performed: introducing the gas containing at least formic acid so that the temperature of the gas containing at least formic acid is not lower than the temperature at which the gas containing at least formic acid is activated and not higher than the melting point of the 2 nd metal terminal, heat-treating the 1 st and 2 nd semiconductor chips to remove the film containing tin oxide by the reducing gas,
the following step 3 is performed: heat-treating the 1 st and 2 nd semiconductor chips at a 3 rd temperature higher than the melting point of the 2 nd metal terminal,
the tin oxide is SnO or SnO 2 。
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