JP2013065761A - Manufacturing method and manufacturing apparatus of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method of a semiconductor device which effectively removes oxide films on surfaces of solder bumps, prevents warpage of a semiconductor element or the like, and improves the connectivity of the solder bumps.SOLUTION: According to one embodiment, solder bumps 3 of a second semiconductor chip 5 are temporarily fixed to metal electrodes 1 of a first semiconductor chip 2 while a space between the first semiconductor chip 2 and the second semiconductor chip 5 is held by spacer protrusions 4. Subsequently, a laminated body, which is temporarily fixed, is heated with an atmosphere of a carboxylic acid gas such as formic acid while a load is applied to the laminated body. Then, the solder bumps 3 are joined with each other while the oxide films on the surfaces of the solder bumps 3 are reduced and removed.

Description

  FIELD Embodiments described herein relate generally to a semiconductor device manufacturing method and a semiconductor device manufacturing apparatus.

  2. Description of the Related Art In recent years, semiconductor devices to which flip chip connection is applied have been used as a mounting method with a short wiring / connection length in order to cope with an increase in the number of pins of a semiconductor chip, a fine pitch, and an increase in signal speed. When flip chip connection is applied to the connection between semiconductor chips or between a semiconductor chip and a silicon interposer, solder bumps are formed on at least one electrode pad of the upper and lower chips (semiconductor chip and silicon interposer). These solder bumps, or one solder bump and the other electrode pad are aligned and laminated so as to face each other, and then the solder bump is heated and melted to be connected (see, for example, Patent Document 1).

  However, in such a method, since the oxide film exists on the surface of the solder bump, the reliability of the solder connection portion is poor. Therefore, in order to remove the oxide film on the surface of the solder bump, a method of applying a flux agent to the surface of the solder bump has been performed. In this method, after the flux agent is applied, the semiconductor bumps are stacked by aligning the solder bumps and electrode pads, and the solder bumps are heated and melted in a reflow furnace and connected, and then the flux agent is washed. It has been removed.

  However, along with the miniaturization of solder bumps and the disposition pitch, it has become difficult to completely clean and remove the flux agent. Therefore, in the above method, the residue of the flux agent and the residue of the flux cleaning agent are problematic. In other words, residues such as flux agents affect the filling of the underfill resin for the purpose of protecting the solder joints and protecting the chip, generating voids, peeling defects due to voids, and poor connections (open defects). There was a problem of being connected to.

  Therefore, a method has been proposed in which the solder bump is heated and melted and connected while reducing and removing the oxide film on the surface of the solder bump with a reducing carboxylic acid (see, for example, Patent Document 2).

However, in this method, there is a problem in that the solder bumps are not connected due to the deformation (warping) of the central portion of the semiconductor chip disposed in the upper layer due to heating when melting the solder bumps. .
In the flip chip connection structure described in Patent Document 1, a spacer is provided at a position that does not interfere with the solder bump so that the chip is mounted at a certain height without tilting when the solder bump is melted. Even in such a structure, there is a possibility that poor connection of the solder bumps may occur due to warpage of the upper semiconductor chip.

Japanese Utility Model Publication No. 4-127649 JP 2001-244283 A

  An object of the present invention is to provide a method for manufacturing a semiconductor device that can prevent warping of a semiconductor element and improve the solder bump connectivity while satisfactorily removing an oxide film on the surface of a solder bump.

  The method of manufacturing a semiconductor device according to the embodiment includes a first semiconductor element having a first bump electrode on one main surface, and a second semiconductor element having a second bump electrode and a spacer protrusion on one main surface. A pair of semiconductor elements in which at least one of the first bump electrode and the second bump electrode is a solder bump, and the first semiconductor element and the second semiconductor element, Are stacked such that the main surface provided with the first bump electrode and the main surface provided with the second bump electrode are opposed to each other, and the first bump electrode and the second bump electrode A stack of the first semiconductor element and the second semiconductor element in which the bump electrodes are temporarily fixed, and a spacer protrusion. And the first semiconductor element and the first semiconductor element. A step of applying a load to the laminated body so as to press-contact the bump electrodes while maintaining a gap between the semiconductor element and a carboxylic acid gas in the heating furnace while continuing the load application. And introducing and heating and maintaining the temperature in the heating furnace at a temperature equal to or higher than the melting point of the solder bump which is at least one of the first bump electrode and the second bump electrode in the atmosphere of the carboxylic acid gas. And a bump electrode bonding step for bonding the first bump electrode and the second bump electrode.

  In addition, the method of manufacturing a semiconductor device according to the embodiment includes a lower layer semiconductor element having a lower layer bump electrode on one main surface, and a first intermediate bump electrode and a second intermediate bump electrode on both main surfaces. One or two or more intermediate semiconductor elements in which the first intermediate bump electrode and the second intermediate bump electrode are connected through a through via, and an upper layer semiconductor having an upper layer bump electrode on one main surface When the semiconductor devices are stacked in this order, one of the opposing semiconductor elements is configured to have a spacer protrusion, and at least one of the opposing bump electrodes is a solder bump. And the lower layer semiconductor element, the intermediate semiconductor element, and the upper layer semiconductor element are arranged on either of the semiconductor elements between the opposing semiconductor elements. -Laminate so that the protrusions are sandwiched, temporarily fix the bump electrodes facing each other, and temporarily fix the multi-layer laminate in which the bump electrodes are temporarily fixed in a heating furnace, A process of applying a load to the multilayer stack so as to press-contact the bump electrodes facing each other while maintaining a gap between the semiconductor elements by the spacer protrusion, and while continuing to load the load, in the heating furnace Bump electrode bonding step of introducing a carboxylic acid gas and heating and holding the temperature in the heating furnace to a temperature equal to or higher than the melting point of the solder bump in the atmosphere of the carboxylic acid gas to bond the opposing bump electrodes together It is characterized by providing.

  In the temporary fixing step, the spacer protrusion can be bonded to the main surface of the semiconductor element facing the semiconductor element provided with the spacer protrusion. Further, the magnitude of the load applied to the stacked body or the multilayer stacked body is a semiconductor element disposed above the first semiconductor element and the second semiconductor element in the bump electrode bonding step. Alternatively, it is preferable to adjust so as to prevent warpage of the upper-layer semiconductor element and to maintain a gap corresponding to the height of the spacer protrusion between the semiconductor elements.

  An apparatus for manufacturing a semiconductor element connection body according to an embodiment includes a plurality of semiconductor elements having bump electrodes on at least one main surface, and at least one of the opposing bump electrodes is a solder bump, and the opposing bump electrodes of each semiconductor element Are aligned and temporarily fixed, and the opposing bump electrodes of the laminated body formed by laminating the spacer protrusions provided on the main surface of one of the semiconductor elements between the opposing semiconductor elements It is an apparatus for manufacturing a semiconductor element connection body by joining, a heating furnace that accommodates the stacked body, a load loading mechanism that applies a load to the stacked body, and exhausting the inside of the heating furnace to form a reduced pressure atmosphere An exhaust mechanism, a carboxylic acid gas introduction mechanism for introducing a carboxylic acid gas into the heating furnace, and a heating mechanism for heating and maintaining the temperature in the heating furnace at a predetermined temperature. And features.

It is sectional drawing which shows the manufacturing process of the semiconductor device by 1st Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device by 2nd Embodiment. It is sectional drawing which shows the manufacturing process of the semiconductor device by 2nd Embodiment.

  Hereinafter, embodiments will be described in detail with reference to the drawings.

<First Embodiment>
FIG. 1 is a cross-sectional view showing a manufacturing process of the semiconductor device according to the first embodiment. The manufacturing method of the semiconductor device according to the first embodiment includes (1-1) a preparation step of preparing a pair of semiconductor elements, (2-1) a temporary fixing step of bump electrodes, and (3-1) a laminate. And (4-1) a bump electrode joining step. Hereinafter, each step will be described.

(1-1) Preparatory Step As shown in FIG. 1A, a first semiconductor element having a metal electrode (for example, an Au electrode) 1 that is a first bump electrode on one main surface (the upper surface in the figure). A semiconductor chip 2 and a solder bump 3 as a second bump electrode on one main surface (the lower surface in the figure), and a region excluding the formation region of the solder bump 3 on the same main surface (hereinafter, non-formed) A semiconductor chip 5 which is a second semiconductor element having a plurality of spacer protrusions 4 made of a non-conductive material is prepared. In the laminated body in which the first semiconductor chip 2 and the second semiconductor chip 5 are stacked, the first semiconductor chip 2 is disposed in the lower layer, and the second semiconductor chip 5 is disposed thereon. To do.

  The first semiconductor chip 2 and the second semiconductor chip 5 are, for example, silicon (Si) chips, but at least one of them may be a silicon (Si) interposer. That is, the combination of the first semiconductor element and the second semiconductor element includes, in addition to the combination of the semiconductor chip and the semiconductor chip described above, a combination of a Si interposer and a semiconductor chip, a combination of a semiconductor chip and a Si interposer, and the like. There is no particular limitation.

The bump electrode refers to an electrode that forms a connection part for electrically and mechanically connecting two semiconductor elements. The first bump electrode and the second bump electrode are arranged, for example, in a matrix in a predetermined region on one main surface of the first semiconductor chip 2 and the second semiconductor chip 5.
In the first embodiment, the first bump electrode provided on the first semiconductor chip 2 is a flat pad-shaped metal electrode 1 (for example, an Au electrode), and the first bump electrode provided on the second semiconductor chip 5 is used. Although the example in which the bump electrode 2 is the protruding solder bump 3 has been described, the combination of the first bump electrode and the second bump electrode may be a combination of a solder bump / solder bump or a solder bump / Au electrode. Good. That is, at least one of the first bump electrode and the second bump electrode may be a solder bump.

  Examples of the constituent material of the solder bump 3 include lead such as Sn—Ag solder alloy, Sn—Cu solder alloy, Sn—Ag—Cu solder alloy, Sn—Bi solder alloy, Sn—In solder alloy, etc. A free solder alloy or a Sn—Pb solder alloy is used. That is, the solder bump 3 may be composed of either a lead-free solder that does not substantially contain lead or a lead solder.

  The solder bump 3 is formed on an electrode pad (not shown) via a barrier metal layer (not shown). For example, it can be formed by using a plating method or by using fine balls made of a solder alloy. Although an oxide film does not exist on the surface of the solder bump 3 immediately after the formation, the surface of the solder bump 3 is oxidized as time passes, and an oxide film is formed.

  The spacer protrusion 4 is provided in a non-formation region of the solder bump 3 on the lower surface of the second semiconductor chip 5, and a gap (gap) between the semiconductor chips is set in a process after the temporary fixing process described later. It functions to maintain the connection height (the set height of the bump connection body composed of the solder bump 3 and the metal electrode 1). That is, in the process after the temporary fixing process, the gap between the first semiconductor chip 2 and the second semiconductor chip 5 is held by the spacer protrusion 4, so that the solder bump 3 is crushed and connection failure ( Occurrence of short circuit) can be suppressed.

  The spacer protrusion 4 is preferably made of a material that does not soften at the melting temperature of the solder. For example, using a thermosetting resin material such as a polyimide resin, a phenol resin, an epoxy resin, a BCB (benzocyclobutene) resin, an acrylic resin, applying a lithography technique, or applying a coating technique using a dispenser, a spacer The protrusion 4 can be formed.

  The spacer protrusion 4 can be formed using a photosensitive and thermosetting resin (for example, a thermosetting resin containing a photosensitizer / photosensitive adhesive resin). Since the spacer protrusion 4 formed of such photosensitive and thermosetting resin is cured by irradiation with ultraviolet rays or the like in the formation stage, it functions as a stopper for holding a gap between the semiconductor chips. Can do. Furthermore, the spacer protrusion 4 made of such resin is thermally cured during heating after the temporary fixing step and bonded to the main surface of the opposing semiconductor chip. As a result, in combination with the load of the load described later, the solder bump bonding step There is an advantage that warpage of the second semiconductor chip 5 can be further suppressed and poor connection of the solder bumps 3 can be prevented.

  The number and arrangement position of the spacer protrusions 4 vary depending on the number and arrangement pattern of the solder bumps 3 provided on the same surface. For example, the arrangement of the solder bumps 3 divides the chip size into five equal parts in the long side direction. In the structure in which four solder bumps are uniformly arranged in each region excluding both ends, the number of the spacer protrusions 4 is 1 to 4 times the number of the solder bumps 3. It is preferable to arrange so as to surround.

(2-1) Bump Electrode Temporary Fixing Step As shown in FIG. 1B, the second electrode is placed on the first semiconductor chip 2 disposed in the lower layer with the surface on which the metal electrode 1 is provided facing upward. The semiconductor chips 5 are stacked and disposed so that the surface on which the solder bumps 3 and the spacer protrusions 4 are formed faces downward. Then, after aligning the metal electrodes 1 of the first semiconductor chip 2 and the solder bumps 3 of the second semiconductor chip 5, the spacer protrusion 4 allows the first semiconductor chip 2 and the second semiconductor chip 5 to be aligned. The solder bump 3 and the metal electrode 1 are temporarily fixed while maintaining a gap therebetween.

  In the temporary fixing, it is only necessary to obtain a connection strength enough to prevent the upper and lower semiconductor chips from being removed when the next step is performed. For temporarily fixing the solder bump 3 and the metal electrode 1, there are methods such as application of ultrasonic waves at room temperature using an ultrasonic flip chip bonder, application of a temperature near the melting point of the solder using a pulse heater heating type flip chip bonder, and the like. Applied.

  The temporary fixing is performed in a state where an oxide film is present on the surface of the solder bump 3, so that the oxide film is bitten at the contact interface between the solder bump 3 and the metal electrode 1. However, since there is a gap at a part of the interface between the solder bump 3 and the metal electrode 1 in the temporarily fixed state, such a gap at the interface is used for removing the surface oxide film and bonding the bump electrode, which will be described later. The oxide film present on the surface of the solder bump is all reduced and removed with the carboxylic acid gas, including the oxide film bitten at the contact interface.

  In such a temporary fixing step, the spacer protrusion 4 provided on the second semiconductor chip 5 functions as a stopper that holds a gap between the first semiconductor chip 2 and the second semiconductor chip 5. However, as described above, when the spacer protrusion 4 is formed of a photosensitive and thermosetting resin, the spacer protrusion 4 is bonded to the upper surface of the first semiconductor chip 2 facing the spacer protrusion 4. As a result, the gap between the semiconductor chips is more stably maintained.

(3-1) Load Loading Step and (4-1) Bump Electrode Joining Step As shown in FIG. 1 (c), the first semiconductor chip 2 and the first semiconductor chip 2 on which the solder bump 3 and the metal electrode 1 are temporarily fixed. The laminated body with the semiconductor chip 5 of 2 is put into a manufacturing apparatus shown below, and heated in a carboxylic acid gas atmosphere while applying a load. Then, the oxide film on the surface of the solder bump 3 is reduced and removed, and the solder bump 3 and the metal electrode 1 are joined to manufacture a semiconductor device (semiconductor element connection body).

  The manufacturing apparatus according to the embodiment includes a heating furnace 6 that houses the laminate, a load load mechanism 7 that applies a load to the accommodated laminate, and an exhaust mechanism 8 that exhausts the inside of the heating furnace 6 to form a reduced-pressure atmosphere. And a carboxylic acid gas introduction mechanism 9 for introducing a carboxylic acid gas into the heating furnace 6 and a heating mechanism 10 for heating and maintaining the temperature in the heating furnace 6 at a predetermined temperature.

  Here, the load loading mechanism 7 is not particularly limited as long as the load can be uniformly applied to the entire upper surface of the second semiconductor chip 5 that is the upper semiconductor chip of the stacked body in the vertical direction. For example, there are a method of placing a weight having a predetermined weight and a method of pressing in a vertical direction by a press device. The exhaust mechanism 8 may be a suction pressure reducing mechanism such as a vacuum pump. Furthermore, the heating mechanism 10 is not particularly limited as long as it can heat the temperature in the heating furnace 6 to a predetermined temperature and can hold the temperature for a predetermined time. Therefore, an electric heating mechanism such as an electric heater is preferable.

The load loading process and the bump electrode bonding process are performed as follows using such a manufacturing apparatus.
That is, after the laminated body of the first semiconductor chip 2 and the second semiconductor chip 5 is placed on the base (heater panel) 10a in which the heating mechanism 10 such as an electric heater in the heating furnace 6 is built, The load mechanism 7 uniformly applies a load to the entire upper surface of the second semiconductor chip 5 in the upper layer of the stacked body. The solder bump 3 of the second semiconductor chip 5 temporarily fixed and the metal electrode 1 of the first semiconductor chip 2 are pressed into contact with each other by the load, but the spacer protrusion 4 provided on the second semiconductor chip 5. As a result, the gap between the first semiconductor chip 2 and the second semiconductor chip 5 is maintained without further reduction. Then, in the state where the gaps between the semiconductor chips are held by the spacer protrusions 4 in this way, the process up to the joining of the solder bumps 3 is performed.

  The magnitude of the applied load can be adjusted so as to prevent the second semiconductor chip 5 from being lifted (warped) and to maintain a gap corresponding to the height of the spacer protrusion 4 between the semiconductor chips. preferable. Specifically, it is preferable to apply a load so that the entire upper surface of the second semiconductor chip 5 is pressurized with a pressure of 9.8 kPa to 49.0 kPa.

Next, while continuing to apply a load to the laminated body, the air in the heating furnace 6 is exhausted by the exhaust mechanism 8 such as a vacuum pump, so that the inside of the heating furnace 6 is in a reduced pressure state. Since oxygen remaining in the heating furnace 6 oxidizes the solder bumps 3, it is preferable to exhaust the inside of the heating furnace 6 to a reduced pressure of 1 × 10 ³ Pa or less, particularly about 5 Pa.

  Next, the carboxylic acid gas is introduced into the heating furnace 6 in such a reduced pressure state using the carboxylic acid gas introduction mechanism 9 and filled. The carboxylic acid gas reduces and removes the oxide film present on the surface of the solder bump 3. The carboxylic acid used as the reducing agent for the oxide film is not particularly limited, and examples thereof include aliphatic monovalent or divalent aliphatic acids such as formic acid, acetic acid, acrylic acid, propionic acid, oxalic acid, succinic acid, and malonic acid. Of the lower carboxylic acids. It is preferable to use formic acid because of its low cost and gasification cost and excellent oxide film reducing action.

  After introducing the carboxylic acid gas such as formic acid into the heating furnace 6, the comb is energized to the heating mechanism 10 such as an electric heater almost simultaneously with the introduction of the carboxylic acid gas, and the temperature in the heating furnace 6 is changed to the temperature of the solder bump 3. Raise to a temperature above the melting point. Since the formic acid reducing action on the surface oxide film of the solder bump 3 is manifested at a temperature of 150 ° C. or higher, the oxide film on the surface of the solder bump 3 is in the process of raising the temperature inside the heating furnace 6 to the melting point of the solder bump 3 or higher. Reduced by formic acid and removed. The “temperature above the melting point of the solder bump” means a temperature above the melting point of the solder composition material constituting the solder bump.

  The atmospheric pressure in the heating furnace 6 after the introduction of the carboxylic acid gas is preferably set so as to be lower than the atmospheric pressure. As a result, the gas generated when the oxide film is reduced with the carboxylic acid gas can be diffused from the temporarily fixed portion between the solder bump 3 and the metal electrode 1 to the surroundings. For example, before the temperature in the heating furnace 6 reaches the melting point of the solder bump 3, the inside of the heating furnace 6 is evacuated to enter the gap at the contact interface (temporary fixing portion) between the solder bump 3 and the metal electrode 1. The generated carboxylic acid gas or gas generated during the reduction of the oxide film can be removed from the contact interface.

  Then, the temperature in the heating furnace 6 is raised to a temperature equal to or higher than the melting point of the solder bump 3, and the temperature is maintained until the solder bump 3 is melted. Thus, the solder bump 3 is melted and joined to the metal electrode 1. Thereafter, the introduction of the carboxylic acid gas is stopped, the energization to the heater panel 10a is stopped, and the temperature in the heating furnace 6 is lowered to resolidify the solder, and the first semiconductor chip 2 and the second semiconductor chip 2 A connection body (semiconductor element connection body) with the semiconductor chip 5 is obtained.

  The semiconductor element connection body thus obtained is sent to a normal assembly process. The assembly process is selected according to the structure of the semiconductor device and is not particularly limited. As an example, first, a thermosetting underfill resin is filled in a gap between the first semiconductor chip 2 and the second semiconductor chip 5 and cured. Further, after the semiconductor element connection body is mounted on, for example, a wiring board, the connection body and the wiring board are connected by wire bonding or the like. After resin molding such a structure, outer lead balls are arranged to form external connection terminals of the semiconductor package.

  In the first embodiment, a laminated body in which the spacer protrusions 4 are interposed between the first semiconductor chip 2 and the second semiconductor chip 5 is heated in a carboxylic acid gas atmosphere while applying a load. By connecting the solder bumps 3 while reducing / removing the oxide film on the surface of the solder bumps 3, it is possible to suppress poor connection of the solder bumps 3 and increase of the resistance of the solder bumps 3 after melting, thereby reducing the yield. Can be improved.

  Next, a method for manufacturing a multilayer semiconductor device according to the second embodiment will be described with reference to the drawings. In the multilayer semiconductor device manufactured in the second embodiment, the second semiconductor chip 5 which is the upper layer semiconductor element in the first embodiment is used as a semiconductor chip (intermediate semiconductor chip) having bump electrodes on both main surfaces. A third semiconductor chip is further laminated on the semiconductor chip, and the opposing bump electrodes are electrically and mechanically connected.

  Hereinafter, a three-layer semiconductor device in which three layers of a lower layer semiconductor chip, an intermediate semiconductor chip, and an upper layer semiconductor chip are stacked will be described, but the number of stacked semiconductor chips may be four or more. In that case, the number of stacked intermediate semiconductor chips is two or more.

<Second Embodiment>
2 and 3 are cross-sectional views showing the manufacturing process of the multilayer semiconductor device according to the second embodiment. The manufacturing method of the multilayer semiconductor device according to the second embodiment includes (1-2) a preparation step of preparing a set of semiconductor elements, (2-2) a temporary fixing step of bump electrodes, and (3-2). A load applying step of applying a load to the multilayer laminate, and (4-2) a step of bonding the bump electrodes. Hereinafter, each step will be described. Note that in the second embodiment, a part of the same portions as those in the first embodiment will not be described.

(1-2) Preparation Step As shown in FIG. 2A, a lower layer semiconductor chip 11, an intermediate semiconductor chip 12, and an upper layer semiconductor chip 13 are prepared.

  The lower layer semiconductor chip 11 has a lower layer metal electrode (for example, an Au electrode) 14 that is a lower layer bump electrode on one main surface (upper surface in the drawing). The intermediate semiconductor chip 12 has an intermediate solder bump 15 that is a first intermediate bump electrode on one main surface, and an intermediate metal electrode (for example, an Au electrode) that is a second intermediate bump electrode on the other main surface. 16 In the intermediate semiconductor chip 12, the intermediate solder bump 15 and the intermediate metal electrode 16 are electrically connected by a through conductor 17 provided through an insulating layer (not shown) in a hole penetrating the semiconductor substrate 12a. ing. A plurality of intermediate spacer protrusions 18 made of a non-conductive material are provided in a non-formation region of the intermediate solder bump 15 on the same main surface as the intermediate solder bump 15. The upper-layer semiconductor chip 13 has upper-layer solder bumps 19 that are upper-layer bump electrodes on one main surface (lower surface in the figure), and a plurality of upper-layer spacer protrusions 20 in the non-formation region of the upper-layer solder bump 19 on the same main surface. Have Since the solder material constituting the intermediate solder bump 15 and the upper layer solder bump 19 and the resin material constituting the intermediate spacer protrusion 18 and the upper layer spacer protrusion 20 can be the same as those in the first embodiment, Description is omitted.

(2-2) Bump Electrode Temporary Fixing Step The lower layer semiconductor chip 11, the intermediate semiconductor chip 12, and the upper layer semiconductor chip 13 are arranged in this order with spacer protrusions (intermediate spacer protrusions 18 and upper layer spacer protrusions 20). Are laminated so that the solder bumps and the metal electrodes facing each other are aligned and temporarily fixed to form a three-layer laminate.

  In forming the three-layer laminate, first, as shown in FIG. 2B, the intermediate semiconductor chip 12 is placed on the lower semiconductor chip 11, and the surface on which the intermediate solder bumps 15 and the intermediate spacer protrusions 18 are formed faces downward. The lower metal electrode 14 of the lower semiconductor chip 11 and the intermediate solder bump 15 of the intermediate semiconductor chip 12 are aligned, and then temporarily fixed by a flip chip bonder or the like. At this time, the height of the gap (gap) between the lower layer semiconductor chip 11 and the intermediate semiconductor chip 12 is maintained by the intermediate spacer protrusion 18 provided on the intermediate semiconductor chip 12.

  Next, the upper semiconductor chip 13 is laminated on the intermediate semiconductor chip 12 of the two-layer laminate thus obtained so that the surfaces on which the upper solder bumps 19 and the upper spacer protrusions 20 are formed face downward. The intermediate metal electrode 16 of the semiconductor chip 12 and the upper layer solder bump 19 of the upper layer semiconductor chip 13 are aligned. An upper layer spacer protrusion 20 provided on the upper layer semiconductor chip 13 keeps a gap between the intermediate semiconductor chip 12 and the upper layer semiconductor chip 13 and connects the upper layer solder bump 19 and the intermediate metal electrode 16 to a flip chip bonder or the like. Is temporarily fixed to obtain a three-layer laminate shown in FIG.

  In the case of manufacturing a multilayer semiconductor device in which the number of stacked semiconductor chips is four or more, after the number of intermediate semiconductor chips is set to two or more and the above-described intermediate semiconductor chip stacking and temporary fixing steps are repeated. Finally, an upper semiconductor chip is stacked and temporarily fixed. Further, instead of stacking and temporarily fixing semiconductor chips one by one in order from the lower layer in this way, by stacking and temporarily fixing a laminate in which two or more semiconductor chips are stacked and temporarily fixed, A laminate of four or more layers can also be obtained.

(3-2) Load application step and (4-2) Bump electrode bonding step As shown in FIG. 3, the three-layer laminate obtained in the temporary fixing step is the same as the apparatus used in the first embodiment. It puts into the manufacturing apparatus comprised similarly, and heats in carboxylic acid gas atmosphere, applying a load. Then, the oxide films on the surfaces of the intermediate solder bump 15 and the upper layer solder bump 19 are reduced and removed, and the temporarily fixed intermediate solder bump 15 and the lower layer metal electrode 14, and the upper layer solder bump 19 and the intermediate metal electrode 16 are removed. The semiconductor device (semiconductor element connection body) is manufactured by bonding.

  The load on the three-layer laminate, the exhaust in the heating furnace 6, the introduction of the carboxylic acid gas, the heating in the heating furnace 6 and the like are performed as in the first embodiment.

  Also in the second embodiment, similarly to the first embodiment, the stacked body in which the height control spacer protrusions are interposed between the semiconductor chips is heated in a carboxylic acid gas atmosphere while applying a load. In addition, bonding solder bumps while reducing and removing the oxide film on the surface of the solder bumps can suppress poor connection of the solder bumps and increase the resistance of the solder bumps after melting, thereby improving the yield. Can do.

  The present invention is not limited to the above-described embodiment, and can be applied to manufacturing processes of various semiconductor devices to which flip chip connection is applied. Such a method of manufacturing a semiconductor device is also included in the present invention. The embodiments of the present invention can be expanded or modified within the scope of the technical idea of the present invention, and the expanded and modified embodiments are also included in the technical scope of the present invention.

  DESCRIPTION OF SYMBOLS 2 ... 1st semiconductor chip, 3 ... Solder bump, 4 ... Spacer protrusion, 5 ... 2nd semiconductor chip, 6 ... Heating furnace, 7 ... Load loading mechanism, 9 ... Carboxylic acid gas introduction mechanism, 10 ... Heating mechanism, DESCRIPTION OF SYMBOLS 11 ... Lower layer semiconductor chip, 12 ... Intermediate semiconductor chip, 13 ... Upper layer semiconductor chip, 15 ... Intermediate solder bump, 17 ... Through conductor, 18 ... Intermediate spacer protrusion, 19 ... Upper layer solder bump, 20 ... Upper layer spacer protrusion

Claims (5)

A first semiconductor element having a first bump electrode on one main surface and a second semiconductor element having a second bump electrode and a spacer protrusion on one main surface, the first bump electrode And preparing a pair of semiconductor elements in which at least one of the second bump electrodes is a solder bump;
Laminating the first semiconductor element and the second semiconductor element such that a main surface provided with the first bump electrode and a main surface provided with the second bump electrode are opposed to each other; A temporary fixing step of aligning and temporarily fixing the first bump electrode and the second bump electrode;
A laminated body of the first semiconductor element and the second semiconductor element in which the bump electrodes are temporarily fixed is disposed in a heating furnace, and the first semiconductor element and the second semiconductor are formed by the spacer protrusion. A step of applying a load to the laminate so as to press-contact the bump electrodes while maintaining a gap between the elements;
Carboxylic acid gas is introduced into the heating furnace while continuing the load, and the temperature in the heating furnace is changed between the first bump electrode and the second bump electrode in the atmosphere of the carboxylic acid gas. A bump electrode joining step for joining the first bump electrode and the second bump electrode by heating and holding at a temperature equal to or higher than the melting point of at least one of the solder bumps. Production method. A lower semiconductor element having a lower bump electrode on one main surface, a first intermediate bump electrode and a second intermediate bump electrode on both main surfaces, respectively, the first intermediate bump electrode and the second intermediate bump electrode When one or two or more of the intermediate semiconductor elements connected to each other through the through vias and the upper semiconductor element having the upper bump electrode on one main surface are stacked in this order Providing a set of semiconductor elements configured such that one of the opposing semiconductor elements has a spacer protrusion and at least one of the opposing bump electrodes is a solder bump;
The lower-layer semiconductor element, the intermediate semiconductor element, and the upper-layer semiconductor element are stacked so that the spacer protrusion provided on one of the semiconductor elements is sandwiched between the opposing semiconductor elements, and the opposing bump electrodes are aligned. A temporary fixing step of temporarily fixing,
The multilayer laminate in which the bump electrodes are temporarily fixed is placed in a heating furnace, and the bumps facing each other are pressed against each other while holding the gaps between the semiconductor elements by the spacer protrusions. A process of applying a load;
While continuing the load, the carboxylic acid gas is introduced into the heating furnace, and the temperature in the heating furnace is heated and maintained at a temperature equal to or higher than the melting point of the solder bump in the atmosphere of the carboxylic acid gas. And a bump electrode joining step for joining the bump electrodes facing each other.   3. The method of manufacturing a semiconductor device according to claim 1, wherein, in the temporary fixing step, the spacer protrusion is bonded to a main surface of a semiconductor element facing the semiconductor element provided with the spacer protrusion.   The load applied to the stacked body or the multilayer stacked body is a semiconductor element disposed above the first semiconductor element and the second semiconductor element in the bump electrode bonding step, or 4. The semiconductor according to claim 1, wherein the semiconductor layer is adjusted so as to prevent warpage of the upper-layer semiconductor element and to maintain a gap corresponding to the height of the spacer protrusion between the semiconductor elements. Device manufacturing method. A plurality of semiconductor elements having bump electrodes on at least one main surface, at least one of the opposing bump electrodes is a solder bump, and the opposing bump electrodes of each semiconductor element are aligned, temporarily fixed, and opposed. An apparatus for manufacturing a semiconductor device by bonding the bump electrodes facing each other in a stacked body in which spacer protrusions provided on the main surface of either semiconductor element are sandwiched between semiconductor elements. ,
A heating furnace containing the laminate,
A load-loading mechanism for applying a load to the laminate,
An exhaust mechanism for evacuating the heating furnace to create a reduced pressure atmosphere;
A carboxylic acid gas introduction mechanism for introducing a carboxylic acid gas into the heating furnace;
And a heating mechanism for heating and maintaining the temperature in the heating furnace to a predetermined temperature.

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