JP2021027631A - Current mode step-down switching regulator - Google Patents

Abstract

To stably switch a mode between a light load mode and a heavy load mode.SOLUTION: A sub circuit 20 in a heavy load mode turns ON a switching transistor MP1 when a feedback voltage Vfb becomes lower than a second reference voltage Vref2, turns OFF the switching transistor MP1 when a current detection voltage V14 becomes higher than a third reference voltage Vref3, and sets a light load mode when a time period in which the current detection voltage V14 is lower than the third reference voltage Vref3 becomes longer than a first time period. The sub circuit in the light load mode turns ON the switching transistor MP1 when the feedback voltage Vfb becomes lower than the second reference voltage Vref2, turns OFF the switching transistor MP1 when the current detection voltage V14 becomes higher than a fourth reference voltage Vref4, and sets the heavy load mode when a time period in which the feedback voltage Vfb is lower than the second reference voltage Vref2 becomes longer than a second time period T2.SELECTED DRAWING: Figure 2

Description

The present invention relates to a current mode step-down switching regulator that enables stable switching between a light load mode and a heavy load mode.

FIG. 7 shows the circuit configuration of the conventional current mode step-down switching regulator. A circuit similar to this is described in Patent Document 1. MP1 is a MOSFET switching transistor, the input voltage Vin is applied to the source and the drain is connected to node N1. 1 is a drive circuit that drives the gate of the switching transistor MP1, 2 is an inverter that inverts the signal input to the drive circuit 1, 3 is an RSFF circuit that operates the drive circuit 1 via the inverter 2, and 4 flows through the switching transistor MP1. This is a current sense circuit that detects the switch current Isw and outputs the switch current detection voltage V4. Reference numeral 5 denotes an error amplifier that amplifies the difference between the feedback voltage Vfb input to the node N2 and the reference voltage Vref1 corresponding to the output target voltage. Reference numeral 6 denotes an oscillator, which generates a clock signal CLK for setting the RSFF circuit 3 and a lamp voltage Vram synchronized with the clock signal CLK. Reference numeral 7 denotes an adder that adds the switch current detection voltage V4 and the lamp voltage Vramp. Reference numeral 8 denotes a comparator, which compares the adder voltage V7 output from the adder 7 with the error voltage V5 output from the error amplifier 5 and generates a PWM control voltage V8 for setting the time until the RSFF circuit 3 is reset. To do. The MN1 is a reset NMOS transistor for dropping the noise component remaining in the output voltage V7 of the adder 7 to “L”, and is turned on when the terminal QB of the RSFF circuit 3 becomes “H”.

L1 is an inductor that stores energy when the switching transistor MP1 is turned on, C1 is an output capacitor, and D1 is connected to the output capacitor C1 and the output terminal N3 with the energy stored in the inductor L1 when the switching transistor MP1 is turned off. It is a diode for the switch that supplies the load. R1 and R2 are resistors for dividing the voltage for detecting the output voltage Vout of the terminal N3, and the feedback voltage Vfb obtained there is input to the node N2.

In this current mode step-down switching regulator, when the RSFF circuit 3 is set by the clock signal CLK, the terminal Q becomes “H”, the output voltage V1 of the drive circuit 1 becomes “L”, and the switching transistor MP1 turns on. Further, when the error voltage V5 and the addition voltage V7 are compared by the comparator 8 and the result is V7> V5, the PWM control voltage V8 output from the comparator 8 becomes “H” and the RSFF circuit 3 is reset. , The terminal Q becomes “L”, the output voltage V1 of the drive circuit 1 becomes “H”, and the switching transistor MP1 turns off. Further, the terminal QB of the RSFF circuit 3 becomes “H”, the transistor MN1 turns on, and the PWM control voltage V7 becomes “L” to mask.

As a result of the above, the switching transistor MP1 is turned on only during the period from the rise of the clock signal CLK to the PWM control voltage V8 becoming “H”. In this way, the switching transistor MP1 is PWM controlled, and the output voltage Vout is negatively feedback controlled so that Vfb = Vref1.

Japanese Patent No. 5063474

By the way, in the current mode step-down switching regulator of FIG. 7, in order to improve the operating efficiency, for example, when the switch current falls below the peak value Ipk, it is determined that the load is light, and at this time, the oscillator 6 is used. It is conceivable to switch the frequency of the generated clock signal CLK to a lower frequency. At this time, the relationship between the output voltage Vout and the output current Iout can be expressed by the equation (1). L1 is the inductance of the inductor L1 and f is the oscillation frequency of the oscillator 6.

However, in this method, the frequency f of the clock signal CLK is lowered when the switch current Isw becomes smaller than the peak value Ipk, and the frequency f is raised when the switch current Isw becomes larger. The frequency f of the clock signal CLK is repeatedly increased and decreased in the vicinity of the peak value Ipk, and the switching between the light load mode and the heavy load mode becomes unstable.

An object of the present invention is to provide a current mode step-down switching regulator in which switching between a light load mode and a heavy load mode can be performed stably.

In order to achieve the above object, the invention according to claim 1 is a switching transistor that switches an input voltage in order to generate an output voltage in a current mode step-down switching regulator in which a heavy load mode and a light load mode are switched. Then, when the clock signal rises, the switching transistor is turned on, and the added voltage obtained by adding the switch current detection voltage that detects the switch current flowing when the switching transistor is turned on to the lamp voltage synchronized with the clock signal is the first reference voltage. When it is larger than the error voltage indicating the difference between the output voltage and the feedback voltage, the main circuit having the first RSFF circuit for turning off the switching transistor, and the clock when the feedback voltage is smaller than the second reference voltage. A sub-circuit having a second RSFF circuit that turns on the switching transistor when a signal rises and turns off the switching transistor when the switch current detection voltage becomes larger than the third reference voltage or the fourth reference voltage larger than the third reference voltage. In the heavy load mode, when the period during which the switch current detection voltage is smaller than the third reference voltage exceeds the first period, the sub-circuit disables the first RSFF circuit and the above. The heavy load mode is performed by effectively setting the second RSFF circuit, switching the frequency of the clock signal from the first frequency to the second frequency having a lower frequency, and switching the third reference voltage to the fourth reference voltage. To the light load mode, the sub circuit invalidates the second RSFF circuit when the period in which the feedback voltage is smaller than the second reference voltage exceeds the second period in the light load mode. By effectively setting the first RSFF circuit together with, switching the frequency of the clock signal from the second frequency to the first frequency, and switching the fourth reference voltage to the third reference voltage, the light load mode It is characterized in that the mode is switched to the heavy load mode.

The invention according to claim 2 is the third aspect of the current mode step-down switching regulator according to claim 1, wherein the period in which the feedback voltage is lower than the second reference voltage in the light load mode is shorter than the second period. During the period, the second RSFF circuit is characterized in that the switching transistor is turned on by the rising edge of the clock signal of the second frequency.

The invention according to claim 3 is the current mode step-down switching regulator according to claim 2, wherein the period in which the feedback voltage is lower than the second reference voltage is shorter than the third period in the light load mode. The clock signal of the second frequency is masked, and the second RSFF circuit is characterized in that the switching transistor is turned on every time the feedback voltage falls below the second reference voltage.

According to the present invention, in the heavy load mode, when the period in which the switch current detection voltage is smaller than the third reference voltage exceeds the first period, the heavy load mode is switched to the light load mode. Further, in the light load mode, when the switch current detection voltage is larger than the fourth reference voltage larger than the third reference voltage and the feedback voltage is lower than the second reference voltage exceeds the second period, the heavy load mode is changed to the light load. Switch to mode. Therefore, the magnitude of the switch current at the time of switching from the heavy load mode to the light load mode can be made larger than the magnitude of the switch current at the time of switching from the light load mode to the heavy load mode. Hysteresis can be given to the switching of the load mode, and the switching between the light load mode and the heavy load mode can be stabilized.

It is explanatory drawing of the switching of a light load mode and a heavy load mode of this invention. It is a circuit diagram of the current mode step-down switching regulator of the Example of this invention. It is a circuit diagram of the oscillator of the Example of this invention. It is an operation waveform figure of switching from a heavy load mode to a light load mode of the Example of this invention. It is an operation waveform figure of switching from a light load mode to a heavy load mode of the Example of this invention. It is an operation waveform figure of an oscillator. It is a circuit diagram of a conventional switching regulator.

In the current mode step-down switching regulator of the present invention, as shown in FIG. 1, the set values of the switch current Isw flowing through the switching transistor are set to two types of Ipk1 and Ipk2, and Ipk1 <Ipk2 is set to operate in the heavy load mode. When the switch current Isw falls below the set value Ipk1, the mode is switched to the light load mode under a predetermined condition. In this light load mode, the conversion efficiency can be improved by switching the frequency f of the clock signal CLK to a frequency lower than the frequency in the heavy load mode.

Further, when the switch current Isw exceeds the set value Ipk2 while operating in the light load mode, the heavy load mode is switched under a predetermined condition. In this heavy load mode, the frequency f of the clock signal CLK is switched to a frequency higher than the frequency in the low load mode.

Assuming that Iout1 is the output current at the time of switching from the heavy load mode to the light load mode and Iout2 is the output current at the time of switching from the light load mode to the heavy load mode, the output currents Iout1 and Iout2 are given by the equations (2) and (3). It will be as shown.

Focusing on the conversion efficiency in the light load mode, the larger the set value Ipk2 is, the more energy is stored in the output capacitor C1 in one switching, so that the output voltage Vout rises more. As described above, in order to increase the conversion efficiency in the light load mode, the larger the set value Ipk2 is, the better. Therefore, for example, if Ipk2 = 2 × Ipk1, then Iout2 = 4 × Iout1 as shown in the equation (4). ..

However, as the set value Ipk2 becomes larger, the output current Iout2 at the time of switching from the light load mode to the heavy load mode becomes larger, and the light load mode is operated even in the region where the heavy load mode should be operated.

Therefore, by increasing the set value Ipk2 and setting a limit on the minimum value of the frequency f of the clock signal CLK, the conversion efficiency in the light load mode is increased, and the current Iout2 for switching from the light load mode to the heavy load mode is increased. Don't go too far. For example, as shown in the equation (5), by multiplying Ipk2 = 3 × Ipk1 and the frequency f by 0.25 times, Iout2 = 2.25 × Iout1 and Iout2 can be prevented from becoming too high than Iout1.

FIG. 2 shows the circuit of the current mode step-down switching regulator according to the embodiment of the present invention. Reference numeral 10 denotes a main circuit mainly for heavy load, and 20 is a sub circuit mainly for light load, both of which are incorporated in the IC.

In the main circuit 10, MP1 is a MOSFET switching transistor, an input voltage Vin is applied to the source, and a drain is connected to the node N1. 11 is a drive circuit that drives the gate of the switching transistor MP1, 12 is an inverter that inverts the signal input to the drive circuit 11, 13 is a first RSFF circuit that operates the drive circuit 11 via the inverter 12 and the switch SW1, and 14 is switching. This is a current sense circuit that detects the switch current Isw flowing through the transistor MP1 and outputs the switch current detection voltage V14. Reference numeral 15 denotes an error amplifier that amplifies the difference between the feedback voltage Vfb input to the node N2 and the first reference voltage Vref1 corresponding to the output target voltage. Reference numeral 16 denotes an oscillator, which generates a clock signal CLK and a lamp voltage Vram synchronized with the clock signal CLK, and its oscillation frequency can be switched between f1 and f2 (f2 = 0.25 × f1) as described later. Reference numeral 17 denotes an adder that adds the switch current detection voltage V14 output from the current sense circuit 14 and the lamp voltage Vramp. Reference numeral 18 denotes a comparator, which compares the adder voltage V17 output from the adder 17 with the error voltage V15 output from the error amplifier 15, and sets the PWM control voltage V18 for setting the time until the first RSFF circuit 13 is reset. Generate. The MN1 is a reset NMOS transistor for dropping the noise component remaining in the output voltage V17 of the adder 17 to “L”, and is turned on when the terminal QB of the first RSFF circuit 13 becomes “H”. The switch SW1 inserted between the Q terminal of the first RSFF circuit 13 and the inverter 12 is turned on in the heavy load mode and turned off in the light load mode.

L1 is an inductor that stores energy when the switching transistor MP1 is turned on, C1 is an output capacitor, and D1 is connected to the output capacitor C1 and the output terminal N3 with the energy stored in the inductor L1 when the switching transistor MP1 is turned off. It is a diode for the switch that supplies the load. R1 and R2 are resistors for dividing the voltage for detecting the output voltage Vout of the terminal N3, and the feedback voltage Vfb obtained there is input to the node N2.

In the sub-circuit 20, 21 is an inverter that drives the drive circuit 11, 22 is a second RSFF circuit, and SW2 is a switch inserted between the inverter 21 and the Q terminal of the second RSFF circuit 22. This switch SW2 is turned off in the heavy load mode and turned on in the light load mode. Reference numeral 23 denotes a comparator that compares the second reference voltage Vref2 with the feedback voltage Vfb. The second reference voltage Vref2 is set to the same value as the first reference voltage Vref1 described above, but is not limited thereto. Reference numeral 24 denotes a one-shot multi-circuit that generates an H pulse when the output voltage V23 of the comparator 23 rises to “H”. Reference numeral 25 denotes a timer circuit, and when the voltage V23 continues “H” for the second period T2, the heavy load mode setting voltage V25 is set to “H”. Reference numeral 26 denotes a comparator, and when the switch SW3 is on, the third reference voltage Vref3 and the switch current detection voltage V14 are compared, and when the switch SW4 is on, the fourth reference voltage Vref4 and the switch current detection voltage V14 are compared. Then, when the output voltage V26 rises to “H”, the second RSFF circuit 22 is reset. The values of the reference voltages Vref3 and Vref4 are set to Vref3 <Vref4. The switch SW3 is on in the heavy load mode and off in the light load mode, and the switch SW4 is off in the heavy load mode and on in the light load mode. Reference numeral 27 denotes a counter for counting the pulse of the clock signal CLK generated by the oscillator 16. The counter 27 counts a predetermined number and sets the light load mode setting voltage V27 to “H” when the first period T1 is reached, but the output voltage V26 of the comparator 26 is set to “H” before reaching the first period T1. When it rises to "", it is reset to "L". Reference numeral 28 denotes an AND circuit, which masks the H pulse of the clock signal CLK when the output voltage V23 of the comparator 23 is “L” and passes the H pulse of the clock signal CLK when it is “H”. Reference numeral 29 denotes an OR circuit, and the voltage V29 is changed to “H” when the output voltage V28 of the AND circuit 28 rises to “H” or when the one-shot pulse voltage V24 output from the one-shot multi-circuit 24 rises to “H”. , And set the second RSFF circuit 22.

In the above, the heavy load mode is switched to the light load mode at the timing when the voltage V27 output from the counter 27 rises to “H”. When the voltage V27 becomes “H”, the switch SW1 is turned off, SW2 is turned on, SW3 is turned off, SW4 is turned on, SW5 described later in the oscillator 16 is turned off, and SW6 is set to on. Further, at the timing when the voltage V25 output from the timer circuit 25 rises to “H”, the light load mode is switched to the heavy load mode. When the voltage 27 becomes “H”, the switch SW1 is turned on, SW2 is turned off, SW3 is turned on, SW4 is turned off, SW5 is turned on, and SW6 is turned off.

FIG. 3 shows the internal circuit of the oscillator 16. I1 is a current source that charges the capacitor C2 with the current I1 when the switch SW5 is turned on, and I2 is a current source that charges the capacitor C2 with the current I2 when the switch SW6 is turned on. The current value is set to I1> I2. The MN2 is an NMOS transistor, which is turned on when the output voltage V24 of the one-shot multi-circuit 24 is “H” to discharge the electric charge of the capacitor C2. The MN3 is also an NMOS transistor, and when it is turned on, the charge of the capacitor C2 is discharged. Reference numeral 161 is a comparator that compares the voltage VC2 of the capacitor C2 with the fifth reference voltage Vref5. Reference numeral 162 denotes an inverter that inverts the output voltage V161 of the comparator 161. The output becomes a clock signal CLK and controls the gate of the transistor MN3. The frequency of the clock signal CLK is f1 when the switch SW5 is on and the switch SW6 is off, and f2 which is lower than f1 when the switch SW5 is off and the switch SW6 is on. Reference numeral 163 is a lamp voltage generation circuit that generates a lamp voltage voltage synchronized with the clock signal CLK.

By the way, when the heavy load mode is set, the oscillator 16 oscillates the clock signal CLK at a high oscillation frequency f1, and the switches are SW1, SW3, SW5 on and SW2, SW4, SW6 off. ing. At this time, since the switch SW2 is off, the second RSFF circuit 22 is in an invalid state, and the sub circuit 20 does not affect the drive circuit 11. Then, since the switch SW1 is on, the first RSFF circuit 13 becomes effective and the main circuit 10 mainly operates.

When the clock signal CLK of the oscillator 16 rises to "H", the first RSFF circuit 13 is set, the Q terminal becomes "H", the output of the inverter 12 becomes "L", and the output voltage V11 of the drive circuit 11 becomes "L". , And the switching transistor MP1 is turned on. After that, when the added voltage V17 of the lamp voltage Vram of the oscillator 16 and the switch current detection voltage V14 is higher than the error voltage V15 of the difference between the feedback voltage Vfb reflecting the output voltage Vout and the first reference voltage Vref1, comparison is made. The output voltage V18 of the device 18 rises to "H", the first RSFF circuit 13 is reset, the Q terminal is inverted to "L", the voltage V11 becomes "H", and the switching transistor MP1 is turned off. After that, the on / off switching operation of the switching transistor MP1 is repeated by the same operation.

At this time, in the sub-circuit 20, as shown in FIG. 4, when the switch current detection voltage V14 of the switching transistor MP1 becomes larger than the third reference voltage Vref3, the output voltage V26 of the comparator 26 becomes “H”. The counter 27 is reset. This is repeated every time the switch current detection voltage V14 becomes larger than the third reference voltage Vref3.

However, when the switch current detection voltage V14 of the switching transistor MP1 becomes smaller than the third reference voltage Vref3, the output voltage V26 of the comparator 26 remains “L” and the counter 27 is not reset. Then, after the output voltage V26 becomes “L”, the counter 27 starts counting the clock signal CLK of the frequency f1, and when the counting continues beyond the first period T1, the output voltage V27 becomes It becomes "H". As a result, the switches SW1, SW3, SW5 are switched off, the switches SW2, SW4, SW6 are switched on, the heavy load mode is released, and the light load mode is set.

As described above, in the heavy load mode, when the switch current detection voltage V14 becomes smaller than the third reference voltage Vref3 and exceeds T1 in the first period, the mode is switched to the light load mode and the oscillation frequency of the clock signal CLK of the oscillator 16 is set. Switches from f1 to f2, and the comparison voltage of the comparator 26 switches from the third reference voltage Vref3 to the larger fourth reference voltage Vref4. The magnitude of the switch current Isw at the time of this switching corresponds to the above-mentioned set value Ipk1. That is, the set value Ipk1 is set by the third reference voltage Vref3.

In this light load mode, when the switch SW1 is turned off and the switch SW2 is turned on, the first RSFF circuit 13 of the main circuit 10 is invalidated, and the drive circuit 11 is controlled by the second RSFF circuit 22 of the sub circuit 20. Become. At this time, since the load is light, the feedback voltage Vfb is higher than the second reference voltage Vref2, and the output voltage V23 of the comparator 23 does not change from “L”.

However, as shown in FIG. 5, when the output voltage Vout drops and a state of Vfb <Vref2 occurs, the output voltage V23 rises to “H”, so that the one-shot multi-circuit 24 to “H” one-shot pulse. The voltage 24 rises, and the second RSFF circuit 22 is set via the OR circuit 29. As a result, the switching transistor MP1 is turned on and the switch current Isw flows.

At this time, since the switch SW3 is off and the switch SW4 is on, when the switch current detection voltage V14 becomes larger than the fourth reference voltage Vref4, the output voltage V26 of the comparator 26 becomes “H”, and the second 2 The RSFF circuit 22 is reset. Since Vref3 <Vref4, the switch current detection voltage V14 when the output voltage V26 of the comparator 26 becomes “H” is larger than the third reference voltage Vref3, and the switch current Isw is also large.

After that, the on / off switching operation of the switching transistor MP1 is repeated by the operation of the second RSFF circuit 22, but at this time, the clock signal CLK of the oscillator 16 is not used, and the value of the feedback voltage Vfb and the switching current detection voltage V14 The value determines the on / off cycle of the switching transistor MP1. This period is longer than the period of the frequency f2 of the clock signal CLK.

When the load becomes heavier, the load current Iout increases, and the time for the feedback voltage Vfb to decrease becomes longer, the output voltage V23 of the comparator 23 does not change from the “H” state, and the one-shot multi-circuit 24 is re-one. The shot pulse voltage V24 is no longer output.

As a result, since the voltage V23 becomes “H”, the AND circuit 28 keeps the gate open, so that the clock signal CLK of the frequency f2 of the oscillator 16 passes through the AND circuit 28 and the OR circuit 29. 2 Set the RSFF circuit 22.

As shown in FIG. 5, when the feedback voltage Vfb is relatively stable in a light load state, the second RSFF circuit 22 is occasionally set by the one-shot pulse voltage V24 at a period longer than the frequency f2, and is a switching transistor. The number of times MP1 is turned on / off is reduced. However, when the period in which the load becomes heavier and the feedback voltage Vfb drops significantly exceeds the third period T3 (however, within a period shorter than the second period T2 by the timer circuit 25), only the third period T3 The AND circuit 28 opens the gate, and the second RSFF circuit 22 is set by the clock signal CLK of the frequency f2 of the oscillator 16.

Further, when the feedback voltage Vfb becomes lower than the second reference voltage Vref2 and the period during which the voltage V23 is “H” exceeds the timer time T2 set by the timer circuit 25, the output voltage V25 of the timer circuit 25 Becomes "H". As a result, the switches SW1, SW3, SW5 are switched on, the switches SW2, SW4, SW6 are switched off, the light load mode is released, and the heavy load mode is set.

As described above, in the light load mode, when the feedback voltage Vfb is lower than the second reference voltage Vref2 for a long time and the time exceeds the second period T2 by the timer circuit 25, the oscillator is switched to the heavy load mode. The oscillation frequency of the clock signal CLK of 16 is switched from f2 to f1, and the fourth reference voltage Vref4 input to the comparator 26 is switched to the third reference voltage Vref3. The switch current detection voltage V14 immediately before switching to the heavy load mode is the fourth reference voltage Vref4, and the value of the switch current Isw at that time corresponds to the set value Ipk2.

In this embodiment, as described above, the switch current Isw value Ipk1 when switching from the heavy load mode to the light load mode and the switch current Isw value Ipk2 when switching from the light load mode to the heavy load mode are set to Ipk1 <Ipk2. Since the output current can be set to Iout1 <Iout2 and the hysteresis operation can be realized, the operation at the switching point between the heavy load mode and the light load mode will not become unstable.

FIG. 6 shows the operating waveform of the oscillator 16. When the capacitor C2 is charged by the current I1 or I2 and its voltage VC2 reaches the reference voltage Vref5, the output voltage V161 of the comparator 161 becomes “L” and the clock signal CLK becomes “H”, so that the transistor MN3 Turns on and the capacitor C2 is discharged. The charge / discharge cycle is shorter when charged with the current I1 than when charged with the current I2. That is, when the switch SW5 is on, it is in the heavy load mode, and the frequency of the clock signal CLK is f1. Further, when the switch SW6 is on, it is in the light load mode, and the frequency of the clock signal CLK is f2. Then, when the feedback voltage Vfb becomes lower than the second reference voltage Vref2 and the one-shot pulse voltage V24 output from the one-shot multi-circuit 24 becomes “H”, the transistor MN2 is turned on during that period and the oscillation operation is performed. It will be reset.

10: Main circuit, 11: Drive circuit, 12: Inverter, 13: RSFF circuit, 14: Current sense circuit, 15: Error amplifier, 16: Oscillator, 17: Adder, 18: Comparer 20: Sub circuit, 21: Inverter, 22: RSFF circuit, 23: Comparer, 24: One-shot multi-circuit, 25: Timer circuit, 26: Comparer, 27: Counter, 28: AND circuit, 29: OR circuit

Claims (3)

In a current mode step-down switching regulator that switches between heavy load mode and light load mode
A switching transistor that switches the input voltage to generate the output voltage,
When the clock signal rises, the switching transistor is turned on, and the added voltage obtained by adding the switch current detection voltage that detects the switch current flowing when the switching transistor is turned on to the lamp voltage synchronized with the clock signal is the first reference voltage and the said. A main circuit having a first RSFF circuit that turns off the switching transistor when it is larger than an error voltage indicating the difference between the output voltage and the feedback voltage
When the clock signal rises when the feedback voltage is smaller than the second reference voltage, the switching transistor is turned on, and the switch current detection voltage is higher than the third reference voltage or the fourth reference voltage larger than the third reference voltage. A sub-circuit having a second RSFF circuit that turns off the switching transistor when it becomes large is provided.
In the heavy load mode, when the period during which the switch current detection voltage is smaller than the third reference voltage exceeds the first period, the sub-circuit disables the first RSFF circuit and disables the second RSFF circuit. Is effectively set, the frequency of the clock signal is switched from the first frequency to the second frequency of a lower frequency, and the third reference voltage is switched to the fourth reference voltage, whereby the heavy load mode is changed to the light. Switch to load mode,
In the light load mode, the sub-circuit invalidates the second RSFF circuit and enables the first RSFF circuit when the period during which the feedback voltage is smaller than the second reference voltage exceeds the second period. By setting, the frequency of the clock signal is switched from the second frequency to the first frequency, and the fourth reference voltage is switched to the third reference voltage, the light load mode is switched to the heavy load mode.
A current mode step-down switching regulator characterized by this. In the current mode step-down switching regulator according to claim 1,
In the light load mode, when the period in which the feedback voltage is lower than the second reference voltage is the third period shorter than the second period, the second RSFF circuit performs the switching due to the rising edge of the clock signal of the second frequency. A current mode step-down switching regulator characterized by turning on a transistor. In the current mode step-down switching regulator according to claim 2,
In the light load mode, when the period during which the feedback voltage is lower than the second reference voltage is shorter than the third period, the clock signal of the second frequency is masked, and in the second RSFF circuit, the feedback voltage is the second. 2. A current mode step-down switching regulator characterized in that the switching transistor is turned on each time the voltage falls below the reference voltage.

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