JP7271361B2 - Current mode step-down switching regulator - Google Patents

Description

The present invention relates to a current mode step-down switching regulator capable of stably switching between a light load mode and a heavy load mode.

FIG. 7 shows the circuit configuration of a conventional current mode step-down switching regulator. A circuit similar to this is described in US Pat. MP1 is a PMOS switching transistor, the input voltage Vin is applied to the source, and the drain is connected to the node N1. 1 is a drive circuit that drives the gate of the switching transistor MP1, 2 is an inverter that inverts the signal input to the drive circuit 1, 3 is an RSFF circuit that operates the drive circuit 1 via the inverter 2, and 4 flows to the switching transistor MP1. It is a current sense circuit that detects a switch current Isw and outputs a switch current detection voltage V4. An error amplifier 5 amplifies the difference between the feedback voltage Vfb input to the node N2 and the reference voltage Vref1 corresponding to the output target voltage. An oscillator 6 generates a clock signal CLK for setting the RSFF circuit 3 and a ramp voltage Vramp synchronized with the clock signal CLK. An adder 7 adds the switch current detection voltage V4 and the ramp voltage Vramp. A comparator 8 compares the addition voltage V7 output from the adder 7 and the error voltage V5 output from the error amplifier 5, and generates a PWM control voltage V8 for setting the time until the RSFF circuit 3 is reset. do. MN1 is a reset NMOS transistor for dropping the noise component remaining in the output voltage V7 of the adder 7 to "L", and is turned on when the terminal QB of the RSFF circuit 3 becomes "H".

L1 is an inductor that stores energy when the switching transistor MP1 is turned on, C1 is an output capacitor, and D1 is connected to the output capacitor C1 and the output terminal N3 to store the energy stored in the inductor L1 when the switching transistor MP1 is turned off. This is the diode for the switch that supplies the load. R1 and R2 are voltage dividing resistors for detecting the output voltage Vout of the terminal N3, and the obtained feedback voltage Vfb is input to the node N2.

In this current mode step-down switching regulator, when the RSFF circuit 3 is set by the clock signal CLK, the terminal Q becomes "H", the output voltage V1 of the driving circuit 1 becomes "L", and the switching transistor MP1 turns on. Further, the error voltage V5 and the addition voltage V7 are compared by the comparator 8, and when the result becomes V7>V5, the PWM control voltage V8 output from the comparator 8 becomes "H", and the RSFF circuit 3 is reset. , the terminal Q becomes "L", the output voltage V1 of the driving circuit 1 becomes "H", and the switching transistor MP1 is turned off. Further, the terminal QB of the RSFF circuit 3 becomes "H" to turn on the transistor MN1, thereby masking the PWM control voltage V7 to "L".

As a result, the switching transistor MP1 is turned on only during the period from the rise of the clock signal CLK until the PWM control voltage V8 becomes "H". In this manner, the switching transistor MP1 is PWM-controlled, and the output voltage Vout is subjected to negative feedback control so that Vfb=Vref1.

Japanese Patent No. 5063474

By the way, in order to improve the operating efficiency of the current mode step-down switching regulator of FIG. It is conceivable to switch the frequency of the generated clock signal CLK to a lower frequency. At this time, the relationship between the output voltage Vout and the output current Iout can be expressed by Equation (1). L1 is the inductance of the inductor L1, and f is the oscillation frequency of the oscillator 6. FIG.

However, in this method, the frequency f of the clock signal CLK is lowered when the switch current Isw becomes smaller than its peak value Ipk, and the frequency f is raised when it becomes larger. The frequency f of the clock signal CLK repeatedly rises and falls in the vicinity of the peak value Ipk, and switching between the light load mode and the heavy load mode becomes unstable.

SUMMARY OF THE INVENTION An object of the present invention is to provide a current mode step-down switching regulator capable of stably switching between a light load mode and a heavy load mode.

To achieve the above object, the invention according to claim 1 provides a switching transistor for switching an input voltage to generate an output voltage in a current mode step-down switching regulator in which switching between a heavy load mode and a light load mode is performed. Then, when the clock signal rises, the switching transistor is turned on, and the added voltage obtained by adding the switch current detection voltage obtained by detecting the switch current flowing when the switching transistor is on to the ramp voltage synchronized with the clock signal is the first reference voltage. a main circuit having a first RSFF circuit for turning off the switching transistor when the feedback voltage is larger than an error voltage indicating the difference between the output voltage and the feedback voltage; and the clock when the feedback voltage is smaller than the second reference voltage. A sub-circuit having a second RSFF circuit that turns on the switching transistor when a signal rises and turns off the switching transistor when the switch current detection voltage is greater than a third reference voltage or a fourth reference voltage greater than the third reference voltage. wherein, in the heavy load mode, the sub-circuit disables the first RSFF circuit and the the heavy load mode by enabling the second RSFF circuit, switching the frequency of the clock signal from a first frequency to a lower second frequency, and switching the third reference voltage to the fourth reference voltage; to the light load mode, and the sub-circuit disables the second RSFF circuit when a period during which the feedback voltage is lower than the second reference voltage exceeds a second period in the light load mode. and enabling the first RSFF circuit, switching the frequency of the clock signal from the second frequency to the first frequency, and switching the fourth reference voltage to the third reference voltage to achieve the light load mode to the heavy load mode.

The invention according to claim 2 is directed to the current mode step-down switching regulator according to claim 1, wherein in the light load mode, the period during which the feedback voltage is lower than the second reference voltage is shorter than the second period. During the period, the second RSFF circuit turns on the switching transistor at the rising edge of the clock signal of the second frequency.

The invention according to claim 3 is the current mode step-down switching regulator according to claim 2, wherein, in the light load mode, when the period during which the feedback voltage is lower than the second reference voltage is shorter than the third period, the A clock signal of a second frequency is masked, and the second RSFF circuit turns on the switching transistor each time the feedback voltage falls below the second reference voltage.

According to the present invention, in the heavy load mode, when the period during which the switch current detection voltage is lower than the third reference voltage exceeds the first period, the heavy load mode is switched to the light load mode. Further, in the light load mode, when the period during which the switch current detection voltage is higher than the fourth reference voltage, which is higher than the third reference voltage, and the feedback voltage is lower than the second reference voltage exceeds the second period, the light load mode is changed from the heavy load mode to the light load mode. switch to mode. Therefore, the magnitude of the switch current at the time of switching from the heavy load mode to the light load mode can be made larger than the magnitude of the switch current at the time of switching from the light load mode to the heavy load mode. Hysteresis can be added to the switching of the load mode, and switching between the light load mode and the heavy load mode can be stabilized.

FIG. 4 is an explanatory diagram of switching between a light load mode and a heavy load mode according to the present invention; 1 is a circuit diagram of a current mode step-down switching regulator according to an embodiment of the present invention; FIG. 1 is a circuit diagram of an oscillator according to an embodiment of the invention; FIG. FIG. 4 is an operation waveform diagram of switching from heavy load mode to light load mode according to the embodiment of the present invention; FIG. 4 is an operation waveform diagram of switching from a light load mode to a heavy load mode according to the embodiment of the present invention; 4 is an operating waveform diagram of an oscillator; FIG. 1 is a circuit diagram of a conventional switching regulator; FIG.

As shown in FIG. 1, the current mode step-down switching regulator of the present invention operates in a heavy load mode by setting two types of switch current Isw, Ipk1 and Ipk2, to satisfy Ipk1<Ipk2. When the switch current Isw drops below the set value Ipk1 during the operation, the switch is switched to the light load mode under predetermined conditions. In this light load mode, the conversion efficiency can be improved by switching the frequency f of the clock signal CLK to a frequency lower than that in the heavy load mode.

Further, when the switch current Isw exceeds the set value Ipk2 during operation in the light load mode, the mode is switched to the heavy load mode under predetermined conditions. In this heavy load mode, the frequency f of the clock signal CLK is switched to a frequency higher than that in the low load mode.

Assuming that Iout1 is the output current when the heavy load mode is switched to the light load mode, and Iout2 is the output current when the light load mode is switched to the heavy load mode, the output currents Iout1 and Iout2 are given by equations (2) and (3). As shown.

Here, focusing on the conversion efficiency in the light load mode, the larger the set value Ipk2, the more energy stored in the output capacitor C1 in one switching operation, and the larger the increase in the output voltage Vout. Thus, in order to increase the conversion efficiency in the light load mode, the larger the set value Ipk2, the better. For example, if Ipk2=2×Ipk1, then Iout2=4×Iout1 as shown in Equation (4). .

However, the larger the set value Ipk2, the larger the output current Iout2 at the time of switching from the light load mode to the heavy load mode.

Therefore, by setting a limit on the minimum value of the frequency f of the clock signal CLK while increasing the set value Ipk2, the current Iout2 at which the light load mode is switched to the heavy load mode increases while increasing the conversion efficiency in the light load mode. Don't overdo it. For example, by setting Ipk2=3×Ipk1 and multiplying the frequency f by 0.25 as shown in Equation (5), Iout2=2.25×Iout1, and Iout2 can be prevented from becoming too much higher than Iout1.

FIG. 2 shows a circuit of a current mode step-down switching regulator according to an embodiment of the present invention. 10 is a main circuit that mainly works for heavy loads, and 20 is a sub-circuit that mainly works for light loads, both of which are incorporated in the IC.

In the main circuit 10, MP1 is a PMOS switching transistor having a source to which an input voltage Vin is applied and a drain connected to a node N1. Reference numeral 11 denotes a drive circuit that drives the gate of the switching transistor MP1; 12, an inverter that inverts the signal input to the drive circuit 11; 13, a first RSFF circuit that operates the drive circuit 11 via the inverter 12 and the switch SW1; It is a current sense circuit that detects a switch current Isw flowing through the transistor MP1 and outputs a switch current detection voltage V14. An error amplifier 15 amplifies the difference between the feedback voltage Vfb input to the node N2 and the first reference voltage Vref1 corresponding to the output target voltage. An oscillator 16 generates a clock signal CLK and a ramp voltage Vramp synchronized with the clock signal CLK, and its oscillation frequency can be switched between f1 and f2 (f2=0.25×f1) as described later. An adder 17 adds the switch current detection voltage V14 output from the current sensing circuit 14 and the ramp voltage Vramp. A comparator 18 compares the addition voltage V17 output from the adder 17 and the error voltage V15 output from the error amplifier 15, and outputs a PWM control voltage V18 for setting the time until the first RSFF circuit 13 is reset. Generate. MN1 is a reset NMOS transistor for dropping the noise component remaining in the output voltage V17 of the adder 17 to "L", and is turned on when the terminal QB of the first RSFF circuit 13 becomes "H". A switch SW1 inserted between the Q terminal of the first RSFF circuit 13 and the inverter 12 is turned on during the heavy load mode and turned off during the light load mode.

L1 is an inductor that stores energy when the switching transistor MP1 is turned on, C1 is an output capacitor, and D1 is connected to the output capacitor C1 and the output terminal N3 to store the energy stored in the inductor L1 when the switching transistor MP1 is turned off. This is the diode for the switch that supplies the load. R1 and R2 are voltage dividing resistors for detecting the output voltage Vout of the terminal N3, and the obtained feedback voltage Vfb is input to the node N2.

In the sub-circuit 20, 21 is an inverter that drives the drive circuit 11, 22 is a second RSFF circuit, and SW2 is a switch inserted between the Q terminal of the inverter 21 and the second RSFF circuit 22. FIG. This switch SW2 is turned off during the heavy load mode and turned on during the light load mode. A comparator 23 compares the second reference voltage Vref2 and the feedback voltage Vfb. The second reference voltage Vref2 is set to the same value as the first reference voltage Vref1, but is not limited thereto. A one-shot multi circuit 24 generates an H pulse when the output voltage V23 of the comparator 23 rises to "H". A timer circuit 25 sets the heavy load mode setting voltage V25 to "H" when the voltage V23 continues to be "H" for the second period T2. A comparator 26 compares the third reference voltage Vref3 with the switch current detection voltage V14 when the switch SW3 is on, and compares the fourth reference voltage Vref4 with the switch current detection voltage V14 when the switch SW4 is on. and resets the second RSFF circuit 22 when its output voltage V26 rises to "H". The values of the reference voltages Vref3 and Vref4 are set to Vref3<Vref4. The switch SW3 is turned on during the heavy load mode and turned off during the light load mode, and the switch SW4 is turned off during the heavy load mode and turned on during the light load mode. A counter 27 counts the pulses of the clock signal CLK generated by the oscillator 16 . The counter 27 counts a predetermined number and sets the light load mode setting voltage V27 to "H" when the first period T1 is reached. ” is reset to “L”. An AND circuit 28 masks the H pulse of the clock signal CLK when the output voltage V23 of the comparator 23 is "L" and passes the H pulse of the clock signal CLK when it is "H". Reference numeral 29 denotes an OR circuit which changes the voltage V29 to "H" when the output voltage V28 of the AND circuit 28 rises to "H" or when the one-shot pulse voltage V24 output from the one-shot multi circuit 24 rises to "H". ” to set the second RSFF circuit 22 .

As described above, the heavy load mode is switched to the light load mode at the timing when the voltage V27 output from the counter 27 rises to "H". When the voltage V27 becomes "H", the switch SW1 is turned off, SW2 is turned on, SW3 is turned off, SW4 is turned on, SW5 in the oscillator 16 is turned off, and SW6 is turned on. Also, at the timing when the voltage V25 output from the timer circuit 25 rises to "H", switching from the light load mode to the heavy load mode is performed. When the voltage 27 becomes "H", the switch SW1 is turned on, SW2 is turned off, SW3 is turned on, SW4 is turned off, SW5 is turned on, and SW6 is turned off.

FIG. 3 shows the internal circuitry of the oscillator 16. As shown in FIG. A current source I1 charges the capacitor C2 with the current I1 when the switch SW5 is turned on, and a current source I2 charges the capacitor C2 with the current I2 when the switch SW6 is turned on. The current values are set to I1>I2. MN2 is an NMOS transistor which turns on when the output voltage V24 of the one-shot multi-circuit 24 is "H" to discharge the capacitor C2. MN3 is also an NMOS transistor, and when it is turned on, it discharges the charge of capacitor C2. A comparator 161 compares the voltage VC2 of the capacitor C2 with the fifth reference voltage Vref5. An inverter 162 inverts the output voltage V161 of the comparator 161, and its output becomes a clock signal CLK, which controls the gate of the transistor MN3. The frequency of the clock signal CLK is f1 when the switch SW5 is on and the switch SW6 is off, and is f2 lower than f1 when the switch SW5 is off and the switch SW6 is on. A ramp voltage generation circuit 163 generates a ramp voltage Vramp in synchronization with the clock signal CLK.

Now, when the heavy load mode is set, the oscillator 16 oscillates the clock signal CLK at a high oscillation frequency f1, and the switches SW1, SW3, and SW5 are turned on, and the switches SW2, SW4, and SW6 are turned off. ing. At this time, since the switch SW2 is off, the second RSFF circuit 22 is disabled, and the sub-circuit 20 does not affect the drive circuit 11. FIG. Since the switch SW1 is on, the first RSFF circuit 13 is enabled and the main circuit 10 mainly operates.

When the clock signal CLK of the oscillator 16 rises to "H", the first RSFF circuit 13 is set, the Q terminal becomes "H", the output of the inverter 12 becomes "L", and the output voltage V11 of the driving circuit 11 becomes "L". ” to turn on the switching transistor MP1. Thereafter, when the sum voltage V17 of the ramp voltage Vramp of the oscillator 16 and the switch current detection voltage V14 becomes higher than the error voltage V15 of the difference between the feedback voltage Vfb reflecting the output voltage Vout and the first reference voltage Vref1, the comparison The output voltage V18 of the device 18 rises to "H", the first RSFF circuit 13 is reset, the Q terminal is inverted to "L", the voltage V11 becomes "H", and the switching transistor MP1 is turned off. After that, the ON/OFF switching operation of the switching transistor MP1 is repeated by the same operation.

At this time, in the sub-circuit 20, as shown in FIG. 4, when the switch current detection voltage V14 of the switching transistor MP1 becomes higher than the third reference voltage Vref3, the output voltage V26 of the comparator 26 becomes "H". Counter 27 is reset. This is repeated each time the switch current detection voltage V14 becomes greater than the third reference voltage Vref3.

However, when the switch current detection voltage V14 of the switching transistor MP1 becomes lower than the third reference voltage Vref3, the output voltage V26 of the comparator 26 remains "L" and the counter 27 is not reset. After the output voltage V26 becomes "L", the counter 27 starts counting the clock signal CLK having the frequency f1, and when the counting continues beyond the first period T1, the output voltage V27 "H". As a result, the switches SW1, SW3, and SW5 are turned off, and the switches SW2, SW4, and SW6 are turned on, so that the heavy load mode is canceled and the light load mode is set.

As described above, in the heavy load mode, when the switch current detection voltage V14 becomes lower than the third reference voltage Vref3 and the first period T1 elapses, the mode is switched to the light load mode, and the oscillation frequency of the clock signal CLK of the oscillator 16 is changed to the light load mode. switches from f1 to f2, and the comparison voltage of comparator 26 switches from the third reference voltage Vref3 to the larger fourth reference voltage Vref4. The magnitude of the switch current Isw at this switching time corresponds to the set value Ipk1 described above. That is, the set value Ipk1 is set by the third reference voltage Vref3.

In this light load mode, the switch SW1 is turned off and the switch SW2 is turned on, so that the first RSFF circuit 13 of the main circuit 10 is disabled and the drive circuit 11 is controlled by the second RSFF circuit 22 of the subcircuit 20. Become. Since the load is light at this time, the feedback voltage Vfb is higher than the second reference voltage Vref2, and the output voltage V23 of the comparator 23 does not change from "L".

However, as shown in FIG. 5, when the output voltage Vout drops and a state of Vfb<Vref2 occurs, the output voltage V23 rises to "H", and the one-shot multi circuit 24 outputs a one-shot pulse of "H". The voltage 24 rises and the second RSFF circuit 22 is set via the OR circuit 29 . As a result, the switching transistor MP1 is turned on and the switch current Isw flows.

At this time, the switch SW3 is turned off and the switch SW4 is turned on. Therefore, when the switch current detection voltage V14 becomes higher than the fourth reference voltage Vref4, the output voltage V26 of the comparator 26 becomes "H", 2RSFF circuit 22 is reset. Since Vref3<Vref4, the switch current detection voltage V14 when the output voltage V26 of the comparator 26 becomes "H" is higher than the third reference voltage Vref3, and the switch current Isw is also higher.

Thereafter, the ON/OFF switching operation of the switching transistor MP1 is repeated by the operation of the second RSFF circuit 22. At this time, the clock signal CLK of the oscillator 16 is not used, and the value of the feedback voltage Vfb and the switching current detection voltage V14 are equal to each other. The value determines the on/off period of the switching transistor MP1. This period is longer than the period of the frequency f2 of the clock signal CLK.

When the load becomes heavier and the load current Iout increases, and the time for the feedback voltage Vfb to drop becomes longer, the output voltage V23 of the comparator 23 does not change from the "H" state, and the one-shot multi circuit 24 repeats the one-shot operation. The shot pulse voltage V24 is no longer output.

As a result, the gate of the AND circuit 28 remains open due to the voltage V23 becoming "H", so that the clock signal CLK of the frequency f2 of the oscillator 16 passes through the AND circuit 28 and the OR circuit 29, 2 RSFF circuit 22 is set.

As shown in FIG. 5, when the feedback voltage Vfb is relatively stable in a light load state, the second RSFF circuit 22 is occasionally set by the one-shot pulse voltage V24 at a period longer than the frequency f2, and the switching transistor Reduces the number of times MP1 is turned on/off. However, when the load becomes heavy and the period during which the feedback voltage Vfb drops significantly exceeds the third period T3 (within a period shorter than the second period T2 by the timer circuit 25), only the third period T3 The AND circuit 28 opens the gate and the second RSFF circuit 22 is set by the clock signal CLK of the oscillator 16 at frequency f2.

Further, when the feedback voltage Vfb becomes lower than the second reference voltage Vref2 and the period during which the voltage V23 is "H" exceeds the timer time T2 set by the timer circuit 25, the output voltage V25 of the timer circuit 25 becomes "H". As a result, the switches SW1, SW3, and SW5 are turned on, and the switches SW2, SW4, and SW6 are turned off, so that the light load mode is canceled and the heavy load mode is set.

As described above, in the light load mode, the time during which the feedback voltage Vfb is lower than the second reference voltage Vref2 becomes longer, and when the time exceeds the second period T2 set by the timer circuit 25, the mode is switched to the heavy load mode, and the oscillator The oscillation frequency of the clock signal CLK of 16 switches from f2 to f1, and the fourth reference voltage Vref4 input to the comparator 26 switches to the third reference voltage Vref3. The switch current detection voltage V14 immediately before switching to the heavy load mode is the fourth reference voltage Vref4, and the value of the switch current Isw at that time corresponds to the set value Ipk2.

In this embodiment, the value Ipk1 of the switch current Isw when switching from the heavy load mode to the light load mode and the value Ipk2 of the switch current Isw when switching from the light load mode to the heavy load mode are defined as Ipk1<Ipk2. , the output current can be set to Iout1<Iout2, and hysteresis operation can be realized, so that the operation at the switching point between the heavy load mode and the light load mode does not become unstable.

FIG. 6 shows operating waveforms of the oscillator 16 . When the capacitor C2 is charged by the current I1 or I2 and its voltage VC2 reaches the reference voltage Vref5, the output voltage V161 of the comparator 161 becomes "L" and the clock signal CLK becomes "H". is turned on to discharge the capacitor C2. Its charge-discharge cycle is shorter when it is charged with current I1 than when it is charged with current I2. That is, when the switch SW5 is on, it is in the heavy load mode, and the frequency of the clock signal CLK is f1. When the switch SW6 is on, it is in the light load mode, and the frequency of the clock signal CLK is f2. Then, when the feedback voltage Vfb becomes lower than the second reference voltage Vref2 and the one-shot pulse voltage V24 output from the one-shot multi circuit 24 becomes "H", the transistor MN2 is turned on during that period, and the oscillation operation is started. reset.

10: main circuit, 11: drive circuit, 12: inverter, 13: RSFF circuit, 14: current sense circuit, 15: error amplifier, 16: oscillator, 17: adder, 18: comparator, 20: sub-circuit, 21: Inverter 22: RSFF circuit 23: Comparator 24: One-shot multi circuit 25: Timer circuit 26: Comparator 27: Counter 28: AND circuit 29: OR circuit

Claims (3)

In a current mode step-down switching regulator that switches between heavy load mode and light load mode,
a switching transistor for switching an input voltage to produce an output voltage;
When the clock signal rises, the switching transistor is turned on, and the addition voltage obtained by adding the switch current detection voltage obtained by detecting the switch current flowing when the switching transistor is on to the ramp voltage synchronized with the clock signal is the first reference voltage and the a main circuit having a first RSFF circuit that turns off the switching transistor when the difference between the output voltage and the feedback voltage is greater than an error voltage;
When the clock signal rises when the feedback voltage is smaller than the second reference voltage, the switching transistor is turned on, and the switch current detection voltage is lower than the third reference voltage or a fourth reference voltage higher than the third reference voltage. a sub-circuit having a second RSFF circuit that turns off the switching transistor when it becomes large;
The sub-circuit disables the first RSFF circuit and disables the second RSFF circuit when a period during which the switch current detection voltage is lower than the third reference voltage exceeds a first period in the heavy load mode. is enabled, the frequency of the clock signal is switched from a first frequency to a lower second frequency, and the third reference voltage is switched to the fourth reference voltage to switch from the heavy load mode to the light load mode. switch to load mode,
The sub-circuit disables the second RSFF circuit and enables the first RSFF circuit when a period during which the feedback voltage is lower than the second reference voltage exceeds a second period in the light load mode. switching the frequency of the clock signal from the second frequency to the first frequency and switching the fourth reference voltage to the third reference voltage to switch from the light load mode to the heavy load mode;
A current mode step-down switching regulator characterized by: A current mode step-down switching regulator according to claim 1, wherein
In the light load mode, when the period during which the feedback voltage is lower than the second reference voltage is a third period shorter than the second period, the second RSFF circuit performs the switching at the rising edge of the clock signal of the second frequency. A current mode step-down switching regulator characterized by turning on a transistor. 3. The current mode step-down switching regulator according to claim 2,
In the light load mode, when the period during which the feedback voltage is less than the second reference voltage is shorter than the third period, the clock signal of the second frequency is masked, and the second RSFF circuit controls the feedback voltage so that the feedback voltage is less than the second reference voltage. 2. A current mode step-down switching regulator characterized by turning on the switching transistor each time the voltage falls below a reference voltage.

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