JP2014023208A - Artificial resonance switching power supply device control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a control circuit for an artificial resonance switching power supply capable of sufficiently lowering the switching frequency when lightly loaded.SOLUTION: The artificial resonance switching power supply causes a switching element to switch on or off on the basis of a bottom detection signal. The switching power supply is provided with a dummy signal generation circuit (37) which, when the resonance waveform is attenuated due to reduction in the switching frequency and the bottom becomes undetectable or when the bottom of the resonance waveform has exceeded a set count, generates a dummy signal in place of the bottom detection signal, and is configured so that the switching frequency is lowered as the number of times the bottom is skipped increases due to the use of this dummy signal.

Description

  The present invention relates to a quasi-resonant switching power supply device, and more particularly to a control circuit for a quasi-resonant switching power supply device that performs bottom skip control in accordance with a load state.

  In the quasi-resonant switching power supply device, the switching frequency increases as the load becomes lighter. For this reason, the switching loss of the power device increases at the time of a light load and the conversion efficiency decreases, and particularly when the load is 50% or less of the rated load, the conversion efficiency is remarkably reduced. Moreover, the increase in the switching loss causes excessive heat generation of the power device.

Therefore, a technique has been proposed in which a so-called bottom skip control method is applied to suppress a monotonous increase in operating frequency at light loads.
In the bottom skip control, a resonance waveform of a drain terminal of a power device (hereinafter referred to as a switching element) composed of a MOSFET, an IGBT, or the like is used. That is, when the load is heavy, the switching element is turned on at the timing of the first bottom in the resonance waveform, and when the load is light, the switching element is turned on not at the first bottom but at the bottom timing after that (bottom skip).
The number of bottom skips in this bottom skip control is set to be larger as the load is lighter, thereby suppressing an increase in switching frequency at light load.

Thus, in bottom skip control, the switching frequency at light load decreases. Since a mere decrease in switching frequency results in a decrease in power supply output voltage, in order to maintain the power supply output voltage stably, it is necessary to widen the ON width of the switching element to compensate for the decrease, that is, the on-time ratio Need to maintain.
However, when bottom skip control is performed by determining the weight of the load based on the ON width of the switching element, if the above ON width is increased, the determination of the weight of the load becomes inappropriate. There is a possibility that the number of bottom skips may return to the original in the switching cycle. When the number of bottom skips is restored to the original value, the switching frequency is disturbed, resulting in a sound.

  Patent Document 1 discloses a technique for preventing the switching frequency from being disturbed. In this technique, two switching frequencies fhi and flo of the upper limit and the lower limit shown in FIG. 12 are set by a timer as a time corresponding to those cycles, and switching is performed within a range of cycles defined by the upper and lower limits. In addition, the number of bottom skips is set by a logic circuit such as an up / down counter.

  That is, when the load becomes light and the switching frequency exceeds the upper limit fhi, the set bottom skip number is increased. Conversely, when the load becomes heavy and the switching frequency falls below the lower limit flo, the set bottom skip number is decreased. The actual bottom number of the resonance waveform is counted by another counter, and the switching element is turned on when the bottom number matches the set bottom skip number.

When switching to a setting in which the number of bottom skips is increased by one and the switching frequency is lowered, the switching frequency range is set so that the switching frequency after switching is above the lower limit flo. Further, when the switching frequency is increased by switching to a setting in which the bottom skip is decreased by one, the switching frequency range is set so that the switching frequency after the switching is lower than the upper limit.
In this way, if the upper and lower limits of the switching frequency are set with hysteresis, the switching frequency is not disturbed at the time of bottom skip switching, and noise can be prevented.

  On the other hand, Patent Document 2 describes that, in a fixed-frequency PWM power supply device, when the load decreases, the switching frequency is reduced by a control voltage corresponding to the load. According to this PWM power supply device, the switching loss is reduced at a light load, so that the efficiency is improved.

JP 2005-503748 A US Patent No. 7,958,851

  From the viewpoint of improving the efficiency at light load, when the load is lightened to a predetermined size, the switching frequency is reduced to a frequency slightly above the audible frequency of about 25 kHz, and the load is higher than the predetermined size. It is desirable to adopt a method of shifting to a burst operation (a well-known method of performing switching at a high switching frequency in a period following a period without switching) when lightening.

  The bottom skip number is set by a logic circuit such as an up / down counter, the bottom of the actual resonance voltage is counted, and the switching element is turned on when the count number matches the set bottom skip number. In the quasi-resonant control, in order to realize the frequency reduction characteristic up to about 25 kHz, it is necessary to count the bottom at least 10 times in consideration of the resonance period (generally about 1 μs to 3 μs).

  However, since the resonance vibration after the transformer has finished releasing energy is attenuated as the number of vibrations increases, the number of possible bottom detections may be less than ten. As described above, when the necessary number of bottoms cannot be detected, the bottom skip control fails, and thus the frequency cannot be lowered sufficiently.

  In the example of FIG. 13 where the resonance period is 1.2 μs, the resonance voltage Vds is attenuated in such a manner that the bottom is generated about 15 times. However, in this case, since it can be detected stably only up to the 12th bottom position, the substantial resonance period is 1.2 μs × 12 = 14.4 μs. The sum of the resonance period 14.4 μs, the switching element on-time 1 μs (period of Vds = 0 V), and the flyback period 2 μs in which the resonance voltage Vds is fixed at the high level is 17.4 μs. For this reason, in this example, the switching frequency is lowered only to about 57.5 kHz.

  If the value of a resonance capacitor or the like connected in parallel to the switching element is set large, the resonance amplitude and period can be set large. However, the increase in the drain capacity of the switching element required in connection with this works in the direction of increasing the switching loss per one time, and therefore deteriorates the efficiency at light load.

  Therefore, an object of the present invention is to provide a control circuit for a quasi-resonant switching power supply device that can sufficiently lower the switching frequency at light load.

  The present invention has a bottom detection circuit that detects the bottom of a resonance waveform and outputs a bottom detection signal, and at the time of light load, the pseudo resonance switching power supply that determines the switching cycle by counting the number of bottoms detected by the bottom detection circuit When the bottom detection circuit is in a state where the bottom cannot be detected, the number of bottoms to be counted is a predetermined number, or the number of bottoms detected by the bottom detection circuit reaches a predetermined number A dummy signal in place of the bottom detection signal is counted.

  The present invention also provides a bottom detection circuit that detects the bottom of the resonance waveform and outputs a bottom detection signal, a first counter that sets the number of bottom skips, a second counter that counts the number of bottoms, A comparator that outputs a match signal when the count value of the first counter matches the count value of the second counter, and based on the bottom detection signal after the comparator outputs the match signal A control circuit for a quasi-resonant switching power supply device that performs switching operation of a switching element, and generates a dummy signal in place of the bottom detection signal when the bottom cannot be detected due to attenuation of the resonance waveform When a circuit is provided and the bottom cannot be detected, the second counter counts the dummy signal. It is characterized in.

Furthermore, the present invention provides a bottom detection circuit that detects the bottom of the resonance waveform and outputs a bottom detection signal, a first counter that sets the number of bottom skips,
A second counter that counts the number of bottoms, and a comparator that outputs a coincidence signal when the count value of the first counter and the count value of the second counter coincide with each other. A control circuit for a quasi-resonant switching power supply device that switches a switching element based on the bottom detection signal after outputting a signal, and includes a dummy signal generation circuit that generates a dummy signal instead of the bottom detection signal, The second counter counts the dummy signal when the value set in the first counter exceeds a predetermined value or the bottom of the resonance waveform exceeds a preset number of times.

In a preferred embodiment, an up / down counter is used as the first counter, and a first reference time for changing a switching frequency compared to a switching period and a second reference time longer than the first reference voltage. A timer circuit for generating a reference time is provided.
In this case, the first counter is up-counted when the switching period is shorter than the first reference time, and the first counter is down-counted when the switching period is longer than the second reference time.

  In a preferred embodiment, the period of the dummy signal is set longer than the period of the resonance waveform. In addition, the timer circuit indicates a time from the first reference time to the second reference time indicating whether the output signal of the first counter or the dummy signal is used. It is configured to be variable using a signal.

1 is a circuit diagram showing an overall configuration of a quasi-resonant switching power supply device according to the present invention. It is a wave form diagram which shows the change of the drain-source voltage of a switching element when the resonance circuit is carrying out resonance operation. It is a circuit diagram which shows the structural example of a bottom control circuit. It is a circuit diagram which shows the structural example of a variable constant current source. It is the graph which illustrated the change of the switching frequency by the control voltage corresponding to load. It is a circuit diagram which shows the structural example of a bottom detection circuit and a dummy signal generation circuit. It is a circuit diagram which shows the structural example of the oscillator in a dummy signal generation circuit. It is a wave form diagram for demonstrating operation | movement of a bottom control circuit. 6 is a graph illustrating the relationship between output power and switching frequency when a dummy signal is not used. 6 is a graph illustrating the relationship between output power and switching frequency when a dummy signal is used. It is a circuit diagram which shows the other structural example of a bottom control circuit. It is a graph which shows the bottom skip operation | movement when hysteresis is set to the upper limit and lower limit of switching frequency. It is a wave form diagram which illustrated the attenuation characteristic of resonance voltage.

FIG. 1 is a circuit diagram showing the overall configuration of a quasi-resonant switching power supply device according to the present invention.
In this switching power supply device, the transformer T has a primary winding P1, a secondary winding S1, and an auxiliary winding P2. The primary winding P1 has one end connected to the input terminal Ti and the other end connected to the drain of a switching element Tr1 made of a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The secondary winding S1 has one end connected to the output terminal To via the diode D1, and the other end connected to the ground point. One end of the auxiliary winding P2 is connected to a ZCD (Zero Current Detection) terminal which is an input terminal of the switching control circuit 1 described later, and the other end is connected to a ground point.

  A smoothing capacitor Ci is provided between the input terminal Ti and the ground point, a smoothing capacitor Co is provided between the output terminal To and the ground point, and a resonance capacitor Cr is provided between the drain of the switching element Tr1 and the ground point. Each is connected. A voltage dividing circuit including voltage dividing resistors Ro1 and Ro2 is connected between the output terminal To and the ground point, and a current detection resistor Rs is connected between the source of the switching element Tr1 and the ground point.

The switching control circuit 1 includes a bottom detection circuit 3, a bottom control circuit 5, an OR circuit 7, a one-shot circuit 9, a restart circuit 11, a flip-flop 13, a drive circuit 15, and a comparator 17. The switching control circuit 1 is integrated.
When detecting the bottom (minimum state) of the output voltage of the auxiliary winding P2 applied to the ZCD terminal, the bottom detection circuit 3 generates a Bot _- in signal of H (High) level. Specific configurations and operations of the bottom detection circuit 3 and the bottom control circuit 5 will be described later.

From the OR circuit 7, an H-level Bot _- out signal from the bottom control circuit 5 or a restart signal from the restart circuit 11 is output. The Bot _- out signal corresponds to the Bot _- in signal or a dummy signal described later. In addition, the restart circuit 11 outputs a restart signal by a timer at the time of start-up when the Bot _- out signal is not generated.
The one-shot circuit 9 is triggered when the Bot _- out signal or the restart signal rises, and forms a Set signal, for example, a pulse signal having a width of 300 ns. The set-priority flip-flop 13 is set by the Set signal. To do. Accordingly, since the Drv signal of H level is output from the flip-flop 13, the drive circuit 15 outputs a drive signal based on this Drv signal from the output terminal OUT, and turns on the switching element Tr1.

As a result, the primary winding P1 of the transformer T, which is an inductor, starts to accumulate energy. At this time, the voltage across the resistor Rs connected in series to the switching element Tr1, that is, the voltage corresponding to the current flowing through the switching element Tr1, is input to one input terminal of the comparator 17 via the IS terminal. A voltage obtained by dividing the output voltage Vo by Ro1 and Ro2 is input to the feedback circuit 18.
The feedback circuit 18 calculates a difference between an input voltage and a reference voltage (not shown), and outputs a feedback signal (error signal) corresponding to the difference to the other input terminal of the comparator 17 via the FB terminal. The feedback signal represents the magnitude of the load, and the value becomes lower as the load is lighter.

  The comparator 17 resets the flip-flop 13 by outputting a reset signal when the voltage across the resistor Rs exceeds the voltage value of the feedback signal. When the flip-flop 13 is reset, the Drv signal becomes L (Low) level, so that the switching element Tr1 is turned off. As a result, the energy accumulated in the primary winding P1 of the transformer T is on the secondary winding S1 side. To be released. During this energy release period, a constant voltage is applied to the switching element Tr1.

When the release of the energy stored in the primary winding P1 is completed, the resonance circuit including the resonance capacitor Cr and the primary winding P1 starts a resonance operation.
FIG. 2 exemplifies the waveform of the drain-source voltage Vds of the switching element Tr1 when the resonant circuit is performing a resonant operation. However, this waveform is for bottom skip control.
The auxiliary winding P2 of the transformer T generates a voltage similar to the resonance oscillation voltage of the resonance circuit, and inputs this voltage to the bottom detection circuit 3 via the ZCD terminal. The voltage generated in the auxiliary winding P2 is a voltage that changes around 0V. The voltage 0 V generated in the auxiliary winding P2 corresponds to the primary side input voltage value VIN shown in FIG.

FIG. 6 shows an example of the bottom detection circuit 3. The bottom detection circuit 3 includes a comparator 61 that compares a voltage input from the ZCD terminal with a reference voltage VL _- zcd (for example, 50 mV) or VH _- zcd (for example, 150 mV). The reference voltages VL _- zcd and VH _- zcd are input to the comparator 61 via the transistors Tr7 and Tr8, respectively. The transistor Tr7 is turned on / off by a signal obtained by inverting the output signal of the comparator 61 by the inverter 59, and the transistor Tr8 is turned on / off by the output signal of the comparator 61.

The comparator 61 has an H level Bot ₋ that indicates that the input voltage has become the bottom when the input voltage from the ZCD terminal becomes lower than the reference voltage VL ₋ zcd (set to a voltage close to 0V). The in signal is output, and then the L-level Bot _- in signal is output when the input voltage exceeds the reference voltage VH _- zcd. According to the bottom detection circuit 3 having such a function as a hysteresis comparator, malfunction due to noise is prevented.
If the upper side of the resonance vibration waveform becomes VH ₋ zcd (150 mV) or less due to attenuation of the resonance waveform accompanying the increase in the number of occurrences of the bottom (see FIG. 13), the bottom detection circuit 3 stops the bottom detection operation.

The bottom detection circuit 3 detects the bottom of the input voltage as described above, and outputs an H-level Bot _- in signal, which is a pulse signal having a pulse width of about 200 ns, to the bottom control circuit 5.
The Bot _- in signal is actually generated at a timing 90 degrees ahead of the bottom of the resonance waveform shown in FIG. Therefore, a delay circuit (not shown) that delays the voltage input to the ZCD terminal (for example, composed of a capacitor and a resistor) is connected to the ZCD terminal so that the bottom timing of the resonance waveform and the Bot _- in signal The generation timing (turn-on timing of the switching element Tr1) is matched.

The bottom control circuit 5 outputs an H level Bot _- out signal based on the H level Bot _- in signal output from the bottom detection circuit 3. That is, the bottom control circuit 5 outputs the first Bot _- in signal as a Bot _- out signal when the load is heavy, and outputs the second and subsequent Bot _- in signals as the Bot _- out signal when the load is light (bottom skip). ). Also, a dummy signal described later is generated, and a Bot _- out signal based on this dummy signal is also output according to the situation.
When the H-level Bot _- out signal is output from the bottom control circuit 5, the switching Tr1 is turned on as described above.
When the Bot _- out signal is not output from the bottom control circuit 5, the restart circuit outputs a signal to the one-shot circuit 9 at the time when the set time (about 30 μs) by the timer has elapsed, and restarts switching.

Hereinafter, the bottom control circuit 5 will be described in more detail with reference to FIG. Note that the Reset signal shown in FIG. 3 is a reset signal applied at startup.
The bottom control circuit 5 is configured to set the upper limit and the lower limit of the switching frequency by the Vcont voltage. The Vcont voltage as a control signal is input to the variable constant current source 19 and changes the value of the constant current Iosc1 for charging the timing capacitor Ct1. The value of the constant current Iosc1 becomes smaller as the Vcont voltage is lower.
In the present embodiment, a feedback signal input to the FB terminal in FIG. 1 is used as the Vcont voltage. As described above, this feedback signal represents the size of the load, and the lighter the load, the lower the voltage.

FIG. 4 shows a configuration example of the variable constant current source 19. Explaining from the rear stage side, the variable constant current source 19 includes a constant current circuit 57 (comprising transistors Tr4 and Tr5) including a current mirror. The reference current in the constant current circuit 57 is determined by controlling the terminal voltage Vt of the current detection resistor Rt to a constant voltage value by the buffer-connected operational amplifier 55 and the transistor Tr6.
The operational amplifier 55 has two + input terminals, and is configured to preferentially input a lower voltage among the voltages input to these input terminals. In the case of a normal load, a voltage V ₋ fmax (for example, 2.5 V) corresponding to the maximum switching frequency is preferentially input to the first + input terminal. At this time, the constant current output from the constant current circuit 57 is Iosc1 = 2.5 V / Rt.

  Another operational amplifier 53 is non-inverting amplified and connected. When the Vcont voltage is input to the + input terminal of the operational amplifier 53, the output voltage Vop1 is Vop1 = (Vcont−Voffset) × (Ri + Rf) / Ri. Here, Voffset is an offset voltage, Ri is an input resistance, and Rf is a feedback resistance. Since the operational amplifier 53 cannot output a negative voltage, the lower limit value of the output voltage Vop1 is 0 V (GND voltage).

The resistors R1 and R2 divide the difference between the stabilized reference voltage Vref (for example, 5 V) and the output voltage Vop1 of the operational amplifier 53, and the divided voltage (to be precise, the difference is divided). The voltage obtained by adding the voltage and the voltage Vop1) is input to the second + input terminal of the operational amplifier 55.
In this way, if the divided voltage is input to the second + input terminal, even if the output voltage Vop1 of the operational amplifier 53 is 0 V which is the lowest, Vref × R2 / ( R1 + R2) voltage is input.

In the present embodiment, the divided voltage is set to 2.5 V with respect to the input of the Vcont voltage at the point where the reduction of the switching frequency starts. Therefore, as the Vcont voltage corresponding to a lighter load is input, the constant current Iosc1 that defines a switching frequency lower than the maximum switching frequency is set.
The constant current Iosc1 is changed by the Vcont voltage until it reaches a magnitude corresponding to the lowest switching frequency (for example, 25 kHz), and as a result, a switching frequency change characteristic (similar to that) illustrated in FIG. 5 is realized. .

In FIG. 3, the one-shot circuit 23 outputs a one-shot pulse signal having a width of about 200 ns shown in FIG. 8 when the Drv signal rises, that is, when the switching element Tr1 shown in FIG. 1 is turned on. This one-shot pulse signal turns on the transistor Tr2 connected in parallel to the timing capacitor Ct1. As a result, the timing capacitor Ct1 is discharged and the voltage between both ends thereof is reset to 0V.
Thereafter, the timing capacitor Ct1 is charged by the constant current Iosc1 supplied from the variable constant current source 19, and as a result, as shown in FIG. 8, the timing capacitor Ct1 has an increasing gradient corresponding to the magnitude of the charging current Iosc1. The terminal voltage rises.

The comparator 21 compares the terminal voltage of the timing capacitor Ct1 with the reference voltage Vref1, and is at the H level until the terminal voltage reaches the reference voltage Vref1, that is, while the time (cycle) corresponding to the upper limit switching frequency elapses. Vfhi signal is output (the period during which the H level vfhi signal is output is defined as the first reference time), and when the time corresponding to the upper limit frequency has elapsed, the L level vfhi signal is output.
As described above, the variable constant current source 19, the timing capacitor Ct1, the comparator 21, and the transistor Tr2 constitute a timer 20 that measures time (first reference time) corresponding to the upper limit switching frequency.

The transistor Tr3 is connected in parallel to the other timing capacitor Ct2. The transistor Tr3 is turned on while the comparator 21 outputs the H level Vfhi signal, and fixes the terminal voltage of the timing capacitor Ct2 to 0V.
When the time corresponding to the period of the upper limit frequency (first reference time) elapses and the L level Vfhi signal is output from the comparator 21, the transistor Tr3 is turned off. Thereby, as shown in FIG. 8, charging of the timing capacitor Ct2 by the constant current Idly from the variable constant current source 25 is started. The comparator 27 compares the terminal voltage of the timing capacitor Ct2 that rises with charging with the reference voltage Vref2, and outputs an H-level Vflo signal when the terminal voltage reaches the reference voltage Vref2.

The charging period until the terminal voltage of the timing capacitor Ct2 reaches the reference voltage Vref2 is a hysteresis width (hysteresis time) when determining the switching period (see FIG. 8). The sum of the first reference time and the hysteresis time is set as the second reference time.
This hysteresis width is set assuming that the bottom skip number does not return to the original value in the next switching cycle when the bottom skip number is switched.
That is, when the assumed resonance period is 1 μs to 1.5 μs, for example, the hysteresis width is set to 2 μs. In this way, even if the switching period is increased by one resonance period, the switching period does not overlap during the period when the Vflo signal is at the H level, so that it is possible to prevent the bottom skip from being restored.

As described above, the variable constant current source 25, the timing capacitor Ct2, the comparator 27, and the transistor Tr3 constitute a timer (hysteresis timer) 26 that measures the hysteresis width.
As a result, when the switching period is shorter than the first reference time, the Vfhi signal becomes H level, and when it is longer than the second reference time, the Vflo signal becomes H level.

The D flip-flop (hereinafter abbreviated as DFF) 29 and DFF 31 are at the rising edge of the Drv signal, that is, at the timing when the switching element Tr1 shown in FIG. Read Vfhi and Vflo signals.
At this time, if the Vfhi signal is H level, the DFF 29 outputs an H level count-up signal to the subsequent up / down counter 33, and if the Vflo signal is H level, the DFF 31 outputs the H level to the up / down counter 33. Countdown signal is output.

The up / down counter 33 stores the number of bottom skips until the switching element Tr1 is turned on as a set value. The up / down counter 33 inputs the Drvb signal obtained by inverting the Drv signal by the inverter 35 to the clock input terminal, and at the timing when the Drvb signal rises (timing when the Drv signal falls), that is, the upper switching element Tr1 It operates as follows at the turn-off timing.
That is, if the count-up signal is H level, it is counted up by one, and if the count-down signal is H level, it is counted down by one. If both the count-up signal and the count-down signal are at the L level, the previous state is maintained.

By the way, in the control method for counting the number of bottom skips, as described above with reference to FIG. 13, the normal bottom detection circuit reduces the number of bottoms necessary for the attenuation of the resonance waveform when the switching frequency becomes low. It cannot be detected.
The dummy signal generation circuit 37 is provided to cope with such a situation. As shown in FIG. 6, the dummy signal generation circuit 37 includes an oscillator 65, a reset set flip-flop (hereinafter abbreviated as RSFF) 67, and a DFF 73. When the Bot _- in signal and the Drv signal from the bottom detection circuit 3 are both at the L level, the EnbL terminal of the oscillator 65 connected to the output terminal of the OR circuit 63 is at the L level.

  The oscillator 65 has a configuration as illustrated in FIG. In this oscillator 65, a constant current Id3 set by the constant current source 650 (actually, a current obtained by amplifying Id3 by the mirror ratio of the current mirror circuit (proportional to Id3) flows. A current Id3 (the same applies hereinafter) flows through the transistor Tr10 and the transistor Tr11 by a current mirror circuit using the drain of the transistor Tr9 as an input. Of the transistors Tr12 to Tr15 connected in series, the transistor Tr12 forms a current mirror combined with the transistor Tr10, and the transistor Tr15 forms a current mirror combined with the transistor Tr11.

When the EnbL terminal becomes H level, the transistor Tr16 is turned on, so that the capacitor Ct3 is discharged and its terminal voltage is fixed at 0V. As a result, the output terminal of the comparator 651 becomes L level, so that the transistor Tr13 is turned on and the transistor Tr18 is turned on via the inverter 652. Transistors Tr14 and Tr17 are turned off. When the transistor Tr18 is turned on, the reference voltage Vref3 is input to one input terminal of the comparator 651.
After that, when the EnbL terminal becomes L level, charging of the capacitor Ct3 by the constant current Id3 is started via the transistors Tr12 and Tr13, so that the terminal voltage of the capacitor Ct3 increases.
The comparator 651 inputs the terminal voltage of the capacitor Ct3 to the other input terminal, and when the terminal voltage rises to the reference voltage Vref3, the output terminal of the comparator 651 becomes H level.

  When the output terminal of the comparator 651 becomes H level, the transistor Tr14 is turned on. Further, the transistor Tr13 is turned off. As a result, the discharge of the capacitor Ct3 by the constant current Id3 is started via the transistors Tr14 and Tr15, and the terminal voltage of the capacitor Ct3 decreases. When the output terminal of the comparator 651 becomes H level, the transistor Tr17 is turned on and the transistor Tr18 is turned off, so that the reference voltage Vref4 (for example, 0.1 V) lower than the reference voltage Vref3 is applied to the other input terminal of the operational amplifier 651. Is entered. Therefore, when the terminal voltage of the capacitor Ct3 falls to the reference voltage Vref4, the output terminal of the operational amplifier 651 becomes L level.

Thereafter, while the EnbL terminal is at the L level, the same operation as described above is repeated.
FIG. 7 shows a waveform example of the terminal voltage of the capacitor Ct3 and the waveform of the oscillation signal (dummy signal) output from the output terminal Osc of the oscillator 65. As shown in the figure, the oscillator 65 outputs the first H level signal after 2 μs has elapsed from the time when the EnbL terminal becomes L level, and then outputs the H level signal at a cycle of 4 μs.

When the Bot _- in signal or Drv signal from the bottom detection circuit 3 becomes H level, that is, when the EnbL terminal becomes H level, the transistor Tr16 shown in FIG. 7 is turned on, so that the capacitor Ct3 is discharged and its terminal The voltage is fixed at 0V.
The charging and discharging period (2 μs each) of the capacitor Ct3 by the constant current Id3 is set longer than the resonance period. That is, the capacitor Ct3, the constant current Id3, and the comparator 651 constitute a timer that measures a predetermined time longer than the resonance period.
As described above, the dummy signal formed by the charging and discharging operations of the capacitor Ct3 is output when the EnbL terminal becomes L level, that is, when the Drv signal and the Bottom-in signal Bot _- in signal become L level. .

When an H level signal (dummy signal) is output from the output terminal Osc of the oscillator 65, the RSFF 67 shown in FIG. 6 is set and its Q output terminal becomes H level. The DFF 73 reads the H level at the rising timing of the Drv signal, and outputs an H level Dmode signal from its Q output terminal. Thereafter, the RSFF 67 is reset by a Drv signal input via a delay circuit composed of inverters 69 and 71 connected in two stages.
The Dmode signal is at the H level at a light load when a dummy signal is output from the Osc terminal of the oscillator 65. When the load increases and the switching element Tr1 shown in FIG. 1 is turned on without operating the dummy signal generation circuit 37, the Dmode signal returns to the L level.

As shown in FIG. 3, the H-level Bot _- in signal output from the bottom detection circuit 3 or the H-level dummy signal output from the dummy signal generation circuit 37 is input to the clock of the counter 41 via the OR circuit 39. Input to terminal CK.
The counter 41 is reset at the timing when the drv signal rises, that is, at the timing when the switching element Tr1 is turned on, and then counts the signal output from the OR circuit 39.

The comparator 43 is connected to the output terminals of the two counters 33 and 41. The comparator 43 is reset at a timing when the switching element Tr1 is turned off and outputs a Mask signal (H level). Since the Mask signal is inverted by the inverter 45 and input to the AND circuit 47, the signal bottom Bottom _- in signal (H level) or the dummy signal (H level) output from the OR circuit 39 passes through the AND circuit 47. Mask.

On the other hand, the comparator 43 compares the output values of the counters 33 and 41, that is, compares the number of bottoms set in the counter 33 with the number of bottoms detected by the counter 41. Invert to level. The AND circuit 47 passes the Bot _- in signal (H level) and the dummy signal (H level) while the Mask signal is maintained at the L level, and outputs it as a Bot _- out signal. This Bot _- out signal becomes a turn-on trigger signal in the next cycle.

When the actual resonance vibration is attenuated and the H-level Bot _- in signal is not output, the counter 41 advances the bottom count using an H-level dummy signal indicating a pseudo bottom. The switching frequency can be lowered sufficiently. Hereinafter, the switching frequency lowering effect by the dummy signal will be described in detail.

  First, a case where no dummy signal is used will be described. In this case, when the bottom skip operation is executed at the time of light load, as shown in FIG. 2, the increase in the resonance period accompanying the bottom skip (usually 1 μs to 2 μs) is added and the switching frequency is lowered. Become. However, as the switching period becomes longer, the frequency reduction rate becomes lower as the number of bottom skips increases by one.

  That is, FIG. 9 shows an example of the change in switching frequency including the case where the number of bottom skips increases from 0 to 15 under the condition of the resonance period of 1.5 μs. The horizontal axis is output power (representing the size of the load). When the number of bottom skips is 10 or more, the switching frequency is about 50 kHz (period is 20 μs). Even if the number of skips increases by one, the switching frequency decreases only to 46.5 kHz (the period is 21.5 μs), which indicates that the frequency decrease rate becomes lower as the number of bottom skips increases by one. Yes. In the example of FIG. 9, even when the number of bottom skips is 15, which is the maximum, the switching frequency is reduced only to about 37 kHz.

On the other hand, according to the above embodiment including the dummy signal generation circuit 37, the period of the dummy signal is set to be longer than the normal resonance period (1 μs to 2 μs). The switching frequency can be sufficiently lowered using this dummy signal.
FIG. 10 shows an example in which the turn-on is delayed based on the actual resonance period of 1.5 μs until the seventh bottom, and then the turn-on is delayed by the dummy signal. In this case, the first dummy signal corresponding to the eighth bottom signal is delayed by 2 μs from the seventh bottom signal, and the dummy signals corresponding to the subsequent bottom signals are further delayed by 4 μs. . As a result, in this example, when the maximum number of bottom skips is set to 15, the switching frequency can be lowered to about 20 kHz.

In FIG. 10, when the load decreases from the 130 W side, the switching period is the first corresponding to the period of the upper limit switching frequency set by the Fmax timer 20 of FIG. 3 based on the voltage (Vcont) of the FB terminal at that time. When the time is shorter than the reference time, the up / down counter 33 is up-counted to increase the skip skip, and as a result, the switching frequency is lowered as shown by the solid line.
On the contrary, when the load increases, the lower limit switching frequency is based on the second reference time (the lower limit switching frequency period) obtained by adding the time set by the hysteresis timer 26 shown in FIG. 3 to the period of the upper limit switching frequency. Is set. If the switching period is longer than the second reference time, the up / down counter 33 counts down and decreases the number of bottom skips, so that the switching frequency increases (see the dotted line in FIG. 10).

  At this time, the hysteresis timer 26 receives the signal D1-D4 output from the output terminals Q1-Q4 of the up / down counter 33 for setting the number of bottom skips or the signal Dm from the Dmode terminal indicating whether the dummy signal is in use. The constant current Idly for charging the capacitor Ct2 is changed by inputting the variable constant current source 25 as a control signal. As a result, a hysteresis width corresponding to the bottom skip state is set.

If the hysteresis width is too narrow, it becomes unstable when switching between bottom skips (hunting occurs). If the setting is too wide, the difference between the switching frequency when the load decreases and the switching frequency when the load increases increases, resulting in a larger variation in operating frequency, resulting in large variations in efficiency. Become.
However, if the variable constant current source 25 is controlled by the signal D1-D4 or Dm as described above, the hysteresis width is optimized in accordance with the bottom skip situation, and thus the above problem does not occur.

When the dummy signal is valid, the change in the resonance period due to the switching of the number of bottom skips is large, so it is necessary to set the hysteresis width long in order to stabilize the operation. Therefore, the hysteresis width is
Hysteresis width = capacitance of capacitor Ct2
× Reference voltage Vref2 / charging current Idly
Based on this relationship, the signal D1-D4 or Dm, which is a digital signal, is decoded and optimally set by switching the capacitance value of the capacitor Ct2, the reference voltage Vref2, or the charging current Idly.

When the counter 41 starts counting the dummy signal, the timing at which the switching element Tr1 is turned on naturally deviates from the bottom generation timing of the resonance waveform, but when the resonance waveform is attenuated, the switching element Since the drain voltage of Tr1 is in a constant voltage state substantially equal to the value VIN of the input voltage Vi (see FIGS. 1 and 2), the switching loss does not change so much even if the turn-on timing of the switching element Tr1 changes.
The reduction effect of the switching loss by reducing the switching frequency, that is, by reducing the number of times of switching of the switching element Tr1, is larger than that.

  FIG. 11 shows a quasi-resonant switching power supply device according to another embodiment of the present invention. In the above embodiment, the dummy signal is used after the bottom cannot be detected at light load. On the other hand, in the present embodiment, the number of bottom detections is set in advance to a number that can be detected almost certainly (for example, 7 times), and if a bottom number exceeding that number is set, a dummy signal is forcibly used. And configured to lower the frequency at light load.

That is, this quasi-resonant switching power supply device includes switch elements 49 and 51 instead of the OR circuit 39 shown in FIG. In the switching element 49 operating in negative logic, when the data Dm output from the Q4 terminal of the up / down counter 33 is at L level, that is, the bottom skip number is set to 7 or less in the up / down counter 33. At this time, the signal is turned on and an H-level Bot _- in signal is output to the counter 41 and the AND circuit 47.
On the other hand, the switch element 51 operating in the positive logic is configured such that when the data Dm output from the Q4 terminal of the up / down counter 33 is at the H level, that is, 8 or more bottom skips are set in the up / down counter 33. Is turned on to output an H level dummy signal to the counter 41 and the AND circuit 47.

If the signal of the output terminal of the counter 41 (decoded signal) is input to the control terminals of the switch elements 49 and 51 instead of the data Dm output from the Q4 terminal of the up / down counter 33, it is set in advance. It is possible to cause the H-level Bot _- in signal to be counted up to the determined number and to count the dummy signal thereafter. For example, when the signal of the output terminal Q4 of the counter 41 is configured to be input to the control terminals of the switch elements 49 and 51, up to seven H-level bot _- in signals are counted, and thereafter dummy signals are counted. Become.

DESCRIPTION OF SYMBOLS 1 Switching control circuit 3 Bottom detection circuit 5 Bottom control circuit 7, 39, 63 OR circuit 9, 23 One shot circuit 11 Restart circuit 13 Flip-flop 15 Drive circuit 17, 21, 27, 43, 61, 651 Comparator 18 Feedback circuit 19, 25 Variable constant current source 20, 26 Timer 23, 35 One shot circuit 29, 31, 73 D flip-flop (DFF)
33 Up / Down Counter 37 Dummy Signal Generation Circuit 35, 45, 59, 69, 71, 652 Inverter 41 Counter 47 AND Circuit 53, 55 Operational Amplifier 57 Constant Current Circuit 65 Oscillator 67 Reset Set Flip-Flop (RSFF)
T transformer P1 primary winding S1 secondary winding P2 auxiliary winding Tr1 switching element Tr2 to Tr18 transistor Ci, Co smoothing capacitor Cr resonance capacitor Ct1, Ct2 timing capacitor Ct3 capacitor D1 diode Ti input terminal To output terminal Rs, Rt Current detection resistor Ro1, Ro2, R1, R2 Voltage dividing resistor Ri Input resistor Rf Feedback resistor

Claims (6)

It has a bottom detection circuit that detects the bottom of the resonance waveform and outputs a bottom detection signal,
A control circuit for a quasi-resonant switching power supply device that counts the number of bottoms detected by the bottom detection circuit at a light load and determines a switching cycle,
A dummy signal that replaces the bottom detection signal when the bottom detection circuit becomes unable to detect the bottom, the number of bottoms to be counted is a predetermined number, or the number of bottoms detected by the bottom detection circuit reaches a predetermined number A control circuit for a quasi-resonant switching power supply device, characterized in that A bottom detection circuit that detects the bottom of the resonance waveform and outputs a bottom detection signal;
A first counter for setting the number of bottom skips;
A second counter for counting the number of bottoms;
A comparator that outputs a match signal when the count value of the first counter matches the count value of the second counter;
A control circuit of a quasi-resonant switching power supply device for switching the switching element based on the bottom detection signal after the comparator outputs a coincidence signal,
When the bottom cannot be detected due to attenuation of the resonance waveform, a dummy signal generation circuit is provided that generates a dummy signal instead of the bottom detection signal. When the bottom cannot be detected, the second counter A control circuit for a quasi-resonant switching power supply device, wherein the dummy signal is counted. A bottom detection circuit that detects the bottom of the resonance waveform and outputs a bottom detection signal;
A first counter for setting the number of bottom skips;
A second counter for counting the number of bottoms;
A comparator that outputs a match signal when the count value of the first counter matches the count value of the second counter;
A control circuit of a quasi-resonant switching power supply device for switching the switching element based on the bottom detection signal after the comparator outputs a coincidence signal,
A dummy signal generation circuit for generating a dummy signal in place of the bottom detection signal is provided, and when the value set in the first counter exceeds a predetermined value or the bottom of the resonance waveform exceeds a preset number of times, the first signal is generated. A control circuit for a quasi-resonant switching power supply apparatus, wherein the counter of 2 counts the dummy signal. The first counter comprises an up / down counter;
A timer circuit for generating a first reference time for changing the switching frequency compared to the switching period and a second reference time longer than the first reference voltage;
When the switching period is shorter than the first reference time, the first counter is up-counted, and when the switching period is longer than the second reference time, the first counter is down-counted. The control circuit of the quasi-resonant switching power supply device according to claim 2 or 3.   5. The control circuit for a quasi-resonant switching power supply device according to claim 1, wherein a period of the dummy signal is set longer than a period of the resonance waveform. 6.   The timer circuit uses a signal indicating whether the output signal of the first counter or the dummy signal is used as a time from the first reference time to the second reference time. The control circuit of the quasi-resonant switching power supply device according to claim 4, wherein the control circuit is configured to be variable using the control circuit.

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