JP2021026135A - Display divice and inspection method - Google Patents

Abstract

To provide a technique capable of further improving in an inspection method of a display device.SOLUTION: The display device having a display panel of active matrix system includes: a plurality of source lines; a plurality of gate lines; a gate drive circuit that sequentially supplies a gate drive signal to a plurality of gate lines; and a failure detection unit that detects a failure on the plurality of gate lines based on the voltage on the source line to which an input signal is supplied synchronizing with the supply of the gate drive signal by the gate drive circuit.SELECTED DRAWING: Figure 2

Description

The present disclosure relates to a display device and a method for inspecting the display device.

Conventionally, as an inspection method of a liquid crystal display device, a method of performing a lighting inspection for each pixel of a liquid crystal panel in a manufacturing process of the liquid crystal display device is known.

Japanese Unexamined Patent Publication No. 2005-122209 International Publication No. 2018/079636

Further improvement is required for the inspection method of the display device.

In order to solve the above problems, the display device according to the embodiment of the present disclosure is a display device having an active matrix type display panel, and has a plurality of source lines, a plurality of gate lines, and a plurality of gate lines. On the other hand, an abnormality of a plurality of gate lines is detected based on the voltage of the gate drive circuit that sequentially supplies the gate drive signal and the voltage of the source line to which the input signal is supplied in synchronization with the supply of the gate drive signal by the gate drive circuit. It is provided with a failure detection unit.

The inspection method of the embodiment of the present disclosure is an inspection method of a display device including an active matrix type display panel having a plurality of source lines and a plurality of gate lines, and is a gate drive signal for a plurality of gate lines. Are sequentially supplied, and an abnormality of a plurality of gate lines is detected based on the voltage of the source line to which the input signal is supplied in synchronization with the supply of the gate drive signal.

Further improvement can be realized by the above aspect.

FIG. 1 is a diagram showing an example of a display device 10 according to the first embodiment. FIG. 2 is a diagram showing an example of the configuration of the active matrix substrate 1 and the control device 100. FIG. 3 is a timing chart showing an example of the operation of the mode for displaying the image of the gate drive circuit 130. FIG. 4 is a timing chart showing an example of the operation of the mode for displaying the image of the source drive circuit 120. FIG. 5 is a diagram for explaining the timing at which the gate drive signal is supplied to the gate line 30 and the timing at which the source drive signal is supplied to the source line 20 in the mode for displaying an image. FIG. 6 is a timing chart showing an example of the operation of the source drive circuit 120 in the first operation mode. FIG. 7 is a flowchart showing an example of the operation of the failure detection unit 160 in the first operation mode. FIG. 8 is a diagram showing a specific example in which the failure detection unit 160 detects a short-circuit abnormality of the source line 20. FIG. 9 is a flowchart showing an example of the operation of the failure detection unit 160 in the second operation mode. FIG. 10 is a diagram showing a specific example in which the failure detection unit 160 detects an open abnormality of the source line 20. FIG. 11 is a timing chart showing an example of the operation of the gate drive circuit 130 and the source drive circuit 120 in the third operation mode. FIG. 12 is a flowchart showing an example of the operation of the failure detection unit 160 in the third operation mode. FIG. 13 is a diagram showing a specific example in which the failure detection unit 160 detects a short-circuit abnormality of the gate wire 30. FIG. 14 is a diagram showing a specific example in which the failure detection unit 160 detects an open abnormality of the gate wire 30. FIG. 15 is a diagram showing an example of the configuration of the active matrix substrate 1 and the control device of the second embodiment.

[Findings underlying this disclosure]
Before concretely explaining the embodiments of the present disclosure, the findings underlying the present disclosure will be described. As described above, as an inspection method for the liquid crystal display device, for example, the method shown in Patent Document 1 is known. Patent Document 1 describes a method of performing a lighting inspection for each pixel of a liquid crystal panel before mounting a drive circuit (driver IC (integrated circuit)) on the liquid crystal panel in a manufacturing process of an active matrix type liquid crystal display device. Has been done. The method of Patent Document 1 is premised on inspection in the manufacturing process of the liquid crystal display device, and cannot be applied after the driver IC is mounted on the liquid crystal panel.

On the other hand, in recent years, liquid crystal display devices have been widely used as in-vehicle display devices. Vehicle-mounted display devices include, for example, a center display that displays map information and the like, and a meter display device that displays information on instruments such as a speedometer. Such an in-vehicle display device is also used for displaying a warning message for notifying an abnormality of a device mounted on a vehicle (for example, an in-vehicle device such as a brake or an airbag).

If the display device mounted on the vehicle breaks down, the warning message as described above cannot be displayed. Therefore, from the viewpoint of fail-safe, a function of detecting a failure of the display device after the display device is mounted on the vehicle is required.

In view of the above, in each embodiment of the present disclosure, a display device having an active matrix type display panel and inspecting the display panel of the own device and an inspection method will be described. Specifically, the display device and the inspection method detect a short-circuit abnormality (short-circuit) and an open abnormality (disconnection) of the gate wire of the display panel. Further, a short-circuit abnormality (short-circuit) and an open abnormality (disconnection) of the source line of the display panel are detected. In each embodiment of the present disclosure, a liquid crystal panel will be described as an example of the display panel, but the present invention is not limited to this, and the display panel may be driven by an active matrix method.

Hereinafter, each embodiment of the present disclosure will be described in detail with reference to the drawings.

[Embodiment 1]
FIG. 1 is a diagram showing an example of a display device 10 according to the first embodiment. The display device 10 is applied to, for example, a display device mounted on a vehicle, and displays an abnormality warning of instruments and an in-vehicle device.

The display device 10 includes a liquid crystal panel 11, a backlight module 12, and a control device 100.

The liquid crystal panel 11 includes an active matrix substrate 1, an opposing substrate 2 arranged to face the active matrix substrate 1, a liquid crystal layer 3 sealed between the active matrix substrate 1 and the opposing substrate 2, and a first. It has a polarizing plate 4 and a second polarizing plate 5.

The active matrix substrate 1 and the opposing substrate 2 are, for example, substrates made of glass. The detailed configuration of the active matrix substrate 1 will be described later. The facing substrate 2 has a facing electrode, a color filter, and the like. The counter electrode is also referred to as a common electrode.

The first polarizing plate 4 is arranged on the back surface side of the active matrix substrate 1. The second polarizing plate 5 is arranged on the display surface side of the active matrix substrate 1.

The backlight module 12 includes one or more light sources and irradiates the liquid crystal panel 11 with light.
The control device 100 controls the operation of the display device 10. For example, the control device 100 controls the active matrix substrate 1. The detailed configuration of the control device 100 will be described later.

FIG. 2 is a diagram showing an example of the configuration of the active matrix substrate 1 and the control device 100. The active matrix substrate 1 has a source line 20 (data line), a gate line 30 (scanning line), a pixel electrode 40, a switching element 50, a signal line 60, a switching element 70, and a control signal line 80. The control device 100 includes a control unit 110, a source drive circuit 120, a gate drive circuit 130, an inspection signal line 140, a voltage detection unit 150, and a failure detection unit 160.

First, the configuration of the active matrix substrate 1 will be described. The active matrix substrate 1 is, for example, a substrate for a VGA panel (640 × 480 pixels). The source line 20 has a plurality of source lines S1 to S1920 extending in parallel in the vertical direction (column direction) of FIG. In the following description, when it is not necessary to distinguish the source lines S1 to S1920 from each other, it is simply referred to as "source line 20". The gate line 30 has a plurality of gate lines G1 to G480 extending in parallel in the lateral direction (row direction) of FIG. In the following description, when it is not necessary to distinguish the gate lines G1 to G480 from each other, it is simply referred to as "gate line 30". Each area partitioned by the source line 20 and the gate line 30 is a sub-pixel area. Each sub-pixel region corresponds to any hue of RGB. One pixel region is formed by three sub-pixel regions (RGB sub-pixel regions) adjacent to the active matrix substrate 1 in FIG. 2 in the horizontal direction (direction in which the gate line extends). The pixel electrode 40 is arranged corresponding to the sub-pixel region.

A plurality of switching elements 50 are arranged corresponding to the intersections of the plurality of gate lines 30 and the plurality of source lines 20. Each switching element 50 is a thin film transistor (TFT) having a gate electrode, a source electrode, and a drain electrode. The gate electrode of the switching element 50 is connected to the gate wire 30, the source electrode is connected to the source wire 20, and the drain electrode is connected to one end of the pixel electrode 40. The other end of the pixel electrode 40 is connected to the counter electrode included in the counter substrate 2 via the liquid crystal layer 3. Here, one pixel (more specifically, a sub-pixel) is formed by a combination of one pixel electrode 40, a counter electrode, and a liquid crystal layer 3 sandwiched between the two. That is, it can be considered that a plurality of pixels are arranged corresponding to the intersections of the plurality of gate lines 30 and the plurality of source lines 20.

As shown in FIG. 2, the signal line 60 has a total of 6 wires (DR1, DR2, DG1, DG2, DB1, DB2), two for each RGB hue. In this example, DR1 and DR2 are wires corresponding to the hue of R (red), DG1 and DG2 are wires corresponding to the hue of G (green), and DB1 and DB2 are wires corresponding to the hue of B (blue). Wiring corresponding to hue. One end of each of these six wiress is connected to the source line 20 via a switching element 102. Specifically, each of the source lines S1 to S1920 is connected to one of the wirings corresponding to the hue of the sub-pixel electrode among these six wirings via the switching element 70. The other end of each of these six wires is connected to the analog ground terminal.

The signal line 60 may be used for a lighting inspection in the manufacturing process of the display device 10. For example, it may be used for a lighting inspection performed before the driver IC or the like is mounted on the liquid crystal panel 11. By inputting an inspection signal for each of the RGB hues to the signal line 60, a lighting inspection can be performed for each of the RGB hues.

The switching element 70 is a switching element for switching connection / non-connection between the source line 20 and the signal line 60, and is provided for each combination of the source line 20 and the signal line 60. The switching element 70 is a transistor having a gate electrode, a source electrode, and a drain electrode. The gate electrode of the switching element 70 is connected to the control signal line 80, the drain electrode is connected to the signal line 60, and the source electrode is connected to the source line 20. The switching element 70 is controlled to an on state or an off state based on a control signal supplied via the control signal line 80. For example, when the voltage level of the control signal is "LOW", the switching element 70 is turned off, and when the voltage level of the control signal is "HIGH", the switching element 70 is turned on.

A control signal for controlling the on state and the off state of the switching element 70 is supplied to the control signal line 80.

Next, the configuration of the control device 100 will be described. As described above, the control device 100 includes a control unit 110, a source drive circuit 120, a gate drive circuit 130, an inspection signal line 140, a voltage detection unit 150, and a failure detection unit 160.

The control unit 110 controls the operations of the source drive circuit 120, the gate drive circuit 130, the voltage detection unit 150, the failure detection unit 160, and the like. Specifically, a mode for displaying an image, a mode for detecting a short-circuit abnormality of the source line 20 (first operation mode), a mode for detecting an open abnormality of the source line 20 (second operation mode), and One of the four modes (third operation mode) for detecting a short-circuit abnormality and an open abnormality of the gate wire 30 is selected. The control unit 110 selects, for example, a first operation mode, a second operation mode, or a third operation mode at a preset timing, and otherwise selects a mode for displaying an image. The mode selection method is not limited to this, and may be, for example, a form in which the mode is selected according to the input of the user. Then, the control unit 110 controls the operations of the source drive circuit 120, the gate drive circuit 130, the voltage detection unit 150, the failure detection unit 160, and the like according to the selected mode.

More specifically, the control unit 110 detects an image display mode, a mode for detecting an abnormality in the source line 20 (first operation mode, a second operation mode), and an abnormality in the gate line 30. The source drive circuit 120 is operated according to each of the four modes of the mode (third mode).

Further, when the control unit 110 selects a mode for displaying an image or a mode for detecting an abnormality in the gate line 30 (third mode), the control unit 110 operates the gate drive circuit 130 according to the selected mode.

Further, the control unit 110 has three modes: a mode for detecting an abnormality in the source line 20 (first operation mode, a second operation mode) and a mode for detecting an abnormality in the gate line 30 (third mode). When any of the above is selected, the voltage detection unit 150 and the failure detection unit 160 are operated according to the selected mode.

Further, when the control unit 110 selects a mode for detecting an open abnormality of the source line 20 (second operation mode), the control unit 110 sets the voltage level of the control signal supplied to the control signal line 80 to “HIGH”. As a result, the switching element 70 is turned on, and the source line 20 and the signal line 60 are connected. On the other hand, when the control unit 110 selects a mode other than the second operation mode, the control unit 110 sets the voltage level of the control signal supplied to the control signal line 80 to “LOW”. As a result, the switching element 70 is turned off. The specific operation of each mode will be described later.

In the case of the image display mode and the third operation mode, the gate drive circuit 130 sequentially supplies gate drive signals to the plurality of gate lines 30. The gate drive signal is a signal for transitioning each of the plurality of switching elements 50 connected to the gate line 30 to which the gate drive signal is supplied to the ON state. Details will be described later.

In the mode of displaying an image, the source drive circuit 120 transmits a source drive signal according to the gradation of the sub-pixel to each of the plurality of source lines 20 in synchronization with the supply of the gate drive signal by the gate drive circuit 130. Supply to. For example, when the gate drive signal is supplied to the first (first row) gate line 30, the source drive signal supplied to the first (first column) source line 20 is The voltage is set to correspond to the gradation of the sub-pixel corresponding to the sub-pixel region partitioned by the gate line 30 in the first row and the source line 20 in the first column. Further, in the case of the mode for detecting an abnormality (first operation mode, second operation mode, third operation mode), the source drive circuit 120 uses a plurality of source lines 20 as input signals which are signals for abnormality detection. Supply to each of. The source drive circuit 120 has three modes: a mode for detecting an abnormality in the source line 20 (first operation mode and a second operation mode) and a mode for detecting an abnormality in the gate line 30 (third mode). In either mode, the source line 20 is sequentially connected to the inspection signal line 140. On the other hand, the source drive circuit 120 does not connect the source line 20 to the inspection signal line 140 in the mode of displaying an image. Details will be described later.

The inspection signal line 140 is a signal line used for detecting an abnormality in the source line 20 or the gate line 30. In this example, the inspection signal line 140 has two wires (Sout1 and Sout2) and is connected to the source line 20 via the switching element 141. Specifically, of the two wires of the inspection signal line 140, one is connected to the odd-numbered source line 20 via the switching element 141, and the other is connected to the odd-numbered source line 20 via the switching element 141. It is connected to 20. In the present embodiment, Sout1 is connected to the odd-numbered source line 20 via the switching element 141, and Sout2 is connected to the even-numbered source line 20 via the switching element 141. The on / off of the switching element 141 is controlled by the source drive circuit 120.

Further, the inspection signal lines 140 (Sout1, Sout2) are connected to the voltage detection unit 150. The output signal of the detection signal line 140 is output to the voltage detection unit 150.

In the mode for detecting an abnormality (first operation mode, second operation mode, third operation mode), the voltage detection unit 150 has a voltage Vout (Vout1, Vout2) of the inspection signal line 140 (Sout1, Sout2). That is, the voltage of the source line 20 connected to the inspection signal line 140 is detected. Then, the detection result is output to the failure detection unit 160.

In the mode for detecting an abnormality (first operation mode, second operation mode, third operation mode), the failure detection unit 160 may use the source line 20 or the source line 20 based on the voltage Vout detected by the voltage detection unit 150. The abnormality of the gate line 30 is detected.

In the present embodiment, in the first operation mode or the second operation mode (corresponding to the second abnormality detection mode), the input signal is supplied to the plurality of source lines 20, and the input signal is supplied to the failure detection unit 160. An abnormality of a plurality of source lines 20 is detected based on the voltage of the source line 20.

Further, in the third operation mode (corresponding to the first abnormality detection mode), the gate drive circuit 130 sequentially supplies gate drive signals to the plurality of gate lines 30, and gates to the plurality of source lines 20. An input signal is supplied in synchronization with the supply of the gate drive signal by the drive circuit 130, and the failure detection unit 160 detects an abnormality in the plurality of gate lines 30 based on the voltage of the source line 20 to which the input signal is supplied. .. In the third operation mode, the failure detection unit 160 detects an abnormality in the plurality of gate lines 30 based on the voltage of the source line 20 to which the input signal is supplied in synchronization with the supply of the gate drive signal by the gate drive circuit 130. To detect. More specifically, the failure detection unit 160 detects an abnormality in the plurality of gate lines 30 to which the gate drive signal is supplied in synchronization with the supply of the input signal based on the voltage of the inspection signal lines 140 (Sout1, Sout2). To detect. Further, the failure detection unit 160 detects an abnormality of a plurality of gate lines 30 outside the image display period of the display device 10. The operation of each mode will be described in detail later.

In the present embodiment, the control unit 110, the voltage detection unit 140, and the failure detection unit 150 are configured as circuits that execute their functions, but the present invention is not limited to this, and for example, one or more processors are used in the non-volatile memory. By reading and executing the stored program, the functions of the control unit 110, the voltage detection unit 140, and the failure detection unit 150 may be realized. Further, for example, the functions of the control unit 110, the voltage detection unit 140, and the failure detection unit 150 may be realized by a combination of hardware and software.

Hereinafter, the operations of the active matrix substrate 1 and the control device 100 will be described. In the following, there are a mode for displaying an image, a mode for detecting a short-circuit abnormality of the source line 20 (first operation mode), a mode for detecting an open abnormality of the source line 20 (second operation mode), and a gate line. The operation of each mode will be described in order, divided into modes for detecting 30 short-circuit abnormalities and open abnormalities (third operation mode).

(Mode to display image)
In the image display mode, the control unit 110 supplies the control signal of the voltage level “LOW” to the control signal line 80. As a result, the switching element 70 is turned off, and the source line 20 and the signal line 60 are not connected (non-conducting). In this state, the gate drive circuit 130 sequentially supplies the gate drive signals to the plurality of gate lines 30, and the source drive circuit 120 supplies the source drive signals to the plurality of source lines 20.

FIG. 3 is a timing chart showing an example of the operation of the gate drive circuit 130 in the mode of displaying an image. The gate drive circuit 130 sequentially supplies gate drive signals to each of the gate lines G1 to G480 for each display period (horizontal scanning period) T of one frame. That is, in the display period T of one frame, the gate drive circuit 130 sequentially supplies a pulsed voltage (gate drive signal) to the plurality of gate lines 30, and repeats this operation for each display period T of one frame. .. Each of the plurality of switching elements 50 transitions to the ON state at the timing when the gate drive signal is supplied to the gate line 30 to which the switching element 50 is connected. As shown in FIG. 3, the gate drive circuit 130 sequentially supplies, for example, a pulsed voltage having a width of 2 clocks to the gate lines G1 to G480. The timing at which the gate drive signal is supplied to the gate lines G1 to G480 is shifted every clock.

FIG. 4 is a timing chart showing an example of the operation of the source drive circuit 120 in the mode of displaying an image. The source drive circuit 120 acquires a signal indicating the color data of the image displayed on the liquid crystal panel 11, and converts the acquired signal into an analog voltage (analog signal). This converted analog signal is the source drive signal. As shown in FIG. 4, the source drive circuit 120 supplies a source drive signal to each of the source lines S1 to S1920 at the rising timing of the load signal LD. The load signal LD is a timing signal for synchronizing with the gate drive signal.

The source drive circuit 120, for example, inverts the phase of the source drive signal input to the odd-numbered source line 20 and the phase of the source drive signal input to the even-numbered source line 20.

FIG. 5 is a diagram for explaining the timing at which the gate drive signal is supplied to the gate line 30 and the timing at which the source drive signal is supplied to the source line 20 in the mode of displaying an image. As described above, the gate drive circuit 70 sequentially supplies the gate drive signals to each of the gate lines G1 to G480 for each display period (horizontal scanning period H) of one frame, and the source drive circuit 60 is gate-driven. The source drive signal is supplied to the plurality of source lines 20 in synchronization with the supply of the gate drive signal by the circuit 70. For example, the source drive signal supplied to the source line S1 in synchronization with the timing when the gate drive signal is supplied to the gate line G1 is a sub pixel corresponding to the sub pixel area partitioned by the gate line G1 and the source line S1. The voltage is set to correspond to the gradation of.

When the switching element 50 is turned on by the gate drive signal, the voltage of the source drive signal is applied to the pixel electrode 40 via the switching element 50. As shown in FIG. 5, the voltage applied to the pixel electrode 40 is determined at the timing of the falling edge of the gate drive signal. When a voltage is applied to the pixel electrode 40, the light transmittance of the liquid crystal layer 3 changes, and a color corresponding to the transmittance is displayed on the liquid crystal panel. The applied voltage is held until the next application of the voltage (writing to the source line 20) depending on the capacity of the liquid crystal layer 3.

Further, as shown in FIG. 5, there is a blanking period between the display period of the Nth frame and the display period of the (N + 1) th frame. The blanking period is also referred to as the vertical blanking interval or vertical synchronization period. During the blanking period, the gate drive signal is not supplied to the gate line 30. Therefore, the voltage supplied to the source line 20 fluctuates and does not affect the image display of the liquid crystal panel 11. Therefore, during this blanking period, a process for detecting a short-circuit abnormality and a gate abnormality of the source line 20 may be performed. During the blanking period, both the process of detecting the short circuit abnormality of the source line and the process of detecting the gate abnormality may be performed, or either one may be performed.

(Mode for detecting short-circuit abnormality of source line 20 (first operation mode))
In the first operation mode, the control unit 110 supplies the control signal of the voltage level “LOW” to the control signal line 80. As a result, the switching element 70 is turned off. In this state, the source drive circuit 120 periodically supplies an input signal, which is a signal for detecting an abnormality, to the plurality of source lines 20. Further, the source drive circuit 120 sequentially connects the source line 20 to the inspection signal line 140.

FIG. 6 is a timing chart showing an example of the operation of the source drive circuit 120 in the first operation mode. The source drive circuit 120 supplies an input signal to the source line 20 at the rising timing of the load signal LD. This input signal is, for example, an analog signal having a voltage equivalent to that of the source drive signal, and is periodically supplied to the source line 20. Further, similarly to the source drive signal, the phase of the input signal input to the odd-numbered source line 20 and the phase of the source drive signal supplied to the even-numbered source line 20 are inverted. Further, the source drive circuit 120 sequentially connects the source line 20 to the inspection signal line 140. Specifically, as shown in FIG. 6, the source drive circuit 120 switches the connection between the source line 20 and the inspection signal line 140 every predetermined period TS. In the example of FIG. 6, in the period TS1, the source drive circuit 120 connects the source line S1 to the wiring Sout1 of the inspection signal line 140, and connects the source line S2 to the wiring Sout2. In the subsequent period TS2, the source drive circuit 120 connects the source line S3 to the inspection signal line 140 Sout1 and connects the source line S4 to the wiring Sout2. This connection switching is performed in order until all of the source lines 20 are connected.

In the first operation mode, the voltage detection unit 150 detects the voltage Vout (Vout1, Vout2) of the inspection signal line 140 (Sout1, Sout2) and outputs the detection result to the failure detection unit 160. Specifically, the voltage Vouts of the wirings Sout1 and Sout2 of the inspection signal line 140 are detected for each period TS in which the inspection signal line 140 and the source line 20 are connected, and the detection results are output to the failure detection unit 160.

In the first operation mode, the failure detection unit 160 compares the voltage Vout detected by the voltage detection unit 150 with the threshold value Vth1, and of each source line 20 connected to the inspection signal lines 140 (Sout1, Sout2). Detects a short circuit abnormality. Specifically, for each of the voltage Vout of the wiring Sout1 and Sout2 of the inspection signal line 140 detected by the voltage detection unit 150, the voltage Vout and the threshold value Vth1 are compared, and the period TS in which the voltage Vout is detected is TS. Detects a short circuit abnormality of the source line 20 connected to the inspection signal line 140. The threshold value Vth1 is set based on the expected value VE1 of the voltage obtained when there is no short circuit abnormality in the source line 20. For example, a predetermined value smaller than the expected value VE1 is set.

FIG. 7 is a flowchart showing an example of the operation of the failure detection unit 160 in the first operation mode. The failure detection unit 160 acquires the detection result of the voltage Vout (Vout1, Vout2) from the voltage detection unit 150 (S101). When the absolute values of Vout1 and Vout2 are equal to or higher than the threshold value Vth1 (S102: NO), it is determined that the short-circuit abnormality has not occurred in each source line 20 connected to the inspection signal lines 140 (Sout1, Sout2). (S104). On the other hand, when each of the absolute values of Vout1 and Vout2 is smaller than the threshold value Vth (S102: YES), it is determined that a short-circuit abnormality has occurred in each source line 20 connected to the inspection signal lines 140 (Sout1, Sout2). (S103). When the failure detection unit 160 executes the determination for all the voltage Vouts detected in each period when the inspection signal line 140 and each source line 20 are connected (S105: YES), the failure detection unit 160 detects a short-circuit abnormality of the source line 20. The detection operation is terminated, and if not (S105: NO), the process returns to S101.

FIG. 8 is a diagram showing a specific example in which the failure detection unit 160 detects a short-circuit abnormality of the source line 20. When there is no short-circuit abnormality or open abnormality in the source line 20, the voltage of the input signal is applied to the source line 20. As a result, the voltage of the inspection signal line 140 connected to the source line 20 also becomes a value corresponding to the voltage of the input signal. Therefore, as shown by the solid line in FIG. 8, the absolute value of the voltage Vout of the output signal of the inspection signal line 140 detected by the voltage detection unit 150 is the same value as the expected value VE1. Therefore, when the absolute value of Vout is a value equal to or higher than the threshold value Vth1, the failure detection unit 160 determines that a short-circuit abnormality has not occurred in the source line 20 (in the case of step S102: No in FIG. 7, step S104). Equivalent).

On the other hand, when a short-circuit abnormality occurs in the source line 20, a voltage equivalent to the voltage of the input signal is not applied to the source line 20. Therefore, the voltage of the inspection signal line 140 connected to the source line 20 does not become a value corresponding to the voltage of the input signal. Therefore, as shown by the broken line in FIG. 8, the absolute value of the voltage Vout of the output signal of the inspection signal line 140 detected by the voltage detection unit 150 is smaller than the threshold value Vth1. Therefore, when the absolute value of Vout is smaller than the threshold value Vth1, the failure detection unit 160 determines that a short abnormality has occurred in the short line 20 (in the case of step S102: Yes and step S103 in FIG. 7). Equivalent).

(Mode for detecting open abnormality of source line 20 (second operation mode))
In the second operation mode, the control unit 110 supplies the control signal of the voltage level “HIGH” to the control signal line 80. As a result, the switching element 70 is turned on, and the source line 20 is connected to the analog ground terminal via the signal line 60. In this state, the source drive circuit 120 periodically supplies an input signal, which is a signal for detecting an abnormality, to the plurality of source lines 20. Further, the source drive circuit 120 sequentially connects the source line 20 to the inspection signal line 140. The operation of the source drive circuit 120 in the second operation mode is the same as the operation in the first operation mode. For example, as shown in FIG. 6, the source drive circuit 120 has the source line 20 for each predetermined period TS. And the inspection signal line 140 are switched.

In the second operation mode, the voltage detection unit 150 detects the voltage Vout (Vout1, Vout2) of the output signal of the inspection signal line 140 (Sout1, Sout2), and outputs the detection result to the failure detection unit 160. Specifically, the voltage Vouts of the wirings Sout1 and Sout2 of the inspection signal line 140 are detected for each period TS in which the inspection signal line 140 and the source line 20 are connected, and the detection results are output to the failure detection unit 160.

In the second operation mode, the failure detection unit 160 compares the voltage Vout detected by the voltage detection unit 150 with the threshold value Vth2, and opens the source line 20 connected to the inspection signal lines 140 (Sout1, Sout2). Detect anomalies. Specifically, for each of the voltages Vout of the wirings Sout1 and Sout2 of the inspection signal line 140 detected by the voltage detection unit 150, the voltage Vout and the threshold value Vth2 are compared, and the period TS in which the voltage Vout is detected is TS. Detects an open abnormality of the source line 20 connected to the inspection signal line 140. The threshold value Vth2 is set based on the expected value VE2 of the voltage obtained when there is no open abnormality in the source line 20. For example, a predetermined value larger than the expected value VE2 is set. In the present embodiment, the expected value VE2 is the voltage AVSS of the analog ground terminal.

FIG. 9 is a flowchart showing an example of the operation of the failure detection unit 160 in the second operation mode. The failure detection unit 160 acquires the detection result of the voltage Vout (Vout1, Vout2) from the voltage detection unit 150 (S201). Then, when the absolute values of Vout1 and Vout2 are each equal to or less than the threshold value Vth2 (S202: NO), it is determined that the source line 20 connected to the inspection signal lines 140 (Sout1, Sout2) does not have an open abnormality (Sout2). S204). On the other hand, when each of the absolute values of Vout1 and Vout2 is larger than the threshold value Vth2 (S202: YES), it is determined that the source line 20 connected to the inspection signal line 140 (Sout1, Sout2) has an open abnormality. (S203). When the failure detection unit 160 executes the determination for all the voltages Vout detected in each period when the inspection signal line 140 and each source line 20 are connected (S205: YES), the failure detection unit 160 detects an open abnormality of the source line 20. The detection operation is terminated, and if not (S205: NO), the process returns to S201.

FIG. 10 is a diagram showing a specific example in which the failure detection unit 160 detects an open abnormality of the source line 20. When there is no open abnormality or short-circuit abnormality in the source line 20, the voltage of the source line 20 becomes equivalent to the voltage AVSS of the analog ground terminal connected via the input signal line 101. Therefore, the voltage of the inspection signal line 140 connected to the source line 20 is also equivalent to that of AVSS. Therefore, as shown by the solid line in FIG. 10, the absolute value of the voltage Vout of the output signal of the inspection signal line 140 detected by the voltage detection unit 150 is the same value as AVSS. Therefore, when the absolute value of Vout is a value equal to or less than the threshold value Vth2, the failure detection unit 160 determines that a short-circuit abnormality has not occurred in the source line 20 (in the case of step S202: No in FIG. 9 and step S204). Equivalent).

On the other hand, when the source line 20 has an open abnormality, the voltage applied by the input signal is held in the source line 20, and the voltage of the source line 20 is not equal to the voltage AVSS of the analog ground terminal. Therefore, the voltage of the inspection signal line 140 connected to the source line 20 is not equal to that of AVSS. Therefore, as shown by the wavy line in FIG. 10, when the absolute value of the voltage Vout of the output signal of the inspection signal line 140 detected by the failure detection unit 160 is larger than the threshold value Vth2, the failure detection unit 160 , It is determined that an open abnormality has occurred in the short line 20 (corresponding to the case of step S202: Yes and step S203 in FIG. 9).

(Mode for detecting short circuit abnormality and open abnormality of gate wire 30 (third operation mode))
In the third operation mode, the control unit 110 supplies the control signal of the voltage level “LOW” to the control signal line 80. As a result, the switching element 70 is turned off. In this state, the gate drive circuit 130 sequentially supplies gate drive signals to the plurality of gate lines 30. Then, the source drive circuit 120 supplies an input signal, which is a signal for detecting an abnormality, to the plurality of source lines 20 in synchronization with the supply of the gate drive signal by the gate drive circuit 130. Further, the source drive circuit 120 sequentially connects the source line 20 to the inspection signal line 140.

FIG. 11 is a timing chart showing an example of the operation of the gate drive circuit 130 and the source drive circuit 120 in the third operation mode. In the third operation mode, the gate drive circuit 130 supplies a gate drive signal to each of the gate lines G1 to G480 in each of a plurality of periods T (horizontal scanning periods T), each of which corresponds to a period of one frame. Do. That is, the gate drive signals G1 to G480 are sequentially output in each of the plurality of horizontal scanning periods T. Here, the timing at which the gate drive signal is supplied to the gate lines G1 to G480 is shifted every two clocks as shown in FIG.

In the third operation mode, the source drive circuit 120 supplies input signals to the plurality of source lines 20 in synchronization with the supply of gate drive signals by the gate drive circuit 70.

Further, the source drive circuit 120 connects one wiring Sout1 of the inspection signal line 140 and one source line 20 of the odd-numbered source lines 20 in each of the plurality of horizontal scanning periods T, and connects the other. The wiring Sout2 is connected to the source line of one of the even-numbered source lines 20. Specifically, the source drive circuit 60 has an odd-numbered source line 20 connected to one wiring Sout1 of the inspection signal line 104 and an even-numbered source connected to the other wiring Sout2 for each horizontal scanning period T. Switch line 20. For example, as shown in FIG. 11, in the first horizontal scanning period T1, one wiring Sout1 and the source line S1 of the inspection signal line 140 are connected, and the other wiring Sout2 and the source line S2 are connected. Subsequently, in the second horizontal scanning period T2, one wiring Sout1 and the source line S3 of the inspection signal line 140 are connected, and the other wiring Sout2 and the source line S4 are connected. This connection switching is performed in order until all of the source lines 20 are connected.

In the third operation mode, the voltage detection unit 150 detects the voltage Vout (Vout1, Vout2) of the output signal from the inspection signal line 140 (Sout1, Sout2), and outputs the detection result to the failure detection unit 160. Specifically, in each of the plurality of horizontal scanning periods T, the voltage Vout in the period corresponding to the supply of the gate drive signal to each gate line 30 is detected, and each of the detection results is output to the failure detection unit 160.

The failure detection unit 160 compares the voltage Vout detected by the voltage detection unit 150 with the threshold value Vth3 and the threshold value Vth4, and detects a short-circuit abnormality and an open abnormality of the gate line 30. Specifically, for each of the voltage Vouts detected in each of the above periods, the voltage Vout detected by the voltage detection unit 150 is compared with the threshold value Vth3 and the threshold value Vth4, and short-circuit abnormality and open abnormality of the gate line 30 are detected. To do. The threshold value Vth3 and the threshold value Vth4 are set based on the expected value VE3 of the voltage obtained when there is no short-circuit abnormality and open abnormality in the gate wire 30. For the threshold value Vth3, for example, a predetermined value smaller than the expected value VE3 is set. For the threshold value Vth4, for example, a predetermined value larger than the expected value VE3 is set.

FIG. 12 is a flowchart showing an example of the operation of the failure detection unit 160 in the third operation mode. The failure detection unit 160 acquires the detection result of the voltage Vout (Vout1, Vout2) from the voltage detection unit 150 (S301). When the absolute values of Vout1 and Vout2 are each of the threshold value Vth3 or more and the threshold value Vth4 or less (S302: NO, S304: NO), it is determined that the gate line 30 has no short-circuit abnormality or open abnormality. (S306). On the other hand, when the absolute values of Vout1 and Vout2 are smaller than the threshold value Vth3 (S302: YES), it is determined that a short-circuit abnormality has occurred in the gate line 30 (S303). If the absolute values of Vout1 and Vout2 are larger than the threshold value Vth4 (S302: NO, S304: YES), it is determined that an open abnormality has occurred in the gate line 30 (S305). The failure detection unit 160 determines for all the voltage Vouts in each period (period for each gate line 30) corresponding to the supply of a plurality of gate drive signals in each of the plurality of horizontal scanning periods T (all source lines 20 are determined). When (judgment by connecting to the inspection signal line 140) is executed (S307: YES), the operation of detecting the short circuit abnormality and the open abnormality of the gate line 30 is terminated, and otherwise (S307: NO), the operation is set to S301. go back.

FIG. 13 is a diagram showing a specific example in which the failure detection unit 160 detects a short-circuit abnormality of the gate wire 30. FIG. 14 is a diagram showing a specific example in which the failure detection unit 160 detects an open abnormality of the gate wire 30.

When a gate drive signal is supplied to the gate line 30 when neither a short circuit abnormality nor an open abnormality has occurred in the gate line 30, the switching element is turned on and the voltage of the input signal supplied to the source line 20 is pixelated. It is applied to the electrode 40. Therefore, the voltage level of the source line 20 becomes smaller, and the voltage level of the inspection signal line 140 connected to the source line 20 also becomes smaller. Therefore, as shown by the solid line in FIG. 13, the absolute value of the voltage Vout of the output signal of the detection signal line 140 detected by the voltage detection unit 150 is the same value as the expected value VE3. When the absolute value of the voltage Vout is equal to or greater than the threshold value Vth3 and equal to or less than the threshold value Vth4, the failure detection unit 160 determines that the gate line 30 has no short-circuit abnormality or gate abnormality (step S302 in FIG. 12: No, corresponding to the case of step S304).

On the other hand, when a short-circuit abnormality occurs in the gate wire 30, when a gate drive signal is supplied to the gate wire 30, a voltage is applied to the adjacent gate wire 30 in which the short-circuit abnormality occurs almost at the same time, and the adjacent gates are connected. The switching element 50 corresponding to the line is turned on almost at the same time, and the voltage of the input signal input to the source line 20 is applied to each pixel electrode. Therefore, the voltage level of the source line 20 becomes smaller than when the short-circuit abnormality and the open abnormality do not occur, and the voltage level of the inspection signal line 140 connected to the source line 20 also becomes smaller. Therefore, as shown by the broken line in FIG. 13, the absolute value of the voltage Vout of the output signal of the detection signal line 140 detected by the voltage detection unit 150 is smaller than the threshold value Vth3. When the absolute value of the voltage Vout is smaller than the threshold value Vth3, the failure detection unit 160 determines that a short-circuit abnormality has occurred in the gate line 30 (corresponding to steps S302: Yes and step S303 in FIG. 12).

Further, when the gate wire 30 has an open abnormality, even if the gate drive signal is supplied to the gate wire 30, a voltage equivalent to that of the gate drive signal is not applied to the gate wire 30. As a result, the switching element 50 is not sufficiently turned on, and the voltage of the input signal input to the source line 20 is not sufficiently applied to the pixel electrodes. Therefore, the voltage level of the source line 20 becomes higher than when the short-circuit abnormality and the open abnormality do not occur, and the voltage level of the inspection signal line 140 connected to the source line 20 also becomes higher. Therefore, as shown by the broken line in FIG. 14, the absolute value of the voltage Vout of the output signal of the detection signal line 140 detected by the voltage detection unit 150 is larger than the threshold value Vth4. When the absolute value of the voltage Vout is larger than the threshold value Vth4, the failure detection unit 160 determines that an open abnormality has occurred in the gate line 30 (corresponding to step S302: No, step S304 in FIG. 12).

As described above, the failure detection unit 160 compares the voltage Vout of the inspection signal line 140 with the two threshold values to detect a short-circuit abnormality and an open abnormality of the gate line 30. When the voltage Vout of the inspection signal line 140 is smaller than the threshold value Vth3 (first threshold value), the failure detection unit 160 detects a short-circuit abnormality of the gate line 30, and the voltage Vout of the inspection signal line 140 is the threshold value Vth3 (first threshold value). ) Is larger than the threshold value Vth4 (second threshold value), an open abnormality of the gate line 30 is detected.

According to the display device 10 of the present embodiment, failure detection of the conventional liquid crystal display device is improved. Specifically, after the liquid crystal display device 1 is mounted on a vehicle or the like, it is possible to detect a short-circuit abnormality and an open abnormality with respect to the source line 20 and the gate line 30 of the liquid crystal panel 11 of the own device. For example, in the liquid crystal display device 10, when a short-circuit abnormality or an open abnormality occurs in a part of the source line 20 or the gate line 30 and an image cannot be displayed in a part of the display area, the liquid crystal display device 1 itself It can be detected by the device and the image can be appropriately displayed in the display area where the image can be displayed.

In the display device 10 of the present embodiment, the abnormality of the gate line 30 is detected based on the voltage of the source line 20 to which the input signal is supplied. Further, an abnormality of the source line 20 is also detected based on the voltage of the source line 20 to which the input signal is supplied. That is, since the abnormality of the source line 20 and the gate line 30 is detected based on the voltage of the source line 20, the voltage line for detecting the abnormality of the source line 20 and the gate line 30 can be shared. As a result, the circuit configuration can be simplified, so that an advantageous effect that, for example, the area outside the display area can be reduced can be achieved.

Further, the display device 10 of the present embodiment is also useful as a display device mounted on a vehicle or the like from the viewpoint of fail-safe. When the abnormality occurs in a part of the source line 20 or the gate line 30, and the area for displaying a high-importance display such as a warning display for a vehicle passenger becomes undisplayable, the display device 10 changes. Detect it in your device. Then, a warning display or the like can be displayed in the display area where the display is possible. That is, it is possible to display a warning or the like while avoiding the place where the abnormality occurs. Since the display device 10 has such a fail-safe function, if the display device 10 is adopted as an in-vehicle display device, it is possible to design an in-vehicle space without providing other devices such as a warning light. .. It is possible to reduce the equipment cost and improve the design.

[Embodiment 2]
The second embodiment is different from the first embodiment in that it has a function of detecting an abnormality in the voltage detection unit in addition to the function of the control device of the first embodiment. Hereinafter, the differences from the first embodiment will be mainly described.

FIG. 15 is a diagram showing an example of the configuration of the active matrix substrate 1 and the control device of the second embodiment. The control device of the second embodiment includes a control unit 110A, a source drive circuit 120, a gate drive circuit 130, an inspection signal line 140, a voltage detection unit 150A, a failure detection unit 160A, and an auxiliary output unit 500.

The control unit 110A has the same function as the control unit 110 of the first embodiment. The control unit 110A further causes the voltage detection unit 150A, the failure detection unit 160A, and the auxiliary output unit 500 to execute the operation of the auxiliary inspection mode. Specifically, the voltage detection unit 150A is controlled to detect the voltage Vout (Vout1, Vout2) of the inspection signal line 140 (Sout1, Sout2). Further, the operation of the failure detection unit 160A is switched to the operation of the auxiliary inspection mode.

The control unit 110A causes each configuration to execute the auxiliary inspection mode at a preset timing, for example. However, in the control device 100A, when any of the modes for detecting an abnormality (first operation mode, second operation mode, third operation mode) is being executed, an auxiliary inspection mode is set for each configuration. Do not let it run. In the control device 100A, each configuration may be made to execute the auxiliary inspection mode while the mode for displaying an image is being executed.

The auxiliary output unit 500 outputs a monitor signal to the inspection signal line 140. More specifically, when the auxiliary output unit 500 receives the execution instruction of the auxiliary inspection mode from the control unit 110A, the auxiliary output unit 500 inspects the inspection signal line 140 whether or not the voltage detection unit 150A is operating normally. Outputs a monitor signal for This monitor signal may be any signal pattern, for example, a toggle pattern that repeats High and Low.

The voltage detection unit 150A has the same function as the voltage detection unit 150 of the first embodiment, and further, in the auxiliary inspection mode, the voltage Vout (Vout1, Vout2) of the output signal from the inspection signal line 140 (Sout1, Sout2). ) Is detected, and the detection result is output to the failure detection unit 160A.

The failure detection unit 160A has the same function as the failure detection unit 160 of the first embodiment, and further inspects the voltage detection unit 150A based on the voltage of the inspection signal line 140 to which the monitor signal is supplied. More specifically, the failure detection unit 160A compares the voltage Vout (Vout1, Vout2) detected by the voltage detection unit 150A with the expected value VEm for the auxiliary inspection mode in the auxiliary inspection mode. Here, the expected value VEm is a value indicating the voltage level of the monitor signal from the auxiliary output unit 500. The failure detection unit 160A determines that the voltage detection unit 150A is operating normally if the difference between the voltage Vout detected by the voltage detection unit 150A and the expected value VEm for the auxiliary inspection mode is within a predetermined range. To do. On the other hand, if the difference between the two is larger than the predetermined range, it is determined that the voltage detection unit 150A is not operating normally.

According to the display device of the second embodiment, the abnormality of the voltage detection unit 150A of the control device 110A can be detected by the own device.

[Modification example]
The first and second embodiments are examples, and the present invention is not limited to the above description. Each component, each processing process, or a combination thereof disclosed in the above-described first and second embodiments can be appropriately modified. For example, it may be modified as described below.

In the first and second embodiments, the display device 10 having the liquid crystal panel 11 and the backlight module 12 is adopted as an example, but the present invention is not limited to this. The present disclosure is applicable to various types of display devices having an active matrix display panel. For example, as the display panel, an organic EL (electro-luminescence) display panel, an inorganic EL display panel, a field emission (FE) display panel, or the like can be adopted.

In the first and second embodiments, the signal line 101 is configured to have a total of six wires, two for each hue of RGB, but the present invention is not limited to this. For example, a configuration having one or more wires for each hue of RGB may be used. For example, it may be configured by one or more wires and connected to the source line 20 without being related to the hue of RGB. It can be appropriately designed according to the standard of the display panel 11, the inspection method in the manufacturing process of the display device 10, the required inspection time, and the like.

In the first and second embodiments described above, the inspection signal line 140 has a configuration having two wirings (Sout1 and Sout2), but the present invention is not limited to this. It may be configured with one wiring, or may be configured with three or more wirings.

In the first and second embodiments, in the mode for detecting an abnormality (first operation mode, second operation mode, third operation mode), the source drive circuit 120 sequentially connects the source line 20 to the inspection signal line 140. I explained that it will be connected, but it is not limited to this. For example, apart from the configuration of the source drive circuit 120, the wiring (Sout1, Sout2) of the inspection signal line 140 and the switch for switching the connection / non-connection between each wiring (Sout1, Sout2) and the plurality of source lines 20 are provided. Provide. Then, in the mode for detecting an abnormality (first operation mode, second operation mode, third operation mode), for example, the control unit 110 controls so that the source line 20 is sequentially connected to the inspection signal line 140. You may.

In the first and second embodiments, in the mode for detecting an abnormality (first operation mode, second operation mode, third operation mode), the source drive circuit 120 sends a signal for abnormality detection to the source line 20. It has been explained that a certain input signal is input, but the present invention is not limited to this. In each operation mode, for example, an input signal may be input from the signal line 60 to the source line 20. In that case, the input signal may be generated by the source drive circuit 120 or by another circuit.

When an input signal is input from the signal line 60 to the source line 20 in the mode for detecting an open abnormality of the source line 20 (second operation mode), the source line is routed through a wiring other than the signal line 60. 20 may be connected to the analog ground terminal.

The display devices 10 of the first and second embodiments may execute at least one of the modes for detecting an abnormality (first operation mode, second operation mode, third operation mode).

In the mode for detecting a short-circuit abnormality of the source line 20 (first operation mode), the display devices 10 of the first and second embodiments detect short-circuit abnormalities in all of the source lines S1 to S1920 included in the source line 20. It may be detected, or a short-circuit abnormality may be detected for a part of it.

In the mode for detecting an open abnormality of the source line 20 (second operation mode), the display devices 10 of the first and second embodiments have different openness for all the source lines S1 to S1920 included in the source line 20. It may be detected all the time, or an open abnormality may be detected for a part of it.

In the mode for detecting the short-circuit abnormality and the open abnormality of the gate wire 30 (third operation mode), the display devices 10 of the first and second embodiments have the detection of the short-circuit abnormality and the detection of the open abnormality of the gate wire 30. Both may be performed, or only one of them may be detected.

The display devices 10 of the first and second embodiments describe all of the gate lines G1 to G480 included in the gate line 30 in a mode (third operation mode) for detecting a short-circuit abnormality and an open abnormality of the gate line 30. A short-circuit abnormality may be detected, or a short-circuit abnormality may be detected for a part of the parts.

The display devices 10 of the first and second embodiments describe all of the gate lines G1 to G480 included in the gate line 30 in a mode (third operation mode) for detecting a short-circuit abnormality and an open abnormality of the gate line 30. An open abnormality may be detected, or an open abnormality may be detected for a part of the parts.

In the display devices 10 of the first and second embodiments, the timing at which each mode of the abnormality detection mode (first operation mode, second operation mode, third operation mode) is executed is appropriately set. You may.

For example, the display device 10 detects an abnormality of the source line 20 (first operation mode, first operation mode) before executing the mode of detecting the short-circuit abnormality and the open abnormality of the gate line 30 (third operation mode). 2 operation modes) may be executed. In the third operation mode, the source line 20 is used. Therefore, by performing the abnormality detection on the source line 20 first, the accuracy of the abnormality detection on the gate line 30 can be ensured.

For example, the display device 10 sets each mode of the mode for detecting an abnormality (first operation mode, second operation mode, third operation mode) as an image after the main power of the display device 10 is turned on. It may be executed before the display of is started (before the mode for displaying the image is executed).

For example, the display device 10 sets each mode of the mode for detecting an abnormality (first operation mode, second operation mode, third operation mode) after finishing the display of the image (mode for displaying the image). After execution), it may be executed before the main power of the display device 10 is turned off.

For example, the display device 10 has a mode of detecting a short-circuit abnormality of the source line 20 (first operation mode) and a mode of detecting an open abnormality of the source line 20 (second operation mode) during the display blanking period. You may do both.

For example, one of the first operation mode and the second operation mode is executed before the display blanking period, and the other operation mode is executed after the display blanking period. Is also good.

For example, the display device 10 has a mode of detecting a short-circuit abnormality of the source line 20 (first operation mode) and a mode of detecting an open abnormality of the source line 20 (second operation mode) during the display blanking period. Either one may be executed.

The display device 10 causes a short abnormality in a predetermined number of source lines 20 in, for example, one blanking period (a period between the display period of the Nth frame and the display period of the (N + 1) th frame). It may be detected.

Further, the display device 10 causes an open abnormality for a predetermined number of source lines 20 in, for example, one blanking period (a period between the display period of the Nth frame and the display period of the (N + 1) th frame). It may be detected.

In the display devices 10 of the first and second embodiments, the timing at which each mode of the mode for detecting an abnormality (first operation mode, second operation mode, third operation mode) is executed is input by the user. May be set by.

In the display devices 10 of the first and second embodiments, each mode of the mode for detecting an abnormality (first operation mode, second operation mode, third operation mode) is instructed by the user to execute each mode. If it is accepted, it may be executed.

The control device 100 of the first and second embodiments may be realized by one IC (integrated circuit). The control device 100 of the first and second embodiments may be realized by a plurality of ICs. For example, the source drive circuit 120 and the gate drive circuit 130 may be incorporated in separate ICs.

The control unit 110 of the first and second embodiments may be configured by, for example, a microcomputer. In the above-described first and second embodiments, some or all of the functions of the voltage detection unit 150 may be realized by a microcomputer. In the above-described first and second embodiments, some or all the functions of the failure detection unit 160 may be realized by a microcomputer.

Each of the above-mentioned components may be realized as a circuit that executes the function, or may be realized by executing a program by one or a plurality of processors.

Each of the above components is typically realized as an LSI or IC which is an integrated circuit. These may be individually chipped, or may be chipped to include some or all of them.

[Supplement]
The display device according to the embodiment of the present disclosure is a display device having an active matrix type display panel, and is a gate drive signal for a plurality of source lines, a plurality of gate lines, and the plurality of gate lines. The abnormality of the plurality of gate lines is detected based on the voltage of the gate drive circuit that sequentially supplies the signals and the source line to which the input signal is supplied in synchronization with the supply of the gate drive signal by the gate drive circuit. It is provided with a failure detection unit.
According to this aspect, failure detection of a conventional liquid crystal display device is improved. Specifically, after the liquid crystal display device 1 is mounted on a vehicle or the like, it is possible to detect an abnormality in the gate line of the display panel of the own device.
Further, according to this aspect, since the abnormality of the gate line is detected based on the voltage of the source line, the circuit configuration can be simplified. For example, the advantageous effect that the area outside the display area can be reduced can be achieved.
In the display device according to the embodiment of the present disclosure, for example, an inspection signal line connected to the plurality of source lines is further provided, and the failure detection unit is based on the voltage of the inspection signal line to obtain the input signal. The abnormality of the plurality of gate lines to which the gate drive signal is supplied may be detected in synchronization with the supply.
According to this aspect, anomalies in a plurality of gate lines are detected based on the voltage of the inspection signal line, that is, the voltage of the source line connected to the inspection signal line. The circuit configuration can be simplified by configuring the configuration via the inspection signal line.
In the display device according to the embodiment of the present disclosure, for example, when the voltage of the inspection signal line is smaller than the first threshold value, the failure detection unit detects a short-circuit abnormality of the plurality of gate lines and performs the inspection. When the voltage of the signal line is larger than the second threshold value larger than the first threshold value, the open abnormality of the plurality of gate lines may be detected.
According to this aspect, it is possible to detect a short circuit abnormality and an open abnormality of the gate line.
The display device according to the embodiment of the present disclosure may further include, for example, a source drive circuit that supplies the input signal to the plurality of source lines.
The display device according to the embodiment of the present disclosure may further include, for example, a signal line connected to the plurality of source lines and inputting the input signal to the plurality of source lines.
In the display device according to the embodiment of the present disclosure, for example, the display device includes a first abnormality detection mode for detecting an abnormality in the gate line and a second abnormality detection mode for detecting an abnormality in the plurality of source lines. In the first abnormality detection mode, the gate drive circuit sequentially supplies gate drive signals to the plurality of gate lines, and the gate drive circuits are supplied to the plurality of source lines by the gate drive circuit. The input signal is supplied in synchronization with the supply of the drive signal, and the failure detection unit detects an abnormality in the plurality of gate lines based on the voltage of the source line to which the input signal is supplied, and the first 2 In the abnormality detection mode, the input signal is supplied to the plurality of source lines, and the failure detection unit detects an abnormality in the plurality of source lines based on the voltage of the source line to which the input signal is supplied. It may be detected.
In the display device according to the embodiment of the present disclosure, for example, the display device further includes a voltage detection unit that detects the voltage of the inspection signal line and an auxiliary output unit that outputs a monitor signal to the inspection signal line. , And the failure detection unit may inspect the voltage detection unit based on the voltage of the inspection signal line to which the monitor signal is supplied.
According to this aspect, the abnormality of the voltage detection unit can be detected by the own device.
In the display device according to the embodiment of the present disclosure, for example, the failure detection unit may detect an abnormality of the plurality of gate lines outside the image display period in the display device.
According to this aspect, an abnormality of the gate line can be detected without affecting the image display of the display device.
The method for inspecting a display device according to an embodiment of the present disclosure is a method for inspecting a display device including an active matrix type display panel having a plurality of source lines and a plurality of gate lines, and the plurality of gate lines. On the other hand, the gate drive signals are sequentially supplied, and the abnormality of the plurality of gate lines is detected based on the voltage of the source line to which the input signal is supplied in synchronization with the supply of the gate drive signal.
According to this aspect, failure detection of a conventional liquid crystal display device is improved. Specifically, after the liquid crystal display device 1 is mounted on a vehicle or the like, it is possible to detect an abnormality in the gate line of the display panel of the own device.
Further, according to this aspect, since the abnormality of the gate line is detected based on the voltage of the source line, the circuit configuration can be simplified. For example, the advantageous effect that the area outside the display area can be reduced can be achieved.

1 Active matrix substrate 2 Opposing substrate 3 Liquid crystal layer 4 1st polarizing plate 5 2nd polarizing plate 10 Display device 11 Liquid crystal panel 12 Backlight module 20 Source line 30 Gate line 40 Pixel electrode 50 Switching element 60 Signal line 70 Switching element 80 Control Signal line 100 Control device 110, 110A Control unit 120 Source drive circuit 130 Gate drive circuit 140 Inspection signal line 150, 150A Voltage detection unit 160, 160A Failure detection unit 500 Auxiliary output unit

Claims (9)

A display device having an active matrix type display panel.
With multiple source lines
With multiple gate lines
A gate drive circuit that sequentially supplies gate drive signals to the plurality of gate lines, and
A failure detection unit that detects an abnormality in the plurality of gate lines based on the voltage of the source line to which an input signal is supplied in synchronization with the supply of the gate drive signal by the gate drive circuit is provided.
Display device. Further provided with inspection signal lines connected to the plurality of source lines,
The failure detection unit detects an abnormality in the plurality of gate lines to which the gate drive signal is supplied in synchronization with the supply of the input signal, based on the voltage of the inspection signal line.
The display device according to claim 1. The failure detection unit
When the voltage of the inspection signal line is smaller than the first threshold value, a short-circuit abnormality of the plurality of gate lines is detected.
When the voltage of the inspection signal line is larger than the second threshold value larger than the first threshold value, an open abnormality of the plurality of gate lines is detected.
The display device according to claim 2. further,
A source drive circuit for supplying the input signal to the plurality of source lines is provided.
The display device according to any one of claims 1 to 3. further,
A signal line connected to the plurality of source lines and inputting the input signal to the plurality of source lines is provided.
The display device according to any one of claims 1 to 3. The display device is
It has a first abnormality detection mode for detecting an abnormality in the gate line and a second abnormality detection mode for detecting an abnormality in the plurality of source lines.
In the first abnormality detection mode,
The gate drive circuit sequentially supplies gate drive signals to the plurality of gate lines.
The input signal is supplied to the plurality of source lines in synchronization with the supply of the gate drive signal by the gate drive circuit.
The failure detection unit detects an abnormality in the plurality of gate lines based on the voltage of the source line to which the input signal is supplied.
In the second abnormality detection mode,
The input signal is supplied to the plurality of source lines.
The failure detection unit detects an abnormality in the plurality of source lines based on the voltage of the source line to which the input signal is supplied.
The display device according to any one of claims 1 to 5. A voltage detection unit that detects the voltage of the inspection signal line and
An auxiliary output unit that outputs a monitor signal to the inspection signal line is provided.
The failure detection unit
The voltage detection unit is inspected based on the voltage of the inspection signal line to which the monitor signal is supplied.
The display device according to any one of claims 2 to 6. The failure detection unit detects an abnormality in the plurality of gate lines outside the image display period in the display device.
The display device according to any one of claims 1 to 7. A method for inspecting a display device including an active matrix display panel having a plurality of source lines and a plurality of gate lines.
Gate drive signals are sequentially supplied to the plurality of gate lines, and the gate drive signals are sequentially supplied.
An abnormality of the plurality of gate lines is detected based on the voltage of the source line to which the input signal is supplied in synchronization with the supply of the gate drive signal.
Inspection methods.

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