JP2021022040A - Communication control system and information processor - Google Patents

Abstract

To avoid deterioration in the efficiency of data transfer between a controller (a master side device) and a controlled device (a slave side device) without destroying data output circuits of both of the devices even upon occurrence of the timing at which both of the devices are in a transmitted state.SOLUTION: In a communication control system which connects together a controller and a controlled device with a bus and performs bi-directional communication, after a predetermined request command composed of n (where n is greater than 1) bits is transmitted from the controller to the controlled device, the bus transfer direction is switched, and upon transmission of replay data corresponding to a request command composed of m (where m is greater than 1) bits from the controlled device to the controller, contents of first binary data composed of a (where a is smaller than n but greater than 1) bits included in the request command and finally transmitted and contents of second binary data composed of b (where b is smaller than m but greater than 1) bits included in the replay data and initially transmitted are identical.SELECTED DRAWING: Figure 8

Description

The present invention relates to a communication control system and an information processing device, and in particular, uses a set of communication paths for a communication interface for performing data communication between a master-side device and a slave-side device in a master-slave relationship, and data transfer directions. The present invention relates to a communication control system in which bidirectional data communication is performed by switching between the two, and an information processing device including a master side device and a slave side device connected by a set of communication paths for bidirectional data communication.

Information processing devices such as personal computers and mobile terminals used today are equipped with a CPU that controls the operation of the entire device, and are ASICs (applications) that are integrated circuits for executing specific functions such as memory and image processing, which are peripheral devices. A specific integrated circuit) and the like are connected to the CPU via a predetermined bus, and bidirectional data communication is performed between the CPU and peripheral devices.

Various types of communication interfaces are used for the bus connecting the CPU and peripheral devices. For example, an SPI (Serial Peripheral Interface) bus capable of high-speed communication is used.
In particular, Quad SPI format communication interfaces that can simultaneously transmit 4-bit data with one clock have come to be used.

In the Quad SPI format communication interface, for example, the CPU which is the master side device and the ASIC which is the slave side device are connected from the clock signal line, the chip select signal line, and the four data lines which are the data transmission paths. Connect with a total of 6 signal lines, switch the data transfer direction so that data collision does not occur with 4 data lines, and bidirectional communication (half-duplex communication) between the CPU and ASIC. )I do.
That is, for example, after transmitting data from the master side device in the transmitting state to the slave side device in the receiving state via the four data lines, a predetermined waiting time of at least one clock cycle or more is provided. After switching the communication state between the two, the master side device is in the reception state, and the slave side device is switched to the transmission state, data is transmitted from the slave side device to the master side device.

Further, in Patent Document 1, the master side device and a plurality of slave side devices are connected to the SPI bus type bus system, and the configuration of the SCK signal line that supplies the data synchronization clock to each slave side device is devised. , The timing of the synchronization clock supplied to each slave side device is sequentially shifted by a predetermined number of bits to send and receive data between one slave side device and the master side device to which the synchronization clock is supplied. A bus system has been proposed in which the number of signal lines does not change even if the number of slave-side devices increases or decreases.

Japanese Unexamined Patent Publication No. 2013-125315

However, in the prior art using the SPI bus, a predetermined waiting time of at least one clock cycle or more is provided in order to switch the data transfer direction so that data collision does not occur in the data lines for transmitting and receiving data. Therefore, the efficiency of data transfer between the slave side device and the master side device is lowered.

When transmitting the device identification number (device ID) of the slave side device and the status information of the slave side device to the master side device in response to the request from the master side device, the slave side device receives the request. After that, although the device identification number and the like can be prepared to be transmitted immediately, the above-mentioned predetermined waiting time is provided, so that the transfer efficiency is lowered.

In the bus system of Patent Document 1, measures to prevent data collision between the master side device and the slave side device are not considered, and only one SDIO signal capable of bidirectional ping-pong transmission is not considered. When data communication is performed by line, it is necessary to provide a predetermined waiting time similar to the above when switching the data transfer direction so that data collision does not occur.

On the other hand, when a predetermined waiting time is not provided or the waiting time is shortened, when the data transfer direction is switched, both the master side device and the slave side device are in the data transmission state. May occur.
When both are in the data transmission state, the transmission signals output from both sides collide on the same data line of the SPI bus.

For example, if the master side device outputs a transmission signal corresponding to data "1" and the slave side device outputs a transmission signal corresponding to data "0" on the same data line of the SPI bus, the transmission signal collision occurs. appear.
When such a collision occurs, the voltage levels of the transmission signal corresponding to the data "1" and the transmission signal corresponding to the data "0" are different, so that the data output buffer circuit of the master side device and the slave side device can be used. An overcurrent exceeding the standard value may flow, and the data output buffer circuit may be destroyed.

Therefore, the data transfer buffer circuit will not be destroyed due to the overcurrent flowing through the master side device and the slave side device, and the data transfer efficiency between the master side device and the slave side device will not decrease. It is desirable to.

Therefore, the present invention has been made in consideration of the above circumstances, and in a communication interface for performing data communication between a master side device and a slave side device in a master-slave relationship, the master side device and the slave side Even if the data transmission state occurs with both devices, the data output circuits of both devices will not be destroyed and the data transfer efficiency between the master side device and the slave side device will not decrease. The task is to make it.

The present invention is a communication control system in which a control device and a controlled device in a master-slave relationship are connected by a bus, the transfer direction of the bus is switched, and bidirectional communication is performed between the control device and the controlled device. After transmitting a predetermined request command consisting of n (n> 1) bits from the control device to the controlled device via the bus, the transfer direction of the bus is switched to obtain the controlled device. When the reply data corresponding to the request command consisting of m (m> 1) bits is transmitted to the control device via the bus, a of the request commands to be transmitted last is transmitted. The content of the first binary data consisting of the number of bits of (n> a> 1) and the second binary consisting of the number of bits of b (m> b> 1) transmitted first among the reply data. It provides a communication control system characterized in that the contents of data are the same.

Further, the content of the first binary data and the content of the second binary data are output to the bus as signals of the same voltage level.

Further, the content of the first binary data and the content of the second binary data are both binary data corresponding to 0 having a plurality of bits, or are composed of a plurality of bits. It is characterized in that it is binary data corresponding to 1.

Further, the bus is a Quad SPI (Serial Peripheral Interface) bus including four data lines, and the request command and the reply data are transmitted at different timings via the four data lines. It is characterized by.

Further, among the request commands transmitted via the four data lines, the first binary data consisting of at least 4 bits or more to be transmitted last and the request commands transmitted via the four data lines are transmitted. Of the reply data, the second binary data consisting of at least 4 bits or more initially transmitted is binary data corresponding to 0 consisting of a plurality of bits, or is composed of a plurality of bits. It is characterized in that it is binary data corresponding to 1.

Further, the controlled device stores the device ID for identifying the controlled device in advance, and the control device transmits a request command including information requesting the device ID to be transmitted to the controlled device. In this case, the controlled device is characterized in that reply data including the device ID of the controlled device is transmitted to the control device.

Further, the controlled device includes a status register that stores information indicating the operating state of the controlled device, and the control device receives a request command requesting that the information stored in the status register be transmitted. When transmitted to the control device, the controlled device transmits reply data including information stored in the status register of the controlled device to the control device.

Further, the controlled device includes a setting register that stores information indicating the setting contents of the controlled device, and the control device receives a request command requesting that the information stored in the setting register be transmitted. When transmitted to the control device, the controlled device transmits reply data including information stored in the setting register of the controlled device to the control device.

The present invention also provides an information processing apparatus including any of the above-mentioned communication control systems.

Further, the present invention is a communication control method of a communication control system in which a control device and a controlled device are connected by a bus, the transfer direction of the bus is switched, and bidirectional communication is performed between the control device and the controlled device. When the control device is in a transmission state capable of transmitting predetermined data to the bus and the controlled device is in a reception state capable of receiving predetermined data from the bus, n from the control device. A predetermined request command consisting of the number of bits (n> 1) is transmitted to the controlled device via the bus, the transfer direction of the bus is switched, the control device is in the receiving state, and the controlled device is controlled. After the device is in the transmission state, reply data corresponding to the request command consisting of m (m> 1) bits is transmitted from the controlled device to the control device via the bus, and the control device is transmitted. Of the request commands, the content of the first binary data consisting of a (n> a> 1) bits to be transmitted last, and b (m> b) of the reply data to be transmitted first. It provides a communication control method of a communication control system characterized in that the content of the second binary data consisting of the number of bits of> 1) is the same.

According to the present invention, after transmitting a predetermined request command consisting of n (n> 1) bits from the control device to the controlled device, the transfer direction of the bus is switched and m (m) from the controlled device. When the reply data corresponding to the request command consisting of the number of bits of> 1) is transmitted to the control device, the first one consisting of the number of a (n> a> 1) bits transmitted last of the request commands. Since the content of the binary data and the content of the second binary data consisting of b (m> b> 1) bits of the first transmitted reply data are the same, the control device (master side). Even if the timing to enter the data transmission state occurs in both the controlled device (device) and the controlled device (slave side device), the circuits of the control device (master side device) and the controlled device (slave side device) are destroyed. It is possible to prevent the data transfer efficiency between the control device (master side device) and the controlled device (slave side device) from being lowered.

It is explanatory drawing of one Example of the communication control system using the SPI of this invention. It is a block diagram of one Example of the control device (master side device) of this invention. It is a block diagram of one Example of the controlled device (slave side device) of this invention. It is explanatory drawing of one Example such as a communication timing when a collision does not occur between a control device and a controlled device. It is explanatory drawing of one Example of communication timing at the time of reading a device ID of a controlled device. It is a schematic explanatory diagram of an Example of communication timing and communication sequence when a collision does not occur between a control device and a controlled device. It is a schematic explanatory diagram of an Example of communication timing and communication sequence when a collision occurs between a control device and a controlled device. In the present invention, it is explanatory drawing of the reading timing at the time of reading a device ID stored in a controlled device, and one Example of the data content transmitted from a controlled device and a controlled device. In the present invention, it is a schematic explanatory view of an embodiment of a communication timing and a communication sequence in which a collision occurs but an overcurrent does not flow. In the present invention, it is a schematic explanatory view of an embodiment of a communication sequence in which a command for reading a device ID stored in a controlled device, a device ID data, and a collision occurs but an overcurrent does not flow. In this invention, it is schematic explanatory diagram of one Example of communication timing and communication sequence when a collision does not occur. In the present invention, it is explanatory drawing of the read timing at the time of reading the status register stored in the controlled device, and one Example of the data content transmitted from a controlled device and a controlled device. In the present invention, it is a schematic explanatory view of an embodiment of a communication sequence in which a command for reading a status register stored in a controlled device, status register data, and a collision occurs but an overcurrent does not flow. In the present invention, it is explanatory drawing of the reading timing at the time of reading a setting register stored in a controlled device, and one Example of the data content transmitted from a controlled device and a controlled device. In the present invention, it is explanatory drawing of one Example of the data output circuit which transmits the device ID stored in the controlled device. In the present invention, it is explanatory drawing of one Example of the data output circuit which transmits the status register information stored in the controlled device. In the present invention, it is explanatory drawing of one Example of the data output circuit which transmits the setting register information stored in the controlled device.

Hereinafter, embodiments of the present invention will be described with reference to the drawings. The description of the following examples does not limit the present invention.
The communication control system of the present invention includes a control device having a master-slave relationship (hereinafter, also referred to as a master side device, simply referred to as a master) and a controlled device (hereinafter, also referred to as a slave side device, simply referred to as a slave).
The control device and the controlled device are connected via a set of communication paths, switch the data transfer direction, and perform bidirectional communication. In principle, based on a request from the control device, The controlled device operates.

As a set of communication paths, for example, a bus can be used.
When using a bus, the control device and the controlled device are connected by a bus, the transfer direction of the bus is switched, and bidirectional communication is performed between the control device and the controlled device.

Further, the control device and the controlled device are incorporated in the information processing device, and the information processing device includes the communication control system of the present invention.
In addition, a predetermined function of the information processing device is executed by performing a predetermined data communication between the control device and the controlled device.
The control device mainly includes a CPU that controls the overall operation of the information processing device, and a communication circuit that performs data communication with an external controlled device or the like via an internal bus.
The controlled device mainly includes a control circuit that executes a function that the controlled device is in charge of, and a communication circuit that performs data communication with an external control device or the like via an internal bus.
The controlled device corresponds to, for example, a semiconductor storage element such as a ROM, RAM, or a flash memory, an ASIC, an FPGA, a CPLD, or the like that executes a specific function.
The information processing device corresponds to, for example, a personal computer, a mobile terminal, an image forming device, an image reading device, a digital multifunction device, or the like.

As will be described later, one set of communication paths is a bus composed of a control line for transferring a clock or the like and a data line for transferring the data itself.
The data line is a signal line used by switching the data transfer direction, and half-duplex communication is performed via the data line. The data line may be one signal line or a plurality of signal lines.
As a form of the communication interface of one set of communication paths, various communication interfaces currently used can be used.

For example, as a set of communication paths, the above-mentioned SPI bus, high-speed I2C whose data line is not an open drain connection, or other synchronous serial interface can be used.
Even if it is an SPI bus, a communication interface form such as a single mode SPI bus, a dual mode SPI bus, or a Quad mode SPI bus can be used.
In the following embodiment, the SPI bus in Quad mode (simply also referred to as QuadSPI) will be used as a set of communication paths connecting the control device and the controlled device.
However, the set of communication paths connecting the control device and the controlled device is not limited to the Quad SPI.

<Connection form between control device and controlled device>
FIG. 1 shows an explanatory diagram of an embodiment of a communication control system using the SPI of the present invention.
FIG. 1A shows a schematic explanatory diagram of a communication control system in a connection form using an SPI bus for connecting a control device and a controlled device.
The control device (master) 1 mainly includes a control unit 11, a master communication unit 12, and an internal bus 13 that connects the control unit 11 and the master communication unit 12.
The controlled device (slave) 2 mainly includes a controlled unit 22, a slave communication unit 21, and an internal bus 23 that connects the controlled unit 22 and the slave communication unit 21.
Further, the control device 1 and the controlled device 2 are connected via an SPI bus, and the SPI bus is composed of a control line 31 and a data line 32.

The control unit 11 is a part that controls the operation of the entire control device 1.
The master communication unit 12 is a part that communicates with the controlled device 2 via the SPI bus, and receives data transferred from the controlled device 2 and a data transmission circuit that transmits data to the controlled device 2. It consists of a data reception circuit for receiving data, a switching circuit for switching the data transfer direction, and the like.
The controlled unit 22 is a part that controls the operation of the entire controlled device, and executes the function that the controlled device 2 is in charge of.
The slave communication unit 21 is a part that communicates with the control device 1 via the SPI bus, and is a data transmission circuit that transmits data to the control device 1 and data that receives data transferred from the control device 1. It consists of a receiving circuit and a switching circuit that switches the data transfer direction.

The control line 31 includes a CLK signal line that transmits a clock and a CS signal line that transmits a chip select signal that selects a device to be controlled.
Binary data is transmitted to the data line 32 in synchronization with the clock transmitted to the control line 31.
The binary data is binary data represented by 0 and 1, and the information transmitted via the SPI bus is binarized and transmitted as binary data having a predetermined number of bits combining 0 and 1. To.
The binary data corresponding to 0 and the binary data corresponding to 1 are output to the SPI bus as signals having different voltage levels.

There are various types of information communicated between the control device 1 and the controlled device 2, but in the following embodiments, the information transmitted from the control device 1 to the controlled device 2 is referred to as a request command. ,
Information transmitted from the controlled device 2 to the control device 1 will be described as return data.
The reply data is mainly information corresponding to the request command, and is information requested to be transmitted to the control device 1.
However, the information communicated between the two devices is not limited to what is called a request command or reply data.

For example, when the control device 1 is in a transmission state capable of transmitting predetermined data to the SPI bus, which is a bus, and the controlled device 2 is in a reception state capable of receiving predetermined data from the SPI bus, the control device 1 , A predetermined request command consisting of n (n> 1) bits is transmitted to the controlled device 2 via the SPI bus.
After that, the transfer direction of the SPI bus is switched, the control device 1 is in the receiving state, the controlled device 2 is in the transmitting state, and then the controlled device 2 requests a request consisting of m (m> 1) bits. The reply data corresponding to the command is transmitted to the control device 1 via the bus.

When such a request command and reply data are transmitted and received, in the present invention, the content of the first binary data consisting of a (n>a> 1) bits of the request command to be transmitted last. And, of the reply data, the content of the second binary data consisting of b (m>b> 1) bits to be transmitted first is set to be the same content.
For example, the content of the first binary data and the content of the second binary data are set as binary data corresponding to 0, each consisting of a plurality of bits.
Assuming that the number of bits is 4 bits, the content of the first binary data and the content of the second binary data are set to "0000".

Alternatively, the content of the first binary data and the content of the second binary data are set as binary data corresponding to 1 each consisting of a plurality of bits.
Assuming that the number of bits is 4 bits, the content of the first binary data and the content of the second binary data are set to "1111".

Since the content of the first binary data of the request command and the content of the second binary data of the reply data are the same, both are output to the SPI bus, which is a bus, as a signal of the same voltage level. Will be done.

As will be described later, even if the first binary data of the request command output to the SPI bus and the second binary data of the reply data output to the SPI bus collide with each other on the SPI bus, the first binary data Since both the second binary data and the second binary data are output to the SPI bus as signals of the same voltage level, overcurrent exceeding the standard value does not flow in the circuits of the control device 1 and the controlled device 2, and the data is destroyed. It can be prevented from being done.
In the present invention, it is not necessary to provide a predetermined waiting time when switching the transfer direction of the SPI bus. For example, in the control device 1, after the transmission of the request command is completed, the transfer direction of the SPI bus may be switched to the reception state without providing a waiting time. Therefore, since no waiting time is provided when switching the transfer direction, the transfer efficiency does not decrease.

FIG. 1B shows a schematic explanatory diagram of a communication control system in a connection form using a Quad SPI bus for connecting a control device and a controlled device.
The QuadSPI bus is a bus that includes four data lines.
Here, the control line 31 and the data line 32 of the SPI bus shown in FIG. 1A are represented by signal lines used in the Quad SPI bus.
In the Quad SPI bus, the control line 31 is a CLK signal line that transmits a clock (hereinafter, also simply referred to as CLK) and a CS signal line that transmits a chip select signal that selects a device to be controlled (hereinafter, also simply referred to as CS). Call).

The clock and chip select signals are always transmitted from the control device 1 to the controlled device 2.
Further, the data line 32 is composed of four signal lines (DQ0, DQ1, DQ2, DQ3) for transferring data, and is a signal line capable of transferring data in both directions.
By using four signal lines (DQ0, DQ1, DQ2, DQ3), 4-bit data can be transferred in one clock cycle.

Further, the above-mentioned request command and reply data are transmitted at different timings via the four data lines 32.
When using the QuadSPI bus as a bus, of the request commands transmitted via the four data lines, the first binary data consisting of at least 4 bits or more transmitted at the end and the four data lines Of the reply data transmitted via, the second binary data consisting of at least 4 bits or more initially transmitted is the binary data corresponding to 0 consisting of a plurality of bits, or a plurality of binary data. Binary data corresponding to 1 consisting of the number of bits.

The configuration of the control device 1 and the controlled device 2 is the same as that in FIG. 1A, and the control unit (CPU) 11 of the control device 1 and the master communication unit (SPI-M) 12 are connected to an internal bus (BUS). -M) 13 is connected, and the controlled unit (CNT) 22 of the controlled device 2 and the slave communication unit (SPI-S) 21 are connected by an internal bus (BUS-S) 23.
For example, in a state where the data transmission circuit of the master communication unit (SPI-M) 12 (not shown) is actively set and the data reception circuit of the slave communication unit (SPI-S) 21 (not shown) is actively set. When a chip select signal for selecting the controlled device 2 is transmitted to the CS signal line, four signals are transmitted at the timing when the predetermined 4-bit unit data is synchronized with the clock output to the CLK signal line. It is transferred from the control device 1 to the controlled device 2 via a line (DQ0, DQ1, DQ2, DQ3).

On the contrary, in a state where the data reception circuit of the master communication unit (SPI-M) 12 (not shown) is actively set and the data transmission circuit of the slave communication unit (SPI-S) 21 (not shown) is actively set. , When a chip select signal for selecting the controlled device 2 is transmitted to the CS signal line, four predetermined 4-bit unit data are synchronized with the clock output to the CLK signal line. It is transferred from the controlled device 2 to the control device 1 via the signal lines (DQ0, DQ1, DQ2, DQ3).

Further, the data transmission circuit of the master communication unit (SPI-M) 12 (not shown) is actively set, and the data transmission circuit of the slave communication unit (SPI-S) 21 (not shown) is actively set. In this case, since both the control device 1 and the controlled device 2 are in the transmission state, if data is transferred to each other at the same time, a collision occurs in the four signal lines of the data line 32, and the transferred data is accurate. Cannot be transmitted to.

In particular, in the same signal line (for example, DQ0) of the data lines 32, the transmission signal corresponding to "1" is output from the control device 1 and the transmission signal corresponding to "0" is output from the controlled device 2. If this happens, a collision will occur at the signal line DQ0, and an overcurrent exceeding the standard value will flow through either or both of the actively set data transmission circuits, destroying the data transmission circuit. there is a possibility.

Similarly, on the same signal line DQ0 of the data lines 32, the transmission signal corresponding to "0" is output from the control device 1, and the transmission signal corresponding to "1" is output from the controlled device 2. In this case as well, a collision may occur at the signal line DQ0, an overcurrent exceeding the standard value may flow in one or both of the data transmission circuits, and the data transmission circuit may be destroyed.
That is, when transmission signals having different voltage levels are transmitted on the same signal line among the data lines 32 and a collision occurs, an overcurrent exceeding the standard value flows in the data transmission circuit, and the data transmission circuit becomes It can be destroyed.

When transmission signals having the same voltage level are simultaneously transmitted from the control device 1 and the controlled device 2, data collisions occur in the same manner, but an overcurrent exceeding the standard value flows in both data transmission circuits. There is no possibility that the data transmission circuit will be destroyed. Also, at this time, the data is accurately transmitted to the other party.
That is, when both the control device 1 and the controlled device 2 simultaneously output the transmission signal corresponding to "1" and the transmission signal corresponding to "0" are simultaneously output, data collision occurs. Although it occurs, an overcurrent exceeding the standard value does not flow in the data transmission circuit, and the data transmission circuit is not destroyed.

<Control device configuration>
FIG. 2 shows a block diagram of an embodiment of the control device (master side device) of the present invention.
Here, the control device (master) 1 includes a storage unit 50 connected to the internal bus (BUS-M) 13 in addition to the control unit (CPU) 11 and the master communication unit (SPI-M) 12 described above. Shows things.
Further, a connection unit 14 composed of six connection terminals connecting to each of the six signal lines of the Quad SPI bus is provided, and the data transmission circuit and the data reception circuit of the master communication unit 12 are connected to the connection unit 14.

The storage unit 50 is a memory for temporarily storing data, and for example, a semiconductor storage element such as a RAM or a flash memory capable of reading and writing data, and other storage media are used. However, the storage unit 50 may be provided inside the control unit 11.
Various data such as data to be transferred to the controlled device 2 and data transmitted from the controlled device 2 are stored in the storage unit 50. For example, request data transferred to the controlled device 2 (request). In response to the command), the device ID 51, the status register information 52, the setting register information 53, and the like acquired from the controlled device 2 are stored as reply data.

The device ID 51 is an identification number for uniquely identifying the controlled device 2.
The status register information 52 is information stored in the status register provided in the controlled device 2.
Information indicating the operating state of the controlled device 2 is stored in the status register, and for example, information such as the BUSY status, IDLE status, and unauthorized access detection status during internal access of the controlled device 2 is stored.
The setting register information 53 is information stored in the setting register provided in the controlled device 2.
Information indicating the setting contents of the controlled device 2 is stored in the setting register, and for example, information such as the access space switching setting, the burst access number setting, and the access delay amount setting of the controlled device 2 is stored.

The master communication unit 12 is a part that communicates with the controlled device 2 via the Quad SPI bus, but when divided into functional blocks, it is mainly divided into a data transmission unit 15, a data reception unit 16, and a collision prevention data generation unit 17. Consists of.

The data transmission unit 15 is a part including a data transmission circuit that assembles data to be transmitted to the controlled device 2 and outputs a transmission signal corresponding to the data to the Quad SPI bus.
As described above, the request command is transmitted from the control device 1 to the controlled device 2, and the request command includes, for example, information requesting that the device ID be transmitted to the controlled device 2.
Information that requires transmission of information stored in the status register of the controlled device 2.
It includes information requesting transmission of information stored in the setting register of the controlled device 2.

The data receiving unit 16 is a part including a data receiving circuit that receives a signal transmitted via the Quad SPI bus and acquires received data.
As described above, after the request command is transmitted from the control device 1 to the controlled device 2, the reply data transmitted from the controlled device 2 is received.

For example, when a request command requesting transmission of a device ID is transmitted to the controlled device 2, reply data including the device ID of the controlled device 2 is received.
Further, when a request command requesting transmission of the information stored in the status register is transmitted to the controlled device 2, the reply data including the information stored in the status register of the controlled device 2 is received. ..
When a request command requesting transmission of the information stored in the setting register is transmitted to the controlled device 2, the reply data including the information stored in the setting register of the controlled device 2 is received.

The collision prevention data generation unit 17 generates collision prevention data to be transferred as the last data of a meaningful series of data having a predetermined number of bits when the communication state of the control device 1 is switched from the transmission state to the reception state. This is a part given to the data transmission unit 15.
The collision prevention data is, for example, 4-bit data "0000", and each bit data "0" is output to four data lines (DQ0 to DQ3) at the same timing.

When the collision prevention data generated by the control device 1 is the 4-bit data "0000", the collision prevention data generated by the controlled device 2 described later is also the same 4-bit data "0000".
That is, the collision prevention data output from the control device 1 and the collision prevention data output from the controlled device 2 are set as data (signal values) having the same bit configuration having the same voltage level.

In this way, the collision prevention data output from the control device 1 and the controlled device 2 is set to the data (signal value) having the same bit configuration as the control device 1 and the controlled device 2 as described later. When both are in the transmission state, the collision prevention data output from both may collide with each other on the QuadSPI bus, but even if the collision prevention data collide with each other, the current exceeding the standard value is generated. This is to prevent the data transmission circuit from being damaged by flowing into the data transmission circuit.

Further, since the collision prevention data may be data (signal value) having the same bit configuration, it may be 4-bit data "1111", and each bit data "1" may be four data lines (4 data lines). It is output to DQ0 to DQ3) at the same timing.
However, when the collision prevention data generated by the control device 1 is the 4-bit data "1111", the collision prevention data generated by the controlled device 2 described later is also the same 4-bit data "1111". ..
Therefore, whether to use "0000" or "1111" as the collision prevention data is unified in advance between the control device 1 and the controlled device 2.

In the communication control system using the Quad SPI bus, the number of bits of the collision prevention data is not limited to 4 bits, and may be an integral multiple of 4 such as 8 bits. However, from the viewpoint of transfer efficiency, it is preferable that the number of bits of the collision prevention data is short, so 4 bits is most preferable.

<Configuration of controlled device>
FIG. 3 shows a block diagram of an embodiment of the controlled device (slave side device) of the present invention.
Here, the controlled device (slave) 2 includes a storage unit 70 connected to the internal bus (BUS-S) 23 in addition to the controlled unit (CNT) 22 and the slave communication unit (SPI-S) 21 described above. Shows what you have. The storage unit 70 includes a status register and a setting register.
Further, a connection unit 24 consisting of six connection terminals connected to each of the six signal lines of the Quad SPI bus is provided, and the data transmission circuit and the data reception circuit of the slave communication unit (SPI-S) 21 are connected to the connection unit 24. Be connected.

The storage unit 70 is a memory for storing data, and for example, a semiconductor storage element such as a RAM or a flash memory capable of reading and writing data, and other storage media are used. However, the storage unit 70 may be provided inside the controlled unit (CNT) 22.
Various data such as data to be transferred to the control device 1 and data transmitted from the control device 1 are stored in the storage unit 70. For example, as described above, the device ID 71 unique to the controlled device, Status register information 72, setting register information 73, and the like are stored.
The device ID 71 is data that is set in advance and is not changed, but the status register information 72 and the setting register information 73 change depending on the operating status of the controlled device 2.

The slave communication unit (SPI-S) 21 is a part that communicates with the control device 1 via the Quad SPI bus, but when divided into functional blocks, like the master communication unit 12, mainly the data transmission unit 25 , A data receiving unit 26, and a collision prevention data generating unit 27.
The data transmission unit 25 is a part including a data transmission circuit that assembles data to be transmitted to the control device 1 and outputs a transmission signal corresponding to the data to the Quad SPI bus.
The data receiving unit 26 is a part including a data receiving circuit that receives a signal transmitted via the Quad SPI bus and acquires received data.

As described above, when the request command is transmitted from the control device 1 to the controlled device 2, the reply data corresponding to the request command is transmitted from the controlled device 2 to the control device 1.
For example, when a request command requesting transmission of a device ID is received from the control device 1, the control device 2 transmits reply data including the device ID of the controlled device 2 to the control device 1.

Further, when a request command requesting transmission of the information stored in the status register is received from the control device 1, the controlled device 2 includes the information stored in the status register of the controlled device 2. The reply data is transmitted to the control device 1.
When a request command requesting transmission of the information stored in the setting register is received from the control device 1, the reply data including the information stored in the setting register of the controlled device 2 is received from the controlled device 2. Is transmitted to the control device 1.

The collision prevention data generation unit 27 generates collision prevention data to be transferred as the first data of a meaningful series of data having a predetermined number of bits when the communication state of the controlled device 2 is switched from the reception state to the transmission state. , Is a part given to the data transmission unit 25.
As described above, the collision prevention data output from the controlled device 2 is data (signal value) having the same bit configuration having the same voltage level as the collision prevention data output from the control device 1.

For example, when the collision prevention data output from the control device 1 is 4-bit data "0000", the collision prevention data output from the controlled device 2 is also 4-bit data "0000", and each bit data "0000". "0" is output to four data lines (DQ0 to DQ3) at the same timing.
Alternatively, when the collision prevention data output from the control device 1 is 4-bit data "1111", the collision prevention data output from the controlled device 2 is also 4-bit data "1111", and each bit data "1111". "1" is output to four data lines (DQ0 to DQ3) at the same timing.

<Explanation of communication timing when no collision occurs>
FIG. 4 shows an explanatory diagram of an embodiment such as communication timing when a collision does not occur between the control device and the controlled device.
The communication timing described here is a communication timing of data communication via the Quad SPI bus of the prior art, and is a communication timing provided with a predetermined waiting time T0 when switching the data transfer direction.

FIG. 4A shows an example of data reading timing in which a collision does not occur when the controlled device 2 is a storage device and the control device 1 reads the data stored in the storage device.
In FIG. 4A, DQ [3: 0] is a collective description of the four data lines (DQ0 to DQ3).
FIG. 4B shows an outline of a data communication sequence when no collision occurs.

First, as an initial state, it is assumed that the control device (master) 1 is in the transmission state and the controlled device (slave) 2 is in the reception state.
At this time, when an event to read the data stored in the storage device which is the controlled device (slave) 2 occurs in the control device (master) 1, the control device (master) 1 means a data read request. The command to be executed is output to the QuadSPI bus.
The command consists of a read request command CM and a read address AD in which the data to be read is stored.

When the command consisting of the read request command CM and the read address AD output from the control device (master) 1 is received by the controlled device (slave) 2, the controlled device (slave) 2 stores the command in the read address AD. Read the data (read data DT).
After outputting the command, the control device (master) 1 switches from the transmission state to the reception state while the predetermined waiting time T0 elapses.
On the other hand, the controlled device (slave) 2 reads the data as described above while the predetermined waiting time T0 elapses after receiving the read address AD, and switches from the reception state to the transmission state.
In this way, after the data transfer direction is switched during the predetermined waiting time T0, the data stored in the controlled device (slave) 2 to the control device (master) 1 at the requested address. (Read data DT) is transmitted.

In data communication via the Quad SPI bus, 4-bit data is transmitted every clock cycle.
In FIG. 4A, since the command CM portion is transmitted in two clock cycles, the number of bits of the command CM is 8 bits. Since the read address AD portion is transmitted in 4 clock cycles, the number of bits of the read address AD is 16 bits. Since the read data DT is transmitted in 4 clock cycles, the number of bits of the read data DT is 16 bits.
However, the number of each bit is not limited to the above.
Further, in FIG. 4A, a time of 2 clock cycles is provided as a waiting time T0 when switching the data transfer direction.

Therefore, when the waiting time T0 is provided, the control device (master) 1 and the controlled device (slave) 2 do not enter the transmission state at the same time, so that a collision on the Quad SPI bus does not occur.
However, even if the controlled device (slave) 2 completes reading the read data DT and is ready to output the read data DT quickly, it reads after the two clock cycles provided as the waiting time T0 have elapsed. Since the data DT is transmitted, the transmission timing will be delayed.

<Explanation of communication timing when reading the device ID without providing the waiting time T0>
Even when reading the device ID of the controlled device (slave), if a waiting time T0 is provided when switching the data transfer direction as described above, it is possible to prevent a collision on the QuadSPI bus. ..
Here, it is shown that there is a communication timing in which a collision does not occur in the QuadSPI bus and a communication timing in which a collision occurs when the device ID of the controlled device (slave) is read without providing the waiting time T0.

FIG. 5 shows an explanatory diagram of an embodiment of communication timing when the device ID of the controlled device is read out.
In FIG. 5, a device ID read command having 8 bits is output from the control device (master) in two steps of 4 bits each during 2 clock cycles.
After that, without waiting for the waiting time T0, the device ID having 16 bits is output from the controlled device (slave) in four times of 4 bits each during 4 clock cycles.

The transfer direction switching timing of the control device (master) and the transfer direction switching timing of the controlled device (slave) are almost the same, and the control device (master) and the controlled device (slave) are in the transmission state at the same time. If there is no timing, no collision will occur.
However, if the switching timing of the transfer directions of both is different and the control device (master) and the controlled device (slave) are in the transmission state at the same time, the 4-bit data in the latter half of the device ID read command and the device A conflict may occur with the first 4-bit data of the ID.

(Communication timing when no collision occurs)
FIG. 6 shows a schematic explanatory diagram of an embodiment of communication timing and communication sequence when a collision does not occur between the control device and the controlled device.
FIG. 6A shows changes in the signal state (voltage level) of the clock fall timing T1 and the four data lines DQ [3: 0] of the Quad SPI bus.
For example, in the data line DQ [3: 0] on the control device (master) side, high impedance (hereinafter referred to as Hi-Z) is used from the state in which the data of the signal value "1" is transmitted at the fall timing T1. ) Changes to the reception status. At this time, there is a slight delay time until the voltage level of the data line DQ [3: 0] changes from the transmission state of "1" to the reception state of Hi-Z.

Further, in the data line DQ [3: 0] on the controlled device (slave) side that was in the Hi-Z reception state, for example, a state in which data having a signal value "0" is transmitted from the Hi-Z reception state. As shown in FIG. 6A, it is assumed that the timing of the change to is later than the timing of the change to the Hi-Z reception state in the above control device (master).
In this case, in the data line DQ [3: 0], the timing at which both the master and the slave become high impedance (Hi-Z) occurs at the same time, but the data with the signal value “0” and the signal value “1” There is no timing to output the data of "" at the same time.
That is, in the data line DQ [3: 0], the data of the signal value "0" and the data of the signal value "1" do not collide.

FIG. 6B shows a schematic explanatory diagram of a communication sequence when a collision does not occur as shown in FIG. 6A.
In FIG. 6B, when the control device (master) is in the transmission state and the controlled device (slave) is in the reception state (Hi-Z), the command with the signal value “1” is transmitted from the master. Then, the slave receives the command of this signal value "1".
After transmitting the command with the signal value "1", the master switches the data transfer direction to enter the reception state (Hi-Z).
On the other hand, in the slave, after receiving the command of the signal value "1", the data transfer direction is switched and the transmission state is set.

At this time, if the timing of the reception state (Hi-Z) in the master is earlier than the timing of the transmission state in the slave, no collision occurs in the data line DQ [3: 0], and then from the slave. When the data of the signal value "0" is output, the data of the signal value "0" is received in the master.
That is, a collision may not occur even if the waiting time T0 is not provided at the timing of switching the data transfer direction. However, as shown below, if the waiting time T0 is not provided, a collision may occur.

(Communication timing when a collision occurs)
FIG. 7 shows a schematic explanatory diagram of an embodiment of communication timing and communication sequence when a collision occurs between the control device and the controlled device.
FIG. 7 (a) shows changes in the signal state (voltage level) of the clock fall timing T1 and the four data lines DQ [3: 0] of the Quad SPI bus, as in FIG. 6 (a). ..

However, in FIG. 7A, the data line DQ [3: 0] on the control device (master) side transmits the data of the signal value “1” at a timing slightly delayed from the fall timing T1. It is assumed that the state has changed to a high impedance (hereinafter referred to as Hi-Z) reception state.
At this time, there is a slight delay time until the voltage level of the data line DQ [3: 0] changes from the transmission state of "1" to the reception state of Hi-Z.

Further, in the data line DQ [3: 0] on the controlled device (slave) side that was in the Hi-Z reception state, for example, a state in which data having a signal value "0" is transmitted from the Hi-Z reception state. As shown in FIG. 7A, the timing of the change to is almost the same as the clock fall timing T1, which is earlier than the timing of the change to the Hi-Z reception state in the above control device (master). Suppose.

In this case, in the data line DQ [3: 0], both the master and the slave do not have the timing of becoming high impedance (Hi-Z) at the same time, and the data of the signal value "1" is output from the master. The timing and the timing of outputting the data of the signal value "0" from the slave overlap each other.
That is, in the data line DQ [3: 0], a collision between the data having the signal value “0” and the data having the signal value “1” occurs.

FIG. 7B shows a schematic explanatory diagram of a communication sequence when a collision occurs as shown in FIG. 7A.
In FIG. 7B, when the control device (master) is in the transmission state and the controlled device (slave) is in the reception state (Hi-Z), the command with the signal value “1” is transmitted from the master. Then, the slave receives the command of this signal value "1".
It is assumed that the master has been in the transmission state for a while after transmitting the command with the signal value "1", and then switches the data transfer direction to enter the reception state (Hi-Z).
On the other hand, it is assumed that the slave receives the command with the signal value "1", switches the data transfer direction, puts it in the transmission state, and immediately transmits the data with the signal value "0".
At this time, it is assumed that the timing at which the slave enters the transmission state and transmits the data of the signal value "0" overlaps with the timing at which the master is in the transmission state.

In this way, the timing of the reception state (Hi-Z) in the master is later than the timing of the transmission state in the slave, and the transmission state of the command with the signal value "1" from the master and the signal value "1" from the slave. When the transmission state of the data of "0" is duplicated, a collision occurs.
When the output of the signal value "1" and the output of the signal value "0" collide, an overcurrent flows from the one with the higher voltage level to the one with the lower voltage level, and the overcurrent exceeds the standard value. The data transmission circuit on the side where the current flows may be destroyed.

However, when the master and slave are in the transmission state at the same time when the data transfer direction is switched, if the voltage level of the same signal value is output from both, data collision will occur. An overcurrent exceeding the standard value does not flow in, and the data transmission circuit is not destroyed.
That is, when the master and the slave simultaneously output the voltage level of the signal value "1" or the timing of outputting the voltage level of the signal value "0" at the same time, and a data collision occurs, The data transmission circuit is not destroyed.

Therefore, in the present invention, as shown below, from the viewpoint of preventing the data transfer efficiency from being lowered, the waiting time T0 is not provided at the timing of switching the data transfer direction, but collision is possible at the switching timing. The configuration of the data output from the master and the configuration of the data output from the slave in the probable part are fixedly set to the signal values having the same voltage level. As a result, it is possible to prevent the data transmission circuits in the master communication unit 12 and the slave communication unit 21 from being destroyed.

<Example 1: In the present invention, description of communication timing when reading the device ID>
FIG. 8 shows an explanatory diagram of an embodiment of the read timing when the device ID stored in the controlled device is read, and the data contents transmitted from the control device and the controlled device.
The read timing of the device ID shown in FIG. 8 is substantially the same as the read timing shown in FIG. 5, but the output command and the data structure of a part of the device ID are fixedly set.

Also in FIG. 8, the device ID read command having an 8-bit number is output from the control device (master) in two steps of 4 bits each during the 2 clock cycles.
That is, the device ID read command is executed with the upper 4-bit data COM1 output first.
It is composed of the lower 4-bit data COM2 that is output later.
Further, as shown in FIG. 8A, the data COM2 of the lower 4 bits of the device ID read command is fixedly set to "0000".
This fixedly set data COM2 "0000" corresponds to the collision prevention data.

On the other hand, when the controlled device (slave) receives the device ID read command, the device ID having 16 bits is divided into 4 times by 4 bits from the controlled device (slave) during 4 clock cycles. Is output.
That is, the device ID is composed of four data (DT1, DT2, DT3, DT4) each having a 4-bit configuration.
Further, as shown in FIG. 8A, the data DT1 of the upper 4 bits of the device ID first output from the slave is fixedly set to "0000".
This fixedly set data DT1 "0000" also corresponds to the collision prevention data.

Here, the data COM2 of the lower 4 bits of the device ID read command and the data DT1 of the upper 4 bits of the device ID, which may collide with each other on the data line DQ [3: 0], have the same voltage level signal value " It is "0000".
Even if a collision occurs on the data line DQ [3: 0] when switching the data transfer direction.
Since the signal values "0000" of the same voltage level collide with each other, it is possible to prevent the data transmission circuit from being destroyed.

Alternatively, if the data COM2 of the lower 4 bits of the device ID read command output last from the master and the data DT1 of the upper 4 bits of the device ID first output from the slave have the same voltage level signal value, The data transmission circuit is not destroyed.
Therefore, as shown in FIG. 8B, the data COM2 of the lower 4 bits of the device ID read command and the data DT1 of the upper 4 bits of the device ID may be fixedly set to "1111".

(Explanation of communication timing where collision occurs when reading device ID, but overcurrent does not flow)
FIG. 9 shows a schematic explanatory view of an embodiment of a communication timing and a communication sequence in which a collision occurs but an overcurrent does not flow in the present invention.
As shown in FIG. 8, at the device ID read timing, the lower 4 bit data COM2 of the device ID read command and the upper 4 bit data DT1 of the device ID may collide, but they may collide. Both the data COM2 and the data DT1 that have the potential have, for example, a signal value of the same voltage level "0000".

FIG. 9A shows changes in the signal state (voltage level) of the clock fall timing T2 and the four data lines DQ [3: 0] of the QuadSPI bus, as in FIG. 7A. ..
However, in FIG. 9A, the data line DQ [3: 0] on the control device (master) side transmits data having a signal value of “0” at a timing slightly delayed from the fall timing T2. It is assumed that the state has changed to a high impedance (Hi-Z) reception state.
At this time, there is a slight delay time until the voltage level of the data line DQ [3: 0] changes from the transmission state of "0" to the reception state of Hi-Z.

In addition, the data line DQ [3: 0] on the controlled device (slave) side that was in the Hi-Z reception state changes from the Hi-Z reception state to the state in which the data with the signal value "0" is transmitted. As shown in FIG. 9A, it is assumed that the timing is almost the same as the clock fall timing T2, which is earlier than the timing when the control device (master) changes to the Hi-Z reception state. ..

In this case, in the data line DQ [3: 0], both the master and the slave do not have the timing of becoming high impedance (Hi-Z) at the same time, and the data of the signal value "0" is output from the master. The timing and the timing of outputting the data of the signal value "0" from the slave overlap each other.
That is, in the data line DQ [3: 0], a collision occurs between the data COM2 having the signal value “0” and the data DT1 having the signal value “0”.

FIG. 9B shows a schematic explanatory diagram of a communication sequence when a collision occurs as shown in FIG. 9A.
In FIG. 9B, when the control device (master) is in the transmission state and the controlled device (slave) is in the reception state (Hi-Z), the command of the lower 4 bits of the signal value “0” is sent from the master. When COM2 is transmitted, the slave receives the command COM2 with this signal value "0".
It is assumed that the master transmits the command COM2 with the signal value "0" and then stays in the transmission state for a while, then switches the data transfer direction and enters the reception state (Hi-Z).
On the other hand, it is assumed that the slave receives the command COM2 with the signal value "0", switches the data transfer direction, puts it in the transmission state, and immediately transmits the reply data with the signal value "0".
That is, it is assumed that the reply data DT1 of the first upper 4 bits of the device ID is transmitted.
At this time, it is assumed that the timing at which the slave enters the transmission state and transmits the reply data DT1 having the signal value “0” overlaps with the timing at which the master is in the transmission state.

In this way, the timing of the reception state (Hi-Z) in the master is later than the timing of the transmission state in the slave, and the transmission state of the command COM2 with the signal value "0" from the master and the signal value from the slave. When the transmission state of the data DT1 of "0" overlaps, a collision occurs.
When the output of the command COM2 with the signal value "0" and the output of the data DT1 with the signal value "0" collide, the output values of both are the same voltage level, so even if a data collision occurs, the standard An overcurrent exceeding the value does not flow into the data transmission circuit, and the data transmission circuit is not destroyed.

(Explanation of communication timing when collision occurs when reading device ID)
FIG. 10 shows a schematic explanatory diagram of an embodiment of a communication sequence in which a collision occurs but an overcurrent does not flow with a command for reading a device ID stored in a controlled device and device ID data in the present invention.
FIG. 10A shows a data structure of an embodiment of the device ID read command IDCMD.
This command IDCMD is 8-bit (C0 to C7) data, and the upper 4 bits (C4 to C7) are information "0111" meaning a request to read the device ID, and the lower 4 bits (C0 to C3). ) Is the collision prevention data fixed at "0000".

FIG. 10B shows a data structure of an embodiment of device ID data IDDT.
This device ID data IDDT is 16-bit (D0 to D15) data, but the upper 4-bit DT1 part (D12 to D15) is collision prevention data fixed to "0000", and the lower 12 bits. The part (D0 to D11) of (DT2, DT3, DT4) is the device ID information.
The lower 4 bits (C0 to C3) of the command IDCMD and the upper 4 bits DT1 (D12 to D15) of the device ID data IDDT may be used as collision prevention data fixed to "1111".

FIG. 10 (c) shows a schematic explanatory diagram of an embodiment of a communication sequence in which a collision occurs at the data “0” but an overcurrent does not flow.
In FIG. 10 (c), it is assumed that the control device (master) is in the transmission state and the controlled device (slave) is in the reception state (Hi-Z).
In this state, when the upper 4-bit COM1 of the device ID read command with the signal value "0111" is transmitted from the master in the first clock cycle, the slave receives the upper 4-bit COM1 "0111" of this command. To.

Further, in the next one clock cycle, when the lower 4-bit COM2 of the device ID read command with the signal value “0000” is transmitted from the master, the lower 4-bit COM2 “0000” of this command is received by the slave.
It is assumed that the master transmits the lower 4-bit COM2 of the command with the signal value "0000", and then stays in the transmission state for a while, then switches the data transfer direction and enters the reception state (Hi-Z).

On the other hand, it is assumed that the slave receives the lower 4-bit COM2 of the signal value "0000", switches the data transfer direction, puts it in the transmission state, and immediately transmits the upper 4-bit DT1 of the device ID of the signal value "0000". ..
At this time, it is assumed that the timing at which the slave enters the transmission state and transmits the data DT1 having the signal value "0000" overlaps with the timing at which the master is in the transmission state.

In this way, the timing of the reception state (Hi-Z) in the master is later than the timing of the transmission state in the slave, and the transmission state of the command COM2 with the signal value "0000" from the master and the signal value from the slave. When the transmission state of the data DT1 of "0000" overlaps, a collision occurs at the data signal value "0000".
When the output of the command COM2 with the signal value "0000" and the output of the data DT1 with the signal value "0000" collide, the output values of both are the same voltage level, so even if a data collision occurs, the standard An overcurrent exceeding the value does not flow into the data transmission circuit, and the data transmission circuit is not destroyed.

After that, when the master switches to the reception state (Hi-Z), if the subsequent data (DT2 to DT4) of the device ID is transmitted from the slave in the transmission state, the subsequent data (DT2) is transmitted in the master. DT4) is received from.
The data DT1 with the first signal value "0000" has a timing at which the outputs of the master and the slave collide, but since the voltage levels are the same, the master can correctly receive the data DT1.

FIG. 15 shows an explanatory diagram of an embodiment of a data output circuit that transmits a device ID stored in a controlled device in the present invention.
This data output circuit is composed of a shift register that outputs the above-mentioned 16-bit device IDs (D0 to D15) by 4 bits at a time.
For example, the shift register consists of 16 D flip-flops, which are connected as shown in FIG. 15, and the 16-bit device IDs (D0 to D15) are divided into 4 bits and input to the D flip-flops. After that, in synchronization with the falling edge of the clock CLK, data for every 4 bits is sequentially output to the 4 data lines DQ [3: 0] of the QuadSPI bus and transmitted to the master.
In FIG. 15, the signal values corresponding to the 4 bits of IDData [12] to [15] are output as 0 and correspond to the data DT1.

(Explanation of communication timing that does not cause a collision when reading the device ID)
FIG. 11 shows a schematic explanatory view of an embodiment of the communication timing and the communication sequence when no collision occurs in the present invention.

FIG. 11 (a) shows changes in the signal state (voltage level) of the clock fall timing T2 and the four data lines DQ [3: 0] of the Quad SPI bus, as in FIG. 9 (a). ..
However, in FIG. 11A, the data line DQ [3: 0] on the control device (master) side has high impedance (from the state where the data of the signal value “0” is transmitted at the fall timing T2. It is assumed that the reception status of Hi-Z) has changed.
At this time, there is a slight delay time until the voltage level of the data line DQ [3: 0] changes from the transmission state of "0" to the reception state of Hi-Z.

In addition, the data line DQ [3: 0] on the controlled device (slave) side that was in the Hi-Z reception state changes from the Hi-Z reception state to the state in which the data with the signal value "0" is transmitted. As shown in FIG. 11A, the timing of the clock is slightly delayed from the clock fall timing T2, which is later than the timing when the above control device (master) changes to the Hi-Z reception state. To do.

In this case, in the data line DQ [3: 0], the timing at which both the master and the slave become high impedance (Hi-Z) occurs at the same time. Further, the timing of outputting the data of the signal value "0" from the master and the timing of outputting the data of the signal value "0" from the slave do not overlap.
That is, in the data line DQ [3: 0], the collision between the data COM2 having the signal value “0” and the data DT1 having the signal value “0” does not occur.

FIG. 11B shows a schematic explanatory diagram of a communication sequence when a collision does not occur as shown in FIG. 11A.
In FIG. 11B, when the control device (master) is in the transmission state and the controlled device (slave) is in the reception state (Hi-Z), a command of the lower 4 bits of the signal value “0” is sent from the master. When COM2 is transmitted, the slave receives the command COM2 with this signal value "0".
It is assumed that the master immediately switches the data transfer direction after transmitting the command COM2 with the signal value "0" and enters the reception state (Hi-Z).

On the other hand, it is assumed that the slave receives the command COM2 with the signal value "0", then switches the data transfer direction, puts it in the transmission state, and transmits the data with the signal value "0". That is, it is assumed that the data DT1 of the first upper 4 bits of the device ID is transmitted.
At this time, it is assumed that the timing at which the slave enters the transmission state and transmits the data DT1 having the signal value “0” is after the master enters the reception state (Hi-Z).

In this way, the timing of the reception state (Hi-Z) at the master is earlier than the timing of the transmission state at the slave, and the timing at which both the master and the slave become high impedance (Hi-Z) occurs at the same time. If the transmission state of the command COM2 with the signal value "0" from the master and the transmission state of the data DT1 with the signal value "0" from the slave do not overlap, no collision occurs.
If no collision occurs, the command COM2 with the signal value "0" from the master and the data DT1 with the signal value "0" from the slave are normally received.

<Example 2: In the present invention, description of communication timing when reading the status register>
FIG. 12 shows an explanatory diagram of an embodiment of the read timing when reading the status register stored in the controlled device and the data contents transmitted from the controlled device and the controlled device in the present invention.
As for the read timing in FIG. 12, a status register read command is output from the master, and the contents of the status register are output from the slave that receives this command.

In FIG. 12, a status register read command having an 8-bit number is output from the control device (master) in two steps of 4 bits each during 2 clock cycles.
That is, the status register read command is composed of the upper 4-bit data COM1 output first and the lower 4-bit data COM2 output later.
Further, as shown in FIG. 12A, the data COM2 of the lower 4 bits of the status register read command is fixedly set to "0000".
This fixedly set data COM2 "0000" corresponds to the collision prevention data.

On the other hand, when the controlled device (slave) receives the status register read command, the status register information having 8 bits from the controlled device (slave) is transmitted twice by 4 bits in 2 clock cycles. It is output separately.
That is, the status register information is composed of two data (ST1 and ST2) each having a 4-bit configuration.
Further, as shown in FIG. 12A, the data ST1 of the upper 4 bits of the status register information first output from the slave is fixedly set to "0000".
This fixedly set data ST1 "0000" also corresponds to the collision prevention data.

Here, the lower 4 bits of data COM2 of the status register read command and the upper 4 bits of data ST1 of the status register information, which may collide with each other on the data line DQ [3: 0], have the same voltage level signal value. It is "0000".
Even if a collision occurs on the data line DQ [3: 0] when switching the data transfer direction.
Since the signal values "0000" of the same voltage level collide with each other, it is possible to prevent the data transmission circuit from being destroyed.

Alternatively, if the lower 4 bits of data COM2 of the status register read command output last from the master and the upper 4 bits of data ST1 of the status register information first output from the slave are signal values of the same voltage level. , The data transmission circuit is not destroyed.
Therefore, as shown in FIG. 12B, the lower 4 bits of data COM2 of the status register read command and the upper 4 bits of data ST1 of the status register information may be fixedly set to "1111". ..

(Explanation of communication timing when a collision occurs when reading the status register)
FIG. 13 shows a schematic explanatory diagram of an embodiment of a communication sequence in which a command for reading a status register stored in a controlled device, status register data, and a collision occurs but an overcurrent does not flow in the present invention.
FIG. 13A shows a data structure of an embodiment of the status register read command STCMD.
This command STCMD is 8-bit (C0 to C7) data, but the upper 4 bits (C4 to C7) are information "0100" meaning a status register read request, and the lower 4 bits (C0 to C3). ) Is the collision prevention data fixed at "0000".

FIG. 13B shows a data structure of an embodiment of the status register data STDT.
This status register data STDT is 8-bit (S0 to S7) data, but the upper 4-bit ST1 part (S4 to S7) is collision prevention data fixed to "0000", and the lower 4 bits. The ST2 part "1001" (S0 to S3) is the status register information.
The lower 4 bits (C0 to C3) of the command STCMD and the upper 4 bits ST1 (S4 to S7) of the status register data STDT may be used as collision prevention data fixed to "1111".

FIG. 13 (c) shows a schematic explanatory diagram of an embodiment of a communication sequence in which a collision occurs at the data “0” but an overcurrent does not flow.
In FIG. 13 (c), it is assumed that the control device (master) is in the transmission state and the controlled device (slave) is in the reception state (Hi-Z).
In this state, when the upper 4-bit COM1 of the status register read command with the signal value "0100" is transmitted from the master in the first clock cycle, the slave receives the upper 4-bit COM1 "0100" of this command. To.

Further, in the next one clock cycle, when the lower 4-bit COM2 of the status register read command of the signal value "0000" is transmitted from the master, the lower 4-bit COM2 "0000" of this command is received by the slave.
It is assumed that the master transmits the lower 4-bit COM2 of the command with the signal value "0000", and then stays in the transmission state for a while, then switches the data transfer direction and enters the reception state (Hi-Z).

On the other hand, it is assumed that the slave receives the lower 4-bit COM2 of the signal value "0000", switches the data transfer direction, puts it in the transmission state, and immediately transmits the upper 4-bit ST1 of the status register of the signal value "0000". ..
At this time, it is assumed that the timing at which the slave is in the transmission state and the data ST1 having the signal value “0000” is transmitted overlaps with the timing at which the master is in the transmission state.

In this way, the timing of the reception state (Hi-Z) in the master is later than the timing of the transmission state in the slave, and the transmission state of the command COM2 with the signal value "0000" from the master and the signal value from the slave. When the transmission state of the data ST1 of "0000" overlaps, a collision occurs at the signal value "0000" of the data.
When the output of the command COM2 with the signal value "0000" and the output of the data ST1 with the signal value "0000" collide, the output values of both are the same voltage level, so even if a data collision occurs, the standard An overcurrent exceeding the value does not flow into the data transmission circuit, and the data transmission circuit is not destroyed.

After that, when the master is switched to the reception state (Hi-Z), if the data SDT2 "1001" in the latter half of the status register is transmitted from the slave in the transmission state, the data ST2 is received in the master.
The data DT1 with the first signal value "0000" has a timing at which the outputs of the master and the slave collide, but since the voltage levels are the same, the master can correctly receive the data DT1.

FIG. 16 shows an explanatory diagram of an embodiment of a data output circuit that transmits status register information stored in the controlled device in the present invention.
This data output circuit is composed of a shift register that outputs the above-mentioned 8-bit status registers (S0 to S7) by 4 bits at a time.
For example, the shift register consists of 16 D flip-flops shown in FIG. 16, but an 8-bit status register (S0 to S7) is divided into 4 bits and input to the 8 D flip-flops, and then , In synchronization with the falling edge of the clock CLK, data for every 4 bits is sequentially output to the four data lines DQ [3: 0] of the QuadSPI bus and transmitted to the master.

In FIG. 16, the lower 4 bits ST2 (S0 to S3) of the status register are signal values corresponding to the 4 bits from [0] to [3] of the Status Data, and are input to the four D flip-flops. The upper 4-bit ST1 (S4 to S7) of the status register is input to another four D flip-flops as a fixed 0.

<Example 3: Description of communication timing when reading the setting register in the present invention>
FIG. 14 shows an explanatory diagram of an embodiment of the read timing when reading the setting register stored in the controlled device and the data contents transmitted from the controlled device and the controlled device in the present invention.
In the setting register, for example, the waiting time of the read process via the internal bus of the controlled device is set.
As for the read timing of FIG. 14, a setting register read command is output from the master, and the contents of the setting register are output from the slave that receives this command.

In FIG. 14, a setting register read command having an 8-bit number is output from the control device (master) in two steps of 4 bits each during 2 clock cycles.
That is, the setting register read command is composed of the upper 4-bit data COM1 output first and the lower 4-bit data COM2 output later.
Further, as shown in FIG. 14A, the data COM2 of the lower 4 bits of the setting register read command is fixedly set to "0000".
This fixedly set data COM2 "0000" corresponds to the collision prevention data.

On the other hand, when the controlled device (slave) receives the setting register read command, the set register information having 16 bits from the controlled device (slave) is changed to 4 times by 4 bits in 4 clock cycles. It is output separately.
That is, the setting register information is composed of four data (SR1, SR2, SR3, SR4) each having a 4-bit configuration.
Further, as shown in FIG. 14A, the data SR1 of the upper 4 bits of the setting register information first output from the slave is fixedly set to "0000".
This fixedly set data SR1 "0000" also corresponds to the collision prevention data.

Here, the data COM2 of the lower 4 bits of the setting register read command and the data SR1 of the upper 4 bits of the setting register information, which may collide with each other on the data line DQ [3: 0], have the same voltage level signal value. It is "0000".
Even if a collision occurs on the data line DQ [3: 0] when switching the data transfer direction.
Since the signal values "0000" of the same voltage level collide with each other, it is possible to prevent the data transmission circuit from being destroyed.

Alternatively, if the data COM2 of the lower 4 bits of the setting register read command output last from the master and the data SR1 of the upper 4 bits of the setting register information first output from the slave are signal values of the same voltage level. , The data transmission circuit is not destroyed.
Therefore, as shown in FIG. 14B, the lower 4 bits of the data COM2 of the setting register read command and the upper 4 bits of the data SR1 of the setting register information may be fixedly set to "1111". ..

The communication sequence in which the command to read the setting register stored in the controlled device and the setting register data are transmitted and received, and a collision occurs but an overcurrent does not flow is the same as the communication sequence shown in FIGS. 10 and 13. The explanation is omitted.

FIG. 17 shows an explanatory diagram of an embodiment of a data output circuit that transmits setting register information stored in a controlled device in the present invention.
This data output circuit is composed of a shift register that outputs the above-mentioned 16-bit setting registers (SR1, SR2, SR3, SR4) by 4 bits at a time.
For example, the shift register consists of 16 D flip-flops shown in FIG. 17, but "0000" is input to the D flip-flop corresponding to SR1 as the upper 4 bits (SR1) of the setting register, and the rest. The 12-bit setting registers (SR2, SR3, SR4) are divided into 4 bits and input to 12 D flip-flops, and then synchronized with the falling edge of the clock CLK, sequentially every 4 bits. The data is output to the four data lines DQ [3: 0] of the QuadSPI bus and transmitted to the master.

In FIG. 17, the lower 12 bits (SR2, SR3, SR4) of the setting register are RegA [0] to [3], RegB [0] to [3], and RegC [0] to [3], respectively. It is a signal value corresponding to 4 bits up to 3] and is input to 4 different D flip-flops, and the upper 4 bits SR1 of the setting register is input to another 4 D flip-flops as a fixed 0. To.

1 Control device (master),
2 Controlled device (slave),
11 Control unit,
12 Master Communication Department,
13 Internal bus,
14 Connection part (connection terminal),
15 Data transmitter,
16 Data receiver,
17 Collision prevention data generator,
21 Slave communication unit,
22 Controlled unit,
23 Internal bus,
24 Connection part (connection terminal),
25 Data transmitter,
26 Data receiver,
27 Collision prevention data generator,
31 control line,
32 data lines,
50 storage,
51 device ID,
52 Status register information,
53 Setting register information,
70 storage,
71 device ID,
72 Status register information,
73 Setting register information

Claims (10)

A communication control system that connects a control device and a controlled device in a master-slave relationship by a bus, switches the transfer direction of the bus, and performs bidirectional communication between the control device and the controlled device.
After transmitting a predetermined request command consisting of n (n> 1) bits from the control device to the controlled device via the bus, the transfer direction of the bus is switched from the controlled device. , When the reply data corresponding to the request command consisting of m (m> 1) bits is transmitted to the control device via the bus,
Of the request commands, the content of the first binary data consisting of a (n>a> 1) bits to be transmitted last, and b (m>) of the reply data to be transmitted first. A communication control system characterized in that the contents of the second binary data having the number of bits of b> 1) are the same. The communication control system according to claim 1, wherein the content of the first binary data and the content of the second binary data are output to the bus as a signal having the same voltage level. The contents of the first binary data and the contents of the second binary data are both binary data corresponding to 0 consisting of a plurality of bits, or
The communication control system according to claim 1, wherein the binary data corresponds to 1 composed of a plurality of bits. The bus is a Quad SPI (Serial Peripheral Interface) bus containing four data lines.
The communication control system according to claim 1, wherein the request command and the reply data are transmitted at different timings via four data lines. Of the request commands transmitted via the four data lines, the first binary data consisting of at least 4 bits or more transmitted last, and the reply transmitted via the four data lines. Of the data, the second binary data consisting of at least 4 bits or more that is transmitted first is
The communication control system according to claim 4, wherein the binary data corresponds to 0 having a plurality of bits, or the binary data corresponds to 1 consisting of a plurality of bits. The controlled device stores a device ID for identifying the controlled device in advance, and stores the device ID.
When a request command including information requesting that the device ID is transmitted is transmitted from the control device to the controlled device.
The communication control system according to claim 1, wherein reply data including a device ID of the controlled device is transmitted from the controlled device to the control device. The controlled device includes a status register that stores information indicating the operating state of the controlled device.
When a request command requesting transmission of information stored in the status register is transmitted from the control device to the controlled device,
The communication control system according to claim 1, wherein reply data including information stored in a status register of the controlled device is transmitted from the controlled device to the control device. The controlled device includes a setting register that stores information indicating the setting contents of the controlled device.
When a request command requesting transmission of information stored in the setting register is transmitted from the control device to the controlled device,
The communication control system according to claim 1, wherein reply data including information stored in a setting register of the controlled device is transmitted from the controlled device to the control device. An information processing device including the communication control system according to any one of claims 1 to 8. A communication control method for a communication control system in which a control device and a controlled device are connected by a bus, the transfer direction of the bus is switched, and bidirectional communication is performed between the controlled device and the controlled device.
When the control device is in a transmission state capable of transmitting predetermined data to the bus and the controlled device is in a reception state capable of receiving predetermined data from the bus.
A predetermined request command consisting of n (n> 1) bits is transmitted from the control device to the controlled device via the bus.
After switching the transfer direction of the bus, the control device is in the receiving state, and the controlled device is in the transmitting state.
Reply data corresponding to the request command consisting of m (m> 1) bits is transmitted from the controlled device to the control device via the bus.
Of the request commands, the content of the first binary data consisting of a (n>a> 1) bits to be transmitted last, and b (m>) of the reply data to be transmitted first. A communication control method of a communication control system, characterized in that the contents of the second binary data having the number of bits of b> 1) are the same.