JP2000047766A - Method and device for parallel data transmission, and method and device for collision prevention in parallel bus system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method and device for parallel data transmission and a collision preventing method in a parallel bus system using an intermediate- distance parallel bus which can perform a high-speed operation in the parallel bus system and improve the reliability at a low cost. SOLUTION: To the parallel bus (system bus) 30 connected to a CPU base 10, extension bases 20-1 to 20-N (extension bases ξ1 to #N) are connected through multidrop buses 40-1 to 40-N and on the parallel bus 30 in the respective extension bases 20-1 to 20-N, bidirectional buffers 23-1 to 23-(N-1) are provided and suppress multiple reflection of data on the parallel bus 30, thereby improving the high-speed operation and reliability of the parallel bus 30 when the intermediate-distance parallel bus 30 is used.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method and apparatus for parallel data transmission and a method and apparatus for preventing collision in a parallel bus system, and more particularly, to connecting a plurality of extension bases to a parallel bus connected to a main base. The present invention relates to a parallel data transmission method and apparatus in which a bidirectional buffer is provided on a parallel bus in the extension base and multiple reflection of data on the parallel bus is prevented by the bidirectional buffer, and a collision prevention method and apparatus in a parallel bus system.

[0002]

2. Description of the Related Art Conventionally, in a programmable logic controller or the like, a plurality of extension bases constituting an extension base are connected to a CPU base constituting a main base via a parallel bus so as to be extendable. Techniques for configuring a system are known.

FIG. 7 is a system configuration diagram showing an example of a programmable logic controller system configured by connecting a plurality of extension bases to a conventional CPU base via a parallel bus so as to be extendable.

In FIG. 7, a programmable logic controller system includes a plurality of parallel buses (system buses) 30 connected to a CPU base 10 via multi-drop buses 40-1, 40-2,. , 20-N (additional bases # 1 to #N) are connected.

Here, a CPU base 10 constitutes a main base of the programmable logic controller system, and the CPU base 10 includes a CPU.
A unit 11, an I / O unit, and the like are accommodated.

Further, the extension bases 20-1, 20-2,
, 20-N are connected to the CPU base 10 so as to be extendable, and each of the plurality of I / O units 21-N.
-1 to 21-N are accommodated.

[0007]

By the way, in a conventional multi-drop programmable logic controller system as shown in FIG.
For example, the CPU base 10 and a plurality of extension bases 20-1, 20-2,.
20-N (extension bases # 1 to #N) and operating this parallel bus 30 at high speed,
.., 20-N causes so-called multiple reflections, which causes a problem that the reliability of the parallel bus 30 is significantly reduced.

In order to solve the problem of the multiple reflection, there has been proposed a configuration for terminating the parallel bus 30 in each of the extension bases 20-1, 20-2,..., 20-N.
In this case, another problem that the cost of the whole system becomes high occurs.

Accordingly, an object of the present invention is to provide a parallel data transmission method and apparatus capable of improving high-speed operation and reliability at a low cost in a parallel bus system using a medium-distance parallel bus. .

Further, the present invention prevents data collision based on a transmission delay of a bus read enable signal for switching a transmission direction of data transmitted between a main base and an extension base transmitted from a main unit. An object of the present invention is to provide a method and an apparatus for preventing collision in a parallel bus system as described above.

[0011]

To achieve the above object, according to the first aspect of the present invention, a plurality of extension bases are connected to a parallel bus connected to a main base, and a plurality of extension bases are connected to the main base. In the parallel data transmission method for transmitting data via the parallel bus between the parallel buses, a bidirectional buffer is provided on the parallel bus in the extension base, and multiple reflection of data on the parallel bus is prevented by the bidirectional buffer. It is characterized by having done.

According to a second aspect of the present invention, in a parallel data transmission apparatus in which a plurality of extension bases are connected to a parallel bus connected to a main base, multiple reflections of data on the parallel bus are provided in the extension bases. It is characterized in that a bidirectional buffer is provided for prevention.

According to a third aspect of the present invention, in a main base to which a plurality of extension bases are connected via a parallel bus, multiple reflection of data on the parallel bus is prevented on the parallel bus in the main base. Characterized in that a bidirectional buffer is provided.

According to a fourth aspect of the present invention, in the extension base connected to the parallel bus connected to the main base, multiple reflection of data on the parallel bus is prevented on the parallel bus in the extension base. Characterized in that a bidirectional buffer is provided.

Therefore, according to the present invention, a plurality of extension bases are connected to the parallel bus (system bus) connected to the CPU base 10 via the multi-drop bus, and both extension bases are provided on the parallel bus in each extension base. Since the bidirectional buffer is provided, the multiple reflection of data on the parallel bus can be suppressed by the bidirectional buffer, thereby improving the high-speed operation and reliability of the parallel bus when using a medium-distance parallel bus. Can be improved.

According to another aspect of the present invention, there is provided a semiconductor device comprising:
According to the invention described above, a plurality of extension bases each accommodating an extension unit are connected in cascade via a parallel bus connected to a main base accommodating a main unit, and the parallel bus is connected between the main unit and the extension unit. In the parallel bus system which performs bidirectional data transmission via the main base or the extension base, data transmitted between the main base and the extension base from a bus read enable signal transmitted from the main unit in the main base or the extension base And a bus gate control signal for disabling the bidirectional buffer is transmitted from the main unit at a timing when the bus read enable signal changes, and the parallel bus is transmitted. Prevent data collision Characterized in that it was.

According to a sixth aspect of the present invention, a plurality of extension bases each accommodating an extension unit are connected via a parallel bus connected to a main base accommodating the main unit, and the main unit and the extension unit are connected. In a parallel bus system that performs bidirectional data transmission via the parallel bus between and when reading data from an extension unit accommodated in the extension base, data from the lower extension base is blocked, A collision between data read from the extension unit and data from the lower extension base is prevented.

According to a seventh aspect of the present invention, in the main unit accommodated in a main base connecting a plurality of extension bases accommodating an extension unit via a parallel bus, the main unit or the extension base is provided. A bus read enable signal generating means for generating a bus read enable signal for switching a transmission direction of data transmitted on the parallel bus with respect to the enableable bidirectional buffer provided in the bus, and a bus read enable signal generating means. And a bus gate control signal generating means for generating a bus gate control signal for disabling the bidirectional buffer with respect to the bidirectional buffer at a timing when the bus read enable signal changes.

According to a further aspect of the present invention, there is provided an extension unit accommodated in an extension base connected to a main base accommodating a main unit via a parallel bus. A unit selection signal generating means for generating a unit selection signal for blocking data from the lower extension base when reading data from the extension unit accommodated in the extension base for the direction buffer. .

Therefore, according to the present invention, a buffer having an enable terminal is used as a bidirectional buffer, and the bidirectional buffer is disabled using the bus gate control signal at the timing when the bus read enable signal causing data collision changes. And the switching between the read direction and the write direction of the bidirectional buffer is performed after the data buses are all set to the high impedance (High-Z) state, so that the state in which the bus read enable signal applied to the bidirectional buffer is different. Even if it occurs, data collision does not occur on the data bus, thereby enabling access to the extension unit without data collision.

[0021]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment of a parallel data transmission method and apparatus according to the present invention;

FIG. 1 is a system configuration diagram showing an embodiment of a programmable logic controller system configured by applying a parallel data transmission method and apparatus and a collision prevention method and apparatus in a parallel bus system according to the present invention.

In FIG. 1, portions that perform the same functions as those of the conventional programmable logic controller system shown in FIG. 7 are denoted by the same reference numerals as those used in FIG. 7 for convenience of explanation.

In the programmable logic controller system according to the present invention shown in FIG. 1, a parallel bus (system bus) 30 connected to the CPU base 10 is provided.
Via the multi-drop buses 40-1 to 40-N, a plurality of extension bases 20-1 to 20-N (extension bases # 1 to ##).
N), and each of the extension bases 20-1 to 20-20.
-N on the parallel bus 30 in the
To 23- (N-1).
1 to 23- (N-1) suppress multiple reflection of data on the parallel bus 30, thereby improving the high-speed operation and the reliability of the parallel bus 30 when the medium-distance parallel bus 30 is used. Be composed.

That is, in FIG. 1, in the programmable logic controller system, the multi-drop bus 40- is connected to the parallel bus 30 connected to the CPU base 10 similarly to the conventional programmable logic controller system shown in FIG. 1, 40-
2, a plurality of extension bases 20-1 through 40-N,
, 20-N (additional bases # 1 to #N) are connected.

The CPU base 10 constitutes a main base of the programmable logic controller system.
The unit 11, the I / O unit 12, and the like are accommodated, and the extension bases 20-1, 20-2,..., 20-N have a plurality of I / O units 21-1 to 21-N, respectively.
Is housed.

However, in the programmable logic controller system shown in FIG. 1, unlike the conventional programmable logic controller system shown in FIG. 7, the bidirectional buffer 13 is provided on the parallel bus 30 in the CPU base 10. , 20-N, the bidirectional buffers 23-1 and 23-2 on the parallel bus 30 respectively.
3-2,... 23- (N-1) are provided, and the multi-drop buses 40-1, 40-2,.
, N on the bidirectional buffers 22-1, 22-2,.
22-N are provided.

In the programmable logic controller system shown in FIG. 1, the parallel bus 30 is connected to the extension bases 20-1 and 20 by the bidirectional buffers 23-1, 23-2,..., 23- (N-1). -2,
, 20-N, and the parallel bus 30 and the multi-drop buses 40-1, 40-2,... By the bidirectional buffers 22-1, 22-2,.
40-N, thereby forming a daisy-chain parallel bus.

According to such a configuration, the bidirectional buffer 13 and the bidirectional buffers 23-1, 23-2,.
.., 20-N on the parallel bus 30 is suppressed, and the bidirectional buffers 22-1, 22-
2, ... 22-N, each extension base 20-1, 20-
2,..., 20-N, the reflection of data to the parallel bus 30 is suppressed.

Thereby, the reliability of the parallel bus 30 is improved, and the bidirectional buffers 23-1, 23-2,.
(N-1) and the bidirectional buffers 22-1, 22-2,
.. 22-N, the parallel data transfer on the parallel bus 30 becomes possible at about 7 to 10 times that of the conventional programmable logic controller system.

The bidirectional buffers 13 and the bidirectional buffers 23-1, 23-2,... 23- (N-1) and the bidirectional buffers 22-1, 22-2,. ., 23- (N-1) and the bidirectional buffers 22-1, 22-2. ,..., 22-N can be minimized.

Now, in the case of employing a daisy chain type parallel bus as shown in FIG.
The CPU unit 11 of the base 10 is an extension base 20-
, 20-N, when reading / writing data from / to the I / O units 21-1 to 21-N, the bidirectional buffer 13 and the bidirectional buffers 23-1 , 23-2, ..., 23- (N-1) and the bidirectional buffers 22-1, 22-2, ..., 22-N, use a bus read enable signal RD generated by the CPU unit 11.

However, using the bus read enable signal RD generated by the CPU unit 11, the bidirectional buffer 13 and the bidirectional buffers 23-1, 23-2,.
3- (N-1) and bidirectional buffers 22-1, 22-
2,... When the method of switching the direction of 22-N is adopted, if the distance of the parallel bus 30 is increased, the transmission delay of the bus read enable signal RD causes a delay in the parallel bus 30.
When data is switched from the read direction to the write direction, data collision occurs on the data bus.

FIG. 2 is a diagram for explaining data collision caused by transmission delay of the bus read enable signal RD.

In FIG. 2, 23-A and 23-B
Denotes a bidirectional buffer provided on the parallel bus 30, 30-1 denotes a data bus (DATA bus) in the parallel bus 30, and 30-2 denotes a bus read enable signal in the parallel bus 30. 5 shows a control signal line for transmitting RD.

Here, due to the transmission delay of the bus read enable signal RD by the control signal line 30-2 in the parallel bus 30, the bus read enable signal RD applied to the terminal Dir of the bidirectional buffer 23-A becomes high level (H
It is assumed that the bus read enable signal RD applied to the terminal Dir of the bidirectional buffer 23-B remains at the high level (High) despite the switching from the (high) to the low level (Low).

In this case, the write direction and the read method of the bidirectional buffer 23-A and the bidirectional buffer 23-B are opposite to each other, and the data between the bidirectional buffer 23-A and the bidirectional buffer 23-B are exchanged. A data collision occurs on the bus 30-1.

When such data collisions overlap, the bidirectional buffer 13 and each of the bidirectional buffers 23-1, 23-2
-2,... 23- (N-1) and bidirectional buffer 22-
, 22-2,..., 22-N may cause deterioration of the buffer IC, thereby reducing the reliability of the device.

In order to prevent this, a configuration has been proposed in which a resistor is serially connected to the buffer IC to suppress overcurrent due to data collision. However, when this method is adopted, the number of parts increases, An adverse effect on the cost / performance of the bus due to signal delay or the like becomes a problem.

Therefore, in the following embodiment, the bidirectional buffer 13 and each of the bidirectional buffers 23-1, 23-
2, ... 23- (N-1) and bidirectional buffer 22-
, 22-2,..., 22-N are used, and at the timing when the bus read enable signal RD at which data collision occurs changes using the bus gate control signal RDZ, Bidirectional buffers 23-1, 23-2,... 2
3- (N-1) and bidirectional buffers 22-1, 22-
2,... 22-N are disabled, and all data buses 30-1 are high impedance (High-Z).
From the state, the read direction and write direction of the bidirectional buffer 13 and the bidirectional buffers 23-1, 23-2,..., 23- (N-1) and the bidirectional buffers 22-1, 22-2,. Is configured to be switched.

FIG. 3 shows a bus gate control signal RD at the timing when the bus read enable signal RD changes.
FIG. 9 is a block diagram showing a configuration in which a bidirectional buffer is disabled using Z.

In FIG. 3, 23-A and 23-B
Denotes a bidirectional buffer provided on the parallel bus 30 and having an enable terminal En.
-1 indicates a data bus (DATA bus) in the parallel bus 30, 30-2 indicates a control signal line for transmitting a bus read enable signal RD in the parallel bus 30,
Reference numeral 30-3 denotes a control signal line for transmitting the bus gate control signal RDZ in the parallel bus 30.

Here, the CPU unit 11 of the CPU base 10 controls the bus gate control signal RDZ to a high level (High) for a predetermined time when the bus read enable signal RD changes. As a result, the bidirectional buffer 23-A and the bidirectional buffer 23-B are disabled and the data bus 3
0-1 are all in a high impedance (High-Z) state. Therefore, even if the bus read enable signal RD applied to the terminal Dir of the bidirectional buffer 23-A and the bidirectional buffer 23-B is different, this state occurs. Therefore, no data collision occurs on the data bus 30-1.

FIG. 4 is a timing chart showing a state in which the bidirectional buffer is disabled using the bus gate control signal RDZ at the timing when the bus read enable signal RD changes in the configuration shown in FIG.

As shown in FIG. 4A, at the timing when the bus read enable signal RD changes,
As shown in (b), the bus gate control signal RD
Since Z becomes a high level (High), FIG.
As shown in FIG.
Is high level, the data bus 30-1 is in a high impedance (High-Z) state, so that the bus read enable signal RD applied to the terminals Dir of the bidirectional buffers 23-A and 23-B. Does not occur, data collision does not occur on the data bus 30-1 in this state.

FIG. 5 is a circuit diagram showing a specific configuration of a programmable logic controller system employing the configuration shown in FIG.

Referring to FIG. 5, the programmable logic controller system includes a CPU unit 101,
The I / O unit 102 and the I / O unit 103 are configured by connecting an extension base 200 that accommodates the I / O unit 201 and the I / O unit 202 to the CPU base 100 that accommodates the I / O unit 103 by bus cables 300-1 and 300-2. You.

Here, the CPU unit 101 accommodated in the CPU base 100 has an ASIC 101-1 that interfaces with the CPU base 100, and the I / O unit 102 has an interface with the CPU base 100. The I / O unit 103 includes a CPU base 100.
ASIC 103-1 that interfaces with the ASIC 103-1.

The I / O accommodated in the extension base 200
The O unit 201 has an ASIC 201-1 that interfaces with the extension base 200.
The / O unit 202 has an ASIC 202-1 that interfaces with the extension base 200.

In FIG. 5, an address data bus signal AD is a signal which is transmitted between the CPU base 100 and the extension base 200 and indicates a master-slave address and data.

The bus read enable signal RD is
A signal output from the CPU unit 101 of the CPU base 100 is used for the I / O unit 201 of the extension base 200.
And 202 are signals used for read enable and data bus direction switching.

The bus write enable signal WR is
A signal output from the CPU unit 101 of the CPU base 100 is used for the I / O unit 201 of the extension base 200.
And 202 are signals used for write enable.

The bus gate control signal RDZ
Is a signal output from the CPU unit 101 of the CPU base 100, a signal used to prevent data collision when switching the direction of the data bus, or an address data bus to the extension base 200 when the CPU base 100 is accessed at high speed. This signal is used to prevent the signal AD and the bus address strobe signal AS from being output.

The unit selection signal SEL is supplied to the CPU
I / O unit 201 or 202 of base 100 or I / O unit 201 or 2 of extension base 200
02, the I / O unit 201 or 202 of the CPU base 100 or the I / O of the extension base 200
This signal is output from the unit 201 or 202, and is used to block a signal from the lower base when reading from the own rack.

Now, referring to FIG.
Is configured to include a one-way buffer 111, an OR circuit 112, and a bidirectional buffer 113.

Here, the one-way buffer 111 has a CPU
A bus gate control signal RDZ output from the ASIC 101-1 of the unit 101;
ASIC 101-1 or I / O unit 102
Bus write enable signal WR output from the ASIC 102-1 of the CPU unit 101;
-1 or ASIC 102 of I / O unit 102
The bus read enable signal RD output from 1 is input, and the output is sent to the bus cable 300-2.

The bidirectional buffer 113 stores the bus gate control signal RDZ output from the ASIC 101-1 of the CPU unit 101 and the I / O unit 1
02 ASIC 102-1 or I / O unit 10
3 is applied to the terminal G via the OR circuit 112 and the ASIC 101-1 of the CPU unit 101 or the bus read output from the ASIC 102-1 of the I / O unit 102. An enable signal RD is applied to a terminal D, and an address data bus signal AD output from the ASIC 101-1 of the CPU unit 101, the ASIC 102-1 of the I / O unit 102, or the ASIC 103-1 of the I / O unit 103 is input. At the same time, the signal of the bus cable 300-1 is input.

The extension base 200 includes a one-way buffer 211, a two-way buffer 212, and a one-way buffer 21.
3, an OR circuit 214 and a bidirectional buffer 215.

Here, the one-way buffer 211 receives the signal of the bus cable 300-2 and converts the bus read enable signal RD and the bus write enable signal WR to the I signal.
201-1 and I / O of I / O unit 201
Output to the ASIC 201-2 of the unit 202.

The bidirectional buffer 212 has a terminal G to which the bus gate control signal RDZ output from the one-way buffer 211 is applied and a terminal D
ASIC 201-1 or I / O of O unit 201
The bus read enable signal RD output from the ASIC 201-2 of the unit 202 is applied, and the signal of the bus cable 300-1 or the AS of the I / O unit 201 is applied.
ASI of IC 201-1 or I / O unit 202
Address data bus signal A output from C201-2
D is input.

The one-way buffer 213 receives a signal from the bus cable 300-2 and sends its output to another extension base (not shown).

The bidirectional buffer 215 is connected to the terminal G by the bus gate control signal RDZ output from the one-way buffer 211 or by the AS of the I / O unit 201.
ASI of IC 201-1 or I / O unit 202
The unit selection signal SEL output from the C201-2 is applied via the OR circuit 214, and the bus read enable signal R output from the one-way buffer 211 is applied to the terminal D.
D is applied, and a signal of the bus cable 300-1 or an address data bus signal AD from another extension base (not shown) is input.

Here, the bidirectional buffer 113 of the CPU base 100 corresponds to the bidirectional buffer 23 -A shown in FIG.
Corresponds to the bidirectional buffer 23-B shown in FIG.

That is, the bidirectional buffer 113 and the bidirectional buffer 215 have a bus direction switching terminal D and an enable terminal G, respectively.
01 is applied to each bus direction switching terminal D, and the bus gate control signal RDZ output from the ASIC 101-1 of the CPU unit 101 is applied to each enable terminal G. Have been.

The ASIC of the CPU unit 101
101-1 controls the bus gate control signal RDZ to a high level (High) for a predetermined time at the timing when the bus read enable signal RD changes, as shown in FIG. As a result, the bidirectional buffer 113 and the bidirectional buffer 212 are controlled to be disabled, whereby the bus line 300-1 enters a high impedance (High-Z) state, and the transmission delay of the bus read enable signal RD causes the bidirectional buffer to be deactivated. Even if the bus read enable signal RD applied to the terminal 113 of the bidirectional buffer 113 differs from the state of the bus read enable signal RD, data collision does not occur on the bus line 300-1 in this state.

In the configuration shown in FIG. 5, the I / O unit 201 or 202 accommodated in the extension unit 200 is connected to the enable terminal G of the bi-directional buffer 212 of the extension unit 200 and the unit generated when the data is read. The selection signal SEL is applied, so that the I / O unit 20 accommodated in the extension unit 200
When reading 1 or 202, data from the lower extension base (not shown) is blocked and the I / O unit 20
It is configured such that the read data from 1 or 202 does not collide with the data from the lower base.

That is, when data is read from the I / O unit 201 or 202 accommodated in the extension unit 200, this I / O unit 201 or 20
The I / O unit 201 or 202 accommodated in the extension unit 200 is selected and data is read from the I / O unit 201 or 202 so that the read data from the extension unit 2 does not collide with the data from the lower extension unit. In this case, the ASIC of each of the I / O units 201 or 202 sets the unit selection signal SEL to a high level (High), and thereby the bidirectional buffer 212
The direction is switched.

The relationship between the bus read enable signal RD, bus gate control signal RDZ, unit selection signal SEL applied to the bidirectional buffer 212 and the operation of the bidirectional buffer 212 is as follows.

1) Address / write data for extension base DL = L, RDZ = L, SEL = L In this case, address / write data flows from the upper base to the lower base.

2) Read data from the lower base DL = H, RDZ = L, SEL = L In this case, read data from the lower base flows to the upper base.

3) Read data from own base DL = H, RDZ = L, SEL = H In this case, read data from the lower base is cut off,
Read data from the own base flows to the upper base.

4) At the time of direction switching RDZ = H In this case, the bus line becomes high impedance,
It becomes low level by pull-down.

The above operation is shown in FIG.

As described above, in the present invention, the parallel bus (system bus) 3 connected to the CPU base 10
0 through a plurality of extension bases 20-1 to 20-N (extension bases # 1 to
#N) and connect each extension base 20-1 to 20-2.
0-N, a bidirectional buffer 23-
1 to 23- (N-1), the multiple reflection of data on the parallel bus 30 can be suppressed by the bidirectional buffers 23-1 to 23- (N-1). The high-speed operation and the reliability of the parallel bus 30 when the middle-distance parallel bus 30 is used can be improved.

[0075]

As described above, according to the present invention, a plurality of extension bases are connected to a parallel bus (system bus) connected to the CPU base 10 via a multi-drop bus, and a plurality of extension bases are connected to each other. Since a bidirectional buffer is provided on the parallel bus, multiple reflection of data on the parallel bus can be suppressed by the bidirectional buffer. High-speed operation and reliability can be improved.

Further, according to the present invention, a buffer with an enable terminal is used as a bidirectional buffer, and at the timing when the bus read enable signal at which data collision occurs changes, the bidirectional buffer is used by using the bus gate control signal. Since the control is disabled and the data buses are all switched to a high impedance (High-Z) state, the read direction and the write direction of the bidirectional buffer are switched, the bus read enable signal applied to the bidirectional buffer is different. Even if the state occurs, data collision does not occur on the data bus, thereby providing an effect that it is possible to access the extension unit without data collision.

[Brief description of the drawings]

FIG. 1 is a system configuration diagram showing an embodiment of a programmable logic controller system configured by applying a parallel data transmission method and device and a collision prevention method and device in a parallel bus system according to the present invention.

FIG. 2 is a diagram illustrating data collision caused by a transmission delay of a bus read enable signal RD.

FIG. 3 is a block diagram showing a configuration in which a bus gate control signal RDZ is used to disable a bidirectional buffer at a timing when a bus read enable signal RD changes.

4 is a timing chart showing a state in which a bidirectional buffer is disabled using a bus gate control signal RDZ at a timing when a bus read enable signal RD changes in the configuration shown in FIG. 3;

FIG. 5 is a circuit diagram showing a specific configuration of a programmable logic controller system employing the configuration shown in FIG. 4;

FIG. 6 is a diagram showing a data flow by controlling a bidirectional buffer connected to an I / O unit in the extension unit shown in FIG. 5;

FIG. 7 is a system configuration diagram showing an example of a programmable logic controller system in which a plurality of extension bases are connected to a conventional CPU base so as to be extendable via a parallel bus.

[Explanation of symbols]

Reference Signs List 10 CPU base 11 CPU unit 12 I / O unit 21-1 to 21-N I / O unit 20-1, 20-2, ..., 20-N Extension base (extension base # 1 to #N) 22-1, 22-2,..., 22-N bidirectional buffer 23-1, 23-2,..., 23- (N-1) bidirectional buffer 23-A, 23-B bidirectional buffer 30 parallel bus 30-1 data bus (DATA) Bus) 30-2, 30-3 Control signal lines 40-1, 40-2, ..., 40-N Multi-drop bus 100 CPU base 101 CPU unit 101-1 ASIC 102 I / O unit 102-1 ASIC 103 I / O unit 103-1 ASIC 111 One-way buffer 102 OR circuit 113 Bidirectional buffer 200 Extension base 201 I / O unit 201 1 ASIC 202 I / O unit 201-1 ASIC 211 one-way buffer 212 bidirectional buffer 213 one-way buffer 214 OR circuit 215 bidirectional buffer

Claims (8)

[Claims] 1. A parallel data transmission method for connecting a plurality of extension bases to a parallel bus connected to a main base and performing data transmission between the main base and the extension base via the parallel bus. A parallel data transmission method, wherein a bidirectional buffer is provided on the parallel bus in an extension base, and multiple reflection of data on the parallel bus is prevented by the bidirectional buffer. 2. A parallel data transmission apparatus in which a plurality of extension bases are connected to a parallel bus connected to a main base, wherein a bidirectional buffer for preventing multiple reflection of data on the parallel bus is provided in the extension base. A parallel data transmission device, characterized in that: 3. A main base to which a plurality of extension bases are connected via a parallel bus, wherein a bidirectional buffer for preventing multiple reflection of data on the parallel bus is provided on the parallel bus in the main base. Main base characterized by. 4. An extension base connected to a parallel bus connected to a main base, wherein a bidirectional buffer for preventing multiple reflection of data on the parallel bus is provided on the parallel bus in the extension base. Extension base characterized by. 5. A plurality of extension bases each accommodating an extension unit are connected in cascade via a parallel bus connected to a main base accommodating a main unit, and the parallel bus is connected between the main unit and the extension unit. In a parallel bus system that performs bidirectional data transmission via a bus, data transmitted between the main base and the extension base from a bus read enable signal transmitted from the main unit to the main base or the extension base An enable bidirectional buffer for switching the transmission direction of the bus, a bus gate control signal for disabling the bidirectional buffer is transmitted from the main unit at a timing when the bus read enable signal changes, and the parallel bus is transmitted. Prevent data collision A method for preventing collision in a parallel bus system, wherein the method is stopped. 6. A plurality of extension bases each accommodating an extension unit are connected via a parallel bus connected to a main base accommodating a main unit, and the parallel bus is connected between the main unit and the extension unit. In a parallel bus system that performs bidirectional data transmission through the extension base, when reading data from the extension unit accommodated in the extension base, data from the lower extension base is blocked, and data is read from the extension unit. A collision prevention method in a parallel bus system, wherein collision between data and data from the lower extension base is prevented. 7. A main unit accommodated in a main base that connects a plurality of extension bases accommodating an extension unit via a parallel bus, wherein the enableable bi-directional device is provided in the main base or the extension base. Bus read enable signal generating means for generating a bus read enable signal for switching a transmission direction of data transmitted on the parallel bus to the buffer; and the bus read enable signal generated by the bus read enable signal generating means changes. And a bus gate control signal generating means for generating a bus gate control signal for disabling the bidirectional buffer with respect to the bidirectional buffer at a timing when the main unit is in the parallel bus system. 8. An extension unit accommodated in an extension base connected to a main base accommodating a main unit via a parallel bus, wherein said extension base is provided in said extension base and is capable of being enabled. And a unit selection signal generating means for generating a unit selection signal for blocking data from the lower extension base when reading data from the extension unit accommodated in the parallel bus system.