JP2000315128A - Bus control system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To realize the speed-up of a bus cycle. SOLUTION: Registers Ra 11, Rb 12, Rc 13, Rd 14 for limiting currents allowed to flow into respective devices (A) 1, (B) 2, (C) 3, (D) 4 are connected to a data bus, and in the case of switching the bus cycle of respective devices 1 to 4, the bus cycle is switched without setting up an idle cycle for preventing the collision of bus signals.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus control system for controlling a bus connecting a plurality of devices.

[0002]

2. Description of the Related Art FIG. 8 is a diagram showing the configuration of a conventional bus control system between a plurality of devices disclosed in Japanese Patent Application Laid-Open No. 10-97496. In the figure, 101 is a microcomputer, 102 is a processor, 103 is a bus control unit, and 104, 105, and 106 are external devices.
A device, a second device, and an n-th device.

Next, the operation will be described. Processor 1
02 is the core logic of the microcomputer 101,
It controls the entire microcomputer 101. Further, the processor 102 outputs an address A with the bus control unit 103, inputs and outputs data Di, outputs a high-active read command Rdi, a write command Wri, and a STARTi indicating a start timing of a bus cycle,
All these signals are given to the bus control unit 103 once. Note that the signal name ending with "i" is
2 shows internal signals of the microcomputer 101.

[0004] The bus control unit 103 refers to the address A by itself and outputs it to the outside as it is. Data Di
With respect to the above, the bus control unit 103 functions as a data transceiver, and becomes data D on an external data bus. The bus control unit 103 also includes a read command * RD, a write command * WR, START indicating a start timing of a bus cycle, the first device 104, the second device 105, and the n-th device.
It outputs the select signals CS1, CS2, CSn of the device 106. Here, a signal with “*” means LOW active.

[0005] Further, the bus control unit 103 includes the first device 1
For example, if a device with a long output disable time is read in one bus cycle, the device can be idle before starting the next bus cycle to avoid data collision. Insert a cycle (buffer period).

[0006]

Since the conventional bus control system is configured as described above, when the connection between the devices is switched or when the signal flow is changed, each device may be changed depending on the connection timing. There is a possibility that the buffer outputs output from the bus to the bus may interfere with each other or collide with each other. Therefore, there are special cycles such as providing idle cycles for idling and adjusting the direction timing of each bus control in the direction control. There was a problem that a device was required and the bus cycle became longer.

In particular, after reading a device having a long output disable time, in order to avoid collision of bus data,
Before starting the next bus cycle, an idle cycle must be inserted, and the insertion of the idle cycle causes a problem that the bus cycle becomes longer.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problems, and has as its object to obtain a bus control system which realizes a high-speed bus cycle by eliminating an idle cycle conventionally inserted. I do.

[0009]

A bus control system according to the present invention controls a bus connecting a plurality of devices, and includes a resistor for limiting a current flowing through each of the devices.
When connecting to the bus corresponding to each device and switching a bus cycle between the devices, the bus cycle is switched without setting an idle cycle for preventing a collision of bus signals.

In the bus control system according to the present invention, the resistance connected to the bus limits the current so that the current flowing to each device at the time of a bus collision becomes equal to or less than the current rating of each device.

In the bus control system according to the present invention, a resistor is connected to a data bus for transmitting data.

In the bus control method according to the present invention, a resistor is connected to an address bus for transmitting an address.

In the bus control system according to the present invention, the mode periods of the bus cycle at the time of switching are overlapped.

In the bus control method according to the present invention, another resistor is connected to a part of the bus between the resistors corresponding to the device, and the output of the first device connected to the bus is connected to the bus. The value of the resistor corresponding to the device and the value of the other resistor are set so that the output of the third device connected to the bus becomes dominant with respect to the input of the second device. Set the value.

In the bus control system according to the present invention, a controllable resistor is connected as a resistor corresponding to the device.

The bus control method according to the present invention is based on an instruction regarding priority from a first device connected to a bus.
The resistance value of the controllable resistor corresponding to the second device connected to the bus is set.

In the bus control system according to the present invention, the controllable resistor corresponding to the second device is constituted by a plurality of fixed resistors and a multiplexer for selecting the plurality of fixed resistors. An instruction related to the priority from the first device is set in a register, and the multiplexer selects the fixed resistor based on the instruction set in the register, whereby a controllable type corresponding to the second device is selected. This sets the resistance value of the resistor.

In the bus control system according to the present invention, another resistor is connected to a part of the bus between the resistors corresponding to the device, and the resistor corresponding to the third device connected to the bus is connected to the other device. A capacitor is connected between the connection point of the resistor and the ground, and the output of the first device connected to the bus is connected to the second device connected to the bus.
The value of the resistor corresponding to the device, the value of the other resistor so that the output of the first device does not dominate the input of the third device, ,
And the capacity value.

In a bus control method according to the present invention, wherein a bus for connecting a plurality of devices is controlled, a resistor for limiting a current flowing through each device is installed in each device and connected to the bus. In the case where the bus cycle is switched between the above-described devices by connecting the bus cycles to each other, the bus cycle is switched without setting an idle cycle for preventing a collision of a bus signal.

In the bus control system according to the present invention, the resistance connected in the buffer limits the current so that the current flowing to each device at the time of a bus collision becomes equal to or less than the current rating of each device.

In the bus control system according to the present invention, a resistor is connected in a buffer connected to a data bus for transmitting data.

In the bus control system according to the present invention, a resistor is connected in a buffer connected to an address bus for transmitting an address.

In the bus control system according to the present invention, another resistor is connected on a part of the bus between the resistors in each buffer, and the resistance in the buffer of the third device connected to the bus and the other resistor are connected. A capacitor is connected in the buffer of the third device between the connection point of the resistor and the ground, and the output of the first device connected to the bus is connected to the input of the second device connected to the bus. And the value of the resistor in the buffer, the value of the other resistor, and the value of the capacitance such that the output of the first device does not dominate the input of the third device. Set the value.

[0024]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a diagram showing a configuration of a bus control system according to a first embodiment of the present invention.
Devices 2, 3, and 4 are devices (A), devices (B), devices (C), and devices (D) connected to a common bus, respectively.
Reference numeral 5 denotes a buffer control means built in the device (A) 1.

In FIG. 1, 6, 7, 8, and 9 are:
Apparatus (A) 1, Apparatus (B) 2, Apparatus (C) 3,
A buffer Bff (A), a buffer Bff, which is built in the device (D) 4 and is controlled by the buffer control means 5 for electrically connecting to a bus for the address A and the data D;
(B), buffer Bff (C), buffer Bff (D)
It is. 11, 12, 13, and 14 are resistors Ra, R that are connected on the data bus and limit the current flowing through each device.
b, Rc and Rd.

In FIG. 1, A is an address on the address bus, D is data on the data bus, and * R
D is a read command, * WR is a write command, STA
RT is a bus cycle start timing signal, CS1, CS
2, Csn is the device (A) 1, the device (B) 2,
This is a select signal for selecting the device (C) 3 and the device (D) 4. Among these signals, a read command * RD, a write command * WR, a bus cycle start timing signal START, and select signals CS1, CS2, Csn are:
Output from the buffer control means 5. Here, a signal with “*” means LOW active.

Next, the operation will be described. Apparatus (A) 1
The buffer control means 5 in the buffer Bff (A)
6, buffer Bff (B) 7, buffer Bff (C)
8, the control of the connection of the buffer Bff (D) 9 and the control of the connection direction are performed.
The f (C) 8 and the buffer Bff (D) 9 connect or disconnect with the bus based on the select signals CS1, CS2, Csn, the read command * RD and the write command * WR from the buffer control means 5, Switch between input and output by changing the direction of signal flow.

Here, a case where the device (A) 1 switches the bus cycle from the read cycle to the write cycle with respect to the device (B) 2 will be described. In describing the bus cycle, the following assumptions are made to facilitate understanding. 30n bus cycle unit time
s, the read cycle for the device (A) 1 with respect to the device (B) 2 is 60 ns, the write cycle is 60 ns, and the device (B)
The output disable time of No. 2 is 10 ns. Further, as the output current rated value of the data pin of the device (A) 1 and the device (B) 2, the HIGH output current value is 100 mA, LOW.
The output current value is 100 mA, and the power supply voltage is 5 V.

The output signal of the device (B) 2 continues to be output on the data bus after the end of the read cycle 60 ns until the end of the output disable time 10 ns. Here, when the write cycle starts continuously, the device (A)
1 starts outputting a signal on the data bus, so that 10 ns
, Bus data collision occurs. There is no problem when data of the same logical value is output by chance, but when data of different logical values is output, a collision of bus data occurs.

That is, a bus data collision occurs, and the data pin of the device (A) 1 and the data pin of the device (B) 2 become "H" and "L", respectively, and the resistors Ra11 and Rb12
Is 0 ohms, a short-circuit occurs, exceeding the rated current value, and giving an impact that causes a decrease in long-term reliability. Therefore, generally, an idle cycle of 30 ns is inserted between the read cycle and the write cycle. Therefore, it takes 60 + 30 + 60 = 150 ns to complete the read cycle and the write cycle.

Here, the inserted resistors Ra11 and Rb12
Are 100 ohms each, I =
From V / R, the current flowing through the data pins of the devices (A) 1 and (B) 2 is I = (5 / (100 + 100)) × 1
000 = 25 (mA). This value corresponds to the value of the device (A) 1
And the output current rating for the data pin of the device (B) 2 is within the above-mentioned range, so that no special problem occurs due to the collision of the bus data.

As described above, the inserted resistors Ra11 and Rb
The value of 12 may be set so as not to exceed the rated output current value of the data pin. That is, when the power supply voltage is 5 V, (resistance Ra11 + resistance Rb12) may be set so that 5 / (resistance Ra11 + resistance Rb12) <100.

When switching from the read cycle to the write cycle, the output disable period 1 of the device (B) 2
During the 0 ns period, the data on the data bus is indefinite, but if the output data of the device (A) 1 can be determined on the data bus during the remaining 20 ns of the unit time 30 ns of the bus cycle, this bus data collision occurs. You can design a bus without having to worry about time. In this case, the total time of the read cycle and the write cycle is 60 + 60 = 120 ns, and the idle cycle 30 ns which has been conventionally inserted can be reduced.

In the above example, the devices (A) 1 and (B)
The case where the read cycle is switched from the read cycle to the write cycle between the two devices has been described. However, when the content of the bus cycle is switched between other devices, the idle cycle 30 ns can be similarly reduced. For example, switching from the bus cycle connecting the device (A) 1 to the device (B) 2 to the bus cycle connecting the device (A) 1 and the device (C) 3, In the control for switching to the bus cycle in which the direction is reversed, the bus control is performed by setting the idling period to avoid the collision of the bus signal between these bus cycles to zero or intentionally overlapping the mode period in the bus cycle. Can be speeded up.

In the embodiment shown in FIG. 1, the resistors Ra11, Rb12, Rc13 and Rd14 are connected on the data bus. Can be faster.

As described above, according to the first embodiment, even if data or address collision occurs on the data bus or the address bus, the current flowing on the data bus or the address bus is reduced by the data pin. Alternatively, by connecting a resistor so as not to exceed the output current rated value of the address pin, the idle cycle conventionally inserted is reduced, and the mode period in the bus cycle is overlapped, thereby realizing a high speed bus cycle. The effect that a bus control method can be obtained is obtained.

Embodiment 2 FIG. 2 is a diagram showing a configuration of a bus control system according to a second embodiment of the present invention. In the figure, reference numeral 15 denotes a resistor Rm connected on a bus between the resistors Rb12 and Rc13, and 16 denotes a resistor Rc13 and a resistor Rc13. Rd
14 is a resistor Rn connected on the bus. Va,
Vb, Vc, and Vd are voltages at the connection points of the device (A) 1, the device (B) 2, the device (C) 3, and the device (D) 4, respectively, and Vm is the voltage at the connection point of the resistors Ra11 and Rm15. Voltage. Other reference numerals are the same as those in FIG. 1 of the first embodiment. In this embodiment, connection is performed by increasing the connection priority between the device (A) 1 and the device (B) 2.

Next, the operation will be described. Here, device (A) 1, device (B) 2, device (C) 3, device (D) 4
The output voltage as “H” is VoutH, the voltage as “L” is VoutL, the voltage whose input can be regarded as “H” is VinH, and the voltage which can be regarded as “L” is VinL.
And Generally, in order to ensure the connection, these voltage relationships include a margin voltage VMM, and VoutH = VinH + VMM VoutL = VinL−VMM.

In the bus cycle, when the device (A) 1 functions as an input, the output voltage Vb of the device (B) 2
Are the output voltages Vc and Vd of the devices (C) 3 and (D) 4, respectively.
Resistances Ra11, Rb1
2, Rc13, Rd14, Rm15, Rn16 are determined.

That is, although the voltages Vc and Vd of the devices (C) 3 and (D) 4 will be VoutH, VoutL
However, when the output of the device (B) 2 is at VoutH, Va> VinH is satisfied, and when the output of the device (B) 2 is at VoutL, Va <VinL is satisfied. At this time, the margin voltage V
The larger the MM, the more freely the resistance value to be inserted can be set.

As an extreme example, the resistance values Ra = 0, Rb =
If 0, the voltage Vb = VoutH> VinH and the voltage Vb = VoutL <VinL can be satisfied regardless of the values of Vc and Vd.

Next, the device (A) 1 receives an input, and the device (B)
2. In the case where the device (C) 3 outputs, a general value of the inserted resistor will be described. When the device (A) 1 is an input, the input impedance is considered to be large, and the voltage V
m = Va, and the value of the voltage Vm satisfies the following condition (1),
By selecting each resistance value so as to satisfy (2), a connection having a priority is established between the devices (A) and (B) 2.

If the voltage Vb of the device (B) 2 is VoutH, the device (A) 1 will surely have the voltage Vb ( V
In order to receive (outH), as condition (1), Vm = (VoutH−VoutL) × (Rc + Rm) /
(Rc + Rm + Rb) + VoutL is set to a value larger than VinH. Here, Vout
H is the voltage of Vb, and VoutL is the voltage of Vc.

If the voltage Vb of the device (B) 2 is VoutL, the device (A) 1 will surely have the voltage Vb ( V
In order to receive (outL), as condition (2), Vm = (VoutH−VoutL) × Rb / (Rc + R)
m + Rb) + VoutL is set to a value smaller than VinL. Here, Vout
H is the voltage of Vc, and VoutL is the voltage of Vb.

Even in a bus cycle in which the device (A) 1 outputs, when Va = VoutH, similarly,
That is, when "H", that is, the voltages Vc and Vd of the device (C) 3 and the device (D) 4 are VouH regardless of Vo.
The input of the device (B) 2 is set so as to satisfy VinH> Vb, even when Va = VoutL, even if it is utL. At this time, the margin voltage VM
The larger M is, the more freely the resistance value can be set.

As an extreme example, the resistance values Ra = 0, Rb =
If it is set to 0, the device (A) 1 and the device (B) 2 can be connected preferentially as described above.

In such a connection, the connection between the device (A) 1 and the device (C) 3 or the connection between the device (A) 1 and the device (D) 4
When changing the connection bus cycle from the connection bus cycle to the connection bus cycle between the device (A) 1 and the device (B) 2, the connection priority is set in advance to the device (A) 1 and the device (B) 2 being high. In the case of logic, even if a collision of bus signals occurs due to a change in bus connection, idling is not particularly provided if the devices (A) 1 and (B) 2 have priority. , It is possible to implement the connection directly.

By setting the resistance values to be inserted as described above, the outputs of the devices (C) 3 and (D) 4 are forcibly forced without being set to high impedance by cutting off the output buffer control. The connection of the device (B) 2 can be executed at the same time, and the control logic can be reduced and the buffer itself can be omitted while ensuring data transmission.

As described above, according to the second embodiment, the resistance is connected on the bus to reduce the idle cycle conventionally inserted or to overlap the mode period in the bus cycle to thereby reduce the bus cycle. In addition to realizing a high-speed cycle, by setting the resistance value appropriately, it is possible to provide a connection priority between certain devices, and it is possible to reduce the control load of device selection. .

Embodiment 3 FIG. 3 is a diagram showing a configuration of a bus control system according to a third embodiment of the present invention. In the figure, reference numeral 23 denotes a capacitance Cd connected between a connection point between the resistors Rn16 and Rd14 and the ground. Other reference numerals are the same as those in FIG. 2 of the second embodiment.

Next, the operation will be described. Apparatus (A) 1
3, the connection between the device (A) 1 and the device (D) 4 is predominantly delayed by connecting a capacitor Cd23 with a time constant (Ra + Rm + Rn) × Cd, as shown in FIG. By setting << (Rm + Rn), the apparatus (A) 1 and the apparatus (B) are relatively
The output of the device (A) 1 can be transmitted to the device (B) 2 by giving a priority to the connection between the two.

As described above, according to the third embodiment, the resistance is connected on the bus to reduce the idle cycle conventionally inserted or to overlap the mode period in the bus cycle to thereby reduce the bus cycle. Cycles can be accelerated, and by connecting a capacitor on the data bus and setting the resistance value and the capacitance value appropriately, it is possible to set the priority of connection between certain devices and to select the device. The effect that the control load can be reduced can be obtained.

Embodiment 4 FIG. 4 is a diagram showing a configuration of a bus control system according to a fourth embodiment of the present invention, wherein resistors Ra11, Rb12, and Rc1 in FIG.
3 and Rd14 into buffers Bff (A) 6 and B
ff (B) 7, Bff (C) 8, and Bff (D) 9.

In the example of FIG. 4, the resistors Ra11, Rb12,
Although Rc13 and Rd14 are incorporated in the respective buffers, the capacitance Cd23 in the third embodiment is
It may be incorporated in the buffer Bff (D) 9 together with d14.

As described above, according to the fourth embodiment, the resistor is built in the buffer connected to the bus to reduce the idle cycle conventionally inserted or to exceed the mode period in the bus cycle. By wrapping, it is possible to realize a high-speed bus cycle, and it is not necessary to dispose a resistor capable of withstanding a bus signal collision on the board wiring, so that the board wiring length can be shortened and the wiring delay can be reduced. The effect is obtained.

Also, by incorporating a resistor and a capacitor in the buffer, connection priority can be provided between certain devices, the control load for selecting devices can be reduced, and the wiring length of the substrate can be shortened. Thus, the effect that the wiring delay can be reduced can be obtained.

Embodiment 5 FIG. 5 is a diagram showing a configuration of a bus control system according to a fifth embodiment of the present invention. In the figure, reference numerals 32, 33, and 34 denote devices (B) 2, devices (C) 3, and devices (D) 4, respectively. Are controllable resistors Rbc, Rcc, and Rdc.

In this embodiment, the resistors Rb12, Rc13, and Rd14 of the second embodiment shown in FIG. 2 are replaced with controllable resistors Rbc32, Rcc33, and Rdc34.
3, The value of Rdc34 is determined based on the set connection priority. As a result, the priority of each device can be easily set by adjusting the value of the controllable resistance.

As described above, according to the fifth embodiment, the resistor and the controllable resistor are connected on the bus to reduce the idle cycle conventionally inserted or to overlap the mode period in the bus cycle. By doing so, the bus cycle can be speeded up, and by adjusting the value of the controllable resistor, the priority of connection can be easily provided between certain devices, and the control load of device selection can be reduced. The effect that it can be obtained is obtained.

Embodiment 6 FIG. FIG. 6 is a diagram showing a configuration of a bus control system according to a sixth embodiment of the present invention. In the figure, reference numerals 42, 43, and 44 denote controllable resistors that can be dynamically controlled by the device (A) 1. , 52, 53, 54
The control register re is built in the device (B) 2, the device (C) 3, and the device (D) 4 and controls the controllable resistors 42, 43, and 44 by a control signal from the device (A) 1.
g (B), reg (C) and reg (D).

In FIG. 6, Rbpin, Rcp
in and Rdpin are the controllable resistors 42, 43, 4
4, Rbout, Rcpout, Rdpo
ut is an output terminal of each of the controllable resistors 42, 43, 44, and Rbpcnt, Rcpcnt, Rdpcnt is a control terminal of each of the controllable resistors 42, 43, 44.

FIG. 7 shows the controllable resistor Rbp in FIG.
42 is a diagram showing a configuration of a controllable resistor Rcp4.
3, the configuration of Rdp44 is also equivalent. In FIG. 7, 6
2 is a multiplexer, and 63, 64, and 65 are fixed resistors Rbp connected between the input terminal Rbpin and the multiplexer 62.

Next, the operation will be described. Control registers reg (B) 52, reg (C) 53, reg (D) 5
4 receives a control signal corresponding to the priority from the device (A) 1 and sets each value corresponding to the priority. Each of the controllable resistors 42, 43, and 44 includes a control register reg (B) 52, reg (C) 53, reg.
(D) The resistance value is controlled by the value set in 54.

In FIG. 7, a multiplexer 62 controls a control register reg input to a control terminal Rbpcnt.
(B) By selecting the number of fixed resistors Rbp between the input terminal Rbpin and the multiplexer 62 from among the fixed resistors Rbp 63, 64, and 65 connected in series according to the set value of 52, the device (A) 1 Input terminal Rbpin and output terminal Rbout corresponding to the priority specified by
Set the resistance value between and.

As described above, according to the sixth embodiment, the resistor and the controllable resistor are connected on the bus to reduce the idle cycle conventionally inserted or to overlap the mode period in the bus cycle. By doing so, the bus cycle can be speeded up, and the priority of the connection can be easily provided between the devices by adjusting the value of the controllable resistor based on the priority instruction from a certain device. As a result, the effect of reducing the control load of device selection can be obtained.

[0066]

As described above, according to the present invention, when a resistor for limiting a current flowing through each device is connected to a bus corresponding to each device and a bus cycle between the devices is switched, By switching the bus cycle without setting an idle cycle for preventing a bus signal collision, there is an effect that a bus control method for realizing a high-speed bus cycle can be obtained.

According to the present invention, the resistance connected to the bus limits the current so that the current flowing to each device at the time of a bus collision becomes equal to or less than the current rating value of each device. Has the effect of not causing a decrease in

According to the present invention, by connecting a resistor to a data bus for transmitting data, it is possible to obtain a bus control system for realizing a faster bus cycle on the data bus.

According to the present invention, by connecting a resistor to an address bus for transmitting an address, it is possible to obtain a bus control method for realizing a high-speed bus cycle on the address bus. .

According to the present invention, there is an effect that a bus control method for realizing a high-speed bus cycle can be obtained by overlapping the mode periods of the bus cycle when switching.

According to the present invention, another resistor is connected to a part of the bus between the resistors corresponding to the device, and the output of the first device connected to the bus is connected to the second bus connected to the bus. By setting the value of the resistor corresponding to the device and the value of the other resistors so that the output of the third device connected to the bus becomes dominant at any value with respect to the input of the device, The priority of connection can be provided between the first device and the second device, and there is an effect that the control load of device selection can be reduced.

According to the present invention, by connecting a controllable resistor as a resistor corresponding to a device, the priority of connection can be easily provided between certain devices, and the control load of device selection can be reduced. There is an effect that can be.

According to the present invention, the first bus connected to the bus
By setting the resistance value of the controllable resistor corresponding to the second device connected to the bus based on the instruction related to the priority from the device, the connection between the first device and the second device is set. There is an effect that priority can be easily provided, and the control load of device selection can be reduced.

According to the present invention, the controllable resistor corresponding to the second device is constituted by a plurality of fixed resistors and a multiplexer for selecting the plurality of fixed resistors, and the first resistor is provided in the register in the second device. A multiplexer sets a resistance value of a controllable resistor corresponding to the second device by setting an instruction relating to the priority from the second device and selecting the fixed resistor based on the instruction set in the register. Accordingly, the priority of connection can be easily provided between the first device and the second device, and there is an effect that the control load of device selection can be reduced.

According to the present invention, another resistor is connected to a part of the bus between the resistors corresponding to the device, and the connection point between the resistor corresponding to the third device connected to the bus and the other resistor is connected to the bus. A capacitor is connected between grounds, and the output of the first device connected to the bus becomes dominant to the input of the second device connected to the bus, and the output of the first device is connected to the third device. The priority of the connection between the first device and the second device by setting the value of the resistor corresponding to the device, the value of the other resistor, and the value of the capacitance so as not to be dominant to the input of the device Can be provided,
This has the effect of reducing the control load of device selection.

According to the present invention, when a resistor for limiting a current flowing through each device is connected to a buffer installed in each device and connected to a bus, and a bus cycle is switched between the devices, a bus signal is used. By switching the bus cycle without setting an idle cycle to prevent collision, the bus cycle can be accelerated, and there is no need to arrange resistors on the board wiring that can withstand the collision of bus signals. In addition, there is an effect that the wiring length of the substrate can be shortened and the wiring delay can be reduced.

According to the present invention, the current flowing to each device at the time of a bus collision becomes equal to or less than the current rating value of each device.
By limiting the current by the resistor connected in the buffer, there is an effect that the long-term reliability of the device is not reduced.

According to the present invention, by connecting a resistor in a buffer connected to a data bus for transmitting data, it is possible to obtain a bus control system for realizing a high-speed bus cycle on the data bus. This has the effect.

According to the present invention, by connecting a resistor in a buffer connected to an address bus for transmitting an address, it is possible to obtain a bus control system for realizing a high-speed bus cycle on the address bus. This has the effect.

According to the present invention, another resistor is connected on a part of the bus between the resistors in each buffer, and the connection point between the resistor in the buffer of the third device connected to the bus and the other resistor is connected. Connecting a capacitor in a buffer of a third device between the first device connected to the bus and the input of a second device connected to the bus; By setting the value of the resistor in the buffer, the value of the other resistor, and the value of the capacitance such that the output of one device does not dominate the input of the third device, The priority of connection can be provided between the second device and the second device, so that the control load of device selection can be reduced, and the wiring length of the substrate can be shortened, and the wiring delay can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a bus control system according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a configuration of a bus control system according to a second embodiment of the present invention.

FIG. 3 is a diagram showing a configuration of a bus control system according to a third embodiment of the present invention.

FIG. 4 is a diagram showing a configuration of a bus control system according to a fourth embodiment of the present invention.

FIG. 5 is a diagram showing a configuration of a bus control system according to a fifth embodiment of the present invention.

FIG. 6 is a diagram showing a configuration of a bus control system according to a sixth embodiment of the present invention.

FIG. 7 is a diagram showing a configuration of a controllable resistor according to a sixth embodiment of the present invention.

FIG. 8 is a diagram showing a configuration of a conventional bus control system.

[Explanation of symbols]

1 device (A) (device), 2 device (B) (device), 3
Equipment (C) (Equipment), 4 Equipment (D) (Equipment), 6
Buffer Bff (A) (Buffer), 7 Buffer Bf
f (B) (buffer), 8 buffers Bff (C) (buffer), 9 buffers Bff (D) (buffer), 11
Resistance Ra (resistance), 12 Resistance Rb (resistance), 13
Resistance Rc (resistance), 14 resistance Rd (resistance), 15 resistance Rm (other resistance), 16 resistance Rn (other resistance), 23 capacitance Cd (capacity), 32 controllable resistance Rbc (controllable resistance) , 33 Controllable resistor Rc
c (controllable resistor), 34 controllable resistor Rdc
(Controllable resistor), 42 controllable resistor Rbp (controllable resistor), 43 controllable resistor Rcp (controllable resistor), 44 controllable resistor Rdp (controllable resistor), 52 register reg ( B) (register), 53
Register reg (C) (register), 54 Register reg (D) (register), 62 multiplexer, 6
3,64,65 Fixed resistance.

 ────────────────────────────────────────────────── ─── Continued on the front page (72) Inventor Mika Horikoshi 2-3-2 Marunouchi, Chiyoda-ku, Tokyo F-term (reference) 5B061 BA01 BB21 BC02 PP00 QQ02 5K032 AA02 CA06 DB12

Claims (15)

[Claims] 1. A bus control method for controlling a bus connecting a plurality of devices, wherein a resistor for limiting a current flowing through each of the devices is connected to the bus corresponding to each of the devices. A bus control method characterized by switching the bus cycle without setting an idle cycle for preventing collision of bus signals when switching between bus cycles. 2. The bus control according to claim 1, wherein a resistor connected on the bus limits the current so that the current flowing to each device at the time of a bus collision becomes equal to or less than the current rating value of each device. method. 3. The bus control method according to claim 1, wherein a resistor is connected to a data bus for transmitting data. 4. An address bus for transmitting an address,
2. The bus control method according to claim 1, wherein a resistor is connected. 5. The bus control method according to claim 1, wherein the mode periods of the bus cycle at the time of switching are overlapped. 6. A device in which another resistor is connected on a part of the bus between the resistors corresponding to the device, and the output of the first device connected to the bus is connected to the output of the second device connected to the bus. The value of the resistor corresponding to the device and the value of the other resistor are set such that the output of the third device connected to the bus becomes dominant with respect to the input regardless of the value. The bus control method according to claim 1, wherein 7. The bus control method according to claim 6, wherein a controllable resistor is connected as the resistor corresponding to the device. 8. A resistance value of a controllable resistor corresponding to a second device connected to the bus is set based on a priority instruction from the first device connected to the bus. The bus control method according to claim 7, wherein 9. The controllable resistor corresponding to the second device is constituted by a plurality of fixed resistors and a multiplexer for selecting the plurality of fixed resistors, wherein a register in the second device is provided to the register in the second device. And setting the resistance value of the controllable resistor corresponding to the second device by the multiplexer selecting the fixed resistance based on the instruction set in the register. 9. The bus control method according to claim 8, wherein: 10. A resistor is connected to a part of the bus between the resistors corresponding to the device, and a connection point between the resistor corresponding to the third device connected to the bus and the other resistor is connected to the ground. And the output of the first device connected to the bus is
The resistance of the resistor associated with the device is controlled so that the input of the second device connected to the bus becomes dominant and the output of the first device does not become dominant to the input of the third device. The bus control method according to claim 1, wherein a value, a value of the other resistor, and a value of the capacitance are set. 11. A bus control method for controlling a bus connecting a plurality of devices, wherein a resistor for limiting a current flowing through each device is provided in a buffer installed in each device and connected to the bus. A bus control method, wherein the bus cycle is switched without setting an idle cycle for preventing a bus signal collision when the bus cycle is switched between the respective devices. 12. The bus control according to claim 11, wherein a resistor connected in the buffer limits the current so that the current flowing to each device at the time of a bus collision becomes equal to or less than the current rating value of each device. method. 13. The bus control method according to claim 11, wherein a resistor is connected in a buffer connected to a data bus for transmitting data. 14. The bus control method according to claim 11, wherein a resistor is connected in a buffer connected to an address bus for transmitting an address. 15. A resistor is connected to a part of the bus between the resistors in each buffer, and a connection point between the resistor in the buffer of the third device connected to the bus and the other resistor is connected to ground. Connecting a capacitor in a buffer of the third device, wherein the output of the first device connected to the bus becomes dominant to the input of the second device connected to the bus; The value of the resistor in the buffer, the value of the other resistor, and the value of the capacitance are set so that the output of the first device does not become dominant with respect to the input of the third device. The bus control method according to claim 11, wherein