CN117725003B - Customized SPI interface and data read-write method suitable for high-speed ADC communication - Google Patents

Abstract

The embodiment of the application provides a customized SPI interface and a data read-write method suitable for high-speed ADC communication, wherein the customized SPI interface comprises the following components: a chip select signal pin CNV, which is used for designating a gated SPI slave machine through a CNV signal and indicating to start conversion in the high-speed ADC; an input pin DIN for configuring a conversion mode of the high-speed ADC by DIN signals; an output pin SDO for outputting ADC conversion data; a clock pin SCK for providing a clock signal; the communication data format of the customized SPI interface is as follows: during normal operation, the reading and writing of data are 16 bits, the reading and writing bit number is high-order priority, and then the low-order communication is carried out sequentially; the one-time programmable OTP data writing is executed when the chip leaves the factory, the conversion parameters of the high-speed ADC are written first, then one or more groups of OTP data are written, wherein one group of OTP data comprises a 5-bit address which is written first and 8-bit data which is written later, and the problem that the common SPI in the related technology cannot support special functions required in the high-speed ADC communication is solved.

Description

Customized SPI interface and data read-write method suitable for high-speed ADC communication

Technical Field

The application relates to the technical field of microelectronics, in particular to a customized SPI interface and a data read-write method suitable for high-speed ADC communication.

Background

With the rise of emerging applications such as 5G, artificial intelligence, internet of things, automotive electronics, etc., high-speed data conversion systems are becoming more common. The importance of a high-speed analog-to-digital converter (Analog to Digital Converter, ADC for short) as the most widely used data conversion system is self-evident. The design of high-speed ADC not only puts high demands on the conversion circuit, but also on the digital interface with which it is mated.

In the low-speed ADC, an integrated circuit bus (Inter-INTEGRATED CIRCUIT, abbreviated as IIC) interface may be used for communication, but in the high-speed ADC, the rate of IIC is difficult to reach more than 10Mbps, and the addressing bits in the frame structure waste a certain communication time, so that it is difficult to meet the requirement of high-speed communication. The synchronous serial bus (SERIAL PERIPHERAL INTERFACE, abbreviated as SPI) interface has the advantages of high-speed and full duplex communication, and can be suitable for the design of a high-speed ADC, but the general SPI also cannot support the special functions required in the high-speed ADC communication, such as flexible writing of one-time programmable (One Time Programmable, abbreviated as OTP) data and flexible configuration of conversion parameters.

Aiming at the problem that the general SPI can not support the special functions needed in the high-speed ADC communication in the prior art, no effective solution exists.

Disclosure of Invention

The embodiment of the application provides a customized SPI interface and a data read-write method suitable for high-speed ADC communication, which are used for solving the problem that a general SPI in the related art cannot support special functions required in the high-speed ADC communication.

In one embodiment of the present application, a custom synchronous serial bus (SPI) interface suitable for high-speed analog-to-digital (ADC) communications is provided, the custom SPI interface comprising: a chip select signal pin CNV, which is used for designating a gated SPI slave machine through a CNV signal and indicating to start conversion in the high-speed ADC; an input pin DIN for configuring a conversion mode of the high-speed ADC by DIN signals; an output pin SDO for outputting ADC conversion data; a clock pin SCK for providing a clock signal; the communication data format of the customized SPI interface is as follows: during normal operation, the reading and writing of data are 16 bits, the reading and writing bit number is high-order priority, and then the low-order communication is carried out sequentially; and executing one-time programmable OTP data writing when the chip leaves the factory, firstly writing the conversion parameters of the high-speed ADC, and then writing one or more groups of OTP data, wherein the group of OTP data comprises a 5-bit address which is written firstly and 8-bit data which is written later.

In an embodiment, the default supported read bit number of the communication format of the custom SPI interface is 16 bits, and when the docked high-speed ADC is smaller than 16 bits, a high-order aligned, low-order zero-filling communication format is adopted.

In an embodiment, the chip select signal pin CNV is further configured to determine whether to generate an interrupt flag bit according to a pull-up time of the CNV signal, where if the CNV signal is high when the internal conversion of the high-speed ADC is completed, the interrupt flag bit is not generated; if the CNV signal is low when the internal conversion of the high-speed ADC is finished, an interrupt flag bit is generated, wherein the interrupt flag bit is used for indicating the high-speed ADC to generate an interrupt signal after the conversion is finished, so that a host reads a conversion result and performs the next conversion.

In an embodiment, the interrupt signal is implemented through the output pin SDO, and the output pin SDO is connected to a high level through an external pull-up resistor when the host needs to use an interrupt function; when each conversion data transmission is completed, the inside of the output pin SDO is changed into high resistance, and the external pull-up resistor pulls up the output of the output pin SDO to high level; after the conversion of the high-speed ADC is completed, the output pin SDO changes from high resistance to low level, and the external part of the output pin SDO shows a jump from high level to low level, where the process of changing from high level to low level is used as an interrupt signal to enable the host to immediately start the transmission of the converted data.

According to another embodiment of the present application, there is further provided a data read-write method, which is applicable to the custom SPI interface of any one of claims 1 to 4, and includes implementing data writing and data reading of the custom SPI interface by a read-write state machine.

In one embodiment, the state transition when the custom SPI interface data is written comprises:

S10: the write_idle state is a state when the read-WRITE state machine is powered on and a state that all states jump to after encountering an EOC signal, wherein the EOC signal is a signal for ending the internal conversion of the high-speed ADC, writing is performed before the first EOC signal is received after the power on, the state is jumped to S15, and the subsequent writing is jumped to S11;

S11: the write_cfg state is a state of normally receiving the WRITE parameter configuration, the write_cfg state takes effect after receiving the EOC signal after receiving the complete WRITE parameter configuration, and when the chip works in the normal mode, the step is skipped to S14; when the chip works in a factory calibration mode, continuing to receive the written DATA DATA after ADDR, and jumping to S12;

S12: the write_addr state is used for receiving the written address, when the chip works in a factory calibration mode, after the parameter configuration of 16 bits is written, the configuration of OTP is carried out, the configuration format is 5-bit address+8-bit data, and the write_addr state is skipped to S13 after the end;

S13: the write_data state is used for receiving written DATA, writing 8-bit DATA in the write_data state, continuing to jump to the write_addr state S12 after writing is completed until an EOC signal is encountered, and ending the transmission;

S14: the write_fin state is used for temporarily storing and judging whether new writing is performed, and after the state of S11 is finished, the state is skipped to the write_fin state, if new writing is continued, the state is skipped to S11, otherwise, the state is skipped to S17;

s15: the write_first_cfg state is a writing state before the EOC signal is received for the FIRST time after power-up, the writing value in the write_first_cfg state is only received and not updated, and the step is skipped to S16 after the writing is completed;

S16: the write_first_fin state is used for temporarily storing the written 14-bit value and judging whether new writing is started, if so, the step is skipped to S15, otherwise, the step is skipped to S17;

s17: the WRITE_WAIT_EOC state is used to WAIT for the EOC signal to finish a complete WRITE, and WAIT for the data to be transferred by the EOC signal to update.

In one embodiment, the state transition at the time of data reading of the custom SPI interface comprises:

s20: the READ_IDLE state is the initial stage of the READ-write state machine, and when the falling edge of the SCK clock is detected, the step S21 is skipped;

s21: the READ_first_CONV state is SPI communication generated in the FIRST switching stage after the READ-write state machine is powered on, and when enough SCK pulses are counted, the step is skipped to S22; if the EOC signal appears when enough SCK clock pulses are not counted, jumping to S23 if the CNV signal is at a high level at the moment, and jumping to S25 if the CNV signal is at a low level at the moment;

S22: the SDO_HIGH state is a HIGH-resistance state, when SPI transmission is completed each time, the output pin SDO is set to be in a HIGH-resistance state, a register, a counter and the like used in the transmission process are reset to be in an initial state after the transmission is completed, when an EOC signal appears, if a CNV signal is in a HIGH level at the moment, the step S23 is skipped, and if the CNV signal is in a low level, the step S25 is skipped;

s23: a read_ NOBUSY _edge state, in which the read_ NOBUSY _edge state is entered at the rising EDGE of the EOC signal, and in which the most significant bit MSB of the conversion result is placed on the SDO signal line for the transmission state of the busy indicator, the read_ NOBUSY _edge state is left for one cycle, i.e., the jump is made to S24;

S24: the READ_ NOBUSY state is SPI transmission state, when the CNV signal is at low level, counting the number of SCK falling edge pulses, and outputting a conversion result from MSB-1; if enough SCK pulses are counted, if the OTP programming result needs to be read, jumping to a state S27, otherwise jumping to a state S22; if EOC signal appears in the transmission process, if CNV signal is high level, jumping to state S23, if CNV signal is low level, jumping to S25;

s25: a READ_BUSY_EDGE state, which is entered on the rising EDGE of the EOC signal, the high resistance state of the output pin SDO is cancelled and the signal of the output pin SDO is set to 0 for the transmission state with a BUSY indicator, and a cycle is stopped in the READ_BUSY_EDGE state and then a jump is made to S26;

S26: the READ_BUSY state is an SPI transmission state, counts the number of SCK falling edge pulses when the CNV signal is at a low level, and outputs a conversion result from the MSB; if enough SCK pulses are counted, if the OTP programming result needs to be read, jumping to a state S27, otherwise jumping to a state S22; if EOC signal appears in the transmission process, if CNV signal is high level, jumping to S23, if CNV signal is low level, jumping to S25;

S27: the MR_READ state is used for transmitting the result of 256-bit margin_read OTP through SPI signals in the current state, the current state can not be entered after completing one-time complete transmission, and the state S22 is skipped after completing the transmission; if the EOC signal appears during the transmission, the process goes to S23 if the CNV signal is at high level, and goes to S25 if the CNV signal is at low level.

The customized SPI interface and the data read-write method suitable for high-speed ADC communication provided by the embodiment of the application comprise the following steps: a chip select signal pin CNV, which is used for designating a gated SPI slave machine through a CNV signal and indicating to start conversion in the high-speed ADC; an input pin DIN for configuring a conversion mode of the high-speed ADC by DIN signals; an output pin SDO for outputting ADC conversion data; a clock pin SCK for providing a clock signal; the communication data format of the customized SPI interface is as follows: during normal operation, the reading and writing of data are 16 bits, the reading and writing bit number is high-order priority, and then the low-order communication is carried out sequentially; the one-time programmable OTP data writing is executed when the chip leaves the factory, the conversion parameters of the high-speed ADC are written first, then one or more groups of OTP data are written, wherein the group of OTP data comprises a 5-bit address which is written first and 8-bit data which is written later, the problem that the common SPI in the related technology cannot support special functions required in the high-speed ADC communication is solved, and the conversion parameters, the writing of OTP content and the reading of the ADC conversion data with any bit number can be realized by customizing an SPI interface.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this specification, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute a limitation on the application. In the drawings:

FIG. 1 is a schematic diagram of an alternative custom SPI interface architecture suitable for high-speed ADC communication, in accordance with an embodiment of the present application;

FIG. 2 is a schematic diagram of an alternative custom SPI interface write state transition, in accordance with an embodiment of the present application;

FIG. 3 is a schematic diagram of an alternative custom SPI interface read state transition, in accordance with an embodiment of the present application;

FIG. 4 is an alternative universal timing diagram for communication without interrupt signals in accordance with an embodiment of the present application;

fig. 5 is an alternative general timing diagram for communication with an interrupt signal in accordance with an embodiment of the present application.

Detailed Description

The application will be described in detail hereinafter with reference to the drawings in conjunction with embodiments. It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.

The design of high-speed ADC not only puts high demands on the conversion circuit, but also on the digital interface with which it is mated. In the low-speed ADC, IIC can be used for communication, but in the high-speed ADC, the rate of IIC is difficult to reach more than 10Mbps, and the addressing bits in the frame structure waste a certain communication time, so that the requirement of high-speed communication is difficult to be met. The general SPI has the advantage of high-speed, full duplex communication, but does not support the special functions required in high-speed ADC communication: 1. flexible generation of interrupt flags is not supported. In order to save communication time, the high-speed ADC performs data conversion faster and more, and can generate an interrupt signal after conversion is finished, so that a host reads a conversion result as soon as possible and performs next conversion. Standard SPI does not have this function. 2. Flexible writing of OTP data is not supported, the universal SPI does not support random adjustment of communication bit width, and random byte length writing of OTP is performed after configuration is written.

An embodiment of the present application proposes a custom SPI interface suitable for high-speed ADC communication, and fig. 1 is a schematic diagram of an alternative custom SPI interface structure suitable for high-speed ADC communication according to an embodiment of the present application, as shown in fig. 1, the custom SPI interface includes: a chip select signal pin CNV, which is used for designating a gated SPI slave machine through a CNV signal and indicating to start conversion in the high-speed ADC; an input pin DIN for configuring a conversion mode of the high-speed ADC by DIN signals; an output pin SDO for outputting ADC conversion data; a clock pin SCK for providing a clock signal; the communication data format of the customized SPI interface is as follows: during normal operation, the reading and writing of data are 16 bits, the reading and writing bit number is high-order priority, and then the low-order communication is carried out sequentially; and executing one-time programmable OTP data writing when the chip leaves the factory, firstly writing the conversion parameters of the high-speed ADC, and then writing one or more groups of OTP data, wherein the group of OTP data comprises a 5-bit address which is written firstly and 8-bit data which is written later.

In the embodiment of the present application, the writing of the interface definition SPI adopts the clock rising edge, and the reading of the interface definition SPI may be performed on both edges, or may be set according to a specific usage habit, which is not limited in the embodiment of the present application.

The custom SPI interface communication data format is shown in table 1 below. During normal operation, the data is read and written into 16 bits, firstly the read and written bits are high-order first, and then the low-order bits are communicated in sequence. CFG is a conversion parameter used to configure what mode of operation the ADC is in.

TABLE 1

The data format at the time of chip shipment writing OTP is shown in table 2 below. The ADC conversion configuration (CFG representing configuration parameters) is written first, and then one or more sets of OTP information can be written. When writing each set of OTP information, the 5-bit address is written first, and then the 8-bit OTP data is written.

TABLE 2

In one embodiment, the default supported read bit number is 16 bits, and the ADC with other output bit numbers such as 14 bits, 12 bits and the like is in the form of high alignment and low zero padding.

The generation of the interrupt flag is determined by the pull-up time of the conversion signal CNV, and the interrupt transfer function is not turned on if CNV is high at the completion of the conversion inside the ADC, and is turned on if CNV is low. The interrupt signal is implemented using the SDO pin, which the host needs to connect to a high level through a pull-up resistor if it is required to use this function. When the transfer of the converted data is completed, the inside of the SDO pin is changed into high resistance, and the external pull-up resistor can pull up the SDO to high level. After the ADC conversion is completed, the SDO is changed from high resistance to low level inside, and the SDO is changed from high level to low level outside. The level change may act as an interrupt signal to cause the host to immediately begin transmission of the new transition data.

According to another embodiment of the present application, a data read-write method suitable for the above-mentioned customized SPI interface is also provided. The realization of the read-write function of the customized SPI interface is specifically completed by a read-write state machine. FIG. 2 is a schematic diagram of an alternative write state transition of a custom SPI interface according to an embodiment of the present application, and as shown in FIG. 2, the write state transition of the custom SPI interface includes:

s10: write_idle (IDLE state). And the state when the chip is powered on. While for all states a jump to the state after having encountered EOC (EOC is the end of conversion signal inside the ADC) is not shown. The first EOC after power-up is preceded by a write jump to S15, and the subsequent writes are all jumped to S11.

S11: write_cfg. The status of the write configuration is normally received and will take effect after EOC after receiving the complete write configuration. In the normal mode, the process jumps to the S14 state. In the factory calibration mode, the written ADDR post-DATA is continuously received, and the process goes to S12.

S12: write_addr. This state is used to receive the written address. When the chip works in a factory calibration mode, after the 16-bit CFG is written, OTP configuration can be carried out, and the configuration format is 5-bit address+8-bit data. After this state is ended, the process goes to S13.

S13: write_data. This state is used to receive the written data. In this mode 8 bits of data are written, after which the writing is completed the jump to the write address state S12 is continued until an EOC signal is encountered, ending the transfer.

S14: write_fin. This state is used for temporary storage and to determine whether a new write has been made. After the state of S11 is ended, the process jumps to this state, and if new writing is continued, the process jumps to S11, and if not, the process jumps to S17.

S15: write_first_cfg. A write state before the first EOC after power up. The written value in this state is received only and not updated. After the writing is completed, the process goes to S16.

S16: write_first_fin. This state is similar to S14, and the written 14-bit value is temporarily stored and it is judged whether or not a new writing is started. If new writing is continued, the process goes to S15, otherwise, the process goes to S17. Unlike S14, this state does not update the written value.

S17: write_wait_eoc. This state is used to wait for the EOC to finish a complete write. Waiting for the EOC signal to update the data being transmitted.

FIG. 3 is a schematic diagram of an alternative read state transition of a custom SPI interface according to an embodiment of the present application, and as shown in FIG. 3, the read state transition of the custom SPI interface includes:

S20: the initial phase (IDLE state) of the READ IDLE state machine. When the SCK clock falling edge is detected, the process goes to S21.

S21: the read_first_conv, the SPI communication that occurs in the FIRST transition phase after power-up, the data that occurs in this phase is converted to invalid data. When a sufficient number of SCK pulses have counted, the state S22 is skipped. If an EOC signal is present during transmission (not counting enough SCK clock pulses), if at this time CNV is high, then it jumps to S23. If CNV is low, the process goes to S25.

S22: when the transmission of the SPI is completed, an additional SCK clock pulse is needed to set the SDO port to be in a HIGH-resistance state, namely, the SDO port is required to be in a state, and registers, counters and the like used in some transmission processes are required to be reset to return to an initial state when the transmission is completed. When the EOC signal occurs, if CNV is high at this time, the process goes to S23. If CNV is low, the process goes to S25.

S23: READ_ NOBUSY _EDGE. When the rising edge of the EOC signal jumps to the state, for the transmission state of the busless indicator, the MSB of the conversion result is required to be put on the SDO signal line, and the CNV signal is still in a high level at the moment, so that the SDO port still presents a high resistance state to the outside, and after the CNV falling edge, the SDO is output, and the time sequence requirement is met at the moment. In this state, one cycle is stopped, i.e., the state is jumped to S24.

S24: READ_ NOBUSY. This state is the SPI transmission state, and when CNV is low, count SCK trailing edge pulse number. And outputs the conversion result from MSB-1 if enough SCK pulses are counted (the counted pulse period selected depending on whether the CFG is currently required to be read back is different). If the OTP writing result needs to be read, the state is skipped to the state S27, otherwise the state is skipped to the state S22. If an EOC signal occurs during transmission, if CNV is high at this time, the process goes to S23. If CNV is low, the process goes to S25.

S25: READ_BUSY_EDGE. The transition to this state occurs on the rising edge of the EOC signal, which is needed at this time to cancel the high impedance state of the SDO port (if any) and set the SDO port to 0 for the transmission state containing the busy indicator. In this state, one cycle is stopped, that is, the state is jumped to S26. The transmission state including the busy indicator generates a busy indication signal corresponding to the interrupt signal.

S26: READ_BUSY. This state is the SPI transmission state, and when CNV is low, count SCK trailing edge pulse number. And the transition result is output from the MSB (SCK default is high, the first falling edge needs to transmit the MSB signal), if there are enough SCK pulses counted (the count pulse period selected depending on whether or not the CFG is currently required to be read back is different). If the OTP writing result needs to be read, the state is skipped to the state S27, otherwise the state is skipped to the state S22. If an EOC signal occurs during transmission, if CNV is high at this time, the process goes to S23. If CNV is low, the process goes to S25.

S27: MR_READ. This mode requires that the result of the 256 bit margin_read OTP be transmitted via the SPI signal, which occurs after the ADC result + register read-back CFG (if needed), and will not jump to this state again after a complete transmission has been made, and will jump to state S22 after the transmission has been completed. If an EOC signal occurs during transmission, if CNV is high at this time, the process goes to S23. If CNV is low, the process goes to S25.

The customized SPI interface realized by the read-write state machine can support data transmission in conversion (RDC), after conversion (RAC) and conversion whole process (RSC) at the same time.

Fig. 4 is an alternative universal timing diagram for communication without interrupt signals according to an embodiment of the present application, and fig. 5 is an alternative universal timing diagram for communication with interrupt signals according to an embodiment of the present application.

Common ADCs are typically read with a fixed time period (RAC) after the current conversion to before the next conversion. Because the CNV signal is used to clear the register storing the converted data and to reset the SPI state machine. And thus cannot continue reading during the transition and throughout the transition.

The embodiment of the application uses a conversion end signal (EOC) instead of starting a conversion signal (CNV) as the start of the SPI communication state machine, and uses the EOC signal to reset the SPI communication state machine and simultaneously send the highest converted bit to the SDO port (the data delay requirement is higher and the data delay requirement can be realized only by combining comprehensive constraint and a back end). The reset by CNV is avoided, so that the communication process can span CNV signals, and the communication efficiency is improved to the greatest extent.

By the customized SPI interface and the data read-write method provided by the embodiment of the application, full duplex conversion parameters, configuration of OTP content and reading of arbitrary bit ADC conversion data can be supported on the premise of ensuring the communication rate; whether to enable the interrupt transmission mode and generate an interrupt flag bit can be determined according to the configuration mode of the chip select signal; SPI communication with different rates during, after and throughout the conversion of the ADC can be supported.

The foregoing embodiment numbers of the present application are merely for the purpose of description, and do not represent the advantages or disadvantages of the embodiments.

In the foregoing embodiments of the present application, the descriptions of the embodiments are emphasized, and for a portion of this disclosure that is not described in detail in this embodiment, reference is made to the related descriptions of other embodiments.

The foregoing is merely a preferred embodiment of the present application and it should be noted that modifications and adaptations to those skilled in the art may be made without departing from the principles of the present application, which are intended to be comprehended within the scope of the present application.

Claims (6)

1. A custom SPI interface suitable for high speed ADC communications, the custom SPI interface comprising:

A chip select signal pin CNV, configured to designate a gated SPI slave in the high-speed ADC by a CNV signal, and instruct the high-speed ADC to start conversion;

an input pin DIN for configuring a conversion mode of the high-speed ADC by DIN signals;

An output pin SDO for outputting ADC conversion data;

a clock pin SCK for providing a clock signal;

The communication data format of the customized SPI interface is as follows: when the high-speed ADC is in butt joint with less than 16 bits, adopting a communication format of high-order alignment and low-order zero filling; and executing one-time programmable OTP data writing when the chip leaves the factory, firstly writing the conversion parameters of the high-speed ADC, and then writing one or more groups of OTP data, wherein one group of OTP data comprises a 5-bit address which is written firstly and 8-bit data which is written later.

2. The custom SPI interface for high speed ADC communications according to claim 1, wherein said chip select signal pin CNV is further configured to determine whether an interrupt flag bit is generated based on a pull-up time of said CNV signal, wherein,

If the CNV signal is high when the internal conversion of the high-speed ADC is finished, no interrupt flag bit is generated;

If the CNV signal is low when the internal conversion of the high-speed ADC is finished, an interrupt flag bit is generated, wherein the interrupt flag bit is used for indicating the high-speed ADC to generate an interrupt signal after the conversion is finished, so that a host reads a conversion result and performs the next conversion.

3. A custom SPI interface suitable for high-speed ADC communication as recited in claim 2, wherein,

The interrupt signal is realized through the output pin SDO, and the output pin SDO is connected to a high level through an external pull-up resistor when the host needs to use an interrupt function;

When each conversion data transmission is completed, the inside of the output pin SDO is changed into high resistance, and the external pull-up resistor pulls up the output of the output pin SDO to high level;

after the conversion of the high-speed ADC is completed, the output pin SDO changes from high resistance to low level, and the external part of the output pin SDO shows a jump from high level to low level, where the process of changing from high level to low level is used as an interrupt signal to enable the host to immediately start the transmission of the converted data.

4. A method of data reading and writing, the method being applicable to a custom SPI interface as claimed in any one of claims 1 to 3, the method comprising:

And the data writing and the data reading of the customized SPI interface are realized through a read-write state machine.

5. The method of claim 4, wherein the state transition when writing the custom SPI interface data comprises:

S10: the write_idle state is a state when the read-WRITE state machine is powered on and a state that all states jump to after encountering an EOC signal, wherein the EOC signal is a signal for ending the internal conversion of the high-speed ADC, writing is performed before the first EOC signal is received after the power on, the state is jumped to S15, and the subsequent writing is jumped to S11;

S11: the write_cfg state is a state of normally receiving the WRITE parameter configuration, the write_cfg state takes effect after receiving the EOC signal after receiving the complete WRITE parameter configuration, and when the chip works in the normal mode, the step is skipped to S14; when the chip works in a factory calibration mode, continuing to receive the written DATA DATA after ADDR, and jumping to S12;

S12: the write_addr state is used for receiving the written address, when the chip works in a factory calibration mode, after the parameter configuration of 16 bits is written, the configuration of OTP is carried out, the configuration format is 5-bit address+8-bit data, and the write_addr state is skipped to S13 after the end;

S13: the write_data state is used for receiving written DATA, writing 8-bit DATA in the write_data state, continuing to jump to the write_addr state S12 after writing is completed until an EOC signal is encountered, and ending the transmission;

S14: the write_fin state is used for temporarily storing and judging whether new writing is performed, and after the state of S11 is finished, the state is skipped to the write_fin state, if new writing is continued, the state is skipped to S11, otherwise, the state is skipped to S17;

s15: the write_first_cfg state is a writing state before the EOC signal is received for the FIRST time after power-up, the writing value in the write_first_cfg state is only received and not updated, and the step is skipped to S16 after the writing is completed;

S16: the write_first_fin state is used for temporarily storing the written 14-bit value and judging whether new writing is started, if so, the step is skipped to S15, otherwise, the step is skipped to S17;

s17: the WRITE_WAIT_EOC state is used to WAIT for the EOC signal to finish a complete WRITE, and WAIT for the data to be transferred by the EOC signal to update.

6. The method of claim 4, wherein the state transition at the time of data reading of the custom SPI interface comprises:

s20: the READ_IDLE state is the initial stage of the READ-write state machine, and when the falling edge of the SCK clock is detected, the step S21 is skipped;

s21: the READ_first_CONV state is SPI communication generated in the FIRST switching stage after the READ-write state machine is powered on, and when enough SCK pulses are counted, the step is skipped to S22; if the EOC signal appears when enough SCK clock pulses are not counted, jumping to S23 if the CNV signal is at a high level at the moment, and jumping to S25 if the CNV signal is at a low level at the moment;

S22: the SDO_HIGH state is a HIGH-resistance state, when SPI transmission is completed each time, the output pin SDO is set to be in a HIGH-resistance state, a register, a counter and the like used in the transmission process are reset to be in an initial state after the transmission is completed, when an EOC signal appears, if a CNV signal is in a HIGH level at the moment, the step S23 is skipped, and if the CNV signal is in a low level, the step S25 is skipped;

s23: a read_ NOBUSY _edge state, in which the read_ NOBUSY _edge state is entered at the rising EDGE of the EOC signal, and in which the most significant bit MSB of the conversion result is placed on the SDO signal line for the transmission state of the busy indicator, the read_ NOBUSY _edge state is left for one cycle, i.e., the jump is made to S24;

S24: the READ_ NOBUSY state is SPI transmission state, when the CNV signal is at low level, counting the number of SCK falling edge pulses, and outputting a conversion result from MSB-1; if enough SCK pulses are counted, if the OTP programming result needs to be read, jumping to a state S27, otherwise jumping to a state S22; if EOC signal appears in the transmission process, if CNV signal is high level, jumping to state S23, if CNV signal is low level, jumping to S25;

s25: a READ_BUSY_EDGE state, which is entered on the rising EDGE of the EOC signal, the high resistance state of the output pin SDO is cancelled and the signal of the output pin SDO is set to 0 for the transmission state with a BUSY indicator, and a cycle is stopped in the READ_BUSY_EDGE state and then a jump is made to S26;

S26: the READ_BUSY state is an SPI transmission state, counts the number of SCK falling edge pulses when the CNV signal is at a low level, and outputs a conversion result from the MSB; if enough SCK pulses are counted, if the OTP programming result needs to be read, jumping to a state S27, otherwise jumping to a state S22; if EOC signal appears in the transmission process, if CNV signal is high level, jumping to S23, if CNV signal is low level, jumping to S25;

s27: the MR_READ state is used for transmitting the result of 256-bit margin_read OTP through SPI signals in the current state, the current state can not be entered after completing one-time complete transmission, and the state S22 is skipped after completing the transmission; if the EOC signal appears during the transmission, the process goes to S23 if the CNV signal is at high level, and goes to S25 if the CNV signal is at low level.